src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_cfg.h"
  29 #include "brw_vec4_live_variables.h"
  30
  31 using namespace brw;
  32
  33 /** @file brw_vec4_live_variables.cpp
  34  *
  35  * Support for computing at the basic block level which variables
  36  * (virtual GRFs in our case) are live at entry and exit.
  37  *
  38  * See Muchnick's Advanced Compiler Design and Implementation, section
  39  * 14.1 (p444).
  40  */
  41
  42 /**
  43  * Sets up the use[] and def[] arrays.
  44  *
  45  * The basic-block-level live variable analysis needs to know which
  46  * variables get used before they're completely defined, and which
  47  * variables are completely defined before they're used.
  48  *
  49  * We independently track each channel of a vec4.  This is because we need to
  50  * be able to recognize a sequence like:
  51  *
  52  * ...
  53  * DP4 tmp.x a b;
  54  * DP4 tmp.y c d;
  55  * MUL result.xy tmp.xy e.xy
  56  * ...
  57  *
  58  * as having tmp live only across that sequence (assuming it's used nowhere
  59  * else), because it's a common pattern.  A more conservative approach that
  60  * doesn't get tmp marked a deffed in this block will tend to result in
  61  * spilling.
  62  */
  63 void
  64 vec4_live_variables::setup_def_use()
  65 {
  66    int ip = 0;
  67
  68    foreach_block (block, cfg) {
  69       assert(ip == block->start_ip);
  70       if (block->num > 0)
  71          assert(cfg->blocks[block->num - 1]->end_ip == ip - 1);
  72
  73       foreach_inst_in_block(vec4_instruction, inst, block) {
  74          struct block_data *bd = &block_data[block->num];
  75
  76          /* Set use[] for this instruction */
  77          for (unsigned int i = 0; i < 3; i++) {
  78             if (inst->src[i].file == GRF) {
  79                int reg = inst->src[i].reg;
  80
  81                for (int j = 0; j < 4; j++) {
  82                   int c = BRW_GET_SWZ(inst->src[i].swizzle, j);
  83                   if (!BITSET_TEST(bd->def, reg * 4 + c))
  84                      BITSET_SET(bd->use, reg * 4 + c);
  85                }
  86             }
  87          }
  88          if (inst->reads_flag()) {
  89             if (!BITSET_TEST(bd->flag_def, 0)) {
  90                BITSET_SET(bd->flag_use, 0);
  91             }
  92          }
  93
  94          /* Check for unconditional writes to whole registers. These
  95           * are the things that screen off preceding definitions of a
  96           * variable, and thus qualify for being in def[].
  97           */
  98          if (inst->dst.file == GRF &&
  99              v->alloc.sizes[inst->dst.reg] == 1 &&
 100              !inst->predicate) {
 101             for (int c = 0; c < 4; c++) {
 102                if (inst->dst.writemask & (1 << c)) {
 103                   int reg = inst->dst.reg;
 104                   if (!BITSET_TEST(bd->use, reg * 4 + c))
 105                      BITSET_SET(bd->def, reg * 4 + c);
 106                }
 107             }
 108          }
 109          if (inst->writes_flag()) {
 110             if (!BITSET_TEST(bd->flag_use, 0)) {
 111                BITSET_SET(bd->flag_def, 0);
 112             }
 113          }
 114
 115          ip++;
 116       }
 117    }
 118 }
 119
 120 /**
 121  * The algorithm incrementally sets bits in liveout and livein,
 122  * propagating it through control flow.  It will eventually terminate
 123  * because it only ever adds bits, and stops when no bits are added in
 124  * a pass.
 125  */
 126 void
 127 vec4_live_variables::compute_live_variables()
 128 {
 129    bool cont = true;
 130
 131    while (cont) {
 132       cont = false;
 133
 134       foreach_block (block, cfg) {
 135          struct block_data *bd = &block_data[block->num];
 136
 137          /* Update livein */
 138          for (int i = 0; i < bitset_words; i++) {
 139             BITSET_WORD new_livein = (bd->use[i] |
 140                                       (bd->liveout[i] &
 141                                        ~bd->def[i]));
 142             if (new_livein & ~bd->livein[i]) {
 143                bd->livein[i] |= new_livein;
 144                cont = true;
 145             }
 146          }
 147          BITSET_WORD new_livein = (bd->flag_use[0] |
 148                                    (bd->flag_liveout[0] &
 149                                     ~bd->flag_def[0]));
 150          if (new_livein & ~bd->flag_livein[0]) {
 151             bd->flag_livein[0] |= new_livein;
 152             cont = true;
 153          }
 154
 155          /* Update liveout */
 156          foreach_list_typed(bblock_link, child_link, link, &block->children) {
 157             struct block_data *child_bd = &block_data[child_link->block->num];
 158
 159             for (int i = 0; i < bitset_words; i++) {
 160                BITSET_WORD new_liveout = (child_bd->livein[i] &
 161                                           ~bd->liveout[i]);
 162                if (new_liveout) {
 163                   bd->liveout[i] |= new_liveout;
 164                   cont = true;
 165                }
 166             }
 167             BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
 168                                        ~bd->flag_liveout[0]);
 169             if (new_liveout) {
 170                bd->flag_liveout[0] |= new_liveout;
 171                cont = true;
 172             }
 173          }
 174       }
 175    }
 176 }
 177
 178 vec4_live_variables::vec4_live_variables(vec4_visitor *v, cfg_t *cfg)
 179    : v(v), cfg(cfg)
 180 {
 181    mem_ctx = ralloc_context(NULL);
 182
 183    num_vars = v->alloc.count * 4;
 184    block_data = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
 185
 186    bitset_words = BITSET_WORDS(num_vars);
 187    for (int i = 0; i < cfg->num_blocks; i++) {
 188       block_data[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 189       block_data[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 190       block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 191       block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
 192
 193       block_data[i].flag_def[0] = 0;
 194       block_data[i].flag_use[0] = 0;
 195       block_data[i].flag_livein[0] = 0;
 196       block_data[i].flag_liveout[0] = 0;
 197    }
 198
 199    setup_def_use();
 200    compute_live_variables();
 201 }
 202
 203 vec4_live_variables::~vec4_live_variables()
 204 {
 205    ralloc_free(mem_ctx);
 206 }
 207
 208 #define MAX_INSTRUCTION (1 << 30)
 209
 210 /**
 211  * Computes a conservative start/end of the live intervals for each virtual GRF.
 212  *
 213  * We could expose per-channel live intervals to the consumer based on the
 214  * information we computed in vec4_live_variables, except that our only
 215  * current user is virtual_grf_interferes().  So we instead union the
 216  * per-channel ranges into a per-vgrf range for virtual_grf_start[] and
 217  * virtual_grf_end[].
 218  *
 219  * We could potentially have virtual_grf_interferes() do the test per-channel,
 220  * which would let some interesting register allocation occur (particularly on
 221  * code-generated GLSL sequences from the Cg compiler which does register
 222  * allocation at the GLSL level and thus reuses components of the variable
 223  * with distinct lifetimes).  But right now the complexity of doing so doesn't
 224  * seem worth it, since having virtual_grf_interferes() be cheap is important
 225  * for register allocation performance.
 226  */
 227 void
 228 vec4_visitor::calculate_live_intervals()
 229 {
 230    if (this->live_intervals)
 231       return;
 232
 233    int *start = ralloc_array(mem_ctx, int, this->alloc.count * 4);
 234    int *end = ralloc_array(mem_ctx, int, this->alloc.count * 4);
 235    ralloc_free(this->virtual_grf_start);
 236    ralloc_free(this->virtual_grf_end);
 237    this->virtual_grf_start = start;
 238    this->virtual_grf_end = end;
 239
 240    for (unsigned i = 0; i < this->alloc.count * 4; i++) {
 241       start[i] = MAX_INSTRUCTION;
 242       end[i] = -1;
 243    }
 244
 245    /* Start by setting up the intervals with no knowledge of control
 246     * flow.
 247     */
 248    int ip = 0;
 249    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 250       for (unsigned int i = 0; i < 3; i++) {
 251          if (inst->src[i].file == GRF) {
 252             int reg = inst->src[i].reg;
 253
 254             for (int j = 0; j < 4; j++) {
 255                int c = BRW_GET_SWZ(inst->src[i].swizzle, j);
 256
 257                start[reg * 4 + c] = MIN2(start[reg * 4 + c], ip);
 258                end[reg * 4 + c] = ip;
 259             }
 260          }
 261       }
 262
 263       if (inst->dst.file == GRF) {
 264          int reg = inst->dst.reg;
 265
 266          for (int c = 0; c < 4; c++) {
 267             if (inst->dst.writemask & (1 << c)) {
 268                start[reg * 4 + c] = MIN2(start[reg * 4 + c], ip);
 269                end[reg * 4 + c] = ip;
 270             }
 271          }
 272       }
 273
 274       ip++;
 275    }
 276
 277    /* Now, extend those intervals using our analysis of control flow.
 278     *
 279     * The control flow-aware analysis was done at a channel level, while at
 280     * this point we're distilling it down to vgrfs.
 281     */
 282    this->live_intervals = new(mem_ctx) vec4_live_variables(this, cfg);
 283
 284    foreach_block (block, cfg) {
 285       struct block_data *bd = &live_intervals->block_data[block->num];
 286
 287       for (int i = 0; i < live_intervals->num_vars; i++) {
 288          if (BITSET_TEST(bd->livein, i)) {
 289             start[i] = MIN2(start[i], block->start_ip);
 290             end[i] = MAX2(end[i], block->start_ip);
 291          }
 292
 293          if (BITSET_TEST(bd->liveout, i)) {
 294             start[i] = MIN2(start[i], block->end_ip);
 295             end[i] = MAX2(end[i], block->end_ip);
 296          }
 297       }
 298    }
 299 }
 300
 301 void
 302 vec4_visitor::invalidate_live_intervals()
 303 {
 304    ralloc_free(live_intervals);
 305    live_intervals = NULL;
 306 }
 307
 308 bool
 309 vec4_visitor::virtual_grf_interferes(int a, int b)
 310 {
 311    int start_a = MIN2(MIN2(virtual_grf_start[a * 4 + 0],
 312                            virtual_grf_start[a * 4 + 1]),
 313                       MIN2(virtual_grf_start[a * 4 + 2],
 314                            virtual_grf_start[a * 4 + 3]));
 315    int start_b = MIN2(MIN2(virtual_grf_start[b * 4 + 0],
 316                            virtual_grf_start[b * 4 + 1]),
 317                       MIN2(virtual_grf_start[b * 4 + 2],
 318                            virtual_grf_start[b * 4 + 3]));
 319    int end_a = MAX2(MAX2(virtual_grf_end[a * 4 + 0],
 320                          virtual_grf_end[a * 4 + 1]),
 321                     MAX2(virtual_grf_end[a * 4 + 2],
 322                          virtual_grf_end[a * 4 + 3]));
 323    int end_b = MAX2(MAX2(virtual_grf_end[b * 4 + 0],
 324                          virtual_grf_end[b * 4 + 1]),
 325                     MAX2(virtual_grf_end[b * 4 + 2],
 326                          virtual_grf_end[b * 4 + 3]));
 327    return !(end_a <= start_b ||
 328             end_b <= start_a);
 329 }