2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "glsl/ir_uniform.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_inputs
> 0)
41 if (nir
->num_uniforms
> 0)
44 nir_setup_system_values();
46 /* get the main function and emit it */
47 nir_foreach_overload(nir
, overload
) {
48 assert(strcmp(overload
->function
->name
, "main") == 0);
49 assert(overload
->impl
);
50 nir_emit_impl(overload
->impl
);
55 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
59 switch (instr
->intrinsic
) {
60 case nir_intrinsic_load_vertex_id
:
61 unreachable("should be lowered by lower_vertex_id().");
63 case nir_intrinsic_load_vertex_id_zero_base
:
64 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
65 if (reg
->file
== BAD_FILE
)
66 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
70 case nir_intrinsic_load_base_vertex
:
71 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
72 if (reg
->file
== BAD_FILE
)
73 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
77 case nir_intrinsic_load_instance_id
:
78 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
79 if (reg
->file
== BAD_FILE
)
80 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
90 setup_system_values_block(nir_block
*block
, void *void_visitor
)
92 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
94 nir_foreach_instr(block
, instr
) {
95 if (instr
->type
!= nir_instr_type_intrinsic
)
98 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
99 v
->nir_setup_system_value_intrinsic(intrin
);
106 vec4_visitor::nir_setup_system_values()
108 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
110 nir_foreach_overload(nir
, overload
) {
111 assert(strcmp(overload
->function
->name
, "main") == 0);
112 assert(overload
->impl
);
113 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
118 vec4_visitor::nir_setup_inputs()
120 nir_inputs
= ralloc_array(mem_ctx
, src_reg
, nir
->num_inputs
);
122 nir_foreach_variable(var
, &nir
->inputs
) {
123 int offset
= var
->data
.driver_location
;
124 unsigned size
= type_size_vec4(var
->type
);
125 for (unsigned i
= 0; i
< size
; i
++) {
126 src_reg src
= src_reg(ATTR
, var
->data
.location
+ i
, var
->type
);
127 nir_inputs
[offset
+ i
] = src
;
133 vec4_visitor::nir_setup_uniforms()
135 uniforms
= nir
->num_uniforms
;
137 nir_foreach_variable(var
, &nir
->uniforms
) {
138 /* UBO's and atomics don't take up space in the uniform file */
139 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
142 if (type_size_vec4(var
->type
) > 0)
143 uniform_size
[var
->data
.driver_location
] = type_size_vec4(var
->type
);
148 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
150 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
152 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
153 unsigned array_elems
=
154 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
156 nir_locals
[reg
->index
] = dst_reg(GRF
, alloc
.allocate(array_elems
));
159 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
161 nir_emit_cf_list(&impl
->body
);
165 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
167 exec_list_validate(list
);
168 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
169 switch (node
->type
) {
171 nir_emit_if(nir_cf_node_as_if(node
));
174 case nir_cf_node_loop
:
175 nir_emit_loop(nir_cf_node_as_loop(node
));
178 case nir_cf_node_block
:
179 nir_emit_block(nir_cf_node_as_block(node
));
183 unreachable("Invalid CFG node block");
189 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
191 /* First, put the condition in f0 */
192 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
193 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
194 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
196 /* We can just predicate based on the X channel, as the condition only
197 * goes on its own line */
198 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
200 nir_emit_cf_list(&if_stmt
->then_list
);
202 /* note: if the else is empty, dead CF elimination will remove it */
203 emit(BRW_OPCODE_ELSE
);
205 nir_emit_cf_list(&if_stmt
->else_list
);
207 emit(BRW_OPCODE_ENDIF
);
211 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
215 nir_emit_cf_list(&loop
->body
);
217 emit(BRW_OPCODE_WHILE
);
221 vec4_visitor::nir_emit_block(nir_block
*block
)
223 nir_foreach_instr(block
, instr
) {
224 nir_emit_instr(instr
);
229 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
233 switch (instr
->type
) {
234 case nir_instr_type_load_const
:
235 nir_emit_load_const(nir_instr_as_load_const(instr
));
238 case nir_instr_type_intrinsic
:
239 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
242 case nir_instr_type_alu
:
243 nir_emit_alu(nir_instr_as_alu(instr
));
246 case nir_instr_type_jump
:
247 nir_emit_jump(nir_instr_as_jump(instr
));
250 case nir_instr_type_tex
:
251 nir_emit_texture(nir_instr_as_tex(instr
));
254 case nir_instr_type_ssa_undef
:
255 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
259 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
265 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
266 unsigned base_offset
, nir_src
*indirect
)
270 reg
= v
->nir_locals
[nir_reg
->index
];
271 reg
= offset(reg
, base_offset
);
274 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
282 vec4_visitor::get_nir_dest(nir_dest dest
)
285 dst_reg dst
= dst_reg(GRF
, alloc
.allocate(1));
286 nir_ssa_values
[dest
.ssa
.index
] = dst
;
289 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
295 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
297 return retype(get_nir_dest(dest
), type
);
301 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
303 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
307 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
308 unsigned num_components
)
313 assert(src
.ssa
!= NULL
);
314 reg
= nir_ssa_values
[src
.ssa
->index
];
317 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
321 reg
= retype(reg
, type
);
323 src_reg reg_as_src
= src_reg(reg
);
324 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
329 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
330 unsigned num_components
)
332 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
336 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
338 /* if type is not specified, default to signed int */
339 return get_nir_src(src
, nir_type_int
, num_components
);
343 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
345 dst_reg reg
= dst_reg(GRF
, alloc
.allocate(1));
346 reg
.type
= BRW_REGISTER_TYPE_D
;
348 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
350 /* @FIXME: consider emitting vector operations to save some MOVs in
351 * cases where the components are representable in 8 bits.
352 * For now, we emit a MOV for each distinct value.
354 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
355 unsigned writemask
= 1 << i
;
357 if ((remaining
& writemask
) == 0)
360 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
361 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
366 reg
.writemask
= writemask
;
367 emit(MOV(reg
, src_reg(instr
->value
.i
[i
])));
369 remaining
&= ~writemask
;
372 /* Set final writemask */
373 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
375 nir_ssa_values
[instr
->def
.index
] = reg
;
379 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
384 bool has_indirect
= false;
386 switch (instr
->intrinsic
) {
388 case nir_intrinsic_load_input_indirect
:
391 case nir_intrinsic_load_input
: {
392 int offset
= instr
->const_index
[0];
393 src
= nir_inputs
[offset
];
396 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[0],
400 dest
= get_nir_dest(instr
->dest
, src
.type
);
401 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
403 emit(MOV(dest
, src
));
407 case nir_intrinsic_store_output_indirect
:
410 case nir_intrinsic_store_output
: {
411 int varying
= instr
->const_index
[0];
413 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
414 instr
->num_components
);
418 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[1],
422 output_reg
[varying
] = dest
;
426 case nir_intrinsic_get_buffer_size
: {
427 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
428 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
430 const unsigned index
=
431 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
432 dst_reg result_dst
= get_nir_dest(instr
->dest
);
433 vec4_instruction
*inst
= new(mem_ctx
)
434 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
437 inst
->mlen
= 1; /* always at least one */
438 inst
->src
[1] = src_reg(index
);
440 /* MRF for the first parameter */
441 src_reg lod
= src_reg(0);
442 int param_base
= inst
->base_mrf
;
443 int writemask
= WRITEMASK_X
;
444 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
448 brw_mark_surface_used(&prog_data
->base
, index
);
452 case nir_intrinsic_store_ssbo_indirect
:
455 case nir_intrinsic_store_ssbo
: {
456 assert(devinfo
->gen
>= 7);
460 nir_const_value
*const_uniform_block
=
461 nir_src_as_const_value(instr
->src
[1]);
462 if (const_uniform_block
) {
463 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
464 const_uniform_block
->u
[0];
465 surf_index
= src_reg(index
);
466 brw_mark_surface_used(&prog_data
->base
, index
);
468 surf_index
= src_reg(this, glsl_type::uint_type
);
469 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
470 src_reg(prog_data
->base
.binding_table
.ssbo_start
)));
471 surf_index
= emit_uniformize(surf_index
);
473 brw_mark_surface_used(&prog_data
->base
,
474 prog_data
->base
.binding_table
.ssbo_start
+
475 nir
->info
.num_ssbos
- 1);
479 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
480 unsigned const_offset_bytes
= 0;
482 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[2], 1)));
484 const_offset_bytes
= instr
->const_index
[0];
485 emit(MOV(dst_reg(offset_reg
), src_reg(const_offset_bytes
)));
489 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
492 unsigned write_mask
= instr
->const_index
[1];
494 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
495 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
496 * typed and untyped messages and across hardware platforms, the
497 * current implementation of the untyped messages will transparently convert
498 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
499 * and enabling only channel X on the SEND instruction.
501 * The above, works well for full vector writes, but not for partial writes
502 * where we want to write some channels and not others, like when we have
503 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
504 * quite restrictive with regards to the channel enables we can configure in
505 * the message descriptor (not all combinations are allowed) we cannot simply
506 * implement these scenarios with a single message while keeping the
507 * aforementioned symmetry in the implementation. For now we de decided that
508 * it is better to keep the symmetry to reduce complexity, so in situations
509 * such as the one described we end up emitting two untyped write messages
510 * (one for xy and another for w).
512 * The code below packs consecutive channels into a single write message,
513 * detects gaps in the vector write and if needed, sends a second message
514 * with the remaining channels. If in the future we decide that we want to
515 * emit a single message at the expense of losing the symmetry in the
516 * implementation we can:
518 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
519 * message payload. In this mode we can write up to 8 offsets and dwords
520 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
521 * and select which of the 8 channels carry data to write by setting the
522 * appropriate writemask in the dst register of the SEND instruction.
523 * It would require to write a new generator opcode specifically for
524 * IvyBridge since we would need to prepare a SIMD8 payload that could
525 * use any channel, not just X.
527 * 2) For Haswell+: Simply send a single write message but set the writemask
528 * on the dst of the SEND instruction to select the channels we want to
529 * write. It would require to modify the current messages to receive
530 * and honor the writemask provided.
532 const vec4_builder bld
= vec4_builder(this).at_end()
533 .annotate(current_annotation
, base_ir
);
535 int swizzle
[4] = { 0, 0, 0, 0};
536 int num_channels
= 0;
537 unsigned skipped_channels
= 0;
538 int num_components
= instr
->num_components
;
539 for (int i
= 0; i
< num_components
; i
++) {
540 /* Check if this channel needs to be written. If so, record the
541 * channel we need to take the data from in the swizzle array
543 int component_mask
= 1 << i
;
544 int write_test
= write_mask
& component_mask
;
546 swizzle
[num_channels
++] = i
;
548 /* If we don't have to write this channel it means we have a gap in the
549 * vector, so write the channels we accumulated until now, if any. Do
550 * the same if this was the last component in the vector.
552 if (!write_test
|| i
== num_components
- 1) {
553 if (num_channels
> 0) {
554 /* We have channels to write, so update the offset we need to
555 * write at to skip the channels we skipped, if any.
557 if (skipped_channels
> 0) {
559 const_offset_bytes
+= 4 * skipped_channels
;
560 offset_reg
= src_reg(const_offset_bytes
);
562 emit(ADD(dst_reg(offset_reg
), offset_reg
,
563 brw_imm_ud(4 * skipped_channels
)));
567 /* Swizzle the data register so we take the data from the channels
568 * we need to write and send the write message. This will write
569 * num_channels consecutive dwords starting at offset.
572 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
573 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
574 1 /* dims */, num_channels
/* size */,
577 /* If we have to do a second write we will have to update the
578 * offset so that we jump over the channels we have just written
581 skipped_channels
= num_channels
;
583 /* Restart the count for the next write message */
587 /* We did not write the current channel, so increase skipped count */
595 case nir_intrinsic_load_ssbo_indirect
:
598 case nir_intrinsic_load_ssbo
: {
599 assert(devinfo
->gen
>= 7);
601 nir_const_value
*const_uniform_block
=
602 nir_src_as_const_value(instr
->src
[0]);
605 if (const_uniform_block
) {
606 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
607 const_uniform_block
->u
[0];
608 surf_index
= src_reg(index
);
610 brw_mark_surface_used(&prog_data
->base
, index
);
612 surf_index
= src_reg(this, glsl_type::uint_type
);
613 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
614 src_reg(prog_data
->base
.binding_table
.ssbo_start
)));
615 surf_index
= emit_uniformize(surf_index
);
617 /* Assume this may touch any UBO. It would be nice to provide
618 * a tighter bound, but the array information is already lowered away.
620 brw_mark_surface_used(&prog_data
->base
,
621 prog_data
->base
.binding_table
.ssbo_start
+
622 nir
->info
.num_ssbos
- 1);
625 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
626 unsigned const_offset_bytes
= 0;
628 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[1], 1)));
630 const_offset_bytes
= instr
->const_index
[0];
631 emit(MOV(dst_reg(offset_reg
), src_reg(const_offset_bytes
)));
634 /* Read the vector */
635 const vec4_builder bld
= vec4_builder(this).at_end()
636 .annotate(current_annotation
, base_ir
);
638 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
639 1 /* dims */, 4 /* size*/,
641 dst_reg dest
= get_nir_dest(instr
->dest
);
642 read_result
.type
= dest
.type
;
643 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
644 emit(MOV(dest
, read_result
));
649 case nir_intrinsic_ssbo_atomic_add
:
650 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
652 case nir_intrinsic_ssbo_atomic_imin
:
653 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
655 case nir_intrinsic_ssbo_atomic_umin
:
656 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
658 case nir_intrinsic_ssbo_atomic_imax
:
659 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
661 case nir_intrinsic_ssbo_atomic_umax
:
662 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
664 case nir_intrinsic_ssbo_atomic_and
:
665 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
667 case nir_intrinsic_ssbo_atomic_or
:
668 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
670 case nir_intrinsic_ssbo_atomic_xor
:
671 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
673 case nir_intrinsic_ssbo_atomic_exchange
:
674 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
676 case nir_intrinsic_ssbo_atomic_comp_swap
:
677 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
680 case nir_intrinsic_load_vertex_id
:
681 unreachable("should be lowered by lower_vertex_id()");
683 case nir_intrinsic_load_vertex_id_zero_base
:
684 case nir_intrinsic_load_base_vertex
:
685 case nir_intrinsic_load_instance_id
: {
686 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
687 src_reg val
= src_reg(nir_system_values
[sv
]);
688 assert(val
.file
!= BAD_FILE
);
689 dest
= get_nir_dest(instr
->dest
, val
.type
);
690 emit(MOV(dest
, val
));
694 case nir_intrinsic_load_uniform_indirect
:
697 case nir_intrinsic_load_uniform
: {
698 dest
= get_nir_dest(instr
->dest
);
700 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0]));
701 src
.reg_offset
= instr
->const_index
[1];
704 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
705 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
708 emit(MOV(dest
, src
));
712 case nir_intrinsic_atomic_counter_read
:
713 case nir_intrinsic_atomic_counter_inc
:
714 case nir_intrinsic_atomic_counter_dec
: {
715 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
716 (unsigned) instr
->const_index
[0];
717 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
718 instr
->num_components
);
719 dest
= get_nir_dest(instr
->dest
);
721 switch (instr
->intrinsic
) {
722 case nir_intrinsic_atomic_counter_inc
:
723 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
724 src_reg(), src_reg());
726 case nir_intrinsic_atomic_counter_dec
:
727 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
728 src_reg(), src_reg());
730 case nir_intrinsic_atomic_counter_read
:
731 emit_untyped_surface_read(surf_index
, dest
, offset
);
734 unreachable("Unreachable");
737 brw_mark_surface_used(stage_prog_data
, surf_index
);
741 case nir_intrinsic_load_ubo_indirect
:
744 case nir_intrinsic_load_ubo
: {
745 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
748 dest
= get_nir_dest(instr
->dest
);
750 if (const_block_index
) {
751 /* The block index is a constant, so just emit the binding table entry
754 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
755 const_block_index
->u
[0];
756 surf_index
= src_reg(index
);
757 brw_mark_surface_used(&prog_data
->base
, index
);
759 /* The block index is not a constant. Evaluate the index expression
760 * per-channel and add the base UBO index; we have to select a value
761 * from any live channel.
763 surf_index
= src_reg(this, glsl_type::uint_type
);
764 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
765 instr
->num_components
),
766 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
767 surf_index
= emit_uniformize(surf_index
);
769 /* Assume this may touch any UBO. It would be nice to provide
770 * a tighter bound, but the array information is already lowered away.
772 brw_mark_surface_used(&prog_data
->base
,
773 prog_data
->base
.binding_table
.ubo_start
+
774 nir
->info
.num_ubos
- 1);
777 unsigned const_offset
= instr
->const_index
[0];
781 offset
= src_reg(const_offset
/ 16);
783 offset
= src_reg(this, glsl_type::uint_type
);
784 emit(SHR(dst_reg(offset
), get_nir_src(instr
->src
[1], nir_type_int
, 1),
788 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
789 packed_consts
.type
= dest
.type
;
791 emit_pull_constant_load_reg(dst_reg(packed_consts
),
794 NULL
, NULL
/* before_block/inst */);
796 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
797 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
798 const_offset
% 16 / 4,
799 const_offset
% 16 / 4,
800 const_offset
% 16 / 4);
802 emit(MOV(dest
, packed_consts
));
806 case nir_intrinsic_memory_barrier
: {
807 const vec4_builder bld
=
808 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
809 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
810 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
815 case nir_intrinsic_shader_clock
: {
816 /* We cannot do anything if there is an event, so ignore it for now */
817 const src_reg shader_clock
= get_timestamp();
818 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
820 dest
= get_nir_dest(instr
->dest
, type
);
821 emit(MOV(dest
, shader_clock
));
826 unreachable("Unknown intrinsic");
831 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
834 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
835 dest
= get_nir_dest(instr
->dest
);
838 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
840 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
842 surface
= src_reg(surf_index
);
843 brw_mark_surface_used(&prog_data
->base
, surf_index
);
845 surface
= src_reg(this, glsl_type::uint_type
);
846 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
847 src_reg(prog_data
->base
.binding_table
.ssbo_start
)));
849 /* Assume this may touch any UBO. This is the same we do for other
850 * UBO/SSBO accesses with non-constant surface.
852 brw_mark_surface_used(&prog_data
->base
,
853 prog_data
->base
.binding_table
.ssbo_start
+
854 nir
->info
.num_ssbos
- 1);
857 src_reg offset
= get_nir_src(instr
->src
[1], 1);
858 src_reg data1
= get_nir_src(instr
->src
[2], 1);
860 if (op
== BRW_AOP_CMPWR
)
861 data2
= get_nir_src(instr
->src
[3], 1);
863 /* Emit the actual atomic operation operation */
864 const vec4_builder bld
=
865 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
867 src_reg atomic_result
=
868 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
870 1 /* dims */, 1 /* rsize */,
873 dest
.type
= atomic_result
.type
;
874 bld
.MOV(dest
, atomic_result
);
878 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
880 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
883 static enum brw_conditional_mod
884 brw_conditional_for_nir_comparison(nir_op op
)
890 return BRW_CONDITIONAL_L
;
895 return BRW_CONDITIONAL_GE
;
899 case nir_op_ball_fequal2
:
900 case nir_op_ball_iequal2
:
901 case nir_op_ball_fequal3
:
902 case nir_op_ball_iequal3
:
903 case nir_op_ball_fequal4
:
904 case nir_op_ball_iequal4
:
905 return BRW_CONDITIONAL_Z
;
909 case nir_op_bany_fnequal2
:
910 case nir_op_bany_inequal2
:
911 case nir_op_bany_fnequal3
:
912 case nir_op_bany_inequal3
:
913 case nir_op_bany_fnequal4
:
914 case nir_op_bany_inequal4
:
915 return BRW_CONDITIONAL_NZ
;
918 unreachable("not reached: bad operation for comparison");
923 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
925 vec4_instruction
*inst
;
927 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
928 nir_op_infos
[instr
->op
].output_type
);
929 dst
.writemask
= instr
->dest
.write_mask
;
932 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
933 op
[i
] = get_nir_src(instr
->src
[i
].src
,
934 nir_op_infos
[instr
->op
].input_types
[i
], 4);
935 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
936 op
[i
].abs
= instr
->src
[i
].abs
;
937 op
[i
].negate
= instr
->src
[i
].negate
;
943 inst
= emit(MOV(dst
, op
[0]));
944 inst
->saturate
= instr
->dest
.saturate
;
950 unreachable("not reached: should be handled by lower_vec_to_movs()");
954 inst
= emit(MOV(dst
, op
[0]));
955 inst
->saturate
= instr
->dest
.saturate
;
960 inst
= emit(MOV(dst
, op
[0]));
966 inst
= emit(ADD(dst
, op
[0], op
[1]));
967 inst
->saturate
= instr
->dest
.saturate
;
971 inst
= emit(MUL(dst
, op
[0], op
[1]));
972 inst
->saturate
= instr
->dest
.saturate
;
976 if (devinfo
->gen
< 8) {
977 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
978 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
980 /* For integer multiplication, the MUL uses the low 16 bits of one of
981 * the operands (src0 through SNB, src1 on IVB and later). The MACH
982 * accumulates in the contribution of the upper 16 bits of that
983 * operand. If we can determine that one of the args is in the low
984 * 16 bits, though, we can just emit a single MUL.
986 if (value0
&& value0
->u
[0] < (1 << 16)) {
987 if (devinfo
->gen
< 7)
988 emit(MUL(dst
, op
[0], op
[1]));
990 emit(MUL(dst
, op
[1], op
[0]));
991 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
992 if (devinfo
->gen
< 7)
993 emit(MUL(dst
, op
[1], op
[0]));
995 emit(MUL(dst
, op
[0], op
[1]));
997 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
999 emit(MUL(acc
, op
[0], op
[1]));
1000 emit(MACH(dst_null_d(), op
[0], op
[1]));
1001 emit(MOV(dst
, src_reg(acc
)));
1004 emit(MUL(dst
, op
[0], op
[1]));
1009 case nir_op_imul_high
:
1010 case nir_op_umul_high
: {
1011 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1013 emit(MUL(acc
, op
[0], op
[1]));
1014 emit(MACH(dst
, op
[0], op
[1]));
1019 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1020 inst
->saturate
= instr
->dest
.saturate
;
1024 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1025 inst
->saturate
= instr
->dest
.saturate
;
1029 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1030 inst
->saturate
= instr
->dest
.saturate
;
1034 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1035 inst
->saturate
= instr
->dest
.saturate
;
1039 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1040 inst
->saturate
= instr
->dest
.saturate
;
1045 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1049 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1053 unreachable("not reached: should be handled by ldexp_to_arith()");
1056 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1057 inst
->saturate
= instr
->dest
.saturate
;
1061 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1062 inst
->saturate
= instr
->dest
.saturate
;
1066 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1067 inst
->saturate
= instr
->dest
.saturate
;
1070 case nir_op_uadd_carry
: {
1071 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1073 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1074 emit(MOV(dst
, src_reg(acc
)));
1078 case nir_op_usub_borrow
: {
1079 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1081 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1082 emit(MOV(dst
, src_reg(acc
)));
1087 inst
= emit(RNDZ(dst
, op
[0]));
1088 inst
->saturate
= instr
->dest
.saturate
;
1091 case nir_op_fceil
: {
1092 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1094 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1095 instr
->src
[0].src
.ssa
->num_components
:
1096 instr
->src
[0].src
.reg
.reg
->num_components
);
1098 op
[0].negate
= !op
[0].negate
;
1099 emit(RNDD(dst_reg(tmp
), op
[0]));
1101 inst
= emit(MOV(dst
, tmp
));
1102 inst
->saturate
= instr
->dest
.saturate
;
1107 inst
= emit(RNDD(dst
, op
[0]));
1108 inst
->saturate
= instr
->dest
.saturate
;
1112 inst
= emit(FRC(dst
, op
[0]));
1113 inst
->saturate
= instr
->dest
.saturate
;
1116 case nir_op_fround_even
:
1117 inst
= emit(RNDE(dst
, op
[0]));
1118 inst
->saturate
= instr
->dest
.saturate
;
1124 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1125 inst
->saturate
= instr
->dest
.saturate
;
1131 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1132 inst
->saturate
= instr
->dest
.saturate
;
1136 case nir_op_fddx_coarse
:
1137 case nir_op_fddx_fine
:
1139 case nir_op_fddy_coarse
:
1140 case nir_op_fddy_fine
:
1141 unreachable("derivatives are not valid in vertex shaders");
1153 emit(CMP(dst
, op
[0], op
[1],
1154 brw_conditional_for_nir_comparison(instr
->op
)));
1157 case nir_op_ball_fequal2
:
1158 case nir_op_ball_iequal2
:
1159 case nir_op_ball_fequal3
:
1160 case nir_op_ball_iequal3
:
1161 case nir_op_ball_fequal4
:
1162 case nir_op_ball_iequal4
: {
1164 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1166 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1167 brw_conditional_for_nir_comparison(instr
->op
)));
1168 emit(MOV(dst
, src_reg(0)));
1169 inst
= emit(MOV(dst
, src_reg(~0)));
1170 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1174 case nir_op_bany_fnequal2
:
1175 case nir_op_bany_inequal2
:
1176 case nir_op_bany_fnequal3
:
1177 case nir_op_bany_inequal3
:
1178 case nir_op_bany_fnequal4
:
1179 case nir_op_bany_inequal4
: {
1181 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1183 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1184 brw_conditional_for_nir_comparison(instr
->op
)));
1186 emit(MOV(dst
, src_reg(0)));
1187 inst
= emit(MOV(dst
, src_reg(~0)));
1188 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1193 if (devinfo
->gen
>= 8) {
1194 op
[0] = resolve_source_modifiers(op
[0]);
1196 emit(NOT(dst
, op
[0]));
1200 if (devinfo
->gen
>= 8) {
1201 op
[0] = resolve_source_modifiers(op
[0]);
1202 op
[1] = resolve_source_modifiers(op
[1]);
1204 emit(XOR(dst
, op
[0], op
[1]));
1208 if (devinfo
->gen
>= 8) {
1209 op
[0] = resolve_source_modifiers(op
[0]);
1210 op
[1] = resolve_source_modifiers(op
[1]);
1212 emit(OR(dst
, op
[0], op
[1]));
1216 if (devinfo
->gen
>= 8) {
1217 op
[0] = resolve_source_modifiers(op
[0]);
1218 op
[1] = resolve_source_modifiers(op
[1]);
1220 emit(AND(dst
, op
[0], op
[1]));
1225 emit(MOV(dst
, negate(op
[0])));
1229 emit(CMP(dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1233 emit(CMP(dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1236 case nir_op_fnoise1_1
:
1237 case nir_op_fnoise1_2
:
1238 case nir_op_fnoise1_3
:
1239 case nir_op_fnoise1_4
:
1240 case nir_op_fnoise2_1
:
1241 case nir_op_fnoise2_2
:
1242 case nir_op_fnoise2_3
:
1243 case nir_op_fnoise2_4
:
1244 case nir_op_fnoise3_1
:
1245 case nir_op_fnoise3_2
:
1246 case nir_op_fnoise3_3
:
1247 case nir_op_fnoise3_4
:
1248 case nir_op_fnoise4_1
:
1249 case nir_op_fnoise4_2
:
1250 case nir_op_fnoise4_3
:
1251 case nir_op_fnoise4_4
:
1252 unreachable("not reached: should be handled by lower_noise");
1254 case nir_op_unpack_half_2x16_split_x
:
1255 case nir_op_unpack_half_2x16_split_y
:
1256 case nir_op_pack_half_2x16_split
:
1257 unreachable("not reached: should not occur in vertex shader");
1259 case nir_op_unpack_snorm_2x16
:
1260 case nir_op_unpack_unorm_2x16
:
1261 case nir_op_pack_snorm_2x16
:
1262 case nir_op_pack_unorm_2x16
:
1263 unreachable("not reached: should be handled by lower_packing_builtins");
1265 case nir_op_unpack_half_2x16
:
1266 /* As NIR does not guarantee that we have a correct swizzle outside the
1267 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1268 * uses the source operand in an operation with WRITEMASK_Y while our
1269 * source operand has only size 1, it accessed incorrect data producing
1270 * regressions in Piglit. We repeat the swizzle of the first component on the
1271 * rest of components to avoid regressions. In the vec4_visitor IR code path
1272 * this is not needed because the operand has already the correct swizzle.
1274 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1275 emit_unpack_half_2x16(dst
, op
[0]);
1278 case nir_op_pack_half_2x16
:
1279 emit_pack_half_2x16(dst
, op
[0]);
1282 case nir_op_unpack_unorm_4x8
:
1283 emit_unpack_unorm_4x8(dst
, op
[0]);
1286 case nir_op_pack_unorm_4x8
:
1287 emit_pack_unorm_4x8(dst
, op
[0]);
1290 case nir_op_unpack_snorm_4x8
:
1291 emit_unpack_snorm_4x8(dst
, op
[0]);
1294 case nir_op_pack_snorm_4x8
:
1295 emit_pack_snorm_4x8(dst
, op
[0]);
1298 case nir_op_bitfield_reverse
:
1299 emit(BFREV(dst
, op
[0]));
1302 case nir_op_bit_count
:
1303 emit(CBIT(dst
, op
[0]));
1306 case nir_op_ufind_msb
:
1307 case nir_op_ifind_msb
: {
1308 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1310 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1311 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1312 * subtract the result from 31 to convert the MSB count into an LSB count.
1315 emit(CMP(dst_null_d(), src
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1317 inst
= emit(ADD(dst
, src
, src_reg(31)));
1318 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1319 inst
->src
[0].negate
= true;
1323 case nir_op_find_lsb
:
1324 emit(FBL(dst
, op
[0]));
1327 case nir_op_ubitfield_extract
:
1328 case nir_op_ibitfield_extract
:
1329 op
[0] = fix_3src_operand(op
[0]);
1330 op
[1] = fix_3src_operand(op
[1]);
1331 op
[2] = fix_3src_operand(op
[2]);
1333 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1337 emit(BFI1(dst
, op
[0], op
[1]));
1341 op
[0] = fix_3src_operand(op
[0]);
1342 op
[1] = fix_3src_operand(op
[1]);
1343 op
[2] = fix_3src_operand(op
[2]);
1345 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1348 case nir_op_bitfield_insert
:
1349 unreachable("not reached: should be handled by "
1350 "lower_instructions::bitfield_insert_to_bfm_bfi");
1353 /* AND(val, 0x80000000) gives the sign bit.
1355 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1358 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1360 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1361 dst
.type
= BRW_REGISTER_TYPE_UD
;
1362 emit(AND(dst
, op
[0], src_reg(0x80000000u
)));
1364 inst
= emit(OR(dst
, src_reg(dst
), src_reg(0x3f800000u
)));
1365 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1366 dst
.type
= BRW_REGISTER_TYPE_F
;
1368 if (instr
->dest
.saturate
) {
1369 inst
= emit(MOV(dst
, src_reg(dst
)));
1370 inst
->saturate
= true;
1375 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1376 * -> non-negative val generates 0x00000000.
1377 * Predicated OR sets 1 if val is positive.
1379 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1380 emit(ASR(dst
, op
[0], src_reg(31)));
1381 inst
= emit(OR(dst
, src_reg(dst
), src_reg(1)));
1382 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1386 emit(SHL(dst
, op
[0], op
[1]));
1390 emit(ASR(dst
, op
[0], op
[1]));
1394 emit(SHR(dst
, op
[0], op
[1]));
1398 op
[0] = fix_3src_operand(op
[0]);
1399 op
[1] = fix_3src_operand(op
[1]);
1400 op
[2] = fix_3src_operand(op
[2]);
1402 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1403 inst
->saturate
= instr
->dest
.saturate
;
1407 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1408 inst
->saturate
= instr
->dest
.saturate
;
1412 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1413 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1414 switch (dst
.writemask
) {
1416 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1419 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1422 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1425 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1428 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1433 case nir_op_fdot_replicated2
:
1434 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1435 inst
->saturate
= instr
->dest
.saturate
;
1438 case nir_op_fdot_replicated3
:
1439 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1440 inst
->saturate
= instr
->dest
.saturate
;
1443 case nir_op_fdot_replicated4
:
1444 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1445 inst
->saturate
= instr
->dest
.saturate
;
1448 case nir_op_fdph_replicated
:
1449 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1450 inst
->saturate
= instr
->dest
.saturate
;
1455 case nir_op_bany4
: {
1457 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1459 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), src_reg(0),
1460 BRW_CONDITIONAL_NZ
));
1461 emit(MOV(dst
, src_reg(0)));
1462 inst
= emit(MOV(dst
, src_reg(~0)));
1463 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1472 unreachable("not reached: should be lowered by lower_source mods");
1475 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1478 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1482 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1485 unreachable("Unimplemented ALU operation");
1488 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1489 * to sign extend the low bit to 0/~0
1491 if (devinfo
->gen
<= 5 &&
1492 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1493 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1494 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1495 masked
.writemask
= dst
.writemask
;
1496 emit(AND(masked
, src_reg(dst
), src_reg(1)));
1497 src_reg masked_neg
= src_reg(masked
);
1498 masked_neg
.negate
= true;
1499 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1504 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1506 switch (instr
->type
) {
1507 case nir_jump_break
:
1508 emit(BRW_OPCODE_BREAK
);
1511 case nir_jump_continue
:
1512 emit(BRW_OPCODE_CONTINUE
);
1515 case nir_jump_return
:
1518 unreachable("unknown jump");
1522 enum ir_texture_opcode
1523 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1525 enum ir_texture_opcode op
;
1528 case nir_texop_lod
: op
= ir_lod
; break;
1529 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1530 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1531 case nir_texop_tex
: op
= ir_tex
; break;
1532 case nir_texop_tg4
: op
= ir_tg4
; break;
1533 case nir_texop_txb
: op
= ir_txb
; break;
1534 case nir_texop_txd
: op
= ir_txd
; break;
1535 case nir_texop_txf
: op
= ir_txf
; break;
1536 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1537 case nir_texop_txl
: op
= ir_txl
; break;
1538 case nir_texop_txs
: op
= ir_txs
; break;
1540 unreachable("unknown texture opcode");
1546 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1547 unsigned components
)
1550 case nir_type_float
:
1551 return glsl_type::vec(components
);
1553 return glsl_type::ivec(components
);
1554 case nir_type_unsigned
:
1555 return glsl_type::uvec(components
);
1557 return glsl_type::bvec(components
);
1559 return glsl_type::error_type
;
1562 return glsl_type::error_type
;
1566 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1568 unsigned sampler
= instr
->sampler_index
;
1569 src_reg sampler_reg
= src_reg(sampler
);
1571 const glsl_type
*coord_type
= NULL
;
1572 src_reg shadow_comparitor
;
1573 src_reg offset_value
;
1575 src_reg sample_index
;
1578 const glsl_type
*dest_type
=
1579 glsl_type_for_nir_alu_type(instr
->dest_type
,
1580 nir_tex_instr_dest_size(instr
));
1581 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1583 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1584 * emitting anything other than setting up the constant result.
1586 if (instr
->op
== nir_texop_tg4
) {
1587 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], instr
->component
);
1588 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1589 emit(MOV(dest
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
1594 /* Load the texture operation sources */
1595 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1596 switch (instr
->src
[i
].src_type
) {
1597 case nir_tex_src_comparitor
:
1598 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1599 BRW_REGISTER_TYPE_F
, 1);
1602 case nir_tex_src_coord
: {
1603 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1605 switch (instr
->op
) {
1607 case nir_texop_txf_ms
:
1608 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1610 coord_type
= glsl_type::ivec(src_size
);
1614 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1616 coord_type
= glsl_type::vec(src_size
);
1622 case nir_tex_src_ddx
:
1623 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1624 nir_tex_instr_src_size(instr
, i
));
1627 case nir_tex_src_ddy
:
1628 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1629 nir_tex_instr_src_size(instr
, i
));
1632 case nir_tex_src_lod
:
1633 switch (instr
->op
) {
1636 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1640 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1645 case nir_tex_src_ms_index
: {
1646 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1647 assert(coord_type
!= NULL
);
1648 if (devinfo
->gen
>= 7 &&
1649 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1650 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1654 mcs
= retype(mcs
, BRW_REGISTER_TYPE_UD
);
1658 case nir_tex_src_offset
:
1659 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1662 case nir_tex_src_sampler_offset
: {
1663 /* The highest sampler which may be used by this operation is
1664 * the last element of the array. Mark it here, because the generator
1665 * doesn't have enough information to determine the bound.
1667 uint32_t array_size
= instr
->sampler_array_size
;
1668 uint32_t max_used
= sampler
+ array_size
- 1;
1669 if (instr
->op
== nir_texop_tg4
) {
1670 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1672 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1675 brw_mark_surface_used(&prog_data
->base
, max_used
);
1677 /* Emit code to evaluate the actual indexing expression */
1678 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1679 src_reg
temp(this, glsl_type::uint_type
);
1680 emit(ADD(dst_reg(temp
), src
, src_reg(sampler
)));
1681 sampler_reg
= emit_uniformize(temp
);
1685 case nir_tex_src_projector
:
1686 unreachable("Should be lowered by do_lower_texture_projection");
1688 case nir_tex_src_bias
:
1689 unreachable("LOD bias is not valid for vertex shaders.\n");
1692 unreachable("unknown texture source");
1696 uint32_t constant_offset
= 0;
1697 for (unsigned i
= 0; i
< 3; i
++) {
1698 if (instr
->const_offset
[i
] != 0) {
1699 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1704 /* Stuff the channel select bits in the top of the texture offset */
1705 if (instr
->op
== nir_texop_tg4
)
1706 constant_offset
|= gather_channel(instr
->component
, sampler
) << 16;
1708 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1710 bool is_cube_array
=
1711 instr
->op
== nir_texop_txs
&&
1712 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1715 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1717 lod
, lod2
, sample_index
,
1718 constant_offset
, offset_value
,
1719 mcs
, is_cube_array
, sampler
, sampler_reg
);
1723 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1725 nir_ssa_values
[instr
->def
.index
] = dst_reg(GRF
, alloc
.allocate(1));