2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_setup_system_values();
43 /* get the main function and emit it */
44 nir_foreach_overload(nir
, overload
) {
45 assert(strcmp(overload
->function
->name
, "main") == 0);
46 assert(overload
->impl
);
47 nir_emit_impl(overload
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
63 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
67 case nir_intrinsic_load_base_vertex
:
68 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
69 if (reg
->file
== BAD_FILE
)
70 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
74 case nir_intrinsic_load_instance_id
:
75 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
76 if (reg
->file
== BAD_FILE
)
77 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
87 setup_system_values_block(nir_block
*block
, void *void_visitor
)
89 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
91 nir_foreach_instr(block
, instr
) {
92 if (instr
->type
!= nir_instr_type_intrinsic
)
95 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
96 v
->nir_setup_system_value_intrinsic(intrin
);
103 vec4_visitor::nir_setup_system_values()
105 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
106 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
107 nir_system_values
[i
] = dst_reg();
110 nir_foreach_overload(nir
, overload
) {
111 assert(strcmp(overload
->function
->name
, "main") == 0);
112 assert(overload
->impl
);
113 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
118 vec4_visitor::nir_setup_uniforms()
120 uniforms
= nir
->num_uniforms
/ 16;
122 nir_foreach_variable(var
, &nir
->uniforms
) {
123 /* UBO's and atomics don't take up space in the uniform file */
124 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
127 if (type_size_vec4(var
->type
) > 0)
128 uniform_size
[var
->data
.driver_location
/ 16] = type_size_vec4(var
->type
);
133 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
135 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
136 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
137 nir_locals
[i
] = dst_reg();
140 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
141 unsigned array_elems
=
142 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
144 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(array_elems
));
147 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
149 nir_emit_cf_list(&impl
->body
);
153 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
155 exec_list_validate(list
);
156 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
157 switch (node
->type
) {
159 nir_emit_if(nir_cf_node_as_if(node
));
162 case nir_cf_node_loop
:
163 nir_emit_loop(nir_cf_node_as_loop(node
));
166 case nir_cf_node_block
:
167 nir_emit_block(nir_cf_node_as_block(node
));
171 unreachable("Invalid CFG node block");
177 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
179 /* First, put the condition in f0 */
180 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
181 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
182 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
184 /* We can just predicate based on the X channel, as the condition only
185 * goes on its own line */
186 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
188 nir_emit_cf_list(&if_stmt
->then_list
);
190 /* note: if the else is empty, dead CF elimination will remove it */
191 emit(BRW_OPCODE_ELSE
);
193 nir_emit_cf_list(&if_stmt
->else_list
);
195 emit(BRW_OPCODE_ENDIF
);
199 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
203 nir_emit_cf_list(&loop
->body
);
205 emit(BRW_OPCODE_WHILE
);
209 vec4_visitor::nir_emit_block(nir_block
*block
)
211 nir_foreach_instr(block
, instr
) {
212 nir_emit_instr(instr
);
217 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
221 switch (instr
->type
) {
222 case nir_instr_type_load_const
:
223 nir_emit_load_const(nir_instr_as_load_const(instr
));
226 case nir_instr_type_intrinsic
:
227 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
230 case nir_instr_type_alu
:
231 nir_emit_alu(nir_instr_as_alu(instr
));
234 case nir_instr_type_jump
:
235 nir_emit_jump(nir_instr_as_jump(instr
));
238 case nir_instr_type_tex
:
239 nir_emit_texture(nir_instr_as_tex(instr
));
242 case nir_instr_type_ssa_undef
:
243 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
247 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
253 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
254 unsigned base_offset
, nir_src
*indirect
)
258 reg
= v
->nir_locals
[nir_reg
->index
];
259 reg
= offset(reg
, base_offset
);
262 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
270 vec4_visitor::get_nir_dest(nir_dest dest
)
273 dst_reg dst
= dst_reg(VGRF
, alloc
.allocate(1));
274 nir_ssa_values
[dest
.ssa
.index
] = dst
;
277 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
283 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
285 return retype(get_nir_dest(dest
), type
);
289 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
291 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
295 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
296 unsigned num_components
)
301 assert(src
.ssa
!= NULL
);
302 reg
= nir_ssa_values
[src
.ssa
->index
];
305 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
309 reg
= retype(reg
, type
);
311 src_reg reg_as_src
= src_reg(reg
);
312 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
317 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
318 unsigned num_components
)
320 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
324 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
326 /* if type is not specified, default to signed int */
327 return get_nir_src(src
, nir_type_int
, num_components
);
331 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
333 dst_reg reg
= dst_reg(VGRF
, alloc
.allocate(1));
334 reg
.type
= BRW_REGISTER_TYPE_D
;
336 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
338 /* @FIXME: consider emitting vector operations to save some MOVs in
339 * cases where the components are representable in 8 bits.
340 * For now, we emit a MOV for each distinct value.
342 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
343 unsigned writemask
= 1 << i
;
345 if ((remaining
& writemask
) == 0)
348 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
349 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
354 reg
.writemask
= writemask
;
355 emit(MOV(reg
, brw_imm_d(instr
->value
.i
[i
])));
357 remaining
&= ~writemask
;
360 /* Set final writemask */
361 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
363 nir_ssa_values
[instr
->def
.index
] = reg
;
367 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
372 switch (instr
->intrinsic
) {
374 case nir_intrinsic_load_input
: {
375 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
377 /* We set EmitNoIndirectInput for VS */
378 assert(const_offset
);
380 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u
[0],
381 glsl_type::uvec4_type
);
383 dest
= get_nir_dest(instr
->dest
, src
.type
);
384 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
386 emit(MOV(dest
, src
));
390 case nir_intrinsic_store_output
: {
391 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
392 assert(const_offset
);
394 int varying
= instr
->const_index
[0] + const_offset
->u
[0];
396 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
397 instr
->num_components
);
399 output_reg
[varying
] = dst_reg(src
);
403 case nir_intrinsic_get_buffer_size
: {
404 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
405 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
407 const unsigned index
=
408 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
409 dst_reg result_dst
= get_nir_dest(instr
->dest
);
410 vec4_instruction
*inst
= new(mem_ctx
)
411 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
414 inst
->mlen
= 1; /* always at least one */
415 inst
->src
[1] = brw_imm_ud(index
);
417 /* MRF for the first parameter */
418 src_reg lod
= brw_imm_d(0);
419 int param_base
= inst
->base_mrf
;
420 int writemask
= WRITEMASK_X
;
421 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
425 brw_mark_surface_used(&prog_data
->base
, index
);
429 case nir_intrinsic_store_ssbo
: {
430 assert(devinfo
->gen
>= 7);
434 nir_const_value
*const_uniform_block
=
435 nir_src_as_const_value(instr
->src
[1]);
436 if (const_uniform_block
) {
437 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
438 const_uniform_block
->u
[0];
439 surf_index
= brw_imm_ud(index
);
440 brw_mark_surface_used(&prog_data
->base
, index
);
442 surf_index
= src_reg(this, glsl_type::uint_type
);
443 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
444 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
445 surf_index
= emit_uniformize(surf_index
);
447 brw_mark_surface_used(&prog_data
->base
,
448 prog_data
->base
.binding_table
.ssbo_start
+
449 nir
->info
.num_ssbos
- 1);
454 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
456 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
458 offset_reg
= get_nir_src(instr
->src
[2], 1);
462 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
465 unsigned write_mask
= instr
->const_index
[0];
467 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
468 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
469 * typed and untyped messages and across hardware platforms, the
470 * current implementation of the untyped messages will transparently convert
471 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
472 * and enabling only channel X on the SEND instruction.
474 * The above, works well for full vector writes, but not for partial writes
475 * where we want to write some channels and not others, like when we have
476 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
477 * quite restrictive with regards to the channel enables we can configure in
478 * the message descriptor (not all combinations are allowed) we cannot simply
479 * implement these scenarios with a single message while keeping the
480 * aforementioned symmetry in the implementation. For now we de decided that
481 * it is better to keep the symmetry to reduce complexity, so in situations
482 * such as the one described we end up emitting two untyped write messages
483 * (one for xy and another for w).
485 * The code below packs consecutive channels into a single write message,
486 * detects gaps in the vector write and if needed, sends a second message
487 * with the remaining channels. If in the future we decide that we want to
488 * emit a single message at the expense of losing the symmetry in the
489 * implementation we can:
491 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
492 * message payload. In this mode we can write up to 8 offsets and dwords
493 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
494 * and select which of the 8 channels carry data to write by setting the
495 * appropriate writemask in the dst register of the SEND instruction.
496 * It would require to write a new generator opcode specifically for
497 * IvyBridge since we would need to prepare a SIMD8 payload that could
498 * use any channel, not just X.
500 * 2) For Haswell+: Simply send a single write message but set the writemask
501 * on the dst of the SEND instruction to select the channels we want to
502 * write. It would require to modify the current messages to receive
503 * and honor the writemask provided.
505 const vec4_builder bld
= vec4_builder(this).at_end()
506 .annotate(current_annotation
, base_ir
);
508 int swizzle
[4] = { 0, 0, 0, 0};
509 int num_channels
= 0;
510 unsigned skipped_channels
= 0;
511 int num_components
= instr
->num_components
;
512 for (int i
= 0; i
< num_components
; i
++) {
513 /* Check if this channel needs to be written. If so, record the
514 * channel we need to take the data from in the swizzle array
516 int component_mask
= 1 << i
;
517 int write_test
= write_mask
& component_mask
;
519 swizzle
[num_channels
++] = i
;
521 /* If we don't have to write this channel it means we have a gap in the
522 * vector, so write the channels we accumulated until now, if any. Do
523 * the same if this was the last component in the vector.
525 if (!write_test
|| i
== num_components
- 1) {
526 if (num_channels
> 0) {
527 /* We have channels to write, so update the offset we need to
528 * write at to skip the channels we skipped, if any.
530 if (skipped_channels
> 0) {
531 if (offset_reg
.file
== IMM
) {
532 offset_reg
.ud
+= 4 * skipped_channels
;
534 emit(ADD(dst_reg(offset_reg
), offset_reg
,
535 brw_imm_ud(4 * skipped_channels
)));
539 /* Swizzle the data register so we take the data from the channels
540 * we need to write and send the write message. This will write
541 * num_channels consecutive dwords starting at offset.
544 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
545 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
546 1 /* dims */, num_channels
/* size */,
549 /* If we have to do a second write we will have to update the
550 * offset so that we jump over the channels we have just written
553 skipped_channels
= num_channels
;
555 /* Restart the count for the next write message */
559 /* We did not write the current channel, so increase skipped count */
567 case nir_intrinsic_load_ssbo
: {
568 assert(devinfo
->gen
>= 7);
570 nir_const_value
*const_uniform_block
=
571 nir_src_as_const_value(instr
->src
[0]);
574 if (const_uniform_block
) {
575 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
576 const_uniform_block
->u
[0];
577 surf_index
= brw_imm_ud(index
);
579 brw_mark_surface_used(&prog_data
->base
, index
);
581 surf_index
= src_reg(this, glsl_type::uint_type
);
582 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
583 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
584 surf_index
= emit_uniformize(surf_index
);
586 /* Assume this may touch any UBO. It would be nice to provide
587 * a tighter bound, but the array information is already lowered away.
589 brw_mark_surface_used(&prog_data
->base
,
590 prog_data
->base
.binding_table
.ssbo_start
+
591 nir
->info
.num_ssbos
- 1);
595 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
597 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
599 offset_reg
= get_nir_src(instr
->src
[1], 1);
602 /* Read the vector */
603 const vec4_builder bld
= vec4_builder(this).at_end()
604 .annotate(current_annotation
, base_ir
);
606 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
607 1 /* dims */, 4 /* size*/,
609 dst_reg dest
= get_nir_dest(instr
->dest
);
610 read_result
.type
= dest
.type
;
611 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
612 emit(MOV(dest
, read_result
));
617 case nir_intrinsic_ssbo_atomic_add
:
618 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
620 case nir_intrinsic_ssbo_atomic_imin
:
621 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
623 case nir_intrinsic_ssbo_atomic_umin
:
624 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
626 case nir_intrinsic_ssbo_atomic_imax
:
627 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
629 case nir_intrinsic_ssbo_atomic_umax
:
630 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
632 case nir_intrinsic_ssbo_atomic_and
:
633 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
635 case nir_intrinsic_ssbo_atomic_or
:
636 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
638 case nir_intrinsic_ssbo_atomic_xor
:
639 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
641 case nir_intrinsic_ssbo_atomic_exchange
:
642 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
644 case nir_intrinsic_ssbo_atomic_comp_swap
:
645 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
648 case nir_intrinsic_load_vertex_id
:
649 unreachable("should be lowered by lower_vertex_id()");
651 case nir_intrinsic_load_vertex_id_zero_base
:
652 case nir_intrinsic_load_base_vertex
:
653 case nir_intrinsic_load_instance_id
: {
654 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
655 src_reg val
= src_reg(nir_system_values
[sv
]);
656 assert(val
.file
!= BAD_FILE
);
657 dest
= get_nir_dest(instr
->dest
, val
.type
);
658 emit(MOV(dest
, val
));
662 case nir_intrinsic_load_uniform
: {
663 /* Offsets are in bytes but they should always be multiples of 16 */
664 assert(instr
->const_index
[0] % 16 == 0);
666 dest
= get_nir_dest(instr
->dest
);
668 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0] / 16));
669 src
.type
= dest
.type
;
671 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
673 /* Offsets are in bytes but they should always be multiples of 16 */
674 assert(const_offset
->u
[0] % 16 == 0);
675 src
.reg_offset
= const_offset
->u
[0] / 16;
677 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
678 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
681 emit(MOV(dest
, src
));
685 case nir_intrinsic_atomic_counter_read
:
686 case nir_intrinsic_atomic_counter_inc
:
687 case nir_intrinsic_atomic_counter_dec
: {
688 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
689 (unsigned) instr
->const_index
[0];
690 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
691 instr
->num_components
);
692 dest
= get_nir_dest(instr
->dest
);
694 switch (instr
->intrinsic
) {
695 case nir_intrinsic_atomic_counter_inc
:
696 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
697 src_reg(), src_reg());
699 case nir_intrinsic_atomic_counter_dec
:
700 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
701 src_reg(), src_reg());
703 case nir_intrinsic_atomic_counter_read
:
704 emit_untyped_surface_read(surf_index
, dest
, offset
);
707 unreachable("Unreachable");
710 brw_mark_surface_used(stage_prog_data
, surf_index
);
714 case nir_intrinsic_load_ubo
: {
715 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
718 dest
= get_nir_dest(instr
->dest
);
720 if (const_block_index
) {
721 /* The block index is a constant, so just emit the binding table entry
724 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
725 const_block_index
->u
[0];
726 surf_index
= brw_imm_ud(index
);
727 brw_mark_surface_used(&prog_data
->base
, index
);
729 /* The block index is not a constant. Evaluate the index expression
730 * per-channel and add the base UBO index; we have to select a value
731 * from any live channel.
733 surf_index
= src_reg(this, glsl_type::uint_type
);
734 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
735 instr
->num_components
),
736 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
737 surf_index
= emit_uniformize(surf_index
);
739 /* Assume this may touch any UBO. It would be nice to provide
740 * a tighter bound, but the array information is already lowered away.
742 brw_mark_surface_used(&prog_data
->base
,
743 prog_data
->base
.binding_table
.ubo_start
+
744 nir
->info
.num_ubos
- 1);
748 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
750 offset
= brw_imm_ud(const_offset
->u
[0] & ~15);
752 offset
= get_nir_src(instr
->src
[1], nir_type_int
, 1);
755 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
756 packed_consts
.type
= dest
.type
;
758 emit_pull_constant_load_reg(dst_reg(packed_consts
),
761 NULL
, NULL
/* before_block/inst */);
763 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
765 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
->u
[0] % 16 / 4,
766 const_offset
->u
[0] % 16 / 4,
767 const_offset
->u
[0] % 16 / 4,
768 const_offset
->u
[0] % 16 / 4);
771 emit(MOV(dest
, packed_consts
));
775 case nir_intrinsic_memory_barrier
: {
776 const vec4_builder bld
=
777 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
778 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
779 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
784 case nir_intrinsic_shader_clock
: {
785 /* We cannot do anything if there is an event, so ignore it for now */
786 const src_reg shader_clock
= get_timestamp();
787 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
789 dest
= get_nir_dest(instr
->dest
, type
);
790 emit(MOV(dest
, shader_clock
));
795 unreachable("Unknown intrinsic");
800 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
803 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
804 dest
= get_nir_dest(instr
->dest
);
807 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
809 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
811 surface
= brw_imm_ud(surf_index
);
812 brw_mark_surface_used(&prog_data
->base
, surf_index
);
814 surface
= src_reg(this, glsl_type::uint_type
);
815 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
816 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
818 /* Assume this may touch any UBO. This is the same we do for other
819 * UBO/SSBO accesses with non-constant surface.
821 brw_mark_surface_used(&prog_data
->base
,
822 prog_data
->base
.binding_table
.ssbo_start
+
823 nir
->info
.num_ssbos
- 1);
826 src_reg offset
= get_nir_src(instr
->src
[1], 1);
827 src_reg data1
= get_nir_src(instr
->src
[2], 1);
829 if (op
== BRW_AOP_CMPWR
)
830 data2
= get_nir_src(instr
->src
[3], 1);
832 /* Emit the actual atomic operation operation */
833 const vec4_builder bld
=
834 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
836 src_reg atomic_result
=
837 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
839 1 /* dims */, 1 /* rsize */,
842 dest
.type
= atomic_result
.type
;
843 bld
.MOV(dest
, atomic_result
);
847 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
849 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
852 static enum brw_conditional_mod
853 brw_conditional_for_nir_comparison(nir_op op
)
859 return BRW_CONDITIONAL_L
;
864 return BRW_CONDITIONAL_GE
;
868 case nir_op_ball_fequal2
:
869 case nir_op_ball_iequal2
:
870 case nir_op_ball_fequal3
:
871 case nir_op_ball_iequal3
:
872 case nir_op_ball_fequal4
:
873 case nir_op_ball_iequal4
:
874 return BRW_CONDITIONAL_Z
;
878 case nir_op_bany_fnequal2
:
879 case nir_op_bany_inequal2
:
880 case nir_op_bany_fnequal3
:
881 case nir_op_bany_inequal3
:
882 case nir_op_bany_fnequal4
:
883 case nir_op_bany_inequal4
:
884 return BRW_CONDITIONAL_NZ
;
887 unreachable("not reached: bad operation for comparison");
892 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
894 vec4_instruction
*inst
;
896 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
897 nir_op_infos
[instr
->op
].output_type
);
898 dst
.writemask
= instr
->dest
.write_mask
;
901 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
902 op
[i
] = get_nir_src(instr
->src
[i
].src
,
903 nir_op_infos
[instr
->op
].input_types
[i
], 4);
904 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
905 op
[i
].abs
= instr
->src
[i
].abs
;
906 op
[i
].negate
= instr
->src
[i
].negate
;
912 inst
= emit(MOV(dst
, op
[0]));
913 inst
->saturate
= instr
->dest
.saturate
;
919 unreachable("not reached: should be handled by lower_vec_to_movs()");
923 inst
= emit(MOV(dst
, op
[0]));
924 inst
->saturate
= instr
->dest
.saturate
;
929 inst
= emit(MOV(dst
, op
[0]));
935 inst
= emit(ADD(dst
, op
[0], op
[1]));
936 inst
->saturate
= instr
->dest
.saturate
;
940 inst
= emit(MUL(dst
, op
[0], op
[1]));
941 inst
->saturate
= instr
->dest
.saturate
;
945 if (devinfo
->gen
< 8) {
946 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
947 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
949 /* For integer multiplication, the MUL uses the low 16 bits of one of
950 * the operands (src0 through SNB, src1 on IVB and later). The MACH
951 * accumulates in the contribution of the upper 16 bits of that
952 * operand. If we can determine that one of the args is in the low
953 * 16 bits, though, we can just emit a single MUL.
955 if (value0
&& value0
->u
[0] < (1 << 16)) {
956 if (devinfo
->gen
< 7)
957 emit(MUL(dst
, op
[0], op
[1]));
959 emit(MUL(dst
, op
[1], op
[0]));
960 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
961 if (devinfo
->gen
< 7)
962 emit(MUL(dst
, op
[1], op
[0]));
964 emit(MUL(dst
, op
[0], op
[1]));
966 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
968 emit(MUL(acc
, op
[0], op
[1]));
969 emit(MACH(dst_null_d(), op
[0], op
[1]));
970 emit(MOV(dst
, src_reg(acc
)));
973 emit(MUL(dst
, op
[0], op
[1]));
978 case nir_op_imul_high
:
979 case nir_op_umul_high
: {
980 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
982 emit(MUL(acc
, op
[0], op
[1]));
983 emit(MACH(dst
, op
[0], op
[1]));
988 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
989 inst
->saturate
= instr
->dest
.saturate
;
993 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
994 inst
->saturate
= instr
->dest
.saturate
;
998 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
999 inst
->saturate
= instr
->dest
.saturate
;
1003 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1004 inst
->saturate
= instr
->dest
.saturate
;
1008 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1009 inst
->saturate
= instr
->dest
.saturate
;
1014 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1018 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1022 unreachable("not reached: should be handled by ldexp_to_arith()");
1025 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1026 inst
->saturate
= instr
->dest
.saturate
;
1030 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1031 inst
->saturate
= instr
->dest
.saturate
;
1035 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1036 inst
->saturate
= instr
->dest
.saturate
;
1039 case nir_op_uadd_carry
: {
1040 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1042 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1043 emit(MOV(dst
, src_reg(acc
)));
1047 case nir_op_usub_borrow
: {
1048 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1050 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1051 emit(MOV(dst
, src_reg(acc
)));
1056 inst
= emit(RNDZ(dst
, op
[0]));
1057 inst
->saturate
= instr
->dest
.saturate
;
1060 case nir_op_fceil
: {
1061 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1063 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1064 instr
->src
[0].src
.ssa
->num_components
:
1065 instr
->src
[0].src
.reg
.reg
->num_components
);
1067 op
[0].negate
= !op
[0].negate
;
1068 emit(RNDD(dst_reg(tmp
), op
[0]));
1070 inst
= emit(MOV(dst
, tmp
));
1071 inst
->saturate
= instr
->dest
.saturate
;
1076 inst
= emit(RNDD(dst
, op
[0]));
1077 inst
->saturate
= instr
->dest
.saturate
;
1081 inst
= emit(FRC(dst
, op
[0]));
1082 inst
->saturate
= instr
->dest
.saturate
;
1085 case nir_op_fround_even
:
1086 inst
= emit(RNDE(dst
, op
[0]));
1087 inst
->saturate
= instr
->dest
.saturate
;
1093 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1094 inst
->saturate
= instr
->dest
.saturate
;
1100 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1101 inst
->saturate
= instr
->dest
.saturate
;
1105 case nir_op_fddx_coarse
:
1106 case nir_op_fddx_fine
:
1108 case nir_op_fddy_coarse
:
1109 case nir_op_fddy_fine
:
1110 unreachable("derivatives are not valid in vertex shaders");
1122 emit(CMP(dst
, op
[0], op
[1],
1123 brw_conditional_for_nir_comparison(instr
->op
)));
1126 case nir_op_ball_fequal2
:
1127 case nir_op_ball_iequal2
:
1128 case nir_op_ball_fequal3
:
1129 case nir_op_ball_iequal3
:
1130 case nir_op_ball_fequal4
:
1131 case nir_op_ball_iequal4
: {
1133 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1135 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1136 brw_conditional_for_nir_comparison(instr
->op
)));
1137 emit(MOV(dst
, brw_imm_d(0)));
1138 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1139 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1143 case nir_op_bany_fnequal2
:
1144 case nir_op_bany_inequal2
:
1145 case nir_op_bany_fnequal3
:
1146 case nir_op_bany_inequal3
:
1147 case nir_op_bany_fnequal4
:
1148 case nir_op_bany_inequal4
: {
1150 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1152 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1153 brw_conditional_for_nir_comparison(instr
->op
)));
1155 emit(MOV(dst
, brw_imm_d(0)));
1156 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1157 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1162 if (devinfo
->gen
>= 8) {
1163 op
[0] = resolve_source_modifiers(op
[0]);
1165 emit(NOT(dst
, op
[0]));
1169 if (devinfo
->gen
>= 8) {
1170 op
[0] = resolve_source_modifiers(op
[0]);
1171 op
[1] = resolve_source_modifiers(op
[1]);
1173 emit(XOR(dst
, op
[0], op
[1]));
1177 if (devinfo
->gen
>= 8) {
1178 op
[0] = resolve_source_modifiers(op
[0]);
1179 op
[1] = resolve_source_modifiers(op
[1]);
1181 emit(OR(dst
, op
[0], op
[1]));
1185 if (devinfo
->gen
>= 8) {
1186 op
[0] = resolve_source_modifiers(op
[0]);
1187 op
[1] = resolve_source_modifiers(op
[1]);
1189 emit(AND(dst
, op
[0], op
[1]));
1194 emit(MOV(dst
, negate(op
[0])));
1198 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1202 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1205 case nir_op_fnoise1_1
:
1206 case nir_op_fnoise1_2
:
1207 case nir_op_fnoise1_3
:
1208 case nir_op_fnoise1_4
:
1209 case nir_op_fnoise2_1
:
1210 case nir_op_fnoise2_2
:
1211 case nir_op_fnoise2_3
:
1212 case nir_op_fnoise2_4
:
1213 case nir_op_fnoise3_1
:
1214 case nir_op_fnoise3_2
:
1215 case nir_op_fnoise3_3
:
1216 case nir_op_fnoise3_4
:
1217 case nir_op_fnoise4_1
:
1218 case nir_op_fnoise4_2
:
1219 case nir_op_fnoise4_3
:
1220 case nir_op_fnoise4_4
:
1221 unreachable("not reached: should be handled by lower_noise");
1223 case nir_op_unpack_half_2x16_split_x
:
1224 case nir_op_unpack_half_2x16_split_y
:
1225 case nir_op_pack_half_2x16_split
:
1226 unreachable("not reached: should not occur in vertex shader");
1228 case nir_op_unpack_snorm_2x16
:
1229 case nir_op_unpack_unorm_2x16
:
1230 case nir_op_pack_snorm_2x16
:
1231 case nir_op_pack_unorm_2x16
:
1232 unreachable("not reached: should be handled by lower_packing_builtins");
1234 case nir_op_unpack_half_2x16
:
1235 /* As NIR does not guarantee that we have a correct swizzle outside the
1236 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1237 * uses the source operand in an operation with WRITEMASK_Y while our
1238 * source operand has only size 1, it accessed incorrect data producing
1239 * regressions in Piglit. We repeat the swizzle of the first component on the
1240 * rest of components to avoid regressions. In the vec4_visitor IR code path
1241 * this is not needed because the operand has already the correct swizzle.
1243 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1244 emit_unpack_half_2x16(dst
, op
[0]);
1247 case nir_op_pack_half_2x16
:
1248 emit_pack_half_2x16(dst
, op
[0]);
1251 case nir_op_unpack_unorm_4x8
:
1252 emit_unpack_unorm_4x8(dst
, op
[0]);
1255 case nir_op_pack_unorm_4x8
:
1256 emit_pack_unorm_4x8(dst
, op
[0]);
1259 case nir_op_unpack_snorm_4x8
:
1260 emit_unpack_snorm_4x8(dst
, op
[0]);
1263 case nir_op_pack_snorm_4x8
:
1264 emit_pack_snorm_4x8(dst
, op
[0]);
1267 case nir_op_bitfield_reverse
:
1268 emit(BFREV(dst
, op
[0]));
1271 case nir_op_bit_count
:
1272 emit(CBIT(dst
, op
[0]));
1275 case nir_op_ufind_msb
:
1276 case nir_op_ifind_msb
: {
1277 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1279 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1280 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1281 * subtract the result from 31 to convert the MSB count into an LSB count.
1284 emit(CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
));
1286 inst
= emit(ADD(dst
, src
, brw_imm_d(31)));
1287 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1288 inst
->src
[0].negate
= true;
1292 case nir_op_find_lsb
:
1293 emit(FBL(dst
, op
[0]));
1296 case nir_op_ubitfield_extract
:
1297 case nir_op_ibitfield_extract
:
1298 op
[0] = fix_3src_operand(op
[0]);
1299 op
[1] = fix_3src_operand(op
[1]);
1300 op
[2] = fix_3src_operand(op
[2]);
1302 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1306 emit(BFI1(dst
, op
[0], op
[1]));
1310 op
[0] = fix_3src_operand(op
[0]);
1311 op
[1] = fix_3src_operand(op
[1]);
1312 op
[2] = fix_3src_operand(op
[2]);
1314 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1317 case nir_op_bitfield_insert
:
1318 unreachable("not reached: should be handled by "
1319 "lower_instructions::bitfield_insert_to_bfm_bfi");
1322 /* AND(val, 0x80000000) gives the sign bit.
1324 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1327 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1329 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1330 dst
.type
= BRW_REGISTER_TYPE_UD
;
1331 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1333 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1334 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1335 dst
.type
= BRW_REGISTER_TYPE_F
;
1337 if (instr
->dest
.saturate
) {
1338 inst
= emit(MOV(dst
, src_reg(dst
)));
1339 inst
->saturate
= true;
1344 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1345 * -> non-negative val generates 0x00000000.
1346 * Predicated OR sets 1 if val is positive.
1348 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1349 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1350 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1351 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1355 emit(SHL(dst
, op
[0], op
[1]));
1359 emit(ASR(dst
, op
[0], op
[1]));
1363 emit(SHR(dst
, op
[0], op
[1]));
1367 op
[0] = fix_3src_operand(op
[0]);
1368 op
[1] = fix_3src_operand(op
[1]);
1369 op
[2] = fix_3src_operand(op
[2]);
1371 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1372 inst
->saturate
= instr
->dest
.saturate
;
1376 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1377 inst
->saturate
= instr
->dest
.saturate
;
1381 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1382 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1383 switch (dst
.writemask
) {
1385 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1388 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1391 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1394 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1397 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1402 case nir_op_fdot_replicated2
:
1403 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1404 inst
->saturate
= instr
->dest
.saturate
;
1407 case nir_op_fdot_replicated3
:
1408 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1409 inst
->saturate
= instr
->dest
.saturate
;
1412 case nir_op_fdot_replicated4
:
1413 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1414 inst
->saturate
= instr
->dest
.saturate
;
1417 case nir_op_fdph_replicated
:
1418 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1419 inst
->saturate
= instr
->dest
.saturate
;
1424 case nir_op_bany4
: {
1426 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1428 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), brw_imm_d(0),
1429 BRW_CONDITIONAL_NZ
));
1430 emit(MOV(dst
, brw_imm_d(0)));
1431 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1432 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1441 unreachable("not reached: should be lowered by lower_source mods");
1444 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1447 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1451 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1454 unreachable("Unimplemented ALU operation");
1457 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1458 * to sign extend the low bit to 0/~0
1460 if (devinfo
->gen
<= 5 &&
1461 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1462 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1463 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1464 masked
.writemask
= dst
.writemask
;
1465 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1466 src_reg masked_neg
= src_reg(masked
);
1467 masked_neg
.negate
= true;
1468 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1473 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1475 switch (instr
->type
) {
1476 case nir_jump_break
:
1477 emit(BRW_OPCODE_BREAK
);
1480 case nir_jump_continue
:
1481 emit(BRW_OPCODE_CONTINUE
);
1484 case nir_jump_return
:
1487 unreachable("unknown jump");
1491 enum ir_texture_opcode
1492 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1494 enum ir_texture_opcode op
;
1497 case nir_texop_lod
: op
= ir_lod
; break;
1498 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1499 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1500 case nir_texop_tex
: op
= ir_tex
; break;
1501 case nir_texop_tg4
: op
= ir_tg4
; break;
1502 case nir_texop_txb
: op
= ir_txb
; break;
1503 case nir_texop_txd
: op
= ir_txd
; break;
1504 case nir_texop_txf
: op
= ir_txf
; break;
1505 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1506 case nir_texop_txl
: op
= ir_txl
; break;
1507 case nir_texop_txs
: op
= ir_txs
; break;
1508 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
1510 unreachable("unknown texture opcode");
1516 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1517 unsigned components
)
1520 case nir_type_float
:
1521 return glsl_type::vec(components
);
1523 return glsl_type::ivec(components
);
1525 return glsl_type::uvec(components
);
1527 return glsl_type::bvec(components
);
1529 return glsl_type::error_type
;
1532 return glsl_type::error_type
;
1536 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1538 unsigned sampler
= instr
->sampler_index
;
1539 src_reg sampler_reg
= brw_imm_ud(sampler
);
1541 const glsl_type
*coord_type
= NULL
;
1542 src_reg shadow_comparitor
;
1543 src_reg offset_value
;
1545 src_reg sample_index
;
1548 const glsl_type
*dest_type
=
1549 glsl_type_for_nir_alu_type(instr
->dest_type
,
1550 nir_tex_instr_dest_size(instr
));
1551 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1553 /* Load the texture operation sources */
1554 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1555 switch (instr
->src
[i
].src_type
) {
1556 case nir_tex_src_comparitor
:
1557 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1558 BRW_REGISTER_TYPE_F
, 1);
1561 case nir_tex_src_coord
: {
1562 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1564 switch (instr
->op
) {
1566 case nir_texop_txf_ms
:
1567 case nir_texop_samples_identical
:
1568 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1570 coord_type
= glsl_type::ivec(src_size
);
1574 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1576 coord_type
= glsl_type::vec(src_size
);
1582 case nir_tex_src_ddx
:
1583 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1584 nir_tex_instr_src_size(instr
, i
));
1587 case nir_tex_src_ddy
:
1588 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1589 nir_tex_instr_src_size(instr
, i
));
1592 case nir_tex_src_lod
:
1593 switch (instr
->op
) {
1596 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1600 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1605 case nir_tex_src_ms_index
: {
1606 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1610 case nir_tex_src_offset
:
1611 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1614 case nir_tex_src_sampler_offset
: {
1615 /* The highest sampler which may be used by this operation is
1616 * the last element of the array. Mark it here, because the generator
1617 * doesn't have enough information to determine the bound.
1619 uint32_t array_size
= instr
->sampler_array_size
;
1620 uint32_t max_used
= sampler
+ array_size
- 1;
1621 if (instr
->op
== nir_texop_tg4
) {
1622 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1624 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1627 brw_mark_surface_used(&prog_data
->base
, max_used
);
1629 /* Emit code to evaluate the actual indexing expression */
1630 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1631 src_reg
temp(this, glsl_type::uint_type
);
1632 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
1633 sampler_reg
= emit_uniformize(temp
);
1637 case nir_tex_src_projector
:
1638 unreachable("Should be lowered by do_lower_texture_projection");
1640 case nir_tex_src_bias
:
1641 unreachable("LOD bias is not valid for vertex shaders.\n");
1644 unreachable("unknown texture source");
1648 if (instr
->op
== nir_texop_txf_ms
||
1649 instr
->op
== nir_texop_samples_identical
) {
1650 assert(coord_type
!= NULL
);
1651 if (devinfo
->gen
>= 7 &&
1652 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1653 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1655 mcs
= brw_imm_ud(0u);
1659 uint32_t constant_offset
= 0;
1660 for (unsigned i
= 0; i
< 3; i
++) {
1661 if (instr
->const_offset
[i
] != 0) {
1662 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1667 /* Stuff the channel select bits in the top of the texture offset */
1668 if (instr
->op
== nir_texop_tg4
) {
1669 if (instr
->component
== 1 &&
1670 (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))) {
1671 /* gather4 sampler is broken for green channel on RG32F --
1672 * we must ask for blue instead.
1674 constant_offset
|= 2 << 16;
1676 constant_offset
|= instr
->component
<< 16;
1680 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1682 bool is_cube_array
=
1683 instr
->op
== nir_texop_txs
&&
1684 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1687 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1689 lod
, lod2
, sample_index
,
1690 constant_offset
, offset_value
,
1691 mcs
, is_cube_array
, sampler
, sampler_reg
);
1695 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1697 nir_ssa_values
[instr
->def
.index
] = dst_reg(VGRF
, alloc
.allocate(1));