2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "glsl/ir_uniform.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_inputs
> 0)
41 if (nir
->num_uniforms
> 0)
44 nir_setup_system_values();
46 /* get the main function and emit it */
47 nir_foreach_overload(nir
, overload
) {
48 assert(strcmp(overload
->function
->name
, "main") == 0);
49 assert(overload
->impl
);
50 nir_emit_impl(overload
->impl
);
55 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
59 switch (instr
->intrinsic
) {
60 case nir_intrinsic_load_vertex_id
:
61 unreachable("should be lowered by lower_vertex_id().");
63 case nir_intrinsic_load_vertex_id_zero_base
:
64 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
65 if (reg
->file
== BAD_FILE
)
66 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
70 case nir_intrinsic_load_base_vertex
:
71 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
72 if (reg
->file
== BAD_FILE
)
73 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
77 case nir_intrinsic_load_instance_id
:
78 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
79 if (reg
->file
== BAD_FILE
)
80 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
90 setup_system_values_block(nir_block
*block
, void *void_visitor
)
92 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
94 nir_foreach_instr(block
, instr
) {
95 if (instr
->type
!= nir_instr_type_intrinsic
)
98 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
99 v
->nir_setup_system_value_intrinsic(intrin
);
106 vec4_visitor::nir_setup_system_values()
108 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
110 nir_foreach_overload(nir
, overload
) {
111 assert(strcmp(overload
->function
->name
, "main") == 0);
112 assert(overload
->impl
);
113 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
118 vec4_visitor::nir_setup_inputs()
120 nir_inputs
= ralloc_array(mem_ctx
, src_reg
, nir
->num_inputs
);
122 nir_foreach_variable(var
, &nir
->inputs
) {
123 int offset
= var
->data
.driver_location
;
124 unsigned size
= type_size_vec4(var
->type
);
125 for (unsigned i
= 0; i
< size
; i
++) {
126 src_reg src
= src_reg(ATTR
, var
->data
.location
+ i
, var
->type
);
127 nir_inputs
[offset
+ i
] = src
;
133 vec4_visitor::nir_setup_uniforms()
135 uniforms
= nir
->num_uniforms
;
137 nir_foreach_variable(var
, &nir
->uniforms
) {
138 /* UBO's and atomics don't take up space in the uniform file */
139 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
142 if (type_size_vec4(var
->type
) > 0)
143 uniform_size
[var
->data
.driver_location
] = type_size_vec4(var
->type
);
148 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
150 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
152 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
153 unsigned array_elems
=
154 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
156 nir_locals
[reg
->index
] = dst_reg(GRF
, alloc
.allocate(array_elems
));
159 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
161 nir_emit_cf_list(&impl
->body
);
165 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
167 exec_list_validate(list
);
168 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
169 switch (node
->type
) {
171 nir_emit_if(nir_cf_node_as_if(node
));
174 case nir_cf_node_loop
:
175 nir_emit_loop(nir_cf_node_as_loop(node
));
178 case nir_cf_node_block
:
179 nir_emit_block(nir_cf_node_as_block(node
));
183 unreachable("Invalid CFG node block");
189 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
191 /* First, put the condition in f0 */
192 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
193 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
194 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
196 emit(IF(BRW_PREDICATE_NORMAL
));
198 nir_emit_cf_list(&if_stmt
->then_list
);
200 /* note: if the else is empty, dead CF elimination will remove it */
201 emit(BRW_OPCODE_ELSE
);
203 nir_emit_cf_list(&if_stmt
->else_list
);
205 emit(BRW_OPCODE_ENDIF
);
209 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
213 nir_emit_cf_list(&loop
->body
);
215 emit(BRW_OPCODE_WHILE
);
219 vec4_visitor::nir_emit_block(nir_block
*block
)
221 nir_foreach_instr(block
, instr
) {
222 nir_emit_instr(instr
);
227 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
231 switch (instr
->type
) {
232 case nir_instr_type_load_const
:
233 nir_emit_load_const(nir_instr_as_load_const(instr
));
236 case nir_instr_type_intrinsic
:
237 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
240 case nir_instr_type_alu
:
241 nir_emit_alu(nir_instr_as_alu(instr
));
244 case nir_instr_type_jump
:
245 nir_emit_jump(nir_instr_as_jump(instr
));
248 case nir_instr_type_tex
:
249 nir_emit_texture(nir_instr_as_tex(instr
));
252 case nir_instr_type_ssa_undef
:
253 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
257 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
263 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
264 unsigned base_offset
, nir_src
*indirect
)
268 reg
= v
->nir_locals
[nir_reg
->index
];
269 reg
= offset(reg
, base_offset
);
272 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
280 vec4_visitor::get_nir_dest(nir_dest dest
)
283 dst_reg dst
= dst_reg(GRF
, alloc
.allocate(1));
284 nir_ssa_values
[dest
.ssa
.index
] = dst
;
287 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
293 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
295 return retype(get_nir_dest(dest
), type
);
299 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
301 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
305 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
306 unsigned num_components
)
311 assert(src
.ssa
!= NULL
);
312 reg
= nir_ssa_values
[src
.ssa
->index
];
315 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
319 reg
= retype(reg
, type
);
321 src_reg reg_as_src
= src_reg(reg
);
322 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
327 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
328 unsigned num_components
)
330 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
334 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
336 /* if type is not specified, default to signed int */
337 return get_nir_src(src
, nir_type_int
, num_components
);
341 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
343 dst_reg reg
= dst_reg(GRF
, alloc
.allocate(1));
344 reg
.type
= BRW_REGISTER_TYPE_D
;
346 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
348 /* @FIXME: consider emitting vector operations to save some MOVs in
349 * cases where the components are representable in 8 bits.
350 * For now, we emit a MOV for each distinct value.
352 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
353 unsigned writemask
= 1 << i
;
355 if ((remaining
& writemask
) == 0)
358 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
359 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
364 reg
.writemask
= writemask
;
365 emit(MOV(reg
, src_reg(instr
->value
.i
[i
])));
367 remaining
&= ~writemask
;
370 /* Set final writemask */
371 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
373 nir_ssa_values
[instr
->def
.index
] = reg
;
377 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
382 bool has_indirect
= false;
384 switch (instr
->intrinsic
) {
386 case nir_intrinsic_load_input_indirect
:
389 case nir_intrinsic_load_input
: {
390 int offset
= instr
->const_index
[0];
391 src
= nir_inputs
[offset
];
394 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[0],
398 dest
= get_nir_dest(instr
->dest
, src
.type
);
399 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
401 emit(MOV(dest
, src
));
405 case nir_intrinsic_store_output_indirect
:
408 case nir_intrinsic_store_output
: {
409 int varying
= instr
->const_index
[0];
411 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
412 instr
->num_components
);
416 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[1],
420 output_reg
[varying
] = dest
;
424 case nir_intrinsic_get_buffer_size
: {
425 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
426 unsigned ubo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
428 src_reg surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
430 dst_reg result_dst
= get_nir_dest(instr
->dest
);
431 vec4_instruction
*inst
= new(mem_ctx
)
432 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
435 inst
->mlen
= 1; /* always at least one */
436 inst
->src
[1] = src_reg(surf_index
);
438 /* MRF for the first parameter */
439 src_reg lod
= src_reg(0);
440 int param_base
= inst
->base_mrf
;
441 int writemask
= WRITEMASK_X
;
442 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
448 case nir_intrinsic_store_ssbo_indirect
:
451 case nir_intrinsic_store_ssbo
: {
452 assert(devinfo
->gen
>= 7);
456 nir_const_value
*const_uniform_block
=
457 nir_src_as_const_value(instr
->src
[1]);
458 if (const_uniform_block
) {
459 unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
460 const_uniform_block
->u
[0];
461 surf_index
= src_reg(index
);
462 brw_mark_surface_used(&prog_data
->base
, index
);
464 surf_index
= src_reg(this, glsl_type::uint_type
);
465 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
466 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
467 surf_index
= emit_uniformize(surf_index
);
469 brw_mark_surface_used(&prog_data
->base
,
470 prog_data
->base
.binding_table
.ubo_start
+
471 nir
->info
.num_ssbos
- 1);
475 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
476 unsigned const_offset_bytes
= 0;
478 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[2], 1)));
480 const_offset_bytes
= instr
->const_index
[0];
481 emit(MOV(dst_reg(offset_reg
), src_reg(const_offset_bytes
)));
485 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
488 unsigned write_mask
= instr
->const_index
[1];
490 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
491 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
492 * typed and untyped messages and across hardware platforms, the
493 * current implementation of the untyped messages will transparently convert
494 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
495 * and enabling only channel X on the SEND instruction.
497 * The above, works well for full vector writes, but not for partial writes
498 * where we want to write some channels and not others, like when we have
499 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
500 * quite restrictive with regards to the channel enables we can configure in
501 * the message descriptor (not all combinations are allowed) we cannot simply
502 * implement these scenarios with a single message while keeping the
503 * aforementioned symmetry in the implementation. For now we de decided that
504 * it is better to keep the symmetry to reduce complexity, so in situations
505 * such as the one described we end up emitting two untyped write messages
506 * (one for xy and another for w).
508 * The code below packs consecutive channels into a single write message,
509 * detects gaps in the vector write and if needed, sends a second message
510 * with the remaining channels. If in the future we decide that we want to
511 * emit a single message at the expense of losing the symmetry in the
512 * implementation we can:
514 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
515 * message payload. In this mode we can write up to 8 offsets and dwords
516 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
517 * and select which of the 8 channels carry data to write by setting the
518 * appropriate writemask in the dst register of the SEND instruction.
519 * It would require to write a new generator opcode specifically for
520 * IvyBridge since we would need to prepare a SIMD8 payload that could
521 * use any channel, not just X.
523 * 2) For Haswell+: Simply send a single write message but set the writemask
524 * on the dst of the SEND instruction to select the channels we want to
525 * write. It would require to modify the current messages to receive
526 * and honor the writemask provided.
528 const vec4_builder bld
= vec4_builder(this).at_end()
529 .annotate(current_annotation
, base_ir
);
531 int swizzle
[4] = { 0, 0, 0, 0};
532 int num_channels
= 0;
533 unsigned skipped_channels
= 0;
534 int num_components
= instr
->num_components
;
535 for (int i
= 0; i
< num_components
; i
++) {
536 /* Check if this channel needs to be written. If so, record the
537 * channel we need to take the data from in the swizzle array
539 int component_mask
= 1 << i
;
540 int write_test
= write_mask
& component_mask
;
542 swizzle
[num_channels
++] = i
;
544 /* If we don't have to write this channel it means we have a gap in the
545 * vector, so write the channels we accumulated until now, if any. Do
546 * the same if this was the last component in the vector.
548 if (!write_test
|| i
== num_components
- 1) {
549 if (num_channels
> 0) {
550 /* We have channels to write, so update the offset we need to
551 * write at to skip the channels we skipped, if any.
553 if (skipped_channels
> 0) {
555 const_offset_bytes
+= 4 * skipped_channels
;
556 offset_reg
= src_reg(const_offset_bytes
);
558 emit(ADD(dst_reg(offset_reg
), offset_reg
,
559 brw_imm_ud(4 * skipped_channels
)));
563 /* Swizzle the data register so we take the data from the channels
564 * we need to write and send the write message. This will write
565 * num_channels consecutive dwords starting at offset.
568 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
569 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
570 1 /* dims */, num_channels
/* size */,
573 /* If we have to do a second write we will have to update the
574 * offset so that we jump over the channels we have just written
577 skipped_channels
= num_channels
;
579 /* Restart the count for the next write message */
583 /* We did not write the current channel, so increase skipped count */
591 case nir_intrinsic_load_ssbo_indirect
:
594 case nir_intrinsic_load_ssbo
: {
595 assert(devinfo
->gen
>= 7);
597 nir_const_value
*const_uniform_block
=
598 nir_src_as_const_value(instr
->src
[0]);
601 if (const_uniform_block
) {
602 unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
603 const_uniform_block
->u
[0];
604 surf_index
= src_reg(index
);
606 brw_mark_surface_used(&prog_data
->base
, index
);
608 surf_index
= src_reg(this, glsl_type::uint_type
);
609 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
610 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
611 surf_index
= emit_uniformize(surf_index
);
613 /* Assume this may touch any UBO. It would be nice to provide
614 * a tighter bound, but the array information is already lowered away.
616 brw_mark_surface_used(&prog_data
->base
,
617 prog_data
->base
.binding_table
.ubo_start
+
618 nir
->info
.num_ssbos
- 1);
621 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
622 unsigned const_offset_bytes
= 0;
624 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[1], 1)));
626 const_offset_bytes
= instr
->const_index
[0];
627 emit(MOV(dst_reg(offset_reg
), src_reg(const_offset_bytes
)));
630 /* Read the vector */
631 const vec4_builder bld
= vec4_builder(this).at_end()
632 .annotate(current_annotation
, base_ir
);
634 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
635 1 /* dims */, 4 /* size*/,
637 dst_reg dest
= get_nir_dest(instr
->dest
);
638 read_result
.type
= dest
.type
;
639 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
640 emit(MOV(dest
, read_result
));
645 case nir_intrinsic_ssbo_atomic_add
:
646 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
648 case nir_intrinsic_ssbo_atomic_min
:
649 if (dest
.type
== BRW_REGISTER_TYPE_D
)
650 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
652 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
654 case nir_intrinsic_ssbo_atomic_max
:
655 if (dest
.type
== BRW_REGISTER_TYPE_D
)
656 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
658 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
660 case nir_intrinsic_ssbo_atomic_and
:
661 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
663 case nir_intrinsic_ssbo_atomic_or
:
664 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
666 case nir_intrinsic_ssbo_atomic_xor
:
667 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
669 case nir_intrinsic_ssbo_atomic_exchange
:
670 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
672 case nir_intrinsic_ssbo_atomic_comp_swap
:
673 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
676 case nir_intrinsic_load_vertex_id
:
677 unreachable("should be lowered by lower_vertex_id()");
679 case nir_intrinsic_load_vertex_id_zero_base
:
680 case nir_intrinsic_load_base_vertex
:
681 case nir_intrinsic_load_instance_id
: {
682 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
683 src_reg val
= src_reg(nir_system_values
[sv
]);
684 assert(val
.file
!= BAD_FILE
);
685 dest
= get_nir_dest(instr
->dest
, val
.type
);
686 emit(MOV(dest
, val
));
690 case nir_intrinsic_load_uniform_indirect
:
693 case nir_intrinsic_load_uniform
: {
694 dest
= get_nir_dest(instr
->dest
);
696 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0]));
697 src
.reg_offset
= instr
->const_index
[1];
700 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
701 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
704 emit(MOV(dest
, src
));
708 case nir_intrinsic_atomic_counter_read
:
709 case nir_intrinsic_atomic_counter_inc
:
710 case nir_intrinsic_atomic_counter_dec
: {
711 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
712 (unsigned) instr
->const_index
[0];
713 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
714 instr
->num_components
);
715 dest
= get_nir_dest(instr
->dest
);
717 switch (instr
->intrinsic
) {
718 case nir_intrinsic_atomic_counter_inc
:
719 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
720 src_reg(), src_reg());
722 case nir_intrinsic_atomic_counter_dec
:
723 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
724 src_reg(), src_reg());
726 case nir_intrinsic_atomic_counter_read
:
727 emit_untyped_surface_read(surf_index
, dest
, offset
);
730 unreachable("Unreachable");
733 brw_mark_surface_used(stage_prog_data
, surf_index
);
737 case nir_intrinsic_load_ubo_indirect
:
740 case nir_intrinsic_load_ubo
: {
741 const uint32_t set
= instr
->const_index
[0];
742 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
745 dest
= get_nir_dest(instr
->dest
);
747 if (const_block_index
) {
748 uint32_t binding
= const_block_index
->u
[0];
750 /* The block index is a constant, so just emit the binding table entry
753 surf_index
= src_reg(stage_prog_data
->bind_map
[set
].index
[binding
]);
755 /* The block index is not a constant. Evaluate the index expression
756 * per-channel and add the base UBO index; we have to select a value
757 * from any live channel.
759 surf_index
= src_reg(this, glsl_type::uint_type
);
760 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
761 instr
->num_components
),
762 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
763 surf_index
= emit_uniformize(surf_index
);
765 /* Assume this may touch any UBO. It would be nice to provide
766 * a tighter bound, but the array information is already lowered away.
768 brw_mark_surface_used(&prog_data
->base
,
769 prog_data
->base
.binding_table
.ubo_start
+
770 nir
->info
.num_ssbos
- 1);
773 unsigned const_offset
= instr
->const_index
[1];
777 offset
= src_reg(const_offset
/ 16);
779 offset
= src_reg(this, glsl_type::uint_type
);
780 emit(SHR(dst_reg(offset
), get_nir_src(instr
->src
[1], nir_type_int
, 1),
784 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
785 packed_consts
.type
= dest
.type
;
787 emit_pull_constant_load_reg(dst_reg(packed_consts
),
790 NULL
, NULL
/* before_block/inst */);
792 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
793 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
794 const_offset
% 16 / 4,
795 const_offset
% 16 / 4,
796 const_offset
% 16 / 4);
798 emit(MOV(dest
, packed_consts
));
802 case nir_intrinsic_memory_barrier
: {
803 const vec4_builder bld
=
804 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
805 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
806 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
812 unreachable("Unknown intrinsic");
817 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
820 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
821 dest
= get_nir_dest(instr
->dest
);
824 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
826 unsigned surf_index
= prog_data
->base
.binding_table
.ubo_start
+
828 surface
= src_reg(surf_index
);
829 brw_mark_surface_used(&prog_data
->base
, surf_index
);
831 surface
= src_reg(this, glsl_type::uint_type
);
832 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
833 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
835 /* Assume this may touch any UBO. This is the same we do for other
836 * UBO/SSBO accesses with non-constant surface.
838 brw_mark_surface_used(&prog_data
->base
,
839 prog_data
->base
.binding_table
.ubo_start
+
840 nir
->info
.num_ssbos
- 1);
843 src_reg offset
= get_nir_src(instr
->src
[1], 1);
844 src_reg data1
= get_nir_src(instr
->src
[2], 1);
846 if (op
== BRW_AOP_CMPWR
)
847 data2
= get_nir_src(instr
->src
[3], 1);
849 /* Emit the actual atomic operation operation */
850 const vec4_builder bld
=
851 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
853 src_reg atomic_result
=
854 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
856 1 /* dims */, 1 /* rsize */,
859 dest
.type
= atomic_result
.type
;
860 bld
.MOV(dest
, atomic_result
);
864 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
866 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
869 static enum brw_conditional_mod
870 brw_conditional_for_nir_comparison(nir_op op
)
876 return BRW_CONDITIONAL_L
;
881 return BRW_CONDITIONAL_GE
;
885 case nir_op_ball_fequal2
:
886 case nir_op_ball_iequal2
:
887 case nir_op_ball_fequal3
:
888 case nir_op_ball_iequal3
:
889 case nir_op_ball_fequal4
:
890 case nir_op_ball_iequal4
:
891 return BRW_CONDITIONAL_Z
;
895 case nir_op_bany_fnequal2
:
896 case nir_op_bany_inequal2
:
897 case nir_op_bany_fnequal3
:
898 case nir_op_bany_inequal3
:
899 case nir_op_bany_fnequal4
:
900 case nir_op_bany_inequal4
:
901 return BRW_CONDITIONAL_NZ
;
904 unreachable("not reached: bad operation for comparison");
909 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
911 vec4_instruction
*inst
;
913 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
914 nir_op_infos
[instr
->op
].output_type
);
915 dst
.writemask
= instr
->dest
.write_mask
;
918 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
919 op
[i
] = get_nir_src(instr
->src
[i
].src
,
920 nir_op_infos
[instr
->op
].input_types
[i
], 4);
921 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
922 op
[i
].abs
= instr
->src
[i
].abs
;
923 op
[i
].negate
= instr
->src
[i
].negate
;
929 inst
= emit(MOV(dst
, op
[0]));
930 inst
->saturate
= instr
->dest
.saturate
;
936 unreachable("not reached: should be handled by lower_vec_to_movs()");
940 inst
= emit(MOV(dst
, op
[0]));
941 inst
->saturate
= instr
->dest
.saturate
;
946 inst
= emit(MOV(dst
, op
[0]));
952 inst
= emit(ADD(dst
, op
[0], op
[1]));
953 inst
->saturate
= instr
->dest
.saturate
;
957 inst
= emit(MUL(dst
, op
[0], op
[1]));
958 inst
->saturate
= instr
->dest
.saturate
;
962 if (devinfo
->gen
< 8) {
963 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
964 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
966 /* For integer multiplication, the MUL uses the low 16 bits of one of
967 * the operands (src0 through SNB, src1 on IVB and later). The MACH
968 * accumulates in the contribution of the upper 16 bits of that
969 * operand. If we can determine that one of the args is in the low
970 * 16 bits, though, we can just emit a single MUL.
972 if (value0
&& value0
->u
[0] < (1 << 16)) {
973 if (devinfo
->gen
< 7)
974 emit(MUL(dst
, op
[0], op
[1]));
976 emit(MUL(dst
, op
[1], op
[0]));
977 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
978 if (devinfo
->gen
< 7)
979 emit(MUL(dst
, op
[1], op
[0]));
981 emit(MUL(dst
, op
[0], op
[1]));
983 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
985 emit(MUL(acc
, op
[0], op
[1]));
986 emit(MACH(dst_null_d(), op
[0], op
[1]));
987 emit(MOV(dst
, src_reg(acc
)));
990 emit(MUL(dst
, op
[0], op
[1]));
995 case nir_op_imul_high
:
996 case nir_op_umul_high
: {
997 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
999 emit(MUL(acc
, op
[0], op
[1]));
1000 emit(MACH(dst
, op
[0], op
[1]));
1005 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1006 inst
->saturate
= instr
->dest
.saturate
;
1010 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1011 inst
->saturate
= instr
->dest
.saturate
;
1015 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1016 inst
->saturate
= instr
->dest
.saturate
;
1020 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1021 inst
->saturate
= instr
->dest
.saturate
;
1025 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1026 inst
->saturate
= instr
->dest
.saturate
;
1031 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1035 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1039 unreachable("not reached: should be handled by ldexp_to_arith()");
1042 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1043 inst
->saturate
= instr
->dest
.saturate
;
1047 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1048 inst
->saturate
= instr
->dest
.saturate
;
1052 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1053 inst
->saturate
= instr
->dest
.saturate
;
1056 case nir_op_uadd_carry
: {
1057 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1059 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1060 emit(MOV(dst
, src_reg(acc
)));
1064 case nir_op_usub_borrow
: {
1065 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1067 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1068 emit(MOV(dst
, src_reg(acc
)));
1073 inst
= emit(RNDZ(dst
, op
[0]));
1074 inst
->saturate
= instr
->dest
.saturate
;
1077 case nir_op_fceil
: {
1078 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1080 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1081 instr
->src
[0].src
.ssa
->num_components
:
1082 instr
->src
[0].src
.reg
.reg
->num_components
);
1084 op
[0].negate
= !op
[0].negate
;
1085 emit(RNDD(dst_reg(tmp
), op
[0]));
1087 inst
= emit(MOV(dst
, tmp
));
1088 inst
->saturate
= instr
->dest
.saturate
;
1093 inst
= emit(RNDD(dst
, op
[0]));
1094 inst
->saturate
= instr
->dest
.saturate
;
1098 inst
= emit(FRC(dst
, op
[0]));
1099 inst
->saturate
= instr
->dest
.saturate
;
1102 case nir_op_fround_even
:
1103 inst
= emit(RNDE(dst
, op
[0]));
1104 inst
->saturate
= instr
->dest
.saturate
;
1110 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1111 inst
->saturate
= instr
->dest
.saturate
;
1117 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1118 inst
->saturate
= instr
->dest
.saturate
;
1122 case nir_op_fddx_coarse
:
1123 case nir_op_fddx_fine
:
1125 case nir_op_fddy_coarse
:
1126 case nir_op_fddy_fine
:
1127 unreachable("derivatives are not valid in vertex shaders");
1139 emit(CMP(dst
, op
[0], op
[1],
1140 brw_conditional_for_nir_comparison(instr
->op
)));
1143 case nir_op_ball_fequal2
:
1144 case nir_op_ball_iequal2
:
1145 case nir_op_ball_fequal3
:
1146 case nir_op_ball_iequal3
:
1147 case nir_op_ball_fequal4
:
1148 case nir_op_ball_iequal4
: {
1149 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1151 switch (instr
->op
) {
1152 case nir_op_ball_fequal2
:
1153 case nir_op_ball_iequal2
:
1154 tmp
.writemask
= WRITEMASK_XY
;
1156 case nir_op_ball_fequal3
:
1157 case nir_op_ball_iequal3
:
1158 tmp
.writemask
= WRITEMASK_XYZ
;
1160 case nir_op_ball_fequal4
:
1161 case nir_op_ball_iequal4
:
1162 tmp
.writemask
= WRITEMASK_XYZW
;
1165 unreachable("not reached");
1168 emit(CMP(tmp
, op
[0], op
[1],
1169 brw_conditional_for_nir_comparison(instr
->op
)));
1170 emit(MOV(dst
, src_reg(0)));
1171 inst
= emit(MOV(dst
, src_reg(~0)));
1172 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1176 case nir_op_bany_fnequal2
:
1177 case nir_op_bany_inequal2
:
1178 case nir_op_bany_fnequal3
:
1179 case nir_op_bany_inequal3
:
1180 case nir_op_bany_fnequal4
:
1181 case nir_op_bany_inequal4
: {
1182 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1184 switch (instr
->op
) {
1185 case nir_op_bany_fnequal2
:
1186 case nir_op_bany_inequal2
:
1187 tmp
.writemask
= WRITEMASK_XY
;
1189 case nir_op_bany_fnequal3
:
1190 case nir_op_bany_inequal3
:
1191 tmp
.writemask
= WRITEMASK_XYZ
;
1193 case nir_op_bany_fnequal4
:
1194 case nir_op_bany_inequal4
:
1195 tmp
.writemask
= WRITEMASK_XYZW
;
1198 unreachable("not reached");
1201 emit(CMP(tmp
, op
[0], op
[1],
1202 brw_conditional_for_nir_comparison(instr
->op
)));
1204 emit(MOV(dst
, src_reg(0)));
1205 inst
= emit(MOV(dst
, src_reg(~0)));
1206 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1211 if (devinfo
->gen
>= 8) {
1212 op
[0] = resolve_source_modifiers(op
[0]);
1214 emit(NOT(dst
, op
[0]));
1218 if (devinfo
->gen
>= 8) {
1219 op
[0] = resolve_source_modifiers(op
[0]);
1220 op
[1] = resolve_source_modifiers(op
[1]);
1222 emit(XOR(dst
, op
[0], op
[1]));
1226 if (devinfo
->gen
>= 8) {
1227 op
[0] = resolve_source_modifiers(op
[0]);
1228 op
[1] = resolve_source_modifiers(op
[1]);
1230 emit(OR(dst
, op
[0], op
[1]));
1234 if (devinfo
->gen
>= 8) {
1235 op
[0] = resolve_source_modifiers(op
[0]);
1236 op
[1] = resolve_source_modifiers(op
[1]);
1238 emit(AND(dst
, op
[0], op
[1]));
1242 emit(AND(dst
, op
[0], src_reg(1)));
1246 op
[0].type
= BRW_REGISTER_TYPE_D
;
1247 dst
.type
= BRW_REGISTER_TYPE_D
;
1248 emit(AND(dst
, op
[0], src_reg(0x3f800000u
)));
1249 dst
.type
= BRW_REGISTER_TYPE_F
;
1253 emit(CMP(dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1257 emit(CMP(dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1260 case nir_op_fnoise1_1
:
1261 case nir_op_fnoise1_2
:
1262 case nir_op_fnoise1_3
:
1263 case nir_op_fnoise1_4
:
1264 case nir_op_fnoise2_1
:
1265 case nir_op_fnoise2_2
:
1266 case nir_op_fnoise2_3
:
1267 case nir_op_fnoise2_4
:
1268 case nir_op_fnoise3_1
:
1269 case nir_op_fnoise3_2
:
1270 case nir_op_fnoise3_3
:
1271 case nir_op_fnoise3_4
:
1272 case nir_op_fnoise4_1
:
1273 case nir_op_fnoise4_2
:
1274 case nir_op_fnoise4_3
:
1275 case nir_op_fnoise4_4
:
1276 unreachable("not reached: should be handled by lower_noise");
1278 case nir_op_unpack_half_2x16_split_x
:
1279 case nir_op_unpack_half_2x16_split_y
:
1280 case nir_op_pack_half_2x16_split
:
1281 unreachable("not reached: should not occur in vertex shader");
1283 case nir_op_unpack_snorm_2x16
:
1284 case nir_op_unpack_unorm_2x16
:
1285 case nir_op_pack_snorm_2x16
:
1286 case nir_op_pack_unorm_2x16
:
1287 unreachable("not reached: should be handled by lower_packing_builtins");
1289 case nir_op_unpack_half_2x16
:
1290 /* As NIR does not guarantee that we have a correct swizzle outside the
1291 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1292 * uses the source operand in an operation with WRITEMASK_Y while our
1293 * source operand has only size 1, it accessed incorrect data producing
1294 * regressions in Piglit. We repeat the swizzle of the first component on the
1295 * rest of components to avoid regressions. In the vec4_visitor IR code path
1296 * this is not needed because the operand has already the correct swizzle.
1298 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1299 emit_unpack_half_2x16(dst
, op
[0]);
1302 case nir_op_pack_half_2x16
:
1303 emit_pack_half_2x16(dst
, op
[0]);
1306 case nir_op_unpack_unorm_4x8
:
1307 emit_unpack_unorm_4x8(dst
, op
[0]);
1310 case nir_op_pack_unorm_4x8
:
1311 emit_pack_unorm_4x8(dst
, op
[0]);
1314 case nir_op_unpack_snorm_4x8
:
1315 emit_unpack_snorm_4x8(dst
, op
[0]);
1318 case nir_op_pack_snorm_4x8
:
1319 emit_pack_snorm_4x8(dst
, op
[0]);
1322 case nir_op_bitfield_reverse
:
1323 emit(BFREV(dst
, op
[0]));
1326 case nir_op_bit_count
:
1327 emit(CBIT(dst
, op
[0]));
1330 case nir_op_ufind_msb
:
1331 case nir_op_ifind_msb
: {
1332 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1334 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1335 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1337 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1338 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1339 * subtract the result from 31 to convert the MSB count into an LSB count.
1342 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1343 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1344 emit(MOV(dst
, temp
));
1346 src_reg src_tmp
= src_reg(dst
);
1347 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1349 src_tmp
.negate
= true;
1350 inst
= emit(ADD(dst
, src_tmp
, src_reg(31)));
1351 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1355 case nir_op_find_lsb
:
1356 emit(FBL(dst
, op
[0]));
1359 case nir_op_ubitfield_extract
:
1360 case nir_op_ibitfield_extract
:
1361 op
[0] = fix_3src_operand(op
[0]);
1362 op
[1] = fix_3src_operand(op
[1]);
1363 op
[2] = fix_3src_operand(op
[2]);
1365 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1369 emit(BFI1(dst
, op
[0], op
[1]));
1373 op
[0] = fix_3src_operand(op
[0]);
1374 op
[1] = fix_3src_operand(op
[1]);
1375 op
[2] = fix_3src_operand(op
[2]);
1377 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1380 case nir_op_bitfield_insert
:
1381 unreachable("not reached: should be handled by "
1382 "lower_instructions::bitfield_insert_to_bfm_bfi");
1385 /* AND(val, 0x80000000) gives the sign bit.
1387 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1390 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1392 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1393 dst
.type
= BRW_REGISTER_TYPE_UD
;
1394 emit(AND(dst
, op
[0], src_reg(0x80000000u
)));
1396 inst
= emit(OR(dst
, src_reg(dst
), src_reg(0x3f800000u
)));
1397 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1398 dst
.type
= BRW_REGISTER_TYPE_F
;
1400 if (instr
->dest
.saturate
) {
1401 inst
= emit(MOV(dst
, src_reg(dst
)));
1402 inst
->saturate
= true;
1407 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1408 * -> non-negative val generates 0x00000000.
1409 * Predicated OR sets 1 if val is positive.
1411 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1412 emit(ASR(dst
, op
[0], src_reg(31)));
1413 inst
= emit(OR(dst
, src_reg(dst
), src_reg(1)));
1414 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1418 emit(SHL(dst
, op
[0], op
[1]));
1422 emit(ASR(dst
, op
[0], op
[1]));
1426 emit(SHR(dst
, op
[0], op
[1]));
1430 op
[0] = fix_3src_operand(op
[0]);
1431 op
[1] = fix_3src_operand(op
[1]);
1432 op
[2] = fix_3src_operand(op
[2]);
1434 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1435 inst
->saturate
= instr
->dest
.saturate
;
1439 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1440 inst
->saturate
= instr
->dest
.saturate
;
1444 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1445 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1446 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1449 case nir_op_fdot_replicated2
:
1450 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1451 inst
->saturate
= instr
->dest
.saturate
;
1454 case nir_op_fdot_replicated3
:
1455 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1456 inst
->saturate
= instr
->dest
.saturate
;
1459 case nir_op_fdot_replicated4
:
1460 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1461 inst
->saturate
= instr
->dest
.saturate
;
1464 case nir_op_fdph_replicated
:
1465 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1466 inst
->saturate
= instr
->dest
.saturate
;
1471 case nir_op_bany4
: {
1472 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1473 tmp
.writemask
= brw_writemask_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1475 emit(CMP(tmp
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1477 emit(MOV(dst
, src_reg(0)));
1478 inst
= emit(MOV(dst
, src_reg(~0)));
1479 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1488 unreachable("not reached: should be lowered by lower_source mods");
1491 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1494 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1498 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1501 unreachable("Unimplemented ALU operation");
1504 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1505 * to sign extend the low bit to 0/~0
1507 if (devinfo
->gen
<= 5 &&
1508 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1509 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1510 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1511 masked
.writemask
= dst
.writemask
;
1512 emit(AND(masked
, src_reg(dst
), src_reg(1)));
1513 src_reg masked_neg
= src_reg(masked
);
1514 masked_neg
.negate
= true;
1515 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1520 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1522 switch (instr
->type
) {
1523 case nir_jump_break
:
1524 emit(BRW_OPCODE_BREAK
);
1527 case nir_jump_continue
:
1528 emit(BRW_OPCODE_CONTINUE
);
1531 case nir_jump_return
:
1534 unreachable("unknown jump");
1538 enum ir_texture_opcode
1539 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1541 enum ir_texture_opcode op
;
1544 case nir_texop_lod
: op
= ir_lod
; break;
1545 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1546 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1547 case nir_texop_tex
: op
= ir_tex
; break;
1548 case nir_texop_tg4
: op
= ir_tg4
; break;
1549 case nir_texop_txb
: op
= ir_txb
; break;
1550 case nir_texop_txd
: op
= ir_txd
; break;
1551 case nir_texop_txf
: op
= ir_txf
; break;
1552 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1553 case nir_texop_txl
: op
= ir_txl
; break;
1554 case nir_texop_txs
: op
= ir_txs
; break;
1556 unreachable("unknown texture opcode");
1562 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1563 unsigned components
)
1566 case nir_type_float
:
1567 return glsl_type::vec(components
);
1569 return glsl_type::ivec(components
);
1570 case nir_type_unsigned
:
1571 return glsl_type::uvec(components
);
1573 return glsl_type::bvec(components
);
1575 return glsl_type::error_type
;
1578 return glsl_type::error_type
;
1582 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1584 unsigned sampler
= instr
->sampler_index
;
1585 src_reg sampler_reg
= src_reg(sampler
);
1587 const glsl_type
*coord_type
= NULL
;
1588 src_reg shadow_comparitor
;
1589 src_reg offset_value
;
1591 src_reg sample_index
;
1594 const glsl_type
*dest_type
=
1595 glsl_type_for_nir_alu_type(instr
->dest_type
,
1596 nir_tex_instr_dest_size(instr
));
1597 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1599 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1600 * emitting anything other than setting up the constant result.
1602 if (instr
->op
== nir_texop_tg4
) {
1603 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], instr
->component
);
1604 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1605 emit(MOV(dest
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
1610 /* Load the texture operation sources */
1611 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1612 switch (instr
->src
[i
].src_type
) {
1613 case nir_tex_src_comparitor
:
1614 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1615 BRW_REGISTER_TYPE_F
, 1);
1618 case nir_tex_src_coord
: {
1619 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1621 switch (instr
->op
) {
1623 case nir_texop_txf_ms
:
1624 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1626 coord_type
= glsl_type::ivec(src_size
);
1630 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1632 coord_type
= glsl_type::vec(src_size
);
1638 case nir_tex_src_ddx
:
1639 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1640 nir_tex_instr_src_size(instr
, i
));
1643 case nir_tex_src_ddy
:
1644 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1645 nir_tex_instr_src_size(instr
, i
));
1648 case nir_tex_src_lod
:
1649 switch (instr
->op
) {
1652 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1656 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1661 case nir_tex_src_ms_index
: {
1662 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1663 assert(coord_type
!= NULL
);
1664 if (devinfo
->gen
>= 7 &&
1665 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1666 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1670 mcs
= retype(mcs
, BRW_REGISTER_TYPE_UD
);
1674 case nir_tex_src_offset
:
1675 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1678 case nir_tex_src_sampler_offset
: {
1679 /* The highest sampler which may be used by this operation is
1680 * the last element of the array. Mark it here, because the generator
1681 * doesn't have enough information to determine the bound.
1683 uint32_t array_size
= instr
->sampler_array_size
;
1684 uint32_t max_used
= sampler
+ array_size
- 1;
1685 if (instr
->op
== nir_texop_tg4
) {
1686 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1688 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1691 brw_mark_surface_used(&prog_data
->base
, max_used
);
1693 /* Emit code to evaluate the actual indexing expression */
1694 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1695 src_reg
temp(this, glsl_type::uint_type
);
1696 emit(ADD(dst_reg(temp
), src
, src_reg(sampler
)));
1697 sampler_reg
= emit_uniformize(temp
);
1701 case nir_tex_src_projector
:
1702 unreachable("Should be lowered by do_lower_texture_projection");
1704 case nir_tex_src_bias
:
1705 unreachable("LOD bias is not valid for vertex shaders.\n");
1708 unreachable("unknown texture source");
1712 uint32_t constant_offset
= 0;
1713 for (unsigned i
= 0; i
< 3; i
++) {
1714 if (instr
->const_offset
[i
] != 0) {
1715 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1720 /* Stuff the channel select bits in the top of the texture offset */
1721 if (instr
->op
== nir_texop_tg4
)
1722 constant_offset
|= gather_channel(instr
->component
, sampler
) << 16;
1724 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1726 bool is_cube_array
=
1727 instr
->op
== nir_texop_txs
&&
1728 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1731 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1733 lod
, lod2
, sample_index
,
1734 constant_offset
, offset_value
,
1735 mcs
, is_cube_array
, sampler
, sampler_reg
);
1739 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1741 nir_ssa_values
[instr
->def
.index
] = dst_reg(GRF
, alloc
.allocate(1));