2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
31 vec4_visitor::emit_nir_code()
33 nir_shader
*nir
= prog
->nir
;
35 if (nir
->num_inputs
> 0)
36 nir_setup_inputs(nir
);
38 if (nir
->num_uniforms
> 0)
39 nir_setup_uniforms(nir
);
41 nir_setup_system_values(nir
);
43 /* get the main function and emit it */
44 nir_foreach_overload(nir
, overload
) {
45 assert(strcmp(overload
->function
->name
, "main") == 0);
46 assert(overload
->impl
);
47 nir_emit_impl(overload
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &this->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
64 *this->make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
68 case nir_intrinsic_load_base_vertex
:
69 reg
= &this->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
70 if (reg
->file
== BAD_FILE
)
71 *reg
= *this->make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
75 case nir_intrinsic_load_instance_id
:
76 reg
= &this->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
77 if (reg
->file
== BAD_FILE
)
78 *reg
= *this->make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
88 setup_system_values_block(nir_block
*block
, void *void_visitor
)
90 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
92 nir_foreach_instr(block
, instr
) {
93 if (instr
->type
!= nir_instr_type_intrinsic
)
96 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
97 v
->nir_setup_system_value_intrinsic(intrin
);
104 vec4_visitor::nir_setup_system_values(nir_shader
*shader
)
106 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
108 nir_foreach_overload(shader
, overload
) {
109 assert(strcmp(overload
->function
->name
, "main") == 0);
110 assert(overload
->impl
);
111 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
116 vec4_visitor::nir_setup_inputs(nir_shader
*shader
)
118 nir_inputs
= ralloc_array(mem_ctx
, src_reg
, shader
->num_inputs
);
120 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
121 int offset
= var
->data
.driver_location
;
122 unsigned size
= type_size_vec4(var
->type
);
123 for (unsigned i
= 0; i
< size
; i
++) {
124 src_reg src
= src_reg(ATTR
, var
->data
.location
+ i
, var
->type
);
125 nir_inputs
[offset
+ i
] = src
;
131 vec4_visitor::nir_setup_uniforms(nir_shader
*shader
)
135 nir_uniform_driver_location
=
136 rzalloc_array(mem_ctx
, unsigned, this->uniform_array_size
);
139 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
140 /* UBO's, atomics and samplers don't take up space in the
142 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic() ||
143 type_size_vec4(var
->type
) == 0) {
147 assert(uniforms
< uniform_array_size
);
148 this->uniform_size
[uniforms
] = type_size_vec4(var
->type
);
150 if (strncmp(var
->name
, "gl_", 3) == 0)
151 nir_setup_builtin_uniform(var
);
153 nir_setup_uniform(var
);
156 /* For ARB_vertex_program, only a single "parameters" variable is
157 * generated to support uniform data.
159 nir_variable
*var
= (nir_variable
*) shader
->uniforms
.get_head();
160 assert(shader
->uniforms
.length() == 1 &&
161 strcmp(var
->name
, "parameters") == 0);
163 assert(uniforms
< uniform_array_size
);
164 this->uniform_size
[uniforms
] = type_size_vec4(var
->type
);
166 struct gl_program_parameter_list
*plist
= prog
->Parameters
;
167 for (unsigned p
= 0; p
< plist
->NumParameters
; p
++) {
168 uniform_vector_size
[uniforms
] = plist
->Parameters
[p
].Size
;
170 /* Parameters should be either vec4 uniforms or single component
171 * constants; matrices and other larger types should have been broken
174 assert(uniform_vector_size
[uniforms
] <= 4);
177 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
178 stage_prog_data
->param
[uniforms
* 4 + i
] = &plist
->ParameterValues
[p
][i
];
181 static const gl_constant_value zero
= { 0.0 };
182 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
185 nir_uniform_driver_location
[uniforms
] = var
->data
.driver_location
;
192 vec4_visitor::nir_setup_uniform(nir_variable
*var
)
194 int namelen
= strlen(var
->name
);
196 /* The data for our (non-builtin) uniforms is stored in a series of
197 * gl_uniform_driver_storage structs for each subcomponent that
198 * glGetUniformLocation() could name. We know it's been set up in the same
199 * order we'd walk the type, so walk the list of storage and find anything
200 * with our name, or the prefix of a component that starts with our name.
202 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
203 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
205 if (storage
->builtin
)
208 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
209 (storage
->name
[namelen
] != 0 &&
210 storage
->name
[namelen
] != '.' &&
211 storage
->name
[namelen
] != '[')) {
215 gl_constant_value
*components
= storage
->storage
;
216 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
217 storage
->type
->matrix_columns
);
219 for (unsigned s
= 0; s
< vector_count
; s
++) {
220 assert(uniforms
< uniform_array_size
);
221 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
224 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
225 stage_prog_data
->param
[uniforms
* 4 + i
] = components
;
229 static const gl_constant_value zero
= { 0.0 };
230 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
233 nir_uniform_driver_location
[uniforms
] = var
->data
.driver_location
;
240 vec4_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
242 const nir_state_slot
*const slots
= var
->state_slots
;
243 assert(var
->state_slots
!= NULL
);
245 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
246 /* This state reference has already been setup by ir_to_mesa,
247 * but we'll get the same index back here. We can reference
248 * ParameterValues directly, since unlike brw_fs.cpp, we never
249 * add new state references during compile.
251 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
252 (gl_state_index
*)slots
[i
].tokens
);
253 gl_constant_value
*values
=
254 &this->prog
->Parameters
->ParameterValues
[index
][0];
256 assert(uniforms
< uniform_array_size
);
258 for (unsigned j
= 0; j
< 4; j
++)
259 stage_prog_data
->param
[uniforms
* 4 + j
] =
260 &values
[GET_SWZ(slots
[i
].swizzle
, j
)];
262 this->uniform_vector_size
[uniforms
] =
263 (var
->type
->is_scalar() || var
->type
->is_vector() ||
264 var
->type
->is_matrix() ? var
->type
->vector_elements
: 4);
266 nir_uniform_driver_location
[uniforms
] = var
->data
.driver_location
;
272 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
274 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
276 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
277 unsigned array_elems
=
278 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
280 nir_locals
[reg
->index
] = dst_reg(GRF
, alloc
.allocate(array_elems
));
283 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
285 nir_emit_cf_list(&impl
->body
);
289 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
291 exec_list_validate(list
);
292 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
293 switch (node
->type
) {
295 nir_emit_if(nir_cf_node_as_if(node
));
298 case nir_cf_node_loop
:
299 nir_emit_loop(nir_cf_node_as_loop(node
));
302 case nir_cf_node_block
:
303 nir_emit_block(nir_cf_node_as_block(node
));
307 unreachable("Invalid CFG node block");
313 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
315 /* First, put the condition in f0 */
316 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
317 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
318 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
320 emit(IF(BRW_PREDICATE_NORMAL
));
322 nir_emit_cf_list(&if_stmt
->then_list
);
324 /* note: if the else is empty, dead CF elimination will remove it */
325 emit(BRW_OPCODE_ELSE
);
327 nir_emit_cf_list(&if_stmt
->else_list
);
329 emit(BRW_OPCODE_ENDIF
);
333 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
337 nir_emit_cf_list(&loop
->body
);
339 emit(BRW_OPCODE_WHILE
);
343 vec4_visitor::nir_emit_block(nir_block
*block
)
345 nir_foreach_instr(block
, instr
) {
346 nir_emit_instr(instr
);
351 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
353 this->base_ir
= instr
;
355 switch (instr
->type
) {
356 case nir_instr_type_load_const
:
357 nir_emit_load_const(nir_instr_as_load_const(instr
));
360 case nir_instr_type_intrinsic
:
361 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
364 case nir_instr_type_alu
:
365 nir_emit_alu(nir_instr_as_alu(instr
));
368 case nir_instr_type_jump
:
369 nir_emit_jump(nir_instr_as_jump(instr
));
372 case nir_instr_type_tex
:
373 nir_emit_texture(nir_instr_as_tex(instr
));
377 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
383 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
384 unsigned base_offset
, nir_src
*indirect
)
388 reg
= v
->nir_locals
[nir_reg
->index
];
389 reg
= offset(reg
, base_offset
);
392 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
400 vec4_visitor::get_nir_dest(nir_dest dest
)
402 assert(!dest
.is_ssa
);
403 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
408 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
410 return retype(get_nir_dest(dest
), type
);
414 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
416 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
420 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
421 unsigned num_components
)
426 assert(src
.ssa
!= NULL
);
427 reg
= nir_ssa_values
[src
.ssa
->index
];
430 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
434 reg
= retype(reg
, type
);
436 src_reg reg_as_src
= src_reg(reg
);
437 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
442 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
443 unsigned num_components
)
445 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
449 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
451 /* if type is not specified, default to signed int */
452 return get_nir_src(src
, nir_type_int
, num_components
);
456 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
458 dst_reg reg
= dst_reg(GRF
, alloc
.allocate(1));
459 reg
.type
= BRW_REGISTER_TYPE_F
;
461 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
463 /* @FIXME: consider emitting vector operations to save some MOVs in
464 * cases where the components are representable in 8 bits.
465 * For now, we emit a MOV for each distinct value.
467 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
468 unsigned writemask
= 1 << i
;
470 if ((remaining
& writemask
) == 0)
473 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
474 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
479 reg
.writemask
= writemask
;
480 emit(MOV(reg
, src_reg(instr
->value
.f
[i
])));
482 remaining
&= ~writemask
;
485 /* Set final writemask */
486 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
488 nir_ssa_values
[instr
->def
.index
] = reg
;
492 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
497 bool has_indirect
= false;
499 switch (instr
->intrinsic
) {
501 case nir_intrinsic_load_input_indirect
:
504 case nir_intrinsic_load_input
: {
505 int offset
= instr
->const_index
[0];
506 src
= nir_inputs
[offset
];
509 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[0],
513 dest
= get_nir_dest(instr
->dest
, src
.type
);
514 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
516 emit(MOV(dest
, src
));
520 case nir_intrinsic_store_output_indirect
:
523 case nir_intrinsic_store_output
: {
524 int varying
= instr
->const_index
[0];
526 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
527 instr
->num_components
);
531 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[1],
535 output_reg
[varying
] = dest
;
539 case nir_intrinsic_load_vertex_id
:
540 unreachable("should be lowered by lower_vertex_id()");
542 case nir_intrinsic_load_vertex_id_zero_base
: {
544 src_reg(nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
]);
545 assert(vertex_id
.file
!= BAD_FILE
);
546 dest
= get_nir_dest(instr
->dest
, vertex_id
.type
);
547 emit(MOV(dest
, vertex_id
));
551 case nir_intrinsic_load_base_vertex
: {
552 src_reg base_vertex
=
553 src_reg(nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
]);
554 assert(base_vertex
.file
!= BAD_FILE
);
555 dest
= get_nir_dest(instr
->dest
, base_vertex
.type
);
556 emit(MOV(dest
, base_vertex
));
560 case nir_intrinsic_load_instance_id
: {
561 src_reg instance_id
=
562 src_reg(nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
]);
563 assert(instance_id
.file
!= BAD_FILE
);
564 dest
= get_nir_dest(instr
->dest
, instance_id
.type
);
565 emit(MOV(dest
, instance_id
));
569 case nir_intrinsic_load_uniform_indirect
:
572 case nir_intrinsic_load_uniform
: {
573 int uniform
= instr
->const_index
[0] + instr
->const_index
[1];
575 dest
= get_nir_dest(instr
->dest
);
578 /* Split addressing into uniform and offset */
579 int offset
= uniform
- nir_uniform_driver_location
[uniform
];
583 assert(uniform
>= 0);
585 src
= src_reg(dst_reg(UNIFORM
, uniform
));
586 src
.reg_offset
= offset
;
587 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
588 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
590 src
= src_reg(dst_reg(UNIFORM
, uniform
));
593 emit(MOV(dest
, src
));
597 case nir_intrinsic_atomic_counter_read
:
598 case nir_intrinsic_atomic_counter_inc
:
599 case nir_intrinsic_atomic_counter_dec
: {
600 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
601 (unsigned) instr
->const_index
[0];
602 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
603 instr
->num_components
);
604 dest
= get_nir_dest(instr
->dest
);
606 switch (instr
->intrinsic
) {
607 case nir_intrinsic_atomic_counter_inc
:
608 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
609 src_reg(), src_reg());
611 case nir_intrinsic_atomic_counter_dec
:
612 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
613 src_reg(), src_reg());
615 case nir_intrinsic_atomic_counter_read
:
616 emit_untyped_surface_read(surf_index
, dest
, offset
);
619 unreachable("Unreachable");
622 brw_mark_surface_used(stage_prog_data
, surf_index
);
626 case nir_intrinsic_load_ubo_indirect
:
629 case nir_intrinsic_load_ubo
: {
630 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
633 dest
= get_nir_dest(instr
->dest
);
635 if (const_block_index
) {
636 /* The block index is a constant, so just emit the binding table entry
639 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
640 const_block_index
->u
[0]);
642 /* The block index is not a constant. Evaluate the index expression
643 * per-channel and add the base UBO index; we have to select a value
644 * from any live channel.
646 surf_index
= src_reg(this, glsl_type::uint_type
);
647 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
648 instr
->num_components
),
649 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
650 surf_index
= emit_uniformize(surf_index
);
652 /* Assume this may touch any UBO. It would be nice to provide
653 * a tighter bound, but the array information is already lowered away.
655 brw_mark_surface_used(&prog_data
->base
,
656 prog_data
->base
.binding_table
.ubo_start
+
657 shader_prog
->NumUniformBlocks
- 1);
660 unsigned const_offset
= instr
->const_index
[0];
664 offset
= src_reg(const_offset
/ 16);
666 offset
= src_reg(this, glsl_type::uint_type
);
667 emit(SHR(dst_reg(offset
), get_nir_src(instr
->src
[1], nir_type_int
, 1),
671 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
672 packed_consts
.type
= dest
.type
;
674 emit_pull_constant_load_reg(dst_reg(packed_consts
),
677 NULL
, NULL
/* before_block/inst */);
679 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
680 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
681 const_offset
% 16 / 4,
682 const_offset
% 16 / 4,
683 const_offset
% 16 / 4);
685 emit(MOV(dest
, packed_consts
));
690 unreachable("Unknown intrinsic");
695 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
697 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
700 static enum brw_conditional_mod
701 brw_conditional_for_nir_comparison(nir_op op
)
707 return BRW_CONDITIONAL_L
;
712 return BRW_CONDITIONAL_GE
;
716 case nir_op_ball_fequal2
:
717 case nir_op_ball_iequal2
:
718 case nir_op_ball_fequal3
:
719 case nir_op_ball_iequal3
:
720 case nir_op_ball_fequal4
:
721 case nir_op_ball_iequal4
:
722 return BRW_CONDITIONAL_Z
;
726 case nir_op_bany_fnequal2
:
727 case nir_op_bany_inequal2
:
728 case nir_op_bany_fnequal3
:
729 case nir_op_bany_inequal3
:
730 case nir_op_bany_fnequal4
:
731 case nir_op_bany_inequal4
:
732 return BRW_CONDITIONAL_NZ
;
735 unreachable("not reached: bad operation for comparison");
740 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
742 vec4_instruction
*inst
;
744 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
745 nir_op_infos
[instr
->op
].output_type
);
746 dst
.writemask
= instr
->dest
.write_mask
;
749 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
750 op
[i
] = get_nir_src(instr
->src
[i
].src
,
751 nir_op_infos
[instr
->op
].input_types
[i
], 4);
752 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
753 op
[i
].abs
= instr
->src
[i
].abs
;
754 op
[i
].negate
= instr
->src
[i
].negate
;
760 inst
= emit(MOV(dst
, op
[0]));
761 inst
->saturate
= instr
->dest
.saturate
;
767 unreachable("not reached: should be handled by lower_vec_to_movs()");
771 inst
= emit(MOV(dst
, op
[0]));
772 inst
->saturate
= instr
->dest
.saturate
;
777 inst
= emit(MOV(dst
, op
[0]));
783 inst
= emit(ADD(dst
, op
[0], op
[1]));
784 inst
->saturate
= instr
->dest
.saturate
;
788 inst
= emit(MUL(dst
, op
[0], op
[1]));
789 inst
->saturate
= instr
->dest
.saturate
;
793 if (devinfo
->gen
< 8) {
794 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
795 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
797 /* For integer multiplication, the MUL uses the low 16 bits of one of
798 * the operands (src0 through SNB, src1 on IVB and later). The MACH
799 * accumulates in the contribution of the upper 16 bits of that
800 * operand. If we can determine that one of the args is in the low
801 * 16 bits, though, we can just emit a single MUL.
803 if (value0
&& value0
->u
[0] < (1 << 16)) {
804 if (devinfo
->gen
< 7)
805 emit(MUL(dst
, op
[0], op
[1]));
807 emit(MUL(dst
, op
[1], op
[0]));
808 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
809 if (devinfo
->gen
< 7)
810 emit(MUL(dst
, op
[1], op
[0]));
812 emit(MUL(dst
, op
[0], op
[1]));
814 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
816 emit(MUL(acc
, op
[0], op
[1]));
817 emit(MACH(dst_null_d(), op
[0], op
[1]));
818 emit(MOV(dst
, src_reg(acc
)));
821 emit(MUL(dst
, op
[0], op
[1]));
826 case nir_op_imul_high
:
827 case nir_op_umul_high
: {
828 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
830 emit(MUL(acc
, op
[0], op
[1]));
831 emit(MACH(dst
, op
[0], op
[1]));
836 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
837 inst
->saturate
= instr
->dest
.saturate
;
841 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
842 inst
->saturate
= instr
->dest
.saturate
;
846 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
847 inst
->saturate
= instr
->dest
.saturate
;
851 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
852 inst
->saturate
= instr
->dest
.saturate
;
856 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
857 inst
->saturate
= instr
->dest
.saturate
;
862 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
866 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
870 unreachable("not reached: should be handled by ldexp_to_arith()");
873 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
874 inst
->saturate
= instr
->dest
.saturate
;
878 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
879 inst
->saturate
= instr
->dest
.saturate
;
883 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
884 inst
->saturate
= instr
->dest
.saturate
;
887 case nir_op_uadd_carry
: {
888 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
890 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
891 emit(MOV(dst
, src_reg(acc
)));
895 case nir_op_usub_borrow
: {
896 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
898 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
899 emit(MOV(dst
, src_reg(acc
)));
904 inst
= emit(RNDZ(dst
, op
[0]));
905 inst
->saturate
= instr
->dest
.saturate
;
909 src_reg tmp
= src_reg(this, glsl_type::float_type
);
911 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
912 instr
->src
[0].src
.ssa
->num_components
:
913 instr
->src
[0].src
.reg
.reg
->num_components
);
915 op
[0].negate
= !op
[0].negate
;
916 emit(RNDD(dst_reg(tmp
), op
[0]));
918 inst
= emit(MOV(dst
, tmp
));
919 inst
->saturate
= instr
->dest
.saturate
;
924 inst
= emit(RNDD(dst
, op
[0]));
925 inst
->saturate
= instr
->dest
.saturate
;
929 inst
= emit(FRC(dst
, op
[0]));
930 inst
->saturate
= instr
->dest
.saturate
;
933 case nir_op_fround_even
:
934 inst
= emit(RNDE(dst
, op
[0]));
935 inst
->saturate
= instr
->dest
.saturate
;
941 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
942 inst
->saturate
= instr
->dest
.saturate
;
948 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
949 inst
->saturate
= instr
->dest
.saturate
;
953 case nir_op_fddx_coarse
:
954 case nir_op_fddx_fine
:
956 case nir_op_fddy_coarse
:
957 case nir_op_fddy_fine
:
958 unreachable("derivatives are not valid in vertex shaders");
970 emit(CMP(dst
, op
[0], op
[1],
971 brw_conditional_for_nir_comparison(instr
->op
)));
974 case nir_op_ball_fequal2
:
975 case nir_op_ball_iequal2
:
976 case nir_op_ball_fequal3
:
977 case nir_op_ball_iequal3
:
978 case nir_op_ball_fequal4
:
979 case nir_op_ball_iequal4
: {
980 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
983 case nir_op_ball_fequal2
:
984 case nir_op_ball_iequal2
:
985 tmp
.writemask
= WRITEMASK_XY
;
987 case nir_op_ball_fequal3
:
988 case nir_op_ball_iequal3
:
989 tmp
.writemask
= WRITEMASK_XYZ
;
991 case nir_op_ball_fequal4
:
992 case nir_op_ball_iequal4
:
993 tmp
.writemask
= WRITEMASK_XYZW
;
996 unreachable("not reached");
999 emit(CMP(tmp
, op
[0], op
[1],
1000 brw_conditional_for_nir_comparison(instr
->op
)));
1001 emit(MOV(dst
, src_reg(0)));
1002 inst
= emit(MOV(dst
, src_reg(~0)));
1003 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1007 case nir_op_bany_fnequal2
:
1008 case nir_op_bany_inequal2
:
1009 case nir_op_bany_fnequal3
:
1010 case nir_op_bany_inequal3
:
1011 case nir_op_bany_fnequal4
:
1012 case nir_op_bany_inequal4
: {
1013 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1015 switch (instr
->op
) {
1016 case nir_op_bany_fnequal2
:
1017 case nir_op_bany_inequal2
:
1018 tmp
.writemask
= WRITEMASK_XY
;
1020 case nir_op_bany_fnequal3
:
1021 case nir_op_bany_inequal3
:
1022 tmp
.writemask
= WRITEMASK_XYZ
;
1024 case nir_op_bany_fnequal4
:
1025 case nir_op_bany_inequal4
:
1026 tmp
.writemask
= WRITEMASK_XYZW
;
1029 unreachable("not reached");
1032 emit(CMP(tmp
, op
[0], op
[1],
1033 brw_conditional_for_nir_comparison(instr
->op
)));
1035 emit(MOV(dst
, src_reg(0)));
1036 inst
= emit(MOV(dst
, src_reg(~0)));
1037 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1042 if (devinfo
->gen
>= 8) {
1043 op
[0] = resolve_source_modifiers(op
[0]);
1045 emit(NOT(dst
, op
[0]));
1049 if (devinfo
->gen
>= 8) {
1050 op
[0] = resolve_source_modifiers(op
[0]);
1051 op
[1] = resolve_source_modifiers(op
[1]);
1053 emit(XOR(dst
, op
[0], op
[1]));
1057 if (devinfo
->gen
>= 8) {
1058 op
[0] = resolve_source_modifiers(op
[0]);
1059 op
[1] = resolve_source_modifiers(op
[1]);
1061 emit(OR(dst
, op
[0], op
[1]));
1065 if (devinfo
->gen
>= 8) {
1066 op
[0] = resolve_source_modifiers(op
[0]);
1067 op
[1] = resolve_source_modifiers(op
[1]);
1069 emit(AND(dst
, op
[0], op
[1]));
1073 emit(AND(dst
, op
[0], src_reg(1)));
1077 op
[0].type
= BRW_REGISTER_TYPE_D
;
1078 dst
.type
= BRW_REGISTER_TYPE_D
;
1079 emit(AND(dst
, op
[0], src_reg(0x3f800000u
)));
1080 dst
.type
= BRW_REGISTER_TYPE_F
;
1084 emit(CMP(dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1088 emit(CMP(dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1091 case nir_op_fnoise1_1
:
1092 case nir_op_fnoise1_2
:
1093 case nir_op_fnoise1_3
:
1094 case nir_op_fnoise1_4
:
1095 case nir_op_fnoise2_1
:
1096 case nir_op_fnoise2_2
:
1097 case nir_op_fnoise2_3
:
1098 case nir_op_fnoise2_4
:
1099 case nir_op_fnoise3_1
:
1100 case nir_op_fnoise3_2
:
1101 case nir_op_fnoise3_3
:
1102 case nir_op_fnoise3_4
:
1103 case nir_op_fnoise4_1
:
1104 case nir_op_fnoise4_2
:
1105 case nir_op_fnoise4_3
:
1106 case nir_op_fnoise4_4
:
1107 unreachable("not reached: should be handled by lower_noise");
1109 case nir_op_unpack_half_2x16_split_x
:
1110 case nir_op_unpack_half_2x16_split_y
:
1111 case nir_op_pack_half_2x16_split
:
1112 unreachable("not reached: should not occur in vertex shader");
1114 case nir_op_unpack_snorm_2x16
:
1115 case nir_op_unpack_unorm_2x16
:
1116 case nir_op_pack_snorm_2x16
:
1117 case nir_op_pack_unorm_2x16
:
1118 unreachable("not reached: should be handled by lower_packing_builtins");
1120 case nir_op_unpack_half_2x16
:
1121 /* As NIR does not guarantee that we have a correct swizzle outside the
1122 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1123 * uses the source operand in an operation with WRITEMASK_Y while our
1124 * source operand has only size 1, it accessed incorrect data producing
1125 * regressions in Piglit. We repeat the swizzle of the first component on the
1126 * rest of components to avoid regressions. In the vec4_visitor IR code path
1127 * this is not needed because the operand has already the correct swizzle.
1129 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1130 emit_unpack_half_2x16(dst
, op
[0]);
1133 case nir_op_pack_half_2x16
:
1134 emit_pack_half_2x16(dst
, op
[0]);
1137 case nir_op_unpack_unorm_4x8
:
1138 emit_unpack_unorm_4x8(dst
, op
[0]);
1141 case nir_op_pack_unorm_4x8
:
1142 emit_pack_unorm_4x8(dst
, op
[0]);
1145 case nir_op_unpack_snorm_4x8
:
1146 emit_unpack_snorm_4x8(dst
, op
[0]);
1149 case nir_op_pack_snorm_4x8
:
1150 emit_pack_snorm_4x8(dst
, op
[0]);
1153 case nir_op_bitfield_reverse
:
1154 emit(BFREV(dst
, op
[0]));
1157 case nir_op_bit_count
:
1158 emit(CBIT(dst
, op
[0]));
1161 case nir_op_ufind_msb
:
1162 case nir_op_ifind_msb
: {
1163 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1165 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1166 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1168 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1169 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1170 * subtract the result from 31 to convert the MSB count into an LSB count.
1173 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1174 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1175 emit(MOV(dst
, temp
));
1177 src_reg src_tmp
= src_reg(dst
);
1178 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1180 src_tmp
.negate
= true;
1181 inst
= emit(ADD(dst
, src_tmp
, src_reg(31)));
1182 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1186 case nir_op_find_lsb
:
1187 emit(FBL(dst
, op
[0]));
1190 case nir_op_ubitfield_extract
:
1191 case nir_op_ibitfield_extract
:
1192 op
[0] = fix_3src_operand(op
[0]);
1193 op
[1] = fix_3src_operand(op
[1]);
1194 op
[2] = fix_3src_operand(op
[2]);
1196 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1200 emit(BFI1(dst
, op
[0], op
[1]));
1204 op
[0] = fix_3src_operand(op
[0]);
1205 op
[1] = fix_3src_operand(op
[1]);
1206 op
[2] = fix_3src_operand(op
[2]);
1208 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1211 case nir_op_bitfield_insert
:
1212 unreachable("not reached: should be handled by "
1213 "lower_instructions::bitfield_insert_to_bfm_bfi");
1216 /* AND(val, 0x80000000) gives the sign bit.
1218 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1221 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1223 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1224 dst
.type
= BRW_REGISTER_TYPE_UD
;
1225 emit(AND(dst
, op
[0], src_reg(0x80000000u
)));
1227 inst
= emit(OR(dst
, src_reg(dst
), src_reg(0x3f800000u
)));
1228 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1229 dst
.type
= BRW_REGISTER_TYPE_F
;
1231 if (instr
->dest
.saturate
) {
1232 inst
= emit(MOV(dst
, src_reg(dst
)));
1233 inst
->saturate
= true;
1238 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1239 * -> non-negative val generates 0x00000000.
1240 * Predicated OR sets 1 if val is positive.
1242 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1243 emit(ASR(dst
, op
[0], src_reg(31)));
1244 inst
= emit(OR(dst
, src_reg(dst
), src_reg(1)));
1245 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1249 emit(SHL(dst
, op
[0], op
[1]));
1253 emit(ASR(dst
, op
[0], op
[1]));
1257 emit(SHR(dst
, op
[0], op
[1]));
1261 op
[0] = fix_3src_operand(op
[0]);
1262 op
[1] = fix_3src_operand(op
[1]);
1263 op
[2] = fix_3src_operand(op
[2]);
1265 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1266 inst
->saturate
= instr
->dest
.saturate
;
1270 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1271 inst
->saturate
= instr
->dest
.saturate
;
1275 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1276 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1277 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1281 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1282 inst
->saturate
= instr
->dest
.saturate
;
1286 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1287 inst
->saturate
= instr
->dest
.saturate
;
1291 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1292 inst
->saturate
= instr
->dest
.saturate
;
1297 case nir_op_bany4
: {
1298 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1299 tmp
.writemask
= brw_writemask_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1301 emit(CMP(tmp
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1303 emit(MOV(dst
, src_reg(0)));
1304 inst
= emit(MOV(dst
, src_reg(~0)));
1305 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1314 unreachable("not reached: should be lowered by lower_source mods");
1317 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1320 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1324 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1327 unreachable("Unimplemented ALU operation");
1330 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1331 * to sign extend the low bit to 0/~0
1333 if (devinfo
->gen
<= 5 &&
1334 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1335 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1336 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1337 masked
.writemask
= dst
.writemask
;
1338 emit(AND(masked
, src_reg(dst
), src_reg(1)));
1339 src_reg masked_neg
= src_reg(masked
);
1340 masked_neg
.negate
= true;
1341 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1346 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1348 switch (instr
->type
) {
1349 case nir_jump_break
:
1350 emit(BRW_OPCODE_BREAK
);
1353 case nir_jump_continue
:
1354 emit(BRW_OPCODE_CONTINUE
);
1357 case nir_jump_return
:
1360 unreachable("unknown jump");
1364 enum ir_texture_opcode
1365 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1367 enum ir_texture_opcode op
;
1370 case nir_texop_lod
: op
= ir_lod
; break;
1371 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1372 case nir_texop_tex
: op
= ir_tex
; break;
1373 case nir_texop_tg4
: op
= ir_tg4
; break;
1374 case nir_texop_txb
: op
= ir_txb
; break;
1375 case nir_texop_txd
: op
= ir_txd
; break;
1376 case nir_texop_txf
: op
= ir_txf
; break;
1377 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1378 case nir_texop_txl
: op
= ir_txl
; break;
1379 case nir_texop_txs
: op
= ir_txs
; break;
1381 unreachable("unknown texture opcode");
1387 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1388 unsigned components
)
1391 case nir_type_float
:
1392 return glsl_type::vec(components
);
1394 return glsl_type::ivec(components
);
1395 case nir_type_unsigned
:
1396 return glsl_type::uvec(components
);
1398 return glsl_type::bvec(components
);
1400 return glsl_type::error_type
;
1403 return glsl_type::error_type
;
1407 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1409 unsigned sampler
= instr
->sampler_index
;
1410 src_reg sampler_reg
= src_reg(sampler
);
1412 const glsl_type
*coord_type
= NULL
;
1413 src_reg shadow_comparitor
;
1414 src_reg offset_value
;
1416 src_reg sample_index
;
1419 const glsl_type
*dest_type
=
1420 glsl_type_for_nir_alu_type(instr
->dest_type
,
1421 nir_tex_instr_dest_size(instr
));
1422 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1424 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1425 * emitting anything other than setting up the constant result.
1427 if (instr
->op
== nir_texop_tg4
) {
1428 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], instr
->component
);
1429 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1430 emit(MOV(dest
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
1435 /* Load the texture operation sources */
1436 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1437 switch (instr
->src
[i
].src_type
) {
1438 case nir_tex_src_comparitor
:
1439 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1440 BRW_REGISTER_TYPE_F
, 1);
1443 case nir_tex_src_coord
: {
1444 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1446 switch (instr
->op
) {
1448 case nir_texop_txf_ms
:
1449 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1451 coord_type
= glsl_type::ivec(src_size
);
1455 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1457 coord_type
= glsl_type::vec(src_size
);
1463 case nir_tex_src_ddx
:
1464 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1465 nir_tex_instr_src_size(instr
, i
));
1468 case nir_tex_src_ddy
:
1469 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1470 nir_tex_instr_src_size(instr
, i
));
1473 case nir_tex_src_lod
:
1474 switch (instr
->op
) {
1477 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1481 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1486 case nir_tex_src_ms_index
: {
1487 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1488 assert(coord_type
!= NULL
);
1489 if (devinfo
->gen
>= 7 &&
1490 key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
)) {
1491 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1495 mcs
= retype(mcs
, BRW_REGISTER_TYPE_UD
);
1499 case nir_tex_src_offset
:
1500 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1503 case nir_tex_src_sampler_offset
: {
1504 /* The highest sampler which may be used by this operation is
1505 * the last element of the array. Mark it here, because the generator
1506 * doesn't have enough information to determine the bound.
1508 uint32_t array_size
= instr
->sampler_array_size
;
1509 uint32_t max_used
= sampler
+ array_size
- 1;
1510 if (instr
->op
== nir_texop_tg4
) {
1511 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1513 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1516 brw_mark_surface_used(&prog_data
->base
, max_used
);
1518 /* Emit code to evaluate the actual indexing expression */
1519 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1520 src_reg
temp(this, glsl_type::uint_type
);
1521 emit(ADD(dst_reg(temp
), src
, src_reg(sampler
)));
1522 sampler_reg
= emit_uniformize(temp
);
1526 case nir_tex_src_projector
:
1527 unreachable("Should be lowered by do_lower_texture_projection");
1529 case nir_tex_src_bias
:
1530 unreachable("LOD bias is not valid for vertex shaders.\n");
1533 unreachable("unknown texture source");
1537 uint32_t constant_offset
= 0;
1538 for (unsigned i
= 0; i
< 3; i
++) {
1539 if (instr
->const_offset
[i
] != 0) {
1540 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1545 /* Stuff the channel select bits in the top of the texture offset */
1546 if (instr
->op
== nir_texop_tg4
)
1547 constant_offset
|= gather_channel(instr
->component
, sampler
) << 16;
1549 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1551 bool is_cube_array
=
1552 instr
->op
== nir_texop_txs
&&
1553 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1556 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1558 lod
, lod2
, sample_index
,
1559 constant_offset
, offset_value
,
1560 mcs
, is_cube_array
, sampler
, sampler_reg
);