2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_setup_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
63 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
66 case nir_intrinsic_load_base_vertex
:
67 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
68 if (reg
->file
== BAD_FILE
)
69 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
);
72 case nir_intrinsic_load_instance_id
:
73 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
74 if (reg
->file
== BAD_FILE
)
75 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
);
78 case nir_intrinsic_load_base_instance
:
79 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
80 if (reg
->file
== BAD_FILE
)
81 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
84 case nir_intrinsic_load_draw_id
:
85 reg
= &nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
86 if (reg
->file
== BAD_FILE
)
87 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_DRAW_ID
);
96 setup_system_values_block(nir_block
*block
, vec4_visitor
*v
)
98 nir_foreach_instr(instr
, block
) {
99 if (instr
->type
!= nir_instr_type_intrinsic
)
102 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
103 v
->nir_setup_system_value_intrinsic(intrin
);
110 vec4_visitor::nir_setup_system_values()
112 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
113 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
114 nir_system_values
[i
] = dst_reg();
117 nir_foreach_function(function
, nir
) {
118 assert(strcmp(function
->name
, "main") == 0);
119 assert(function
->impl
);
120 nir_foreach_block(block
, function
->impl
) {
121 setup_system_values_block(block
, this);
127 vec4_visitor::nir_setup_uniforms()
129 uniforms
= nir
->num_uniforms
/ 16;
133 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
135 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
136 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
137 nir_locals
[i
] = dst_reg();
140 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
141 unsigned array_elems
=
142 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
143 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
144 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
146 if (reg
->bit_size
== 64)
147 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
150 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
152 nir_emit_cf_list(&impl
->body
);
156 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
158 exec_list_validate(list
);
159 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
160 switch (node
->type
) {
162 nir_emit_if(nir_cf_node_as_if(node
));
165 case nir_cf_node_loop
:
166 nir_emit_loop(nir_cf_node_as_loop(node
));
169 case nir_cf_node_block
:
170 nir_emit_block(nir_cf_node_as_block(node
));
174 unreachable("Invalid CFG node block");
180 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
182 /* First, put the condition in f0 */
183 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
184 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
185 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
187 /* We can just predicate based on the X channel, as the condition only
188 * goes on its own line */
189 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
191 nir_emit_cf_list(&if_stmt
->then_list
);
193 /* note: if the else is empty, dead CF elimination will remove it */
194 emit(BRW_OPCODE_ELSE
);
196 nir_emit_cf_list(&if_stmt
->else_list
);
198 emit(BRW_OPCODE_ENDIF
);
202 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
206 nir_emit_cf_list(&loop
->body
);
208 emit(BRW_OPCODE_WHILE
);
212 vec4_visitor::nir_emit_block(nir_block
*block
)
214 nir_foreach_instr(instr
, block
) {
215 nir_emit_instr(instr
);
220 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
224 switch (instr
->type
) {
225 case nir_instr_type_load_const
:
226 nir_emit_load_const(nir_instr_as_load_const(instr
));
229 case nir_instr_type_intrinsic
:
230 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
233 case nir_instr_type_alu
:
234 nir_emit_alu(nir_instr_as_alu(instr
));
237 case nir_instr_type_jump
:
238 nir_emit_jump(nir_instr_as_jump(instr
));
241 case nir_instr_type_tex
:
242 nir_emit_texture(nir_instr_as_tex(instr
));
245 case nir_instr_type_ssa_undef
:
246 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
250 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
256 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
257 unsigned base_offset
, nir_src
*indirect
)
261 reg
= v
->nir_locals
[nir_reg
->index
];
262 if (nir_reg
->bit_size
== 64)
263 reg
.type
= BRW_REGISTER_TYPE_DF
;
264 reg
= offset(reg
, 8, base_offset
);
267 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
275 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
279 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
280 if (dest
.ssa
.bit_size
== 64)
281 dst
.type
= BRW_REGISTER_TYPE_DF
;
282 nir_ssa_values
[dest
.ssa
.index
] = dst
;
285 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
291 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
293 return retype(get_nir_dest(dest
), type
);
297 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
299 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
303 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
304 unsigned num_components
)
309 assert(src
.ssa
!= NULL
);
310 reg
= nir_ssa_values
[src
.ssa
->index
];
313 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
317 reg
= retype(reg
, type
);
319 src_reg reg_as_src
= src_reg(reg
);
320 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
325 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
326 unsigned num_components
)
328 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
333 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
335 /* if type is not specified, default to signed int */
336 return get_nir_src(src
, nir_type_int32
, num_components
);
340 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
342 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
343 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
346 /* The only constant offset we should find is 0. brw_nir.c's
347 * add_const_offset_to_base() will fold other constant offsets
348 * into instr->const_index[0].
350 assert(const_value
->u32
[0] == 0);
354 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
358 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
362 if (instr
->def
.bit_size
== 64) {
363 reg
= dst_reg(VGRF
, alloc
.allocate(2));
364 reg
.type
= BRW_REGISTER_TYPE_DF
;
366 reg
= dst_reg(VGRF
, alloc
.allocate(1));
367 reg
.type
= BRW_REGISTER_TYPE_D
;
370 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
372 /* @FIXME: consider emitting vector operations to save some MOVs in
373 * cases where the components are representable in 8 bits.
374 * For now, we emit a MOV for each distinct value.
376 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
377 unsigned writemask
= 1 << i
;
379 if ((remaining
& writemask
) == 0)
382 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
383 if ((instr
->def
.bit_size
== 32 &&
384 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
385 (instr
->def
.bit_size
== 64 &&
386 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
391 reg
.writemask
= writemask
;
392 if (instr
->def
.bit_size
== 64) {
393 emit(MOV(reg
, setup_imm_df(instr
->value
.f64
[i
])));
395 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
398 remaining
&= ~writemask
;
401 /* Set final writemask */
402 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
404 nir_ssa_values
[instr
->def
.index
] = reg
;
408 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
413 switch (instr
->intrinsic
) {
415 case nir_intrinsic_load_input
: {
416 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
418 /* We set EmitNoIndirectInput for VS */
419 assert(const_offset
);
421 dest
= get_nir_dest(instr
->dest
);
422 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
424 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
425 glsl_type::uvec4_type
);
426 src
= retype(src
, dest
.type
);
428 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
430 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
431 src
.swizzle
= BRW_SWIZZLE_XYZW
;
432 shuffle_64bit_data(tmp
, src
, false);
433 emit(MOV(dest
, src_reg(tmp
)));
435 /* Swizzle source based on component layout qualifier */
436 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
437 emit(MOV(dest
, src
));
442 case nir_intrinsic_store_output
: {
443 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
444 assert(const_offset
);
446 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
448 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
451 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
452 instr
->num_components
);
453 data
= src_reg(this, glsl_type::dvec4_type
);
454 shuffle_64bit_data(dst_reg(data
), src
, true);
455 src
= retype(data
, BRW_REGISTER_TYPE_F
);
457 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
458 instr
->num_components
);
461 unsigned c
= nir_intrinsic_component(instr
);
462 output_reg
[varying
][c
] = dst_reg(src
);
463 output_num_components
[varying
][c
] = instr
->num_components
;
465 unsigned num_components
= instr
->num_components
;
469 output_reg
[varying
][c
] = dst_reg(src
);
470 output_num_components
[varying
][c
] = MIN2(4, num_components
);
472 if (is_64bit
&& num_components
> 4) {
473 assert(num_components
<= 8);
474 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
475 output_num_components
[varying
+ 1][c
] = num_components
- 4;
480 case nir_intrinsic_get_buffer_size
: {
481 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
482 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
484 const unsigned index
=
485 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
486 dst_reg result_dst
= get_nir_dest(instr
->dest
);
487 vec4_instruction
*inst
= new(mem_ctx
)
488 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
491 inst
->mlen
= 1; /* always at least one */
492 inst
->src
[1] = brw_imm_ud(index
);
494 /* MRF for the first parameter */
495 src_reg lod
= brw_imm_d(0);
496 int param_base
= inst
->base_mrf
;
497 int writemask
= WRITEMASK_X
;
498 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
502 brw_mark_surface_used(&prog_data
->base
, index
);
506 case nir_intrinsic_store_ssbo
: {
507 assert(devinfo
->gen
>= 7);
511 nir_const_value
*const_uniform_block
=
512 nir_src_as_const_value(instr
->src
[1]);
513 if (const_uniform_block
) {
514 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
515 const_uniform_block
->u32
[0];
516 surf_index
= brw_imm_ud(index
);
517 brw_mark_surface_used(&prog_data
->base
, index
);
519 surf_index
= src_reg(this, glsl_type::uint_type
);
520 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
521 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
522 surf_index
= emit_uniformize(surf_index
);
524 brw_mark_surface_used(&prog_data
->base
,
525 prog_data
->base
.binding_table
.ssbo_start
+
526 nir
->info
->num_ssbos
- 1);
531 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
533 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
535 offset_reg
= get_nir_src(instr
->src
[2], 1);
539 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
542 unsigned write_mask
= instr
->const_index
[0];
544 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
545 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
546 * typed and untyped messages and across hardware platforms, the
547 * current implementation of the untyped messages will transparently convert
548 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
549 * and enabling only channel X on the SEND instruction.
551 * The above, works well for full vector writes, but not for partial writes
552 * where we want to write some channels and not others, like when we have
553 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
554 * quite restrictive with regards to the channel enables we can configure in
555 * the message descriptor (not all combinations are allowed) we cannot simply
556 * implement these scenarios with a single message while keeping the
557 * aforementioned symmetry in the implementation. For now we de decided that
558 * it is better to keep the symmetry to reduce complexity, so in situations
559 * such as the one described we end up emitting two untyped write messages
560 * (one for xy and another for w).
562 * The code below packs consecutive channels into a single write message,
563 * detects gaps in the vector write and if needed, sends a second message
564 * with the remaining channels. If in the future we decide that we want to
565 * emit a single message at the expense of losing the symmetry in the
566 * implementation we can:
568 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
569 * message payload. In this mode we can write up to 8 offsets and dwords
570 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
571 * and select which of the 8 channels carry data to write by setting the
572 * appropriate writemask in the dst register of the SEND instruction.
573 * It would require to write a new generator opcode specifically for
574 * IvyBridge since we would need to prepare a SIMD8 payload that could
575 * use any channel, not just X.
577 * 2) For Haswell+: Simply send a single write message but set the writemask
578 * on the dst of the SEND instruction to select the channels we want to
579 * write. It would require to modify the current messages to receive
580 * and honor the writemask provided.
582 const vec4_builder bld
= vec4_builder(this).at_end()
583 .annotate(current_annotation
, base_ir
);
585 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
586 if (type_slots
== 2) {
587 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
588 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
589 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
592 uint8_t swizzle
[4] = { 0, 0, 0, 0};
593 int num_channels
= 0;
594 unsigned skipped_channels
= 0;
595 int num_components
= instr
->num_components
;
596 for (int i
= 0; i
< num_components
; i
++) {
597 /* Read components Z/W of a dvec from the appropriate place. We will
598 * also have to adjust the swizzle (we do that with the '% 4' below)
600 if (i
== 2 && type_slots
== 2)
601 val_reg
= byte_offset(val_reg
, REG_SIZE
);
603 /* Check if this channel needs to be written. If so, record the
604 * channel we need to take the data from in the swizzle array
606 int component_mask
= 1 << i
;
607 int write_test
= write_mask
& component_mask
;
609 /* If we are writing doubles we have to write 2 channels worth of
610 * of data (64 bits) for each double component.
612 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
614 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
617 /* If we don't have to write this channel it means we have a gap in the
618 * vector, so write the channels we accumulated until now, if any. Do
619 * the same if this was the last component in the vector, if we have
620 * enough channels for a full vec4 write or if we have processed
621 * components XY of a dvec (since components ZW are not in the same
624 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
625 (i
== 1 && type_slots
== 2)) {
626 if (num_channels
> 0) {
627 /* We have channels to write, so update the offset we need to
628 * write at to skip the channels we skipped, if any.
630 if (skipped_channels
> 0) {
631 if (offset_reg
.file
== IMM
) {
632 offset_reg
.ud
+= 4 * skipped_channels
;
634 emit(ADD(dst_reg(offset_reg
), offset_reg
,
635 brw_imm_ud(4 * skipped_channels
)));
639 /* Swizzle the data register so we take the data from the channels
640 * we need to write and send the write message. This will write
641 * num_channels consecutive dwords starting at offset.
644 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
645 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
646 1 /* dims */, num_channels
/* size */,
649 /* If we have to do a second write we will have to update the
650 * offset so that we jump over the channels we have just written
653 skipped_channels
= num_channels
;
655 /* Restart the count for the next write message */
659 /* If we didn't write the channel, increase skipped count */
661 skipped_channels
+= type_slots
;
668 case nir_intrinsic_load_ssbo
: {
669 assert(devinfo
->gen
>= 7);
671 nir_const_value
*const_uniform_block
=
672 nir_src_as_const_value(instr
->src
[0]);
675 if (const_uniform_block
) {
676 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
677 const_uniform_block
->u32
[0];
678 surf_index
= brw_imm_ud(index
);
680 brw_mark_surface_used(&prog_data
->base
, index
);
682 surf_index
= src_reg(this, glsl_type::uint_type
);
683 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
684 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
685 surf_index
= emit_uniformize(surf_index
);
687 /* Assume this may touch any UBO. It would be nice to provide
688 * a tighter bound, but the array information is already lowered away.
690 brw_mark_surface_used(&prog_data
->base
,
691 prog_data
->base
.binding_table
.ssbo_start
+
692 nir
->info
->num_ssbos
- 1);
696 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
698 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
700 offset_reg
= get_nir_src(instr
->src
[1], 1);
703 /* Read the vector */
704 const vec4_builder bld
= vec4_builder(this).at_end()
705 .annotate(current_annotation
, base_ir
);
708 dst_reg dest
= get_nir_dest(instr
->dest
);
709 if (type_sz(dest
.type
) < 8) {
710 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
711 1 /* dims */, 4 /* size*/,
714 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
717 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
718 1 /* dims */, 4 /* size*/,
720 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
722 if (offset_reg
.file
== IMM
)
725 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
727 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
728 1 /* dims */, 4 /* size*/,
730 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
733 read_result
= src_reg(this, glsl_type::dvec4_type
);
734 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
737 read_result
.type
= dest
.type
;
738 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
739 emit(MOV(dest
, read_result
));
743 case nir_intrinsic_ssbo_atomic_add
:
744 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
746 case nir_intrinsic_ssbo_atomic_imin
:
747 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
749 case nir_intrinsic_ssbo_atomic_umin
:
750 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
752 case nir_intrinsic_ssbo_atomic_imax
:
753 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
755 case nir_intrinsic_ssbo_atomic_umax
:
756 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
758 case nir_intrinsic_ssbo_atomic_and
:
759 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
761 case nir_intrinsic_ssbo_atomic_or
:
762 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
764 case nir_intrinsic_ssbo_atomic_xor
:
765 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
767 case nir_intrinsic_ssbo_atomic_exchange
:
768 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
770 case nir_intrinsic_ssbo_atomic_comp_swap
:
771 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
774 case nir_intrinsic_load_vertex_id
:
775 unreachable("should be lowered by lower_vertex_id()");
777 case nir_intrinsic_load_vertex_id_zero_base
:
778 case nir_intrinsic_load_base_vertex
:
779 case nir_intrinsic_load_instance_id
:
780 case nir_intrinsic_load_base_instance
:
781 case nir_intrinsic_load_draw_id
:
782 case nir_intrinsic_load_invocation_id
: {
783 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
784 src_reg val
= src_reg(nir_system_values
[sv
]);
785 assert(val
.file
!= BAD_FILE
);
786 dest
= get_nir_dest(instr
->dest
, val
.type
);
787 emit(MOV(dest
, val
));
791 case nir_intrinsic_load_uniform
: {
792 /* Offsets are in bytes but they should always be multiples of 4 */
793 assert(nir_intrinsic_base(instr
) % 4 == 0);
795 dest
= get_nir_dest(instr
->dest
);
797 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
798 src
.type
= dest
.type
;
800 /* Uniforms don't actually have to be vec4 aligned. In the case that
801 * it isn't, we have to use a swizzle to shift things around. They
802 * do still have the std140 alignment requirement that vec2's have to
803 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
805 * The swizzle also works in the indirect case as the generator adds
806 * the swizzle to the offset for us.
808 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / 4;
809 assert(shift
+ instr
->num_components
<= 4);
811 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
813 /* Offsets are in bytes but they should always be multiples of 4 */
814 assert(const_offset
->u32
[0] % 4 == 0);
816 unsigned offset
= const_offset
->u32
[0] + shift
* 4;
817 src
.offset
= ROUND_DOWN_TO(offset
, 16);
818 shift
= (offset
% 16) / 4;
819 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
821 emit(MOV(dest
, src
));
823 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
825 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
827 /* MOV_INDIRECT is going to stomp the whole thing anyway */
828 dest
.writemask
= WRITEMASK_XYZW
;
830 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
831 indirect
, brw_imm_ud(instr
->const_index
[1]));
836 case nir_intrinsic_atomic_counter_read
:
837 case nir_intrinsic_atomic_counter_inc
:
838 case nir_intrinsic_atomic_counter_dec
: {
839 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
840 (unsigned) instr
->const_index
[0];
841 const vec4_builder bld
=
842 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
844 /* Get some metadata from the image intrinsic. */
845 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
847 /* Get the arguments of the atomic intrinsic. */
848 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int32
,
849 instr
->num_components
);
850 const src_reg surface
= brw_imm_ud(surf_index
);
851 const src_reg src0
= (info
->num_srcs
>= 2
852 ? get_nir_src(instr
->src
[1]) : src_reg());
853 const src_reg src1
= (info
->num_srcs
>= 3
854 ? get_nir_src(instr
->src
[2]) : src_reg());
858 dest
= get_nir_dest(instr
->dest
);
860 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
861 tmp
= emit_untyped_read(bld
, surface
, offset
, 1, 1);
863 tmp
= emit_untyped_atomic(bld
, surface
, offset
,
866 get_atomic_counter_op(instr
->intrinsic
));
869 bld
.MOV(retype(dest
, tmp
.type
), tmp
);
870 brw_mark_surface_used(stage_prog_data
, surf_index
);
874 case nir_intrinsic_load_ubo
: {
875 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
878 dest
= get_nir_dest(instr
->dest
);
880 if (const_block_index
) {
881 /* The block index is a constant, so just emit the binding table entry
884 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
885 const_block_index
->u32
[0];
886 surf_index
= brw_imm_ud(index
);
887 brw_mark_surface_used(&prog_data
->base
, index
);
889 /* The block index is not a constant. Evaluate the index expression
890 * per-channel and add the base UBO index; we have to select a value
891 * from any live channel.
893 surf_index
= src_reg(this, glsl_type::uint_type
);
894 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
895 instr
->num_components
),
896 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
897 surf_index
= emit_uniformize(surf_index
);
899 /* Assume this may touch any UBO. It would be nice to provide
900 * a tighter bound, but the array information is already lowered away.
902 brw_mark_surface_used(&prog_data
->base
,
903 prog_data
->base
.binding_table
.ubo_start
+
904 nir
->info
->num_ubos
- 1);
908 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
910 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
912 offset_reg
= get_nir_src(instr
->src
[1], nir_type_uint32
, 1);
915 src_reg packed_consts
;
916 if (nir_dest_bit_size(instr
->dest
) == 32) {
917 packed_consts
= src_reg(this, glsl_type::vec4_type
);
918 emit_pull_constant_load_reg(dst_reg(packed_consts
),
921 NULL
, NULL
/* before_block/inst */);
923 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
924 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
926 emit_pull_constant_load_reg(dst_reg(temp_float
),
927 surf_index
, offset_reg
, NULL
, NULL
);
928 if (offset_reg
.file
== IMM
)
931 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
932 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
933 surf_index
, offset_reg
, NULL
, NULL
);
935 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
936 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
939 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
941 unsigned type_size
= type_sz(dest
.type
);
942 packed_consts
.swizzle
+=
943 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
944 const_offset
->u32
[0] % 16 / type_size
,
945 const_offset
->u32
[0] % 16 / type_size
,
946 const_offset
->u32
[0] % 16 / type_size
);
949 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
954 case nir_intrinsic_memory_barrier
: {
955 const vec4_builder bld
=
956 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
957 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
958 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
959 ->size_written
= 2 * REG_SIZE
;
963 case nir_intrinsic_shader_clock
: {
964 /* We cannot do anything if there is an event, so ignore it for now */
965 const src_reg shader_clock
= get_timestamp();
966 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
968 dest
= get_nir_dest(instr
->dest
, type
);
969 emit(MOV(dest
, shader_clock
));
974 unreachable("Unknown intrinsic");
979 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
982 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
983 dest
= get_nir_dest(instr
->dest
);
986 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
988 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
989 const_surface
->u32
[0];
990 surface
= brw_imm_ud(surf_index
);
991 brw_mark_surface_used(&prog_data
->base
, surf_index
);
993 surface
= src_reg(this, glsl_type::uint_type
);
994 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
995 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
997 /* Assume this may touch any UBO. This is the same we do for other
998 * UBO/SSBO accesses with non-constant surface.
1000 brw_mark_surface_used(&prog_data
->base
,
1001 prog_data
->base
.binding_table
.ssbo_start
+
1002 nir
->info
->num_ssbos
- 1);
1005 src_reg offset
= get_nir_src(instr
->src
[1], 1);
1006 src_reg data1
= get_nir_src(instr
->src
[2], 1);
1008 if (op
== BRW_AOP_CMPWR
)
1009 data2
= get_nir_src(instr
->src
[3], 1);
1011 /* Emit the actual atomic operation operation */
1012 const vec4_builder bld
=
1013 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
1015 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
1017 1 /* dims */, 1 /* rsize */,
1019 BRW_PREDICATE_NONE
);
1020 dest
.type
= atomic_result
.type
;
1021 bld
.MOV(dest
, atomic_result
);
1025 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
1027 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1030 static enum brw_conditional_mod
1031 brw_conditional_for_nir_comparison(nir_op op
)
1037 return BRW_CONDITIONAL_L
;
1042 return BRW_CONDITIONAL_GE
;
1046 case nir_op_ball_fequal2
:
1047 case nir_op_ball_iequal2
:
1048 case nir_op_ball_fequal3
:
1049 case nir_op_ball_iequal3
:
1050 case nir_op_ball_fequal4
:
1051 case nir_op_ball_iequal4
:
1052 return BRW_CONDITIONAL_Z
;
1056 case nir_op_bany_fnequal2
:
1057 case nir_op_bany_inequal2
:
1058 case nir_op_bany_fnequal3
:
1059 case nir_op_bany_inequal3
:
1060 case nir_op_bany_fnequal4
:
1061 case nir_op_bany_inequal4
:
1062 return BRW_CONDITIONAL_NZ
;
1065 unreachable("not reached: bad operation for comparison");
1070 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1071 enum brw_predicate
*predicate
)
1073 if (!instr
->src
[0].src
.is_ssa
||
1074 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1077 nir_alu_instr
*cmp_instr
=
1078 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1080 switch (cmp_instr
->op
) {
1081 case nir_op_bany_fnequal2
:
1082 case nir_op_bany_inequal2
:
1083 case nir_op_bany_fnequal3
:
1084 case nir_op_bany_inequal3
:
1085 case nir_op_bany_fnequal4
:
1086 case nir_op_bany_inequal4
:
1087 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1089 case nir_op_ball_fequal2
:
1090 case nir_op_ball_iequal2
:
1091 case nir_op_ball_fequal3
:
1092 case nir_op_ball_iequal3
:
1093 case nir_op_ball_fequal4
:
1094 case nir_op_ball_iequal4
:
1095 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1101 unsigned size_swizzle
=
1102 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1105 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1106 for (unsigned i
= 0; i
< 2; i
++) {
1107 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1108 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1109 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1110 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1111 unsigned base_swizzle
=
1112 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1113 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1114 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1115 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1118 emit(CMP(dst_null_d(), op
[0], op
[1],
1119 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1125 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1130 vec4_instruction
*inst
;
1134 /* LZD of an absolute value source almost always does the right
1135 * thing. There are two problem values:
1137 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1138 * 0. However, findMSB(int(0x80000000)) == 30.
1140 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1141 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1143 * For a value of zero or negative one, -1 will be returned.
1145 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1146 * findMSB(-(1<<x)) should return x-1.
1148 * For all negative number cases, including 0x80000000 and
1149 * 0xffffffff, the correct value is obtained from LZD if instead of
1150 * negating the (already negative) value the logical-not is used. A
1151 * conditonal logical-not can be achieved in two instructions.
1153 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1155 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1156 bld
.XOR(dst_reg(temp
), temp
, src
);
1159 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1160 retype(temp
, BRW_REGISTER_TYPE_UD
));
1162 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1163 * from the LSB side. Subtract the result from 31 to convert the MSB count
1164 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1165 * which is exactly what findMSB() is supposed to return.
1167 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1169 inst
->src
[0].negate
= true;
1173 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1175 brw_reg_type single_type
)
1177 /* BDW PRM vol 15 - workarounds:
1178 * DF->f format conversion for Align16 has wrong emask calculation when
1179 * source is immediate.
1181 if (devinfo
->gen
== 8 && single_type
== BRW_REGISTER_TYPE_F
&&
1182 src
.file
== BRW_IMMEDIATE_VALUE
) {
1183 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1184 inst
->saturate
= saturate
;
1188 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1189 emit(MOV(temp
, src
));
1191 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1192 temp2
= retype(temp2
, single_type
);
1193 emit(VEC4_OPCODE_FROM_DOUBLE
, temp2
, src_reg(temp
))
1194 ->size_written
= 2 * REG_SIZE
;
1196 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(temp2
)));
1197 inst
->saturate
= saturate
;
1201 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1203 brw_reg_type single_type
)
1205 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1206 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), single_type
);
1207 emit(MOV(dst_reg(tmp_src
), retype(src
, single_type
)));
1208 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1209 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1210 inst
->saturate
= saturate
;
1214 vec4_visitor::setup_imm_df(double v
)
1216 assert(devinfo
->gen
>= 7);
1218 if (devinfo
->gen
>= 8)
1219 return brw_imm_df(v
);
1221 /* gen7.5 does not support DF immediates straighforward but the DIM
1222 * instruction allows to set the 64-bit immediate value.
1224 if (devinfo
->is_haswell
) {
1225 dst_reg dst
= retype(dst_reg(VGRF
, alloc
.allocate(2)), BRW_REGISTER_TYPE_DF
);
1226 emit(DIM(dst
, brw_imm_df(v
)))->force_writemask_all
= true;
1227 return swizzle(src_reg(retype(dst
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
1230 /* gen7 does not support DF immediates */
1241 /* Write the low 32-bit of the constant to the X:UD channel and the
1242 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
1243 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
1244 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
1245 * XXXX so any access to the VGRF only reads the constant data in these
1249 retype(dst_reg(VGRF
, alloc
.allocate(2)), BRW_REGISTER_TYPE_UD
);
1250 for (int n
= 0; n
< 2; n
++) {
1251 emit(MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
)))
1252 ->force_writemask_all
= true;
1253 emit(MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
)))
1254 ->force_writemask_all
= true;
1257 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
1261 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1263 vec4_instruction
*inst
;
1265 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1266 nir_dest_bit_size(instr
->dest
.dest
));
1267 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1268 dst
.writemask
= instr
->dest
.write_mask
;
1271 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1272 nir_alu_type src_type
= (nir_alu_type
)
1273 (nir_op_infos
[instr
->op
].input_types
[i
] |
1274 nir_src_bit_size(instr
->src
[i
].src
));
1275 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1276 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1277 op
[i
].abs
= instr
->src
[i
].abs
;
1278 op
[i
].negate
= instr
->src
[i
].negate
;
1281 switch (instr
->op
) {
1284 inst
= emit(MOV(dst
, op
[0]));
1285 inst
->saturate
= instr
->dest
.saturate
;
1291 unreachable("not reached: should be handled by lower_vec_to_movs()");
1295 inst
= emit(MOV(dst
, op
[0]));
1296 inst
->saturate
= instr
->dest
.saturate
;
1301 inst
= emit(MOV(dst
, op
[0]));
1305 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
,
1306 BRW_REGISTER_TYPE_F
);
1310 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
,
1311 BRW_REGISTER_TYPE_F
);
1316 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
,
1317 instr
->op
== nir_op_d2i
? BRW_REGISTER_TYPE_D
:
1318 BRW_REGISTER_TYPE_UD
);
1323 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
,
1324 instr
->op
== nir_op_i2d
? BRW_REGISTER_TYPE_D
:
1325 BRW_REGISTER_TYPE_UD
);
1329 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1331 inst
= emit(ADD(dst
, op
[0], op
[1]));
1332 inst
->saturate
= instr
->dest
.saturate
;
1336 inst
= emit(MUL(dst
, op
[0], op
[1]));
1337 inst
->saturate
= instr
->dest
.saturate
;
1341 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1342 if (devinfo
->gen
< 8) {
1343 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1344 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1346 /* For integer multiplication, the MUL uses the low 16 bits of one of
1347 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1348 * accumulates in the contribution of the upper 16 bits of that
1349 * operand. If we can determine that one of the args is in the low
1350 * 16 bits, though, we can just emit a single MUL.
1352 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1353 if (devinfo
->gen
< 7)
1354 emit(MUL(dst
, op
[0], op
[1]));
1356 emit(MUL(dst
, op
[1], op
[0]));
1357 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1358 if (devinfo
->gen
< 7)
1359 emit(MUL(dst
, op
[1], op
[0]));
1361 emit(MUL(dst
, op
[0], op
[1]));
1363 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1365 emit(MUL(acc
, op
[0], op
[1]));
1366 emit(MACH(dst_null_d(), op
[0], op
[1]));
1367 emit(MOV(dst
, src_reg(acc
)));
1370 emit(MUL(dst
, op
[0], op
[1]));
1375 case nir_op_imul_high
:
1376 case nir_op_umul_high
: {
1377 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1378 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1380 if (devinfo
->gen
>= 8)
1381 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1383 emit(MUL(acc
, op
[0], op
[1]));
1385 emit(MACH(dst
, op
[0], op
[1]));
1390 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1391 inst
->saturate
= instr
->dest
.saturate
;
1395 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1396 inst
->saturate
= instr
->dest
.saturate
;
1400 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1401 inst
->saturate
= instr
->dest
.saturate
;
1405 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1406 inst
->saturate
= instr
->dest
.saturate
;
1410 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1411 inst
->saturate
= instr
->dest
.saturate
;
1416 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1417 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1422 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1423 * appears that our hardware just does the right thing for signed
1426 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1427 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1431 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1432 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1434 /* Math instructions don't support conditional mod */
1435 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1436 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1438 /* Now, we need to determine if signs of the sources are different.
1439 * When we XOR the sources, the top bit is 0 if they are the same and 1
1440 * if they are different. We can then use a conditional modifier to
1441 * turn that into a predicate. This leads us to an XOR.l instruction.
1443 * Technically, according to the PRM, you're not allowed to use .l on a
1444 * XOR instruction. However, emperical experiments and Curro's reading
1445 * of the simulator source both indicate that it's safe.
1447 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1448 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1449 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1450 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1452 /* If the result of the initial remainder operation is non-zero and the
1453 * two sources have different signs, add in a copy of op[1] to get the
1454 * final integer modulus value.
1456 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1457 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1462 unreachable("not reached: should be handled by ldexp_to_arith()");
1465 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1466 inst
->saturate
= instr
->dest
.saturate
;
1470 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1471 inst
->saturate
= instr
->dest
.saturate
;
1475 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1476 inst
->saturate
= instr
->dest
.saturate
;
1479 case nir_op_uadd_carry
: {
1480 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1481 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1483 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1484 emit(MOV(dst
, src_reg(acc
)));
1488 case nir_op_usub_borrow
: {
1489 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1490 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1492 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1493 emit(MOV(dst
, src_reg(acc
)));
1498 inst
= emit(RNDZ(dst
, op
[0]));
1499 inst
->saturate
= instr
->dest
.saturate
;
1502 case nir_op_fceil
: {
1503 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1505 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1506 instr
->src
[0].src
.ssa
->num_components
:
1507 instr
->src
[0].src
.reg
.reg
->num_components
);
1509 op
[0].negate
= !op
[0].negate
;
1510 emit(RNDD(dst_reg(tmp
), op
[0]));
1512 inst
= emit(MOV(dst
, tmp
));
1513 inst
->saturate
= instr
->dest
.saturate
;
1518 inst
= emit(RNDD(dst
, op
[0]));
1519 inst
->saturate
= instr
->dest
.saturate
;
1523 inst
= emit(FRC(dst
, op
[0]));
1524 inst
->saturate
= instr
->dest
.saturate
;
1527 case nir_op_fround_even
:
1528 inst
= emit(RNDE(dst
, op
[0]));
1529 inst
->saturate
= instr
->dest
.saturate
;
1532 case nir_op_fquantize2f16
: {
1533 /* See also vec4_visitor::emit_pack_half_2x16() */
1534 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1535 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1536 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1538 /* Check for denormal */
1539 src_reg abs_src0
= op
[0];
1540 abs_src0
.abs
= true;
1541 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1542 BRW_CONDITIONAL_L
));
1543 /* Get the appropriately signed zero */
1544 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1545 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1546 brw_imm_ud(0x80000000)));
1547 /* Do the actual F32 -> F16 -> F32 conversion */
1548 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1549 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1550 /* Select that or zero based on normal status */
1551 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1552 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1553 inst
->saturate
= instr
->dest
.saturate
;
1559 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1561 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1562 inst
->saturate
= instr
->dest
.saturate
;
1567 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1569 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1570 inst
->saturate
= instr
->dest
.saturate
;
1574 case nir_op_fddx_coarse
:
1575 case nir_op_fddx_fine
:
1577 case nir_op_fddy_coarse
:
1578 case nir_op_fddy_fine
:
1579 unreachable("derivatives are not valid in vertex shaders");
1587 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1593 enum brw_conditional_mod conditional_mod
=
1594 brw_conditional_for_nir_comparison(instr
->op
);
1596 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1597 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1599 /* Produce a 32-bit boolean result from the DF comparison by selecting
1600 * only the low 32-bit in each DF produced. Do this in a temporary
1601 * so we can then move from there to the result using align16 again
1602 * to honor the original writemask.
1604 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1605 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1606 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1607 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1608 emit(MOV(dst
, src_reg(result
)));
1613 case nir_op_ball_iequal2
:
1614 case nir_op_ball_iequal3
:
1615 case nir_op_ball_iequal4
:
1616 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1618 case nir_op_ball_fequal2
:
1619 case nir_op_ball_fequal3
:
1620 case nir_op_ball_fequal4
: {
1622 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1624 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1625 brw_conditional_for_nir_comparison(instr
->op
)));
1626 emit(MOV(dst
, brw_imm_d(0)));
1627 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1628 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1632 case nir_op_bany_inequal2
:
1633 case nir_op_bany_inequal3
:
1634 case nir_op_bany_inequal4
:
1635 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1637 case nir_op_bany_fnequal2
:
1638 case nir_op_bany_fnequal3
:
1639 case nir_op_bany_fnequal4
: {
1641 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1643 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1644 brw_conditional_for_nir_comparison(instr
->op
)));
1646 emit(MOV(dst
, brw_imm_d(0)));
1647 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1648 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1653 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1654 if (devinfo
->gen
>= 8) {
1655 op
[0] = resolve_source_modifiers(op
[0]);
1657 emit(NOT(dst
, op
[0]));
1661 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1662 if (devinfo
->gen
>= 8) {
1663 op
[0] = resolve_source_modifiers(op
[0]);
1664 op
[1] = resolve_source_modifiers(op
[1]);
1666 emit(XOR(dst
, op
[0], op
[1]));
1670 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1671 if (devinfo
->gen
>= 8) {
1672 op
[0] = resolve_source_modifiers(op
[0]);
1673 op
[1] = resolve_source_modifiers(op
[1]);
1675 emit(OR(dst
, op
[0], op
[1]));
1679 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1680 if (devinfo
->gen
>= 8) {
1681 op
[0] = resolve_source_modifiers(op
[0]);
1682 op
[1] = resolve_source_modifiers(op
[1]);
1684 emit(AND(dst
, op
[0], op
[1]));
1689 emit(MOV(dst
, negate(op
[0])));
1693 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1697 /* We use a MOV with conditional_mod to check if the provided value is
1698 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1699 * source modifier on the source operand to trigger this, as source
1700 * modifiers don't affect the result of the testing against 0.0.
1702 src_reg value
= op
[0];
1704 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1705 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1707 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1708 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1709 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1710 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1715 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1718 case nir_op_fnoise1_1
:
1719 case nir_op_fnoise1_2
:
1720 case nir_op_fnoise1_3
:
1721 case nir_op_fnoise1_4
:
1722 case nir_op_fnoise2_1
:
1723 case nir_op_fnoise2_2
:
1724 case nir_op_fnoise2_3
:
1725 case nir_op_fnoise2_4
:
1726 case nir_op_fnoise3_1
:
1727 case nir_op_fnoise3_2
:
1728 case nir_op_fnoise3_3
:
1729 case nir_op_fnoise3_4
:
1730 case nir_op_fnoise4_1
:
1731 case nir_op_fnoise4_2
:
1732 case nir_op_fnoise4_3
:
1733 case nir_op_fnoise4_4
:
1734 unreachable("not reached: should be handled by lower_noise");
1736 case nir_op_unpack_half_2x16_split_x
:
1737 case nir_op_unpack_half_2x16_split_y
:
1738 case nir_op_pack_half_2x16_split
:
1739 unreachable("not reached: should not occur in vertex shader");
1741 case nir_op_unpack_snorm_2x16
:
1742 case nir_op_unpack_unorm_2x16
:
1743 case nir_op_pack_snorm_2x16
:
1744 case nir_op_pack_unorm_2x16
:
1745 unreachable("not reached: should be handled by lower_packing_builtins");
1747 case nir_op_pack_uvec4_to_uint
:
1748 unreachable("not reached");
1750 case nir_op_pack_uvec2_to_uint
: {
1751 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1752 tmp1
.writemask
= WRITEMASK_X
;
1753 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1754 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1756 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1757 tmp2
.writemask
= WRITEMASK_X
;
1758 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1759 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1761 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1765 case nir_op_pack_64_2x32_split
: {
1766 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1767 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1768 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1769 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1770 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1771 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1772 emit(MOV(dst
, src_reg(result
)));
1776 case nir_op_unpack_64_2x32_split_x
:
1777 case nir_op_unpack_64_2x32_split_y
: {
1778 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1779 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1780 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1781 emit(MOV(tmp
, op
[0]));
1782 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1783 emit(oper
, tmp2
, src_reg(tmp
));
1784 emit(MOV(dst
, src_reg(tmp2
)));
1788 case nir_op_unpack_half_2x16
:
1789 /* As NIR does not guarantee that we have a correct swizzle outside the
1790 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1791 * uses the source operand in an operation with WRITEMASK_Y while our
1792 * source operand has only size 1, it accessed incorrect data producing
1793 * regressions in Piglit. We repeat the swizzle of the first component on the
1794 * rest of components to avoid regressions. In the vec4_visitor IR code path
1795 * this is not needed because the operand has already the correct swizzle.
1797 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1798 emit_unpack_half_2x16(dst
, op
[0]);
1801 case nir_op_pack_half_2x16
:
1802 emit_pack_half_2x16(dst
, op
[0]);
1805 case nir_op_unpack_unorm_4x8
:
1806 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1807 emit_unpack_unorm_4x8(dst
, op
[0]);
1810 case nir_op_pack_unorm_4x8
:
1811 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1812 emit_pack_unorm_4x8(dst
, op
[0]);
1815 case nir_op_unpack_snorm_4x8
:
1816 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1817 emit_unpack_snorm_4x8(dst
, op
[0]);
1820 case nir_op_pack_snorm_4x8
:
1821 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1822 emit_pack_snorm_4x8(dst
, op
[0]);
1825 case nir_op_bitfield_reverse
:
1826 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1827 emit(BFREV(dst
, op
[0]));
1830 case nir_op_bit_count
:
1831 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1832 emit(CBIT(dst
, op
[0]));
1835 case nir_op_ufind_msb
:
1836 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1837 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1840 case nir_op_ifind_msb
: {
1841 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1842 vec4_builder bld
= vec4_builder(this).at_end();
1845 if (devinfo
->gen
< 7) {
1846 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1848 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1850 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1851 * count from the LSB side. If FBH didn't return an error
1852 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1853 * count into an LSB count.
1855 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1857 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1858 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1859 inst
->src
[0].negate
= true;
1864 case nir_op_find_lsb
: {
1865 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1866 vec4_builder bld
= vec4_builder(this).at_end();
1868 if (devinfo
->gen
< 7) {
1869 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1871 /* (x & -x) generates a value that consists of only the LSB of x.
1872 * For all powers of 2, findMSB(y) == findLSB(y).
1874 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1875 src_reg negated_src
= src
;
1877 /* One must be negated, and the other must be non-negated. It
1878 * doesn't matter which is which.
1880 negated_src
.negate
= true;
1883 bld
.AND(temp
, src
, negated_src
);
1884 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1886 bld
.FBL(dst
, op
[0]);
1891 case nir_op_ubitfield_extract
:
1892 case nir_op_ibitfield_extract
:
1893 unreachable("should have been lowered");
1896 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1897 op
[0] = fix_3src_operand(op
[0]);
1898 op
[1] = fix_3src_operand(op
[1]);
1899 op
[2] = fix_3src_operand(op
[2]);
1901 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1905 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1906 emit(BFI1(dst
, op
[0], op
[1]));
1910 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1911 op
[0] = fix_3src_operand(op
[0]);
1912 op
[1] = fix_3src_operand(op
[1]);
1913 op
[2] = fix_3src_operand(op
[2]);
1915 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1918 case nir_op_bitfield_insert
:
1919 unreachable("not reached: should have been lowered");
1922 if (type_sz(op
[0].type
) < 8) {
1923 /* AND(val, 0x80000000) gives the sign bit.
1925 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1928 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1930 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1931 dst
.type
= BRW_REGISTER_TYPE_UD
;
1932 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1934 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1935 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1936 dst
.type
= BRW_REGISTER_TYPE_F
;
1938 if (instr
->dest
.saturate
) {
1939 inst
= emit(MOV(dst
, src_reg(dst
)));
1940 inst
->saturate
= true;
1943 /* For doubles we do the same but we need to consider:
1945 * - We use a MOV with conditional_mod instead of a CMP so that we can
1946 * skip loading a 0.0 immediate. We use a source modifier on the
1947 * source of the MOV so that we flush denormalized values to 0.
1948 * Since we want to compare against 0, this won't alter the result.
1949 * - We need to extract the high 32-bit of each DF where the sign
1951 * - We need to produce a DF result.
1954 /* Check for zero */
1955 src_reg value
= op
[0];
1957 inst
= emit(MOV(dst_null_df(), value
));
1958 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1960 /* AND each high 32-bit channel with 0x80000000u */
1961 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1962 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1963 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1965 /* Add 1.0 to each channel, predicated to skip the cases where the
1966 * channel's value was 0
1968 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1969 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1971 /* Now convert the result from float to double */
1972 emit_conversion_to_double(dst
, src_reg(tmp
), instr
->dest
.saturate
,
1973 BRW_REGISTER_TYPE_F
);
1978 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1979 * -> non-negative val generates 0x00000000.
1980 * Predicated OR sets 1 if val is positive.
1982 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1983 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1984 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1985 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1986 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1990 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1991 emit(SHL(dst
, op
[0], op
[1]));
1995 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1996 emit(ASR(dst
, op
[0], op
[1]));
2000 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
2001 emit(SHR(dst
, op
[0], op
[1]));
2005 if (type_sz(dst
.type
) == 8) {
2006 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
2007 emit(MUL(mul_dst
, op
[1], op
[0]));
2008 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
2009 inst
->saturate
= instr
->dest
.saturate
;
2011 op
[0] = fix_3src_operand(op
[0]);
2012 op
[1] = fix_3src_operand(op
[1]);
2013 op
[2] = fix_3src_operand(op
[2]);
2015 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
2016 inst
->saturate
= instr
->dest
.saturate
;
2021 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
2022 inst
->saturate
= instr
->dest
.saturate
;
2026 enum brw_predicate predicate
;
2027 if (!optimize_predicate(instr
, &predicate
)) {
2028 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
2029 switch (dst
.writemask
) {
2031 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
2034 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
2037 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
2040 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
2043 predicate
= BRW_PREDICATE_NORMAL
;
2047 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
2048 inst
->predicate
= predicate
;
2051 case nir_op_fdot_replicated2
:
2052 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
2053 inst
->saturate
= instr
->dest
.saturate
;
2056 case nir_op_fdot_replicated3
:
2057 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
2058 inst
->saturate
= instr
->dest
.saturate
;
2061 case nir_op_fdot_replicated4
:
2062 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
2063 inst
->saturate
= instr
->dest
.saturate
;
2066 case nir_op_fdph_replicated
:
2067 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
2068 inst
->saturate
= instr
->dest
.saturate
;
2073 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
2077 unreachable("not reached: should be lowered by lower_source mods");
2080 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
2083 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
2087 unreachable("not reached: should be handled by ir_sub_to_add_neg");
2090 unreachable("Unimplemented ALU operation");
2093 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2094 * to sign extend the low bit to 0/~0
2096 if (devinfo
->gen
<= 5 &&
2097 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2098 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2099 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2100 masked
.writemask
= dst
.writemask
;
2101 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2102 src_reg masked_neg
= src_reg(masked
);
2103 masked_neg
.negate
= true;
2104 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2109 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2111 switch (instr
->type
) {
2112 case nir_jump_break
:
2113 emit(BRW_OPCODE_BREAK
);
2116 case nir_jump_continue
:
2117 emit(BRW_OPCODE_CONTINUE
);
2120 case nir_jump_return
:
2123 unreachable("unknown jump");
2127 enum ir_texture_opcode
2128 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2130 enum ir_texture_opcode op
;
2133 case nir_texop_lod
: op
= ir_lod
; break;
2134 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2135 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2136 case nir_texop_tex
: op
= ir_tex
; break;
2137 case nir_texop_tg4
: op
= ir_tg4
; break;
2138 case nir_texop_txb
: op
= ir_txb
; break;
2139 case nir_texop_txd
: op
= ir_txd
; break;
2140 case nir_texop_txf
: op
= ir_txf
; break;
2141 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2142 case nir_texop_txl
: op
= ir_txl
; break;
2143 case nir_texop_txs
: op
= ir_txs
; break;
2144 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2146 unreachable("unknown texture opcode");
2152 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2153 unsigned components
)
2155 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2160 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2162 unsigned texture
= instr
->texture_index
;
2163 unsigned sampler
= instr
->sampler_index
;
2164 src_reg texture_reg
= brw_imm_ud(texture
);
2165 src_reg sampler_reg
= brw_imm_ud(sampler
);
2167 const glsl_type
*coord_type
= NULL
;
2168 src_reg shadow_comparator
;
2169 src_reg offset_value
;
2171 src_reg sample_index
;
2174 const glsl_type
*dest_type
=
2175 glsl_type_for_nir_alu_type(instr
->dest_type
,
2176 nir_tex_instr_dest_size(instr
));
2177 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2179 /* The hardware requires a LOD for buffer textures */
2180 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2183 /* Load the texture operation sources */
2184 uint32_t constant_offset
= 0;
2185 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2186 switch (instr
->src
[i
].src_type
) {
2187 case nir_tex_src_comparator
:
2188 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2189 BRW_REGISTER_TYPE_F
, 1);
2192 case nir_tex_src_coord
: {
2193 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2195 switch (instr
->op
) {
2197 case nir_texop_txf_ms
:
2198 case nir_texop_samples_identical
:
2199 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2201 coord_type
= glsl_type::ivec(src_size
);
2205 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2207 coord_type
= glsl_type::vec(src_size
);
2213 case nir_tex_src_ddx
:
2214 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2215 nir_tex_instr_src_size(instr
, i
));
2218 case nir_tex_src_ddy
:
2219 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2220 nir_tex_instr_src_size(instr
, i
));
2223 case nir_tex_src_lod
:
2224 switch (instr
->op
) {
2227 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2231 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2236 case nir_tex_src_ms_index
: {
2237 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2241 case nir_tex_src_offset
: {
2242 nir_const_value
*const_offset
=
2243 nir_src_as_const_value(instr
->src
[i
].src
);
2244 if (!const_offset
||
2245 !brw_texture_offset(const_offset
->i32
,
2246 nir_tex_instr_src_size(instr
, i
),
2247 &constant_offset
)) {
2249 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2254 case nir_tex_src_texture_offset
: {
2255 /* The highest texture which may be used by this operation is
2256 * the last element of the array. Mark it here, because the generator
2257 * doesn't have enough information to determine the bound.
2259 uint32_t array_size
= instr
->texture_array_size
;
2260 uint32_t max_used
= texture
+ array_size
- 1;
2261 if (instr
->op
== nir_texop_tg4
) {
2262 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2264 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2267 brw_mark_surface_used(&prog_data
->base
, max_used
);
2269 /* Emit code to evaluate the actual indexing expression */
2270 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2271 src_reg
temp(this, glsl_type::uint_type
);
2272 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2273 texture_reg
= emit_uniformize(temp
);
2277 case nir_tex_src_sampler_offset
: {
2278 /* Emit code to evaluate the actual indexing expression */
2279 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2280 src_reg
temp(this, glsl_type::uint_type
);
2281 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2282 sampler_reg
= emit_uniformize(temp
);
2286 case nir_tex_src_projector
:
2287 unreachable("Should be lowered by do_lower_texture_projection");
2289 case nir_tex_src_bias
:
2290 unreachable("LOD bias is not valid for vertex shaders.\n");
2293 unreachable("unknown texture source");
2297 if (instr
->op
== nir_texop_txf_ms
||
2298 instr
->op
== nir_texop_samples_identical
) {
2299 assert(coord_type
!= NULL
);
2300 if (devinfo
->gen
>= 7 &&
2301 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2302 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2304 mcs
= brw_imm_ud(0u);
2308 /* Stuff the channel select bits in the top of the texture offset */
2309 if (instr
->op
== nir_texop_tg4
) {
2310 if (instr
->component
== 1 &&
2311 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2312 /* gather4 sampler is broken for green channel on RG32F --
2313 * we must ask for blue instead.
2315 constant_offset
|= 2 << 16;
2317 constant_offset
|= instr
->component
<< 16;
2321 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2323 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2325 lod
, lod2
, sample_index
,
2326 constant_offset
, offset_value
, mcs
,
2327 texture
, texture_reg
, sampler_reg
);
2331 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2333 nir_ssa_values
[instr
->def
.index
] =
2334 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2337 /* SIMD4x2 64bit data is stored in register space like this:
2339 * r0.0:DF x0 y0 z0 w0
2340 * r1.0:DF x1 y1 z1 w1
2342 * When we need to write data such as this to memory using 32-bit write
2343 * messages we need to shuffle it in this fashion:
2345 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2346 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2348 * We need to do the inverse operation when we read using 32-bit messages,
2349 * which we can do by applying the same exact shuffling on the 64-bit data
2350 * read, only that because the data for each vertex is positioned differently
2351 * we need to apply different channel enables.
2353 * This function takes 64bit data and shuffles it as explained above.
2355 * The @for_write parameter is used to specify if the shuffling is being done
2356 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2357 * write message (for_write = true), or instead we are doing the inverse
2358 * operation and we have just read 64-bit data using a 32-bit messages that we
2359 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2361 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2362 * otherwise the instructions are emitted normally at the end. The function
2363 * returns the last instruction inserted.
2365 * Notice that @src and @dst cannot be the same register.
2368 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2369 bblock_t
*block
, vec4_instruction
*ref
)
2371 assert(type_sz(src
.type
) == 8);
2372 assert(type_sz(dst
.type
) == 8);
2373 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2374 assert(!ref
== !block
);
2376 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2377 vec4_builder(this).at(block
, ref
->next
);
2379 /* Resolve swizzle in src */
2380 vec4_instruction
*inst
;
2381 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2382 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2383 inst
= bld
.MOV(data
, src
);
2384 src
= src_reg(data
);
2387 /* dst+0.XY = src+0.XY */
2388 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2390 /* dst+0.ZW = src+1.XY */
2391 inst
= bld
.group(4, for_write
? 1 : 0)
2392 .MOV(writemask(dst
, WRITEMASK_ZW
),
2393 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2395 /* dst+1.XY = src+0.ZW */
2396 inst
= bld
.group(4, for_write
? 0 : 1)
2397 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2398 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2400 /* dst+1.ZW = src+1.ZW */
2401 inst
= bld
.group(4, 1)
2402 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2403 byte_offset(src
, REG_SIZE
));