2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "glsl/ir_uniform.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 nir_shader
*nir
= prog
->nir
;
40 if (nir
->num_inputs
> 0)
41 nir_setup_inputs(nir
);
43 if (nir
->num_uniforms
> 0)
44 nir_setup_uniforms(nir
);
46 nir_setup_system_values(nir
);
48 /* get the main function and emit it */
49 nir_foreach_overload(nir
, overload
) {
50 assert(strcmp(overload
->function
->name
, "main") == 0);
51 assert(overload
->impl
);
52 nir_emit_impl(overload
->impl
);
57 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
61 switch (instr
->intrinsic
) {
62 case nir_intrinsic_load_vertex_id
:
63 unreachable("should be lowered by lower_vertex_id().");
65 case nir_intrinsic_load_vertex_id_zero_base
:
66 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
67 if (reg
->file
== BAD_FILE
)
68 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
72 case nir_intrinsic_load_base_vertex
:
73 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
74 if (reg
->file
== BAD_FILE
)
75 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
79 case nir_intrinsic_load_instance_id
:
80 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
81 if (reg
->file
== BAD_FILE
)
82 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
92 setup_system_values_block(nir_block
*block
, void *void_visitor
)
94 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
96 nir_foreach_instr(block
, instr
) {
97 if (instr
->type
!= nir_instr_type_intrinsic
)
100 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
101 v
->nir_setup_system_value_intrinsic(intrin
);
108 vec4_visitor::nir_setup_system_values(nir_shader
*shader
)
110 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
112 nir_foreach_overload(shader
, overload
) {
113 assert(strcmp(overload
->function
->name
, "main") == 0);
114 assert(overload
->impl
);
115 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
120 vec4_visitor::nir_setup_inputs(nir_shader
*shader
)
122 nir_inputs
= ralloc_array(mem_ctx
, src_reg
, shader
->num_inputs
);
124 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
125 int offset
= var
->data
.driver_location
;
126 unsigned size
= type_size_vec4(var
->type
);
127 for (unsigned i
= 0; i
< size
; i
++) {
128 src_reg src
= src_reg(ATTR
, var
->data
.location
+ i
, var
->type
);
129 nir_inputs
[offset
+ i
] = src
;
135 vec4_visitor::nir_setup_uniforms(nir_shader
*shader
)
137 uniforms
= shader
->num_uniforms
;
140 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
141 /* UBO's, atomics and samplers don't take up space in the
143 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic() ||
144 type_size_vec4(var
->type
) == 0) {
148 uniform_size
[var
->data
.driver_location
] = type_size_vec4(var
->type
);
150 if (strncmp(var
->name
, "gl_", 3) == 0)
151 nir_setup_builtin_uniform(var
);
153 nir_setup_uniform(var
);
156 /* For ARB_vertex_program, only a single "parameters" variable is
157 * generated to support uniform data.
159 nir_variable
*var
= (nir_variable
*) shader
->uniforms
.get_head();
160 assert(shader
->uniforms
.length() == 1 &&
161 strcmp(var
->name
, "parameters") == 0);
163 assert(var
->data
.driver_location
== 0);
164 uniform_size
[0] = type_size_vec4(var
->type
);
166 struct gl_program_parameter_list
*plist
= prog
->Parameters
;
167 for (unsigned p
= 0; p
< plist
->NumParameters
; p
++) {
168 /* Parameters should be either vec4 uniforms or single component
169 * constants; matrices and other larger types should have been broken
172 assert(plist
->Parameters
[p
].Size
<= 4);
175 for (i
= 0; i
< plist
->Parameters
[p
].Size
; i
++) {
176 stage_prog_data
->param
[p
* 4 + i
] = &plist
->ParameterValues
[p
][i
];
179 static const gl_constant_value zero
= { 0.0 };
180 stage_prog_data
->param
[p
* 4 + i
] = &zero
;
187 vec4_visitor::nir_setup_uniform(nir_variable
*var
)
189 int namelen
= strlen(var
->name
);
191 /* The data for our (non-builtin) uniforms is stored in a series of
192 * gl_uniform_driver_storage structs for each subcomponent that
193 * glGetUniformLocation() could name. We know it's been set up in the same
194 * order we'd walk the type, so walk the list of storage and find anything
195 * with our name, or the prefix of a component that starts with our name.
197 unsigned index
= var
->data
.driver_location
* 4;
198 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
199 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
201 if (storage
->builtin
)
204 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
205 (storage
->name
[namelen
] != 0 &&
206 storage
->name
[namelen
] != '.' &&
207 storage
->name
[namelen
] != '[')) {
211 gl_constant_value
*components
= storage
->storage
;
212 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
213 storage
->type
->matrix_columns
);
215 for (unsigned s
= 0; s
< vector_count
; s
++) {
217 for (i
= 0; i
< storage
->type
->vector_elements
; i
++) {
218 stage_prog_data
->param
[index
++] = components
++;
221 static const gl_constant_value zero
= { 0.0 };
222 stage_prog_data
->param
[index
++] = &zero
;
229 vec4_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
231 const nir_state_slot
*const slots
= var
->state_slots
;
232 assert(var
->state_slots
!= NULL
);
234 unsigned uniform_index
= var
->data
.driver_location
* 4;
235 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
236 /* This state reference has already been setup by ir_to_mesa,
237 * but we'll get the same index back here. We can reference
238 * ParameterValues directly, since unlike brw_fs.cpp, we never
239 * add new state references during compile.
241 int index
= _mesa_add_state_reference(prog
->Parameters
,
242 (gl_state_index
*)slots
[i
].tokens
);
243 gl_constant_value
*values
=
244 &prog
->Parameters
->ParameterValues
[index
][0];
246 for (unsigned j
= 0; j
< 4; j
++)
247 stage_prog_data
->param
[uniform_index
++] =
248 &values
[GET_SWZ(slots
[i
].swizzle
, j
)];
253 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
255 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
257 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
258 unsigned array_elems
=
259 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
261 nir_locals
[reg
->index
] = dst_reg(GRF
, alloc
.allocate(array_elems
));
264 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
266 nir_emit_cf_list(&impl
->body
);
270 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
272 exec_list_validate(list
);
273 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
274 switch (node
->type
) {
276 nir_emit_if(nir_cf_node_as_if(node
));
279 case nir_cf_node_loop
:
280 nir_emit_loop(nir_cf_node_as_loop(node
));
283 case nir_cf_node_block
:
284 nir_emit_block(nir_cf_node_as_block(node
));
288 unreachable("Invalid CFG node block");
294 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
296 /* First, put the condition in f0 */
297 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
298 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
299 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
301 emit(IF(BRW_PREDICATE_NORMAL
));
303 nir_emit_cf_list(&if_stmt
->then_list
);
305 /* note: if the else is empty, dead CF elimination will remove it */
306 emit(BRW_OPCODE_ELSE
);
308 nir_emit_cf_list(&if_stmt
->else_list
);
310 emit(BRW_OPCODE_ENDIF
);
314 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
318 nir_emit_cf_list(&loop
->body
);
320 emit(BRW_OPCODE_WHILE
);
324 vec4_visitor::nir_emit_block(nir_block
*block
)
326 nir_foreach_instr(block
, instr
) {
327 nir_emit_instr(instr
);
332 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
336 switch (instr
->type
) {
337 case nir_instr_type_load_const
:
338 nir_emit_load_const(nir_instr_as_load_const(instr
));
341 case nir_instr_type_intrinsic
:
342 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
345 case nir_instr_type_alu
:
346 nir_emit_alu(nir_instr_as_alu(instr
));
349 case nir_instr_type_jump
:
350 nir_emit_jump(nir_instr_as_jump(instr
));
353 case nir_instr_type_tex
:
354 nir_emit_texture(nir_instr_as_tex(instr
));
357 case nir_instr_type_ssa_undef
:
358 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
362 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
368 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
369 unsigned base_offset
, nir_src
*indirect
)
373 reg
= v
->nir_locals
[nir_reg
->index
];
374 reg
= offset(reg
, base_offset
);
377 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
385 vec4_visitor::get_nir_dest(nir_dest dest
)
388 dst_reg dst
= dst_reg(GRF
, alloc
.allocate(1));
389 nir_ssa_values
[dest
.ssa
.index
] = dst
;
392 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
398 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
400 return retype(get_nir_dest(dest
), type
);
404 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
406 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
410 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
411 unsigned num_components
)
416 assert(src
.ssa
!= NULL
);
417 reg
= nir_ssa_values
[src
.ssa
->index
];
420 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
424 reg
= retype(reg
, type
);
426 src_reg reg_as_src
= src_reg(reg
);
427 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
432 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
433 unsigned num_components
)
435 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
439 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
441 /* if type is not specified, default to signed int */
442 return get_nir_src(src
, nir_type_int
, num_components
);
446 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
448 dst_reg reg
= dst_reg(GRF
, alloc
.allocate(1));
449 reg
.type
= BRW_REGISTER_TYPE_D
;
451 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
453 /* @FIXME: consider emitting vector operations to save some MOVs in
454 * cases where the components are representable in 8 bits.
455 * For now, we emit a MOV for each distinct value.
457 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
458 unsigned writemask
= 1 << i
;
460 if ((remaining
& writemask
) == 0)
463 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
464 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
469 reg
.writemask
= writemask
;
470 emit(MOV(reg
, src_reg(instr
->value
.i
[i
])));
472 remaining
&= ~writemask
;
475 /* Set final writemask */
476 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
478 nir_ssa_values
[instr
->def
.index
] = reg
;
482 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
487 bool has_indirect
= false;
489 switch (instr
->intrinsic
) {
491 case nir_intrinsic_load_input_indirect
:
494 case nir_intrinsic_load_input
: {
495 int offset
= instr
->const_index
[0];
496 src
= nir_inputs
[offset
];
499 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[0],
503 dest
= get_nir_dest(instr
->dest
, src
.type
);
504 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
506 emit(MOV(dest
, src
));
510 case nir_intrinsic_store_output_indirect
:
513 case nir_intrinsic_store_output
: {
514 int varying
= instr
->const_index
[0];
516 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
517 instr
->num_components
);
521 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[1],
525 output_reg
[varying
] = dest
;
529 case nir_intrinsic_get_buffer_size
: {
530 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
531 unsigned ubo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
533 assert(shader
->base
.UniformBlocks
[ubo_index
].IsShaderStorage
);
535 src_reg surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
537 dst_reg result_dst
= get_nir_dest(instr
->dest
);
538 vec4_instruction
*inst
= new(mem_ctx
)
539 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
542 inst
->mlen
= 1; /* always at least one */
543 inst
->src
[1] = src_reg(surf_index
);
545 /* MRF for the first parameter */
546 src_reg lod
= src_reg(0);
547 int param_base
= inst
->base_mrf
;
548 int writemask
= WRITEMASK_X
;
549 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
555 case nir_intrinsic_store_ssbo_indirect
:
558 case nir_intrinsic_store_ssbo
: {
559 assert(devinfo
->gen
>= 7);
563 nir_const_value
*const_uniform_block
=
564 nir_src_as_const_value(instr
->src
[1]);
565 if (const_uniform_block
) {
566 unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
567 const_uniform_block
->u
[0];
568 surf_index
= src_reg(index
);
569 brw_mark_surface_used(&prog_data
->base
, index
);
571 surf_index
= src_reg(this, glsl_type::uint_type
);
572 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
573 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
574 surf_index
= emit_uniformize(surf_index
);
576 brw_mark_surface_used(&prog_data
->base
,
577 prog_data
->base
.binding_table
.ubo_start
+
578 shader_prog
->NumBufferInterfaceBlocks
- 1);
582 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
583 unsigned const_offset_bytes
= 0;
585 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[2], 1)));
587 const_offset_bytes
= instr
->const_index
[0];
588 emit(MOV(dst_reg(offset_reg
), src_reg(const_offset_bytes
)));
592 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
595 unsigned write_mask
= instr
->const_index
[1];
597 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
598 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
599 * typed and untyped messages and across hardware platforms, the
600 * current implementation of the untyped messages will transparently convert
601 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
602 * and enabling only channel X on the SEND instruction.
604 * The above, works well for full vector writes, but not for partial writes
605 * where we want to write some channels and not others, like when we have
606 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
607 * quite restrictive with regards to the channel enables we can configure in
608 * the message descriptor (not all combinations are allowed) we cannot simply
609 * implement these scenarios with a single message while keeping the
610 * aforementioned symmetry in the implementation. For now we de decided that
611 * it is better to keep the symmetry to reduce complexity, so in situations
612 * such as the one described we end up emitting two untyped write messages
613 * (one for xy and another for w).
615 * The code below packs consecutive channels into a single write message,
616 * detects gaps in the vector write and if needed, sends a second message
617 * with the remaining channels. If in the future we decide that we want to
618 * emit a single message at the expense of losing the symmetry in the
619 * implementation we can:
621 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
622 * message payload. In this mode we can write up to 8 offsets and dwords
623 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
624 * and select which of the 8 channels carry data to write by setting the
625 * appropriate writemask in the dst register of the SEND instruction.
626 * It would require to write a new generator opcode specifically for
627 * IvyBridge since we would need to prepare a SIMD8 payload that could
628 * use any channel, not just X.
630 * 2) For Haswell+: Simply send a single write message but set the writemask
631 * on the dst of the SEND instruction to select the channels we want to
632 * write. It would require to modify the current messages to receive
633 * and honor the writemask provided.
635 const vec4_builder bld
= vec4_builder(this).at_end()
636 .annotate(current_annotation
, base_ir
);
638 int swizzle
[4] = { 0, 0, 0, 0};
639 int num_channels
= 0;
640 unsigned skipped_channels
= 0;
641 int num_components
= instr
->num_components
;
642 for (int i
= 0; i
< num_components
; i
++) {
643 /* Check if this channel needs to be written. If so, record the
644 * channel we need to take the data from in the swizzle array
646 int component_mask
= 1 << i
;
647 int write_test
= write_mask
& component_mask
;
649 swizzle
[num_channels
++] = i
;
651 /* If we don't have to write this channel it means we have a gap in the
652 * vector, so write the channels we accumulated until now, if any. Do
653 * the same if this was the last component in the vector.
655 if (!write_test
|| i
== num_components
- 1) {
656 if (num_channels
> 0) {
657 /* We have channels to write, so update the offset we need to
658 * write at to skip the channels we skipped, if any.
660 if (skipped_channels
> 0) {
662 const_offset_bytes
+= 4 * skipped_channels
;
663 offset_reg
= src_reg(const_offset_bytes
);
665 emit(ADD(dst_reg(offset_reg
), offset_reg
,
666 brw_imm_ud(4 * skipped_channels
)));
670 /* Swizzle the data register so we take the data from the channels
671 * we need to write and send the write message. This will write
672 * num_channels consecutive dwords starting at offset.
675 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
676 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
677 1 /* dims */, num_channels
/* size */,
680 /* If we have to do a second write we will have to update the
681 * offset so that we jump over the channels we have just written
684 skipped_channels
= num_channels
;
686 /* Restart the count for the next write message */
690 /* We did not write the current channel, so increase skipped count */
698 case nir_intrinsic_load_ssbo_indirect
:
701 case nir_intrinsic_load_ssbo
: {
702 assert(devinfo
->gen
>= 7);
704 nir_const_value
*const_uniform_block
=
705 nir_src_as_const_value(instr
->src
[0]);
708 if (const_uniform_block
) {
709 unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
710 const_uniform_block
->u
[0];
711 surf_index
= src_reg(index
);
713 brw_mark_surface_used(&prog_data
->base
, index
);
715 surf_index
= src_reg(this, glsl_type::uint_type
);
716 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
717 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
718 surf_index
= emit_uniformize(surf_index
);
720 /* Assume this may touch any UBO. It would be nice to provide
721 * a tighter bound, but the array information is already lowered away.
723 brw_mark_surface_used(&prog_data
->base
,
724 prog_data
->base
.binding_table
.ubo_start
+
725 shader_prog
->NumBufferInterfaceBlocks
- 1);
728 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
729 unsigned const_offset_bytes
= 0;
731 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[1], 1)));
733 const_offset_bytes
= instr
->const_index
[0];
734 emit(MOV(dst_reg(offset_reg
), src_reg(const_offset_bytes
)));
737 /* Read the vector */
738 const vec4_builder bld
= vec4_builder(this).at_end()
739 .annotate(current_annotation
, base_ir
);
741 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
742 1 /* dims */, 4 /* size*/,
744 dst_reg dest
= get_nir_dest(instr
->dest
);
745 read_result
.type
= dest
.type
;
746 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
747 emit(MOV(dest
, read_result
));
752 case nir_intrinsic_ssbo_atomic_add
:
753 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
755 case nir_intrinsic_ssbo_atomic_min
:
756 if (dest
.type
== BRW_REGISTER_TYPE_D
)
757 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
759 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
761 case nir_intrinsic_ssbo_atomic_max
:
762 if (dest
.type
== BRW_REGISTER_TYPE_D
)
763 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
765 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
767 case nir_intrinsic_ssbo_atomic_and
:
768 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
770 case nir_intrinsic_ssbo_atomic_or
:
771 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
773 case nir_intrinsic_ssbo_atomic_xor
:
774 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
776 case nir_intrinsic_ssbo_atomic_exchange
:
777 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
779 case nir_intrinsic_ssbo_atomic_comp_swap
:
780 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
783 case nir_intrinsic_load_vertex_id
:
784 unreachable("should be lowered by lower_vertex_id()");
786 case nir_intrinsic_load_vertex_id_zero_base
:
787 case nir_intrinsic_load_base_vertex
:
788 case nir_intrinsic_load_instance_id
: {
789 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
790 src_reg val
= src_reg(nir_system_values
[sv
]);
791 assert(val
.file
!= BAD_FILE
);
792 dest
= get_nir_dest(instr
->dest
, val
.type
);
793 emit(MOV(dest
, val
));
797 case nir_intrinsic_load_uniform_indirect
:
800 case nir_intrinsic_load_uniform
: {
801 dest
= get_nir_dest(instr
->dest
);
803 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0]));
804 src
.reg_offset
= instr
->const_index
[1];
807 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
808 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
811 emit(MOV(dest
, src
));
815 case nir_intrinsic_atomic_counter_read
:
816 case nir_intrinsic_atomic_counter_inc
:
817 case nir_intrinsic_atomic_counter_dec
: {
818 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
819 (unsigned) instr
->const_index
[0];
820 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
821 instr
->num_components
);
822 dest
= get_nir_dest(instr
->dest
);
824 switch (instr
->intrinsic
) {
825 case nir_intrinsic_atomic_counter_inc
:
826 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
827 src_reg(), src_reg());
829 case nir_intrinsic_atomic_counter_dec
:
830 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
831 src_reg(), src_reg());
833 case nir_intrinsic_atomic_counter_read
:
834 emit_untyped_surface_read(surf_index
, dest
, offset
);
837 unreachable("Unreachable");
840 brw_mark_surface_used(stage_prog_data
, surf_index
);
844 case nir_intrinsic_load_ubo_indirect
:
847 case nir_intrinsic_load_ubo
: {
848 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
851 dest
= get_nir_dest(instr
->dest
);
853 if (const_block_index
) {
854 /* The block index is a constant, so just emit the binding table entry
857 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
858 const_block_index
->u
[0]);
860 /* The block index is not a constant. Evaluate the index expression
861 * per-channel and add the base UBO index; we have to select a value
862 * from any live channel.
864 surf_index
= src_reg(this, glsl_type::uint_type
);
865 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
866 instr
->num_components
),
867 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
868 surf_index
= emit_uniformize(surf_index
);
870 /* Assume this may touch any UBO. It would be nice to provide
871 * a tighter bound, but the array information is already lowered away.
873 brw_mark_surface_used(&prog_data
->base
,
874 prog_data
->base
.binding_table
.ubo_start
+
875 shader_prog
->NumBufferInterfaceBlocks
- 1);
878 unsigned const_offset
= instr
->const_index
[0];
882 offset
= src_reg(const_offset
/ 16);
884 offset
= src_reg(this, glsl_type::uint_type
);
885 emit(SHR(dst_reg(offset
), get_nir_src(instr
->src
[1], nir_type_int
, 1),
889 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
890 packed_consts
.type
= dest
.type
;
892 emit_pull_constant_load_reg(dst_reg(packed_consts
),
895 NULL
, NULL
/* before_block/inst */);
897 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
898 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
899 const_offset
% 16 / 4,
900 const_offset
% 16 / 4,
901 const_offset
% 16 / 4);
903 emit(MOV(dest
, packed_consts
));
907 case nir_intrinsic_memory_barrier
: {
908 const vec4_builder bld
=
909 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
910 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
911 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
917 unreachable("Unknown intrinsic");
922 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
925 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
926 dest
= get_nir_dest(instr
->dest
);
929 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
931 unsigned surf_index
= prog_data
->base
.binding_table
.ubo_start
+
933 surface
= src_reg(surf_index
);
934 brw_mark_surface_used(&prog_data
->base
, surf_index
);
936 surface
= src_reg(this, glsl_type::uint_type
);
937 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
938 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
940 /* Assume this may touch any UBO. This is the same we do for other
941 * UBO/SSBO accesses with non-constant surface.
943 brw_mark_surface_used(&prog_data
->base
,
944 prog_data
->base
.binding_table
.ubo_start
+
945 shader_prog
->NumBufferInterfaceBlocks
- 1);
948 src_reg offset
= get_nir_src(instr
->src
[1], 1);
949 src_reg data1
= get_nir_src(instr
->src
[2], 1);
951 if (op
== BRW_AOP_CMPWR
)
952 data2
= get_nir_src(instr
->src
[3], 1);
954 /* Emit the actual atomic operation operation */
955 const vec4_builder bld
=
956 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
958 src_reg atomic_result
=
959 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
961 1 /* dims */, 1 /* rsize */,
964 dest
.type
= atomic_result
.type
;
965 bld
.MOV(dest
, atomic_result
);
969 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
971 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
974 static enum brw_conditional_mod
975 brw_conditional_for_nir_comparison(nir_op op
)
981 return BRW_CONDITIONAL_L
;
986 return BRW_CONDITIONAL_GE
;
990 case nir_op_ball_fequal2
:
991 case nir_op_ball_iequal2
:
992 case nir_op_ball_fequal3
:
993 case nir_op_ball_iequal3
:
994 case nir_op_ball_fequal4
:
995 case nir_op_ball_iequal4
:
996 return BRW_CONDITIONAL_Z
;
1000 case nir_op_bany_fnequal2
:
1001 case nir_op_bany_inequal2
:
1002 case nir_op_bany_fnequal3
:
1003 case nir_op_bany_inequal3
:
1004 case nir_op_bany_fnequal4
:
1005 case nir_op_bany_inequal4
:
1006 return BRW_CONDITIONAL_NZ
;
1009 unreachable("not reached: bad operation for comparison");
1014 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1016 vec4_instruction
*inst
;
1018 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
1019 nir_op_infos
[instr
->op
].output_type
);
1020 dst
.writemask
= instr
->dest
.write_mask
;
1023 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1024 op
[i
] = get_nir_src(instr
->src
[i
].src
,
1025 nir_op_infos
[instr
->op
].input_types
[i
], 4);
1026 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1027 op
[i
].abs
= instr
->src
[i
].abs
;
1028 op
[i
].negate
= instr
->src
[i
].negate
;
1031 switch (instr
->op
) {
1034 inst
= emit(MOV(dst
, op
[0]));
1035 inst
->saturate
= instr
->dest
.saturate
;
1041 unreachable("not reached: should be handled by lower_vec_to_movs()");
1045 inst
= emit(MOV(dst
, op
[0]));
1046 inst
->saturate
= instr
->dest
.saturate
;
1051 inst
= emit(MOV(dst
, op
[0]));
1057 inst
= emit(ADD(dst
, op
[0], op
[1]));
1058 inst
->saturate
= instr
->dest
.saturate
;
1062 inst
= emit(MUL(dst
, op
[0], op
[1]));
1063 inst
->saturate
= instr
->dest
.saturate
;
1067 if (devinfo
->gen
< 8) {
1068 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1069 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1071 /* For integer multiplication, the MUL uses the low 16 bits of one of
1072 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1073 * accumulates in the contribution of the upper 16 bits of that
1074 * operand. If we can determine that one of the args is in the low
1075 * 16 bits, though, we can just emit a single MUL.
1077 if (value0
&& value0
->u
[0] < (1 << 16)) {
1078 if (devinfo
->gen
< 7)
1079 emit(MUL(dst
, op
[0], op
[1]));
1081 emit(MUL(dst
, op
[1], op
[0]));
1082 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
1083 if (devinfo
->gen
< 7)
1084 emit(MUL(dst
, op
[1], op
[0]));
1086 emit(MUL(dst
, op
[0], op
[1]));
1088 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1090 emit(MUL(acc
, op
[0], op
[1]));
1091 emit(MACH(dst_null_d(), op
[0], op
[1]));
1092 emit(MOV(dst
, src_reg(acc
)));
1095 emit(MUL(dst
, op
[0], op
[1]));
1100 case nir_op_imul_high
:
1101 case nir_op_umul_high
: {
1102 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1104 emit(MUL(acc
, op
[0], op
[1]));
1105 emit(MACH(dst
, op
[0], op
[1]));
1110 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1111 inst
->saturate
= instr
->dest
.saturate
;
1115 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1116 inst
->saturate
= instr
->dest
.saturate
;
1120 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1121 inst
->saturate
= instr
->dest
.saturate
;
1125 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1126 inst
->saturate
= instr
->dest
.saturate
;
1130 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1131 inst
->saturate
= instr
->dest
.saturate
;
1136 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1140 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1144 unreachable("not reached: should be handled by ldexp_to_arith()");
1147 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1148 inst
->saturate
= instr
->dest
.saturate
;
1152 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1161 case nir_op_uadd_carry
: {
1162 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1164 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1165 emit(MOV(dst
, src_reg(acc
)));
1169 case nir_op_usub_borrow
: {
1170 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1172 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1173 emit(MOV(dst
, src_reg(acc
)));
1178 inst
= emit(RNDZ(dst
, op
[0]));
1179 inst
->saturate
= instr
->dest
.saturate
;
1182 case nir_op_fceil
: {
1183 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1185 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1186 instr
->src
[0].src
.ssa
->num_components
:
1187 instr
->src
[0].src
.reg
.reg
->num_components
);
1189 op
[0].negate
= !op
[0].negate
;
1190 emit(RNDD(dst_reg(tmp
), op
[0]));
1192 inst
= emit(MOV(dst
, tmp
));
1193 inst
->saturate
= instr
->dest
.saturate
;
1198 inst
= emit(RNDD(dst
, op
[0]));
1199 inst
->saturate
= instr
->dest
.saturate
;
1203 inst
= emit(FRC(dst
, op
[0]));
1204 inst
->saturate
= instr
->dest
.saturate
;
1207 case nir_op_fround_even
:
1208 inst
= emit(RNDE(dst
, op
[0]));
1209 inst
->saturate
= instr
->dest
.saturate
;
1215 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1216 inst
->saturate
= instr
->dest
.saturate
;
1222 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1223 inst
->saturate
= instr
->dest
.saturate
;
1227 case nir_op_fddx_coarse
:
1228 case nir_op_fddx_fine
:
1230 case nir_op_fddy_coarse
:
1231 case nir_op_fddy_fine
:
1232 unreachable("derivatives are not valid in vertex shaders");
1244 emit(CMP(dst
, op
[0], op
[1],
1245 brw_conditional_for_nir_comparison(instr
->op
)));
1248 case nir_op_ball_fequal2
:
1249 case nir_op_ball_iequal2
:
1250 case nir_op_ball_fequal3
:
1251 case nir_op_ball_iequal3
:
1252 case nir_op_ball_fequal4
:
1253 case nir_op_ball_iequal4
: {
1254 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1256 switch (instr
->op
) {
1257 case nir_op_ball_fequal2
:
1258 case nir_op_ball_iequal2
:
1259 tmp
.writemask
= WRITEMASK_XY
;
1261 case nir_op_ball_fequal3
:
1262 case nir_op_ball_iequal3
:
1263 tmp
.writemask
= WRITEMASK_XYZ
;
1265 case nir_op_ball_fequal4
:
1266 case nir_op_ball_iequal4
:
1267 tmp
.writemask
= WRITEMASK_XYZW
;
1270 unreachable("not reached");
1273 emit(CMP(tmp
, op
[0], op
[1],
1274 brw_conditional_for_nir_comparison(instr
->op
)));
1275 emit(MOV(dst
, src_reg(0)));
1276 inst
= emit(MOV(dst
, src_reg(~0)));
1277 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1281 case nir_op_bany_fnequal2
:
1282 case nir_op_bany_inequal2
:
1283 case nir_op_bany_fnequal3
:
1284 case nir_op_bany_inequal3
:
1285 case nir_op_bany_fnequal4
:
1286 case nir_op_bany_inequal4
: {
1287 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1289 switch (instr
->op
) {
1290 case nir_op_bany_fnequal2
:
1291 case nir_op_bany_inequal2
:
1292 tmp
.writemask
= WRITEMASK_XY
;
1294 case nir_op_bany_fnequal3
:
1295 case nir_op_bany_inequal3
:
1296 tmp
.writemask
= WRITEMASK_XYZ
;
1298 case nir_op_bany_fnequal4
:
1299 case nir_op_bany_inequal4
:
1300 tmp
.writemask
= WRITEMASK_XYZW
;
1303 unreachable("not reached");
1306 emit(CMP(tmp
, op
[0], op
[1],
1307 brw_conditional_for_nir_comparison(instr
->op
)));
1309 emit(MOV(dst
, src_reg(0)));
1310 inst
= emit(MOV(dst
, src_reg(~0)));
1311 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1316 if (devinfo
->gen
>= 8) {
1317 op
[0] = resolve_source_modifiers(op
[0]);
1319 emit(NOT(dst
, op
[0]));
1323 if (devinfo
->gen
>= 8) {
1324 op
[0] = resolve_source_modifiers(op
[0]);
1325 op
[1] = resolve_source_modifiers(op
[1]);
1327 emit(XOR(dst
, op
[0], op
[1]));
1331 if (devinfo
->gen
>= 8) {
1332 op
[0] = resolve_source_modifiers(op
[0]);
1333 op
[1] = resolve_source_modifiers(op
[1]);
1335 emit(OR(dst
, op
[0], op
[1]));
1339 if (devinfo
->gen
>= 8) {
1340 op
[0] = resolve_source_modifiers(op
[0]);
1341 op
[1] = resolve_source_modifiers(op
[1]);
1343 emit(AND(dst
, op
[0], op
[1]));
1347 emit(AND(dst
, op
[0], src_reg(1)));
1351 op
[0].type
= BRW_REGISTER_TYPE_D
;
1352 dst
.type
= BRW_REGISTER_TYPE_D
;
1353 emit(AND(dst
, op
[0], src_reg(0x3f800000u
)));
1354 dst
.type
= BRW_REGISTER_TYPE_F
;
1358 emit(CMP(dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1362 emit(CMP(dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1365 case nir_op_fnoise1_1
:
1366 case nir_op_fnoise1_2
:
1367 case nir_op_fnoise1_3
:
1368 case nir_op_fnoise1_4
:
1369 case nir_op_fnoise2_1
:
1370 case nir_op_fnoise2_2
:
1371 case nir_op_fnoise2_3
:
1372 case nir_op_fnoise2_4
:
1373 case nir_op_fnoise3_1
:
1374 case nir_op_fnoise3_2
:
1375 case nir_op_fnoise3_3
:
1376 case nir_op_fnoise3_4
:
1377 case nir_op_fnoise4_1
:
1378 case nir_op_fnoise4_2
:
1379 case nir_op_fnoise4_3
:
1380 case nir_op_fnoise4_4
:
1381 unreachable("not reached: should be handled by lower_noise");
1383 case nir_op_unpack_half_2x16_split_x
:
1384 case nir_op_unpack_half_2x16_split_y
:
1385 case nir_op_pack_half_2x16_split
:
1386 unreachable("not reached: should not occur in vertex shader");
1388 case nir_op_unpack_snorm_2x16
:
1389 case nir_op_unpack_unorm_2x16
:
1390 case nir_op_pack_snorm_2x16
:
1391 case nir_op_pack_unorm_2x16
:
1392 unreachable("not reached: should be handled by lower_packing_builtins");
1394 case nir_op_unpack_half_2x16
:
1395 /* As NIR does not guarantee that we have a correct swizzle outside the
1396 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1397 * uses the source operand in an operation with WRITEMASK_Y while our
1398 * source operand has only size 1, it accessed incorrect data producing
1399 * regressions in Piglit. We repeat the swizzle of the first component on the
1400 * rest of components to avoid regressions. In the vec4_visitor IR code path
1401 * this is not needed because the operand has already the correct swizzle.
1403 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1404 emit_unpack_half_2x16(dst
, op
[0]);
1407 case nir_op_pack_half_2x16
:
1408 emit_pack_half_2x16(dst
, op
[0]);
1411 case nir_op_unpack_unorm_4x8
:
1412 emit_unpack_unorm_4x8(dst
, op
[0]);
1415 case nir_op_pack_unorm_4x8
:
1416 emit_pack_unorm_4x8(dst
, op
[0]);
1419 case nir_op_unpack_snorm_4x8
:
1420 emit_unpack_snorm_4x8(dst
, op
[0]);
1423 case nir_op_pack_snorm_4x8
:
1424 emit_pack_snorm_4x8(dst
, op
[0]);
1427 case nir_op_bitfield_reverse
:
1428 emit(BFREV(dst
, op
[0]));
1431 case nir_op_bit_count
:
1432 emit(CBIT(dst
, op
[0]));
1435 case nir_op_ufind_msb
:
1436 case nir_op_ifind_msb
: {
1437 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1439 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1440 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1442 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1443 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1444 * subtract the result from 31 to convert the MSB count into an LSB count.
1447 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1448 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1449 emit(MOV(dst
, temp
));
1451 src_reg src_tmp
= src_reg(dst
);
1452 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1454 src_tmp
.negate
= true;
1455 inst
= emit(ADD(dst
, src_tmp
, src_reg(31)));
1456 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1460 case nir_op_find_lsb
:
1461 emit(FBL(dst
, op
[0]));
1464 case nir_op_ubitfield_extract
:
1465 case nir_op_ibitfield_extract
:
1466 op
[0] = fix_3src_operand(op
[0]);
1467 op
[1] = fix_3src_operand(op
[1]);
1468 op
[2] = fix_3src_operand(op
[2]);
1470 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1474 emit(BFI1(dst
, op
[0], op
[1]));
1478 op
[0] = fix_3src_operand(op
[0]);
1479 op
[1] = fix_3src_operand(op
[1]);
1480 op
[2] = fix_3src_operand(op
[2]);
1482 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1485 case nir_op_bitfield_insert
:
1486 unreachable("not reached: should be handled by "
1487 "lower_instructions::bitfield_insert_to_bfm_bfi");
1490 /* AND(val, 0x80000000) gives the sign bit.
1492 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1495 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1497 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1498 dst
.type
= BRW_REGISTER_TYPE_UD
;
1499 emit(AND(dst
, op
[0], src_reg(0x80000000u
)));
1501 inst
= emit(OR(dst
, src_reg(dst
), src_reg(0x3f800000u
)));
1502 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1503 dst
.type
= BRW_REGISTER_TYPE_F
;
1505 if (instr
->dest
.saturate
) {
1506 inst
= emit(MOV(dst
, src_reg(dst
)));
1507 inst
->saturate
= true;
1512 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1513 * -> non-negative val generates 0x00000000.
1514 * Predicated OR sets 1 if val is positive.
1516 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1517 emit(ASR(dst
, op
[0], src_reg(31)));
1518 inst
= emit(OR(dst
, src_reg(dst
), src_reg(1)));
1519 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1523 emit(SHL(dst
, op
[0], op
[1]));
1527 emit(ASR(dst
, op
[0], op
[1]));
1531 emit(SHR(dst
, op
[0], op
[1]));
1535 op
[0] = fix_3src_operand(op
[0]);
1536 op
[1] = fix_3src_operand(op
[1]);
1537 op
[2] = fix_3src_operand(op
[2]);
1539 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1540 inst
->saturate
= instr
->dest
.saturate
;
1544 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1545 inst
->saturate
= instr
->dest
.saturate
;
1549 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1550 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1551 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1554 case nir_op_fdot_replicated2
:
1555 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1556 inst
->saturate
= instr
->dest
.saturate
;
1559 case nir_op_fdot_replicated3
:
1560 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1561 inst
->saturate
= instr
->dest
.saturate
;
1564 case nir_op_fdot_replicated4
:
1565 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1566 inst
->saturate
= instr
->dest
.saturate
;
1569 case nir_op_fdph_replicated
:
1570 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1571 inst
->saturate
= instr
->dest
.saturate
;
1576 case nir_op_bany4
: {
1577 dst_reg tmp
= dst_reg(this, glsl_type::bool_type
);
1578 tmp
.writemask
= brw_writemask_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1580 emit(CMP(tmp
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1582 emit(MOV(dst
, src_reg(0)));
1583 inst
= emit(MOV(dst
, src_reg(~0)));
1584 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1593 unreachable("not reached: should be lowered by lower_source mods");
1596 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1599 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1603 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1606 unreachable("Unimplemented ALU operation");
1609 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1610 * to sign extend the low bit to 0/~0
1612 if (devinfo
->gen
<= 5 &&
1613 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1614 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1615 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1616 masked
.writemask
= dst
.writemask
;
1617 emit(AND(masked
, src_reg(dst
), src_reg(1)));
1618 src_reg masked_neg
= src_reg(masked
);
1619 masked_neg
.negate
= true;
1620 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1625 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1627 switch (instr
->type
) {
1628 case nir_jump_break
:
1629 emit(BRW_OPCODE_BREAK
);
1632 case nir_jump_continue
:
1633 emit(BRW_OPCODE_CONTINUE
);
1636 case nir_jump_return
:
1639 unreachable("unknown jump");
1643 enum ir_texture_opcode
1644 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1646 enum ir_texture_opcode op
;
1649 case nir_texop_lod
: op
= ir_lod
; break;
1650 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1651 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1652 case nir_texop_tex
: op
= ir_tex
; break;
1653 case nir_texop_tg4
: op
= ir_tg4
; break;
1654 case nir_texop_txb
: op
= ir_txb
; break;
1655 case nir_texop_txd
: op
= ir_txd
; break;
1656 case nir_texop_txf
: op
= ir_txf
; break;
1657 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1658 case nir_texop_txl
: op
= ir_txl
; break;
1659 case nir_texop_txs
: op
= ir_txs
; break;
1661 unreachable("unknown texture opcode");
1667 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1668 unsigned components
)
1671 case nir_type_float
:
1672 return glsl_type::vec(components
);
1674 return glsl_type::ivec(components
);
1675 case nir_type_unsigned
:
1676 return glsl_type::uvec(components
);
1678 return glsl_type::bvec(components
);
1680 return glsl_type::error_type
;
1683 return glsl_type::error_type
;
1687 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1689 unsigned sampler
= instr
->sampler_index
;
1690 src_reg sampler_reg
= src_reg(sampler
);
1692 const glsl_type
*coord_type
= NULL
;
1693 src_reg shadow_comparitor
;
1694 src_reg offset_value
;
1696 src_reg sample_index
;
1699 const glsl_type
*dest_type
=
1700 glsl_type_for_nir_alu_type(instr
->dest_type
,
1701 nir_tex_instr_dest_size(instr
));
1702 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1704 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1705 * emitting anything other than setting up the constant result.
1707 if (instr
->op
== nir_texop_tg4
) {
1708 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], instr
->component
);
1709 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1710 emit(MOV(dest
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
1715 /* Load the texture operation sources */
1716 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1717 switch (instr
->src
[i
].src_type
) {
1718 case nir_tex_src_comparitor
:
1719 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1720 BRW_REGISTER_TYPE_F
, 1);
1723 case nir_tex_src_coord
: {
1724 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1726 switch (instr
->op
) {
1728 case nir_texop_txf_ms
:
1729 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1731 coord_type
= glsl_type::ivec(src_size
);
1735 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1737 coord_type
= glsl_type::vec(src_size
);
1743 case nir_tex_src_ddx
:
1744 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1745 nir_tex_instr_src_size(instr
, i
));
1748 case nir_tex_src_ddy
:
1749 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1750 nir_tex_instr_src_size(instr
, i
));
1753 case nir_tex_src_lod
:
1754 switch (instr
->op
) {
1757 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1761 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1766 case nir_tex_src_ms_index
: {
1767 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1768 assert(coord_type
!= NULL
);
1769 if (devinfo
->gen
>= 7 &&
1770 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1771 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1775 mcs
= retype(mcs
, BRW_REGISTER_TYPE_UD
);
1779 case nir_tex_src_offset
:
1780 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1783 case nir_tex_src_sampler_offset
: {
1784 /* The highest sampler which may be used by this operation is
1785 * the last element of the array. Mark it here, because the generator
1786 * doesn't have enough information to determine the bound.
1788 uint32_t array_size
= instr
->sampler_array_size
;
1789 uint32_t max_used
= sampler
+ array_size
- 1;
1790 if (instr
->op
== nir_texop_tg4
) {
1791 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1793 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1796 brw_mark_surface_used(&prog_data
->base
, max_used
);
1798 /* Emit code to evaluate the actual indexing expression */
1799 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1800 src_reg
temp(this, glsl_type::uint_type
);
1801 emit(ADD(dst_reg(temp
), src
, src_reg(sampler
)));
1802 sampler_reg
= emit_uniformize(temp
);
1806 case nir_tex_src_projector
:
1807 unreachable("Should be lowered by do_lower_texture_projection");
1809 case nir_tex_src_bias
:
1810 unreachable("LOD bias is not valid for vertex shaders.\n");
1813 unreachable("unknown texture source");
1817 uint32_t constant_offset
= 0;
1818 for (unsigned i
= 0; i
< 3; i
++) {
1819 if (instr
->const_offset
[i
] != 0) {
1820 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1825 /* Stuff the channel select bits in the top of the texture offset */
1826 if (instr
->op
== nir_texop_tg4
)
1827 constant_offset
|= gather_channel(instr
->component
, sampler
) << 16;
1829 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1831 bool is_cube_array
=
1832 instr
->op
== nir_texop_txs
&&
1833 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1836 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1838 lod
, lod2
, sample_index
,
1839 constant_offset
, offset_value
,
1840 mcs
, is_cube_array
, sampler
, sampler_reg
);
1844 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1846 nir_ssa_values
[instr
->def
.index
] = dst_reg(GRF
, alloc
.allocate(1));