2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_setup_system_values();
43 /* get the main function and emit it */
44 nir_foreach_overload(nir
, overload
) {
45 assert(strcmp(overload
->function
->name
, "main") == 0);
46 assert(overload
->impl
);
47 nir_emit_impl(overload
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
63 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
67 case nir_intrinsic_load_base_vertex
:
68 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
69 if (reg
->file
== BAD_FILE
)
70 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
74 case nir_intrinsic_load_instance_id
:
75 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
76 if (reg
->file
== BAD_FILE
)
77 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
87 setup_system_values_block(nir_block
*block
, void *void_visitor
)
89 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
91 nir_foreach_instr(block
, instr
) {
92 if (instr
->type
!= nir_instr_type_intrinsic
)
95 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
96 v
->nir_setup_system_value_intrinsic(intrin
);
103 vec4_visitor::nir_setup_system_values()
105 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
106 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
107 nir_system_values
[i
] = dst_reg();
110 nir_foreach_overload(nir
, overload
) {
111 assert(strcmp(overload
->function
->name
, "main") == 0);
112 assert(overload
->impl
);
113 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
118 vec4_visitor::nir_setup_uniforms()
120 uniforms
= nir
->num_uniforms
/ 16;
124 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
126 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
127 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
128 nir_locals
[i
] = dst_reg();
131 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
132 unsigned array_elems
=
133 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
135 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(array_elems
));
138 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
140 nir_emit_cf_list(&impl
->body
);
144 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
146 exec_list_validate(list
);
147 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
148 switch (node
->type
) {
150 nir_emit_if(nir_cf_node_as_if(node
));
153 case nir_cf_node_loop
:
154 nir_emit_loop(nir_cf_node_as_loop(node
));
157 case nir_cf_node_block
:
158 nir_emit_block(nir_cf_node_as_block(node
));
162 unreachable("Invalid CFG node block");
168 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
170 /* First, put the condition in f0 */
171 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
172 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
173 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
175 /* We can just predicate based on the X channel, as the condition only
176 * goes on its own line */
177 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
179 nir_emit_cf_list(&if_stmt
->then_list
);
181 /* note: if the else is empty, dead CF elimination will remove it */
182 emit(BRW_OPCODE_ELSE
);
184 nir_emit_cf_list(&if_stmt
->else_list
);
186 emit(BRW_OPCODE_ENDIF
);
190 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
194 nir_emit_cf_list(&loop
->body
);
196 emit(BRW_OPCODE_WHILE
);
200 vec4_visitor::nir_emit_block(nir_block
*block
)
202 nir_foreach_instr(block
, instr
) {
203 nir_emit_instr(instr
);
208 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
212 switch (instr
->type
) {
213 case nir_instr_type_load_const
:
214 nir_emit_load_const(nir_instr_as_load_const(instr
));
217 case nir_instr_type_intrinsic
:
218 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
221 case nir_instr_type_alu
:
222 nir_emit_alu(nir_instr_as_alu(instr
));
225 case nir_instr_type_jump
:
226 nir_emit_jump(nir_instr_as_jump(instr
));
229 case nir_instr_type_tex
:
230 nir_emit_texture(nir_instr_as_tex(instr
));
233 case nir_instr_type_ssa_undef
:
234 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
238 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
244 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
245 unsigned base_offset
, nir_src
*indirect
)
249 reg
= v
->nir_locals
[nir_reg
->index
];
250 reg
= offset(reg
, base_offset
);
253 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
261 vec4_visitor::get_nir_dest(nir_dest dest
)
264 dst_reg dst
= dst_reg(VGRF
, alloc
.allocate(1));
265 nir_ssa_values
[dest
.ssa
.index
] = dst
;
268 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
274 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
276 return retype(get_nir_dest(dest
), type
);
280 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
282 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
286 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
287 unsigned num_components
)
292 assert(src
.ssa
!= NULL
);
293 reg
= nir_ssa_values
[src
.ssa
->index
];
296 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
300 reg
= retype(reg
, type
);
302 src_reg reg_as_src
= src_reg(reg
);
303 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
308 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
309 unsigned num_components
)
311 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
315 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
317 /* if type is not specified, default to signed int */
318 return get_nir_src(src
, nir_type_int
, num_components
);
322 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
324 dst_reg reg
= dst_reg(VGRF
, alloc
.allocate(1));
325 reg
.type
= BRW_REGISTER_TYPE_D
;
327 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
329 /* @FIXME: consider emitting vector operations to save some MOVs in
330 * cases where the components are representable in 8 bits.
331 * For now, we emit a MOV for each distinct value.
333 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
334 unsigned writemask
= 1 << i
;
336 if ((remaining
& writemask
) == 0)
339 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
340 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
345 reg
.writemask
= writemask
;
346 emit(MOV(reg
, brw_imm_d(instr
->value
.i
[i
])));
348 remaining
&= ~writemask
;
351 /* Set final writemask */
352 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
354 nir_ssa_values
[instr
->def
.index
] = reg
;
358 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
363 switch (instr
->intrinsic
) {
365 case nir_intrinsic_load_input
: {
366 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
368 /* We set EmitNoIndirectInput for VS */
369 assert(const_offset
);
371 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u
[0],
372 glsl_type::uvec4_type
);
374 dest
= get_nir_dest(instr
->dest
, src
.type
);
375 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
377 emit(MOV(dest
, src
));
381 case nir_intrinsic_store_output
: {
382 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
383 assert(const_offset
);
385 int varying
= instr
->const_index
[0] + const_offset
->u
[0];
387 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
388 instr
->num_components
);
390 output_reg
[varying
] = dst_reg(src
);
394 case nir_intrinsic_get_buffer_size
: {
395 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
396 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
398 const unsigned index
=
399 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
400 dst_reg result_dst
= get_nir_dest(instr
->dest
);
401 vec4_instruction
*inst
= new(mem_ctx
)
402 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
405 inst
->mlen
= 1; /* always at least one */
406 inst
->src
[1] = brw_imm_ud(index
);
408 /* MRF for the first parameter */
409 src_reg lod
= brw_imm_d(0);
410 int param_base
= inst
->base_mrf
;
411 int writemask
= WRITEMASK_X
;
412 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
416 brw_mark_surface_used(&prog_data
->base
, index
);
420 case nir_intrinsic_store_ssbo
: {
421 assert(devinfo
->gen
>= 7);
425 nir_const_value
*const_uniform_block
=
426 nir_src_as_const_value(instr
->src
[1]);
427 if (const_uniform_block
) {
428 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
429 const_uniform_block
->u
[0];
430 surf_index
= brw_imm_ud(index
);
431 brw_mark_surface_used(&prog_data
->base
, index
);
433 surf_index
= src_reg(this, glsl_type::uint_type
);
434 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
435 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
436 surf_index
= emit_uniformize(surf_index
);
438 brw_mark_surface_used(&prog_data
->base
,
439 prog_data
->base
.binding_table
.ssbo_start
+
440 nir
->info
.num_ssbos
- 1);
445 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
447 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
449 offset_reg
= get_nir_src(instr
->src
[2], 1);
453 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
456 unsigned write_mask
= instr
->const_index
[0];
458 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
459 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
460 * typed and untyped messages and across hardware platforms, the
461 * current implementation of the untyped messages will transparently convert
462 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
463 * and enabling only channel X on the SEND instruction.
465 * The above, works well for full vector writes, but not for partial writes
466 * where we want to write some channels and not others, like when we have
467 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
468 * quite restrictive with regards to the channel enables we can configure in
469 * the message descriptor (not all combinations are allowed) we cannot simply
470 * implement these scenarios with a single message while keeping the
471 * aforementioned symmetry in the implementation. For now we de decided that
472 * it is better to keep the symmetry to reduce complexity, so in situations
473 * such as the one described we end up emitting two untyped write messages
474 * (one for xy and another for w).
476 * The code below packs consecutive channels into a single write message,
477 * detects gaps in the vector write and if needed, sends a second message
478 * with the remaining channels. If in the future we decide that we want to
479 * emit a single message at the expense of losing the symmetry in the
480 * implementation we can:
482 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
483 * message payload. In this mode we can write up to 8 offsets and dwords
484 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
485 * and select which of the 8 channels carry data to write by setting the
486 * appropriate writemask in the dst register of the SEND instruction.
487 * It would require to write a new generator opcode specifically for
488 * IvyBridge since we would need to prepare a SIMD8 payload that could
489 * use any channel, not just X.
491 * 2) For Haswell+: Simply send a single write message but set the writemask
492 * on the dst of the SEND instruction to select the channels we want to
493 * write. It would require to modify the current messages to receive
494 * and honor the writemask provided.
496 const vec4_builder bld
= vec4_builder(this).at_end()
497 .annotate(current_annotation
, base_ir
);
499 int swizzle
[4] = { 0, 0, 0, 0};
500 int num_channels
= 0;
501 unsigned skipped_channels
= 0;
502 int num_components
= instr
->num_components
;
503 for (int i
= 0; i
< num_components
; i
++) {
504 /* Check if this channel needs to be written. If so, record the
505 * channel we need to take the data from in the swizzle array
507 int component_mask
= 1 << i
;
508 int write_test
= write_mask
& component_mask
;
510 swizzle
[num_channels
++] = i
;
512 /* If we don't have to write this channel it means we have a gap in the
513 * vector, so write the channels we accumulated until now, if any. Do
514 * the same if this was the last component in the vector.
516 if (!write_test
|| i
== num_components
- 1) {
517 if (num_channels
> 0) {
518 /* We have channels to write, so update the offset we need to
519 * write at to skip the channels we skipped, if any.
521 if (skipped_channels
> 0) {
522 if (offset_reg
.file
== IMM
) {
523 offset_reg
.ud
+= 4 * skipped_channels
;
525 emit(ADD(dst_reg(offset_reg
), offset_reg
,
526 brw_imm_ud(4 * skipped_channels
)));
530 /* Swizzle the data register so we take the data from the channels
531 * we need to write and send the write message. This will write
532 * num_channels consecutive dwords starting at offset.
535 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
536 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
537 1 /* dims */, num_channels
/* size */,
540 /* If we have to do a second write we will have to update the
541 * offset so that we jump over the channels we have just written
544 skipped_channels
= num_channels
;
546 /* Restart the count for the next write message */
550 /* We did not write the current channel, so increase skipped count */
558 case nir_intrinsic_load_ssbo
: {
559 assert(devinfo
->gen
>= 7);
561 nir_const_value
*const_uniform_block
=
562 nir_src_as_const_value(instr
->src
[0]);
565 if (const_uniform_block
) {
566 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
567 const_uniform_block
->u
[0];
568 surf_index
= brw_imm_ud(index
);
570 brw_mark_surface_used(&prog_data
->base
, index
);
572 surf_index
= src_reg(this, glsl_type::uint_type
);
573 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
574 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
575 surf_index
= emit_uniformize(surf_index
);
577 /* Assume this may touch any UBO. It would be nice to provide
578 * a tighter bound, but the array information is already lowered away.
580 brw_mark_surface_used(&prog_data
->base
,
581 prog_data
->base
.binding_table
.ssbo_start
+
582 nir
->info
.num_ssbos
- 1);
586 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
588 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
590 offset_reg
= get_nir_src(instr
->src
[1], 1);
593 /* Read the vector */
594 const vec4_builder bld
= vec4_builder(this).at_end()
595 .annotate(current_annotation
, base_ir
);
597 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
598 1 /* dims */, 4 /* size*/,
600 dst_reg dest
= get_nir_dest(instr
->dest
);
601 read_result
.type
= dest
.type
;
602 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
603 emit(MOV(dest
, read_result
));
608 case nir_intrinsic_ssbo_atomic_add
:
609 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
611 case nir_intrinsic_ssbo_atomic_imin
:
612 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
614 case nir_intrinsic_ssbo_atomic_umin
:
615 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
617 case nir_intrinsic_ssbo_atomic_imax
:
618 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
620 case nir_intrinsic_ssbo_atomic_umax
:
621 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
623 case nir_intrinsic_ssbo_atomic_and
:
624 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
626 case nir_intrinsic_ssbo_atomic_or
:
627 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
629 case nir_intrinsic_ssbo_atomic_xor
:
630 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
632 case nir_intrinsic_ssbo_atomic_exchange
:
633 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
635 case nir_intrinsic_ssbo_atomic_comp_swap
:
636 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
639 case nir_intrinsic_load_vertex_id
:
640 unreachable("should be lowered by lower_vertex_id()");
642 case nir_intrinsic_load_vertex_id_zero_base
:
643 case nir_intrinsic_load_base_vertex
:
644 case nir_intrinsic_load_instance_id
: {
645 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
646 src_reg val
= src_reg(nir_system_values
[sv
]);
647 assert(val
.file
!= BAD_FILE
);
648 dest
= get_nir_dest(instr
->dest
, val
.type
);
649 emit(MOV(dest
, val
));
653 case nir_intrinsic_load_uniform
: {
654 /* Offsets are in bytes but they should always be multiples of 16 */
655 assert(instr
->const_index
[0] % 16 == 0);
657 dest
= get_nir_dest(instr
->dest
);
659 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0] / 16));
660 src
.type
= dest
.type
;
662 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
664 /* Offsets are in bytes but they should always be multiples of 16 */
665 assert(const_offset
->u
[0] % 16 == 0);
666 src
.reg_offset
= const_offset
->u
[0] / 16;
668 emit(MOV(dest
, src
));
670 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
672 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
673 indirect
, brw_imm_ud(instr
->const_index
[1]));
678 case nir_intrinsic_atomic_counter_read
:
679 case nir_intrinsic_atomic_counter_inc
:
680 case nir_intrinsic_atomic_counter_dec
: {
681 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
682 (unsigned) instr
->const_index
[0];
683 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
684 instr
->num_components
);
685 dest
= get_nir_dest(instr
->dest
);
687 switch (instr
->intrinsic
) {
688 case nir_intrinsic_atomic_counter_inc
:
689 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
690 src_reg(), src_reg());
692 case nir_intrinsic_atomic_counter_dec
:
693 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
694 src_reg(), src_reg());
696 case nir_intrinsic_atomic_counter_read
:
697 emit_untyped_surface_read(surf_index
, dest
, offset
);
700 unreachable("Unreachable");
703 brw_mark_surface_used(stage_prog_data
, surf_index
);
707 case nir_intrinsic_load_ubo
: {
708 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
711 dest
= get_nir_dest(instr
->dest
);
713 if (const_block_index
) {
714 /* The block index is a constant, so just emit the binding table entry
717 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
718 const_block_index
->u
[0];
719 surf_index
= brw_imm_ud(index
);
720 brw_mark_surface_used(&prog_data
->base
, index
);
722 /* The block index is not a constant. Evaluate the index expression
723 * per-channel and add the base UBO index; we have to select a value
724 * from any live channel.
726 surf_index
= src_reg(this, glsl_type::uint_type
);
727 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
728 instr
->num_components
),
729 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
730 surf_index
= emit_uniformize(surf_index
);
732 /* Assume this may touch any UBO. It would be nice to provide
733 * a tighter bound, but the array information is already lowered away.
735 brw_mark_surface_used(&prog_data
->base
,
736 prog_data
->base
.binding_table
.ubo_start
+
737 nir
->info
.num_ubos
- 1);
741 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
743 offset
= brw_imm_ud(const_offset
->u
[0] & ~15);
745 offset
= get_nir_src(instr
->src
[1], nir_type_int
, 1);
748 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
749 packed_consts
.type
= dest
.type
;
751 emit_pull_constant_load_reg(dst_reg(packed_consts
),
754 NULL
, NULL
/* before_block/inst */);
756 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
758 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
->u
[0] % 16 / 4,
759 const_offset
->u
[0] % 16 / 4,
760 const_offset
->u
[0] % 16 / 4,
761 const_offset
->u
[0] % 16 / 4);
764 emit(MOV(dest
, packed_consts
));
768 case nir_intrinsic_memory_barrier
: {
769 const vec4_builder bld
=
770 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
771 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
772 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
777 case nir_intrinsic_shader_clock
: {
778 /* We cannot do anything if there is an event, so ignore it for now */
779 const src_reg shader_clock
= get_timestamp();
780 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
782 dest
= get_nir_dest(instr
->dest
, type
);
783 emit(MOV(dest
, shader_clock
));
788 unreachable("Unknown intrinsic");
793 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
796 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
797 dest
= get_nir_dest(instr
->dest
);
800 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
802 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
804 surface
= brw_imm_ud(surf_index
);
805 brw_mark_surface_used(&prog_data
->base
, surf_index
);
807 surface
= src_reg(this, glsl_type::uint_type
);
808 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
809 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
811 /* Assume this may touch any UBO. This is the same we do for other
812 * UBO/SSBO accesses with non-constant surface.
814 brw_mark_surface_used(&prog_data
->base
,
815 prog_data
->base
.binding_table
.ssbo_start
+
816 nir
->info
.num_ssbos
- 1);
819 src_reg offset
= get_nir_src(instr
->src
[1], 1);
820 src_reg data1
= get_nir_src(instr
->src
[2], 1);
822 if (op
== BRW_AOP_CMPWR
)
823 data2
= get_nir_src(instr
->src
[3], 1);
825 /* Emit the actual atomic operation operation */
826 const vec4_builder bld
=
827 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
829 src_reg atomic_result
=
830 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
832 1 /* dims */, 1 /* rsize */,
835 dest
.type
= atomic_result
.type
;
836 bld
.MOV(dest
, atomic_result
);
840 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
842 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
845 static enum brw_conditional_mod
846 brw_conditional_for_nir_comparison(nir_op op
)
852 return BRW_CONDITIONAL_L
;
857 return BRW_CONDITIONAL_GE
;
861 case nir_op_ball_fequal2
:
862 case nir_op_ball_iequal2
:
863 case nir_op_ball_fequal3
:
864 case nir_op_ball_iequal3
:
865 case nir_op_ball_fequal4
:
866 case nir_op_ball_iequal4
:
867 return BRW_CONDITIONAL_Z
;
871 case nir_op_bany_fnequal2
:
872 case nir_op_bany_inequal2
:
873 case nir_op_bany_fnequal3
:
874 case nir_op_bany_inequal3
:
875 case nir_op_bany_fnequal4
:
876 case nir_op_bany_inequal4
:
877 return BRW_CONDITIONAL_NZ
;
880 unreachable("not reached: bad operation for comparison");
885 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
887 vec4_instruction
*inst
;
889 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
890 nir_op_infos
[instr
->op
].output_type
);
891 dst
.writemask
= instr
->dest
.write_mask
;
894 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
895 op
[i
] = get_nir_src(instr
->src
[i
].src
,
896 nir_op_infos
[instr
->op
].input_types
[i
], 4);
897 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
898 op
[i
].abs
= instr
->src
[i
].abs
;
899 op
[i
].negate
= instr
->src
[i
].negate
;
905 inst
= emit(MOV(dst
, op
[0]));
906 inst
->saturate
= instr
->dest
.saturate
;
912 unreachable("not reached: should be handled by lower_vec_to_movs()");
916 inst
= emit(MOV(dst
, op
[0]));
917 inst
->saturate
= instr
->dest
.saturate
;
922 inst
= emit(MOV(dst
, op
[0]));
928 inst
= emit(ADD(dst
, op
[0], op
[1]));
929 inst
->saturate
= instr
->dest
.saturate
;
933 inst
= emit(MUL(dst
, op
[0], op
[1]));
934 inst
->saturate
= instr
->dest
.saturate
;
938 if (devinfo
->gen
< 8) {
939 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
940 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
942 /* For integer multiplication, the MUL uses the low 16 bits of one of
943 * the operands (src0 through SNB, src1 on IVB and later). The MACH
944 * accumulates in the contribution of the upper 16 bits of that
945 * operand. If we can determine that one of the args is in the low
946 * 16 bits, though, we can just emit a single MUL.
948 if (value0
&& value0
->u
[0] < (1 << 16)) {
949 if (devinfo
->gen
< 7)
950 emit(MUL(dst
, op
[0], op
[1]));
952 emit(MUL(dst
, op
[1], op
[0]));
953 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
954 if (devinfo
->gen
< 7)
955 emit(MUL(dst
, op
[1], op
[0]));
957 emit(MUL(dst
, op
[0], op
[1]));
959 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
961 emit(MUL(acc
, op
[0], op
[1]));
962 emit(MACH(dst_null_d(), op
[0], op
[1]));
963 emit(MOV(dst
, src_reg(acc
)));
966 emit(MUL(dst
, op
[0], op
[1]));
971 case nir_op_imul_high
:
972 case nir_op_umul_high
: {
973 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
975 emit(MUL(acc
, op
[0], op
[1]));
976 emit(MACH(dst
, op
[0], op
[1]));
981 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
982 inst
->saturate
= instr
->dest
.saturate
;
986 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
987 inst
->saturate
= instr
->dest
.saturate
;
991 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
992 inst
->saturate
= instr
->dest
.saturate
;
996 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
997 inst
->saturate
= instr
->dest
.saturate
;
1001 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1002 inst
->saturate
= instr
->dest
.saturate
;
1007 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1011 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1015 unreachable("not reached: should be handled by ldexp_to_arith()");
1018 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1019 inst
->saturate
= instr
->dest
.saturate
;
1023 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1024 inst
->saturate
= instr
->dest
.saturate
;
1028 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1029 inst
->saturate
= instr
->dest
.saturate
;
1032 case nir_op_uadd_carry
: {
1033 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1035 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1036 emit(MOV(dst
, src_reg(acc
)));
1040 case nir_op_usub_borrow
: {
1041 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1043 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1044 emit(MOV(dst
, src_reg(acc
)));
1049 inst
= emit(RNDZ(dst
, op
[0]));
1050 inst
->saturate
= instr
->dest
.saturate
;
1053 case nir_op_fceil
: {
1054 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1056 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1057 instr
->src
[0].src
.ssa
->num_components
:
1058 instr
->src
[0].src
.reg
.reg
->num_components
);
1060 op
[0].negate
= !op
[0].negate
;
1061 emit(RNDD(dst_reg(tmp
), op
[0]));
1063 inst
= emit(MOV(dst
, tmp
));
1064 inst
->saturate
= instr
->dest
.saturate
;
1069 inst
= emit(RNDD(dst
, op
[0]));
1070 inst
->saturate
= instr
->dest
.saturate
;
1074 inst
= emit(FRC(dst
, op
[0]));
1075 inst
->saturate
= instr
->dest
.saturate
;
1078 case nir_op_fround_even
:
1079 inst
= emit(RNDE(dst
, op
[0]));
1080 inst
->saturate
= instr
->dest
.saturate
;
1086 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1087 inst
->saturate
= instr
->dest
.saturate
;
1093 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1094 inst
->saturate
= instr
->dest
.saturate
;
1098 case nir_op_fddx_coarse
:
1099 case nir_op_fddx_fine
:
1101 case nir_op_fddy_coarse
:
1102 case nir_op_fddy_fine
:
1103 unreachable("derivatives are not valid in vertex shaders");
1115 emit(CMP(dst
, op
[0], op
[1],
1116 brw_conditional_for_nir_comparison(instr
->op
)));
1119 case nir_op_ball_fequal2
:
1120 case nir_op_ball_iequal2
:
1121 case nir_op_ball_fequal3
:
1122 case nir_op_ball_iequal3
:
1123 case nir_op_ball_fequal4
:
1124 case nir_op_ball_iequal4
: {
1126 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1128 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1129 brw_conditional_for_nir_comparison(instr
->op
)));
1130 emit(MOV(dst
, brw_imm_d(0)));
1131 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1132 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1136 case nir_op_bany_fnequal2
:
1137 case nir_op_bany_inequal2
:
1138 case nir_op_bany_fnequal3
:
1139 case nir_op_bany_inequal3
:
1140 case nir_op_bany_fnequal4
:
1141 case nir_op_bany_inequal4
: {
1143 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1145 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1146 brw_conditional_for_nir_comparison(instr
->op
)));
1148 emit(MOV(dst
, brw_imm_d(0)));
1149 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1150 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1155 if (devinfo
->gen
>= 8) {
1156 op
[0] = resolve_source_modifiers(op
[0]);
1158 emit(NOT(dst
, op
[0]));
1162 if (devinfo
->gen
>= 8) {
1163 op
[0] = resolve_source_modifiers(op
[0]);
1164 op
[1] = resolve_source_modifiers(op
[1]);
1166 emit(XOR(dst
, op
[0], op
[1]));
1170 if (devinfo
->gen
>= 8) {
1171 op
[0] = resolve_source_modifiers(op
[0]);
1172 op
[1] = resolve_source_modifiers(op
[1]);
1174 emit(OR(dst
, op
[0], op
[1]));
1178 if (devinfo
->gen
>= 8) {
1179 op
[0] = resolve_source_modifiers(op
[0]);
1180 op
[1] = resolve_source_modifiers(op
[1]);
1182 emit(AND(dst
, op
[0], op
[1]));
1187 emit(MOV(dst
, negate(op
[0])));
1191 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1195 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1198 case nir_op_fnoise1_1
:
1199 case nir_op_fnoise1_2
:
1200 case nir_op_fnoise1_3
:
1201 case nir_op_fnoise1_4
:
1202 case nir_op_fnoise2_1
:
1203 case nir_op_fnoise2_2
:
1204 case nir_op_fnoise2_3
:
1205 case nir_op_fnoise2_4
:
1206 case nir_op_fnoise3_1
:
1207 case nir_op_fnoise3_2
:
1208 case nir_op_fnoise3_3
:
1209 case nir_op_fnoise3_4
:
1210 case nir_op_fnoise4_1
:
1211 case nir_op_fnoise4_2
:
1212 case nir_op_fnoise4_3
:
1213 case nir_op_fnoise4_4
:
1214 unreachable("not reached: should be handled by lower_noise");
1216 case nir_op_unpack_half_2x16_split_x
:
1217 case nir_op_unpack_half_2x16_split_y
:
1218 case nir_op_pack_half_2x16_split
:
1219 unreachable("not reached: should not occur in vertex shader");
1221 case nir_op_unpack_snorm_2x16
:
1222 case nir_op_unpack_unorm_2x16
:
1223 case nir_op_pack_snorm_2x16
:
1224 case nir_op_pack_unorm_2x16
:
1225 unreachable("not reached: should be handled by lower_packing_builtins");
1227 case nir_op_unpack_half_2x16
:
1228 /* As NIR does not guarantee that we have a correct swizzle outside the
1229 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1230 * uses the source operand in an operation with WRITEMASK_Y while our
1231 * source operand has only size 1, it accessed incorrect data producing
1232 * regressions in Piglit. We repeat the swizzle of the first component on the
1233 * rest of components to avoid regressions. In the vec4_visitor IR code path
1234 * this is not needed because the operand has already the correct swizzle.
1236 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1237 emit_unpack_half_2x16(dst
, op
[0]);
1240 case nir_op_pack_half_2x16
:
1241 emit_pack_half_2x16(dst
, op
[0]);
1244 case nir_op_unpack_unorm_4x8
:
1245 emit_unpack_unorm_4x8(dst
, op
[0]);
1248 case nir_op_pack_unorm_4x8
:
1249 emit_pack_unorm_4x8(dst
, op
[0]);
1252 case nir_op_unpack_snorm_4x8
:
1253 emit_unpack_snorm_4x8(dst
, op
[0]);
1256 case nir_op_pack_snorm_4x8
:
1257 emit_pack_snorm_4x8(dst
, op
[0]);
1260 case nir_op_bitfield_reverse
:
1261 emit(BFREV(dst
, op
[0]));
1264 case nir_op_bit_count
:
1265 emit(CBIT(dst
, op
[0]));
1268 case nir_op_ufind_msb
:
1269 case nir_op_ifind_msb
: {
1270 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1272 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1273 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1274 * subtract the result from 31 to convert the MSB count into an LSB count.
1277 emit(CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
));
1279 inst
= emit(ADD(dst
, src
, brw_imm_d(31)));
1280 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1281 inst
->src
[0].negate
= true;
1285 case nir_op_find_lsb
:
1286 emit(FBL(dst
, op
[0]));
1289 case nir_op_ubitfield_extract
:
1290 case nir_op_ibitfield_extract
:
1291 op
[0] = fix_3src_operand(op
[0]);
1292 op
[1] = fix_3src_operand(op
[1]);
1293 op
[2] = fix_3src_operand(op
[2]);
1295 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1299 emit(BFI1(dst
, op
[0], op
[1]));
1303 op
[0] = fix_3src_operand(op
[0]);
1304 op
[1] = fix_3src_operand(op
[1]);
1305 op
[2] = fix_3src_operand(op
[2]);
1307 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1310 case nir_op_bitfield_insert
:
1311 unreachable("not reached: should be handled by "
1312 "lower_instructions::bitfield_insert_to_bfm_bfi");
1315 /* AND(val, 0x80000000) gives the sign bit.
1317 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1320 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1322 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1323 dst
.type
= BRW_REGISTER_TYPE_UD
;
1324 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1326 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1327 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1328 dst
.type
= BRW_REGISTER_TYPE_F
;
1330 if (instr
->dest
.saturate
) {
1331 inst
= emit(MOV(dst
, src_reg(dst
)));
1332 inst
->saturate
= true;
1337 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1338 * -> non-negative val generates 0x00000000.
1339 * Predicated OR sets 1 if val is positive.
1341 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1342 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1343 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1344 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1348 emit(SHL(dst
, op
[0], op
[1]));
1352 emit(ASR(dst
, op
[0], op
[1]));
1356 emit(SHR(dst
, op
[0], op
[1]));
1360 op
[0] = fix_3src_operand(op
[0]);
1361 op
[1] = fix_3src_operand(op
[1]);
1362 op
[2] = fix_3src_operand(op
[2]);
1364 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1365 inst
->saturate
= instr
->dest
.saturate
;
1369 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1370 inst
->saturate
= instr
->dest
.saturate
;
1374 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1375 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1376 switch (dst
.writemask
) {
1378 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1381 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1384 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1387 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1390 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1395 case nir_op_fdot_replicated2
:
1396 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1397 inst
->saturate
= instr
->dest
.saturate
;
1400 case nir_op_fdot_replicated3
:
1401 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1402 inst
->saturate
= instr
->dest
.saturate
;
1405 case nir_op_fdot_replicated4
:
1406 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1407 inst
->saturate
= instr
->dest
.saturate
;
1410 case nir_op_fdph_replicated
:
1411 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1412 inst
->saturate
= instr
->dest
.saturate
;
1417 case nir_op_bany4
: {
1419 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1421 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), brw_imm_d(0),
1422 BRW_CONDITIONAL_NZ
));
1423 emit(MOV(dst
, brw_imm_d(0)));
1424 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1425 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1434 unreachable("not reached: should be lowered by lower_source mods");
1437 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1440 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1444 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1447 unreachable("Unimplemented ALU operation");
1450 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1451 * to sign extend the low bit to 0/~0
1453 if (devinfo
->gen
<= 5 &&
1454 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1455 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1456 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1457 masked
.writemask
= dst
.writemask
;
1458 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1459 src_reg masked_neg
= src_reg(masked
);
1460 masked_neg
.negate
= true;
1461 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1466 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1468 switch (instr
->type
) {
1469 case nir_jump_break
:
1470 emit(BRW_OPCODE_BREAK
);
1473 case nir_jump_continue
:
1474 emit(BRW_OPCODE_CONTINUE
);
1477 case nir_jump_return
:
1480 unreachable("unknown jump");
1484 enum ir_texture_opcode
1485 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1487 enum ir_texture_opcode op
;
1490 case nir_texop_lod
: op
= ir_lod
; break;
1491 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1492 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1493 case nir_texop_tex
: op
= ir_tex
; break;
1494 case nir_texop_tg4
: op
= ir_tg4
; break;
1495 case nir_texop_txb
: op
= ir_txb
; break;
1496 case nir_texop_txd
: op
= ir_txd
; break;
1497 case nir_texop_txf
: op
= ir_txf
; break;
1498 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1499 case nir_texop_txl
: op
= ir_txl
; break;
1500 case nir_texop_txs
: op
= ir_txs
; break;
1501 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
1503 unreachable("unknown texture opcode");
1509 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1510 unsigned components
)
1513 case nir_type_float
:
1514 return glsl_type::vec(components
);
1516 return glsl_type::ivec(components
);
1518 return glsl_type::uvec(components
);
1520 return glsl_type::bvec(components
);
1522 return glsl_type::error_type
;
1525 return glsl_type::error_type
;
1529 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1531 unsigned sampler
= instr
->sampler_index
;
1532 src_reg sampler_reg
= brw_imm_ud(sampler
);
1534 const glsl_type
*coord_type
= NULL
;
1535 src_reg shadow_comparitor
;
1536 src_reg offset_value
;
1538 src_reg sample_index
;
1541 const glsl_type
*dest_type
=
1542 glsl_type_for_nir_alu_type(instr
->dest_type
,
1543 nir_tex_instr_dest_size(instr
));
1544 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1546 /* Load the texture operation sources */
1547 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1548 switch (instr
->src
[i
].src_type
) {
1549 case nir_tex_src_comparitor
:
1550 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1551 BRW_REGISTER_TYPE_F
, 1);
1554 case nir_tex_src_coord
: {
1555 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1557 switch (instr
->op
) {
1559 case nir_texop_txf_ms
:
1560 case nir_texop_samples_identical
:
1561 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1563 coord_type
= glsl_type::ivec(src_size
);
1567 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1569 coord_type
= glsl_type::vec(src_size
);
1575 case nir_tex_src_ddx
:
1576 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1577 nir_tex_instr_src_size(instr
, i
));
1580 case nir_tex_src_ddy
:
1581 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1582 nir_tex_instr_src_size(instr
, i
));
1585 case nir_tex_src_lod
:
1586 switch (instr
->op
) {
1589 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1593 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1598 case nir_tex_src_ms_index
: {
1599 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1603 case nir_tex_src_offset
:
1604 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1607 case nir_tex_src_sampler_offset
: {
1608 /* The highest sampler which may be used by this operation is
1609 * the last element of the array. Mark it here, because the generator
1610 * doesn't have enough information to determine the bound.
1612 uint32_t array_size
= instr
->sampler_array_size
;
1613 uint32_t max_used
= sampler
+ array_size
- 1;
1614 if (instr
->op
== nir_texop_tg4
) {
1615 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1617 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1620 brw_mark_surface_used(&prog_data
->base
, max_used
);
1622 /* Emit code to evaluate the actual indexing expression */
1623 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1624 src_reg
temp(this, glsl_type::uint_type
);
1625 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
1626 sampler_reg
= emit_uniformize(temp
);
1630 case nir_tex_src_projector
:
1631 unreachable("Should be lowered by do_lower_texture_projection");
1633 case nir_tex_src_bias
:
1634 unreachable("LOD bias is not valid for vertex shaders.\n");
1637 unreachable("unknown texture source");
1641 if (instr
->op
== nir_texop_txf_ms
||
1642 instr
->op
== nir_texop_samples_identical
) {
1643 assert(coord_type
!= NULL
);
1644 if (devinfo
->gen
>= 7 &&
1645 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1646 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1648 mcs
= brw_imm_ud(0u);
1652 uint32_t constant_offset
= 0;
1653 for (unsigned i
= 0; i
< 3; i
++) {
1654 if (instr
->const_offset
[i
] != 0) {
1655 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1660 /* Stuff the channel select bits in the top of the texture offset */
1661 if (instr
->op
== nir_texop_tg4
) {
1662 if (instr
->component
== 1 &&
1663 (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))) {
1664 /* gather4 sampler is broken for green channel on RG32F --
1665 * we must ask for blue instead.
1667 constant_offset
|= 2 << 16;
1669 constant_offset
|= instr
->component
<< 16;
1673 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1675 bool is_cube_array
=
1676 instr
->op
== nir_texop_txs
&&
1677 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1680 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1682 lod
, lod2
, sample_index
,
1683 constant_offset
, offset_value
,
1684 mcs
, is_cube_array
, sampler
, sampler_reg
);
1688 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1690 nir_ssa_values
[instr
->def
.index
] = dst_reg(VGRF
, alloc
.allocate(1));