2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_setup_system_values();
43 /* get the main function and emit it */
44 nir_foreach_overload(nir
, overload
) {
45 assert(strcmp(overload
->function
->name
, "main") == 0);
46 assert(overload
->impl
);
47 nir_emit_impl(overload
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
63 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
67 case nir_intrinsic_load_base_vertex
:
68 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
69 if (reg
->file
== BAD_FILE
)
70 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
74 case nir_intrinsic_load_instance_id
:
75 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
76 if (reg
->file
== BAD_FILE
)
77 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
87 setup_system_values_block(nir_block
*block
, void *void_visitor
)
89 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
91 nir_foreach_instr(block
, instr
) {
92 if (instr
->type
!= nir_instr_type_intrinsic
)
95 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
96 v
->nir_setup_system_value_intrinsic(intrin
);
103 vec4_visitor::nir_setup_system_values()
105 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
106 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
107 nir_system_values
[i
] = dst_reg();
110 nir_foreach_overload(nir
, overload
) {
111 assert(strcmp(overload
->function
->name
, "main") == 0);
112 assert(overload
->impl
);
113 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
118 vec4_visitor::nir_setup_uniforms()
120 uniforms
= nir
->num_uniforms
;
122 nir_foreach_variable(var
, &nir
->uniforms
) {
123 /* UBO's and atomics don't take up space in the uniform file */
124 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
127 if (type_size_vec4(var
->type
) > 0)
128 uniform_size
[var
->data
.driver_location
] = type_size_vec4(var
->type
);
133 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
135 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
136 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
137 nir_locals
[i
] = dst_reg();
140 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
141 unsigned array_elems
=
142 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
144 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(array_elems
));
147 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
149 nir_emit_cf_list(&impl
->body
);
153 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
155 exec_list_validate(list
);
156 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
157 switch (node
->type
) {
159 nir_emit_if(nir_cf_node_as_if(node
));
162 case nir_cf_node_loop
:
163 nir_emit_loop(nir_cf_node_as_loop(node
));
166 case nir_cf_node_block
:
167 nir_emit_block(nir_cf_node_as_block(node
));
171 unreachable("Invalid CFG node block");
177 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
179 /* First, put the condition in f0 */
180 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
181 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
182 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
184 /* We can just predicate based on the X channel, as the condition only
185 * goes on its own line */
186 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
188 nir_emit_cf_list(&if_stmt
->then_list
);
190 /* note: if the else is empty, dead CF elimination will remove it */
191 emit(BRW_OPCODE_ELSE
);
193 nir_emit_cf_list(&if_stmt
->else_list
);
195 emit(BRW_OPCODE_ENDIF
);
199 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
203 nir_emit_cf_list(&loop
->body
);
205 emit(BRW_OPCODE_WHILE
);
209 vec4_visitor::nir_emit_block(nir_block
*block
)
211 nir_foreach_instr(block
, instr
) {
212 nir_emit_instr(instr
);
217 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
221 switch (instr
->type
) {
222 case nir_instr_type_load_const
:
223 nir_emit_load_const(nir_instr_as_load_const(instr
));
226 case nir_instr_type_intrinsic
:
227 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
230 case nir_instr_type_alu
:
231 nir_emit_alu(nir_instr_as_alu(instr
));
234 case nir_instr_type_jump
:
235 nir_emit_jump(nir_instr_as_jump(instr
));
238 case nir_instr_type_tex
:
239 nir_emit_texture(nir_instr_as_tex(instr
));
242 case nir_instr_type_ssa_undef
:
243 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
247 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
253 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
254 unsigned base_offset
, nir_src
*indirect
)
258 reg
= v
->nir_locals
[nir_reg
->index
];
259 reg
= offset(reg
, base_offset
);
262 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
270 vec4_visitor::get_nir_dest(nir_dest dest
)
273 dst_reg dst
= dst_reg(VGRF
, alloc
.allocate(1));
274 nir_ssa_values
[dest
.ssa
.index
] = dst
;
277 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
283 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
285 return retype(get_nir_dest(dest
), type
);
289 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
291 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
295 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
296 unsigned num_components
)
301 assert(src
.ssa
!= NULL
);
302 reg
= nir_ssa_values
[src
.ssa
->index
];
305 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
309 reg
= retype(reg
, type
);
311 src_reg reg_as_src
= src_reg(reg
);
312 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
317 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
318 unsigned num_components
)
320 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
324 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
326 /* if type is not specified, default to signed int */
327 return get_nir_src(src
, nir_type_int
, num_components
);
331 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
333 dst_reg reg
= dst_reg(VGRF
, alloc
.allocate(1));
334 reg
.type
= BRW_REGISTER_TYPE_D
;
336 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
338 /* @FIXME: consider emitting vector operations to save some MOVs in
339 * cases where the components are representable in 8 bits.
340 * For now, we emit a MOV for each distinct value.
342 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
343 unsigned writemask
= 1 << i
;
345 if ((remaining
& writemask
) == 0)
348 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
349 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
354 reg
.writemask
= writemask
;
355 emit(MOV(reg
, brw_imm_d(instr
->value
.i
[i
])));
357 remaining
&= ~writemask
;
360 /* Set final writemask */
361 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
363 nir_ssa_values
[instr
->def
.index
] = reg
;
367 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
372 bool has_indirect
= false;
374 switch (instr
->intrinsic
) {
376 case nir_intrinsic_load_input_indirect
:
379 case nir_intrinsic_load_input
: {
380 int offset
= instr
->const_index
[0];
381 src
= src_reg(ATTR
, offset
, glsl_type::uvec4_type
);
384 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[0],
388 dest
= get_nir_dest(instr
->dest
, src
.type
);
389 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
391 emit(MOV(dest
, src
));
395 case nir_intrinsic_store_output_indirect
:
398 case nir_intrinsic_store_output
: {
399 int varying
= instr
->const_index
[0];
401 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
402 instr
->num_components
);
406 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[1],
410 output_reg
[varying
] = dest
;
414 case nir_intrinsic_get_buffer_size
: {
415 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
416 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
418 const unsigned index
=
419 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
420 dst_reg result_dst
= get_nir_dest(instr
->dest
);
421 vec4_instruction
*inst
= new(mem_ctx
)
422 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
425 inst
->mlen
= 1; /* always at least one */
426 inst
->src
[1] = brw_imm_ud(index
);
428 /* MRF for the first parameter */
429 src_reg lod
= brw_imm_d(0);
430 int param_base
= inst
->base_mrf
;
431 int writemask
= WRITEMASK_X
;
432 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
436 brw_mark_surface_used(&prog_data
->base
, index
);
440 case nir_intrinsic_store_ssbo_indirect
:
443 case nir_intrinsic_store_ssbo
: {
444 assert(devinfo
->gen
>= 7);
448 nir_const_value
*const_uniform_block
=
449 nir_src_as_const_value(instr
->src
[1]);
450 if (const_uniform_block
) {
451 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
452 const_uniform_block
->u
[0];
453 surf_index
= brw_imm_ud(index
);
454 brw_mark_surface_used(&prog_data
->base
, index
);
456 surf_index
= src_reg(this, glsl_type::uint_type
);
457 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
458 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
459 surf_index
= emit_uniformize(surf_index
);
461 brw_mark_surface_used(&prog_data
->base
,
462 prog_data
->base
.binding_table
.ssbo_start
+
463 nir
->info
.num_ssbos
- 1);
467 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
468 unsigned const_offset_bytes
= 0;
470 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[2], 1)));
472 const_offset_bytes
= instr
->const_index
[0];
473 emit(MOV(dst_reg(offset_reg
), brw_imm_ud(const_offset_bytes
)));
477 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
480 unsigned write_mask
= instr
->const_index
[1];
482 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
483 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
484 * typed and untyped messages and across hardware platforms, the
485 * current implementation of the untyped messages will transparently convert
486 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
487 * and enabling only channel X on the SEND instruction.
489 * The above, works well for full vector writes, but not for partial writes
490 * where we want to write some channels and not others, like when we have
491 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
492 * quite restrictive with regards to the channel enables we can configure in
493 * the message descriptor (not all combinations are allowed) we cannot simply
494 * implement these scenarios with a single message while keeping the
495 * aforementioned symmetry in the implementation. For now we de decided that
496 * it is better to keep the symmetry to reduce complexity, so in situations
497 * such as the one described we end up emitting two untyped write messages
498 * (one for xy and another for w).
500 * The code below packs consecutive channels into a single write message,
501 * detects gaps in the vector write and if needed, sends a second message
502 * with the remaining channels. If in the future we decide that we want to
503 * emit a single message at the expense of losing the symmetry in the
504 * implementation we can:
506 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
507 * message payload. In this mode we can write up to 8 offsets and dwords
508 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
509 * and select which of the 8 channels carry data to write by setting the
510 * appropriate writemask in the dst register of the SEND instruction.
511 * It would require to write a new generator opcode specifically for
512 * IvyBridge since we would need to prepare a SIMD8 payload that could
513 * use any channel, not just X.
515 * 2) For Haswell+: Simply send a single write message but set the writemask
516 * on the dst of the SEND instruction to select the channels we want to
517 * write. It would require to modify the current messages to receive
518 * and honor the writemask provided.
520 const vec4_builder bld
= vec4_builder(this).at_end()
521 .annotate(current_annotation
, base_ir
);
523 int swizzle
[4] = { 0, 0, 0, 0};
524 int num_channels
= 0;
525 unsigned skipped_channels
= 0;
526 int num_components
= instr
->num_components
;
527 for (int i
= 0; i
< num_components
; i
++) {
528 /* Check if this channel needs to be written. If so, record the
529 * channel we need to take the data from in the swizzle array
531 int component_mask
= 1 << i
;
532 int write_test
= write_mask
& component_mask
;
534 swizzle
[num_channels
++] = i
;
536 /* If we don't have to write this channel it means we have a gap in the
537 * vector, so write the channels we accumulated until now, if any. Do
538 * the same if this was the last component in the vector.
540 if (!write_test
|| i
== num_components
- 1) {
541 if (num_channels
> 0) {
542 /* We have channels to write, so update the offset we need to
543 * write at to skip the channels we skipped, if any.
545 if (skipped_channels
> 0) {
547 const_offset_bytes
+= 4 * skipped_channels
;
548 offset_reg
= brw_imm_ud(const_offset_bytes
);
550 emit(ADD(dst_reg(offset_reg
), offset_reg
,
551 brw_imm_ud(4 * skipped_channels
)));
555 /* Swizzle the data register so we take the data from the channels
556 * we need to write and send the write message. This will write
557 * num_channels consecutive dwords starting at offset.
560 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
561 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
562 1 /* dims */, num_channels
/* size */,
565 /* If we have to do a second write we will have to update the
566 * offset so that we jump over the channels we have just written
569 skipped_channels
= num_channels
;
571 /* Restart the count for the next write message */
575 /* We did not write the current channel, so increase skipped count */
583 case nir_intrinsic_load_ssbo_indirect
:
586 case nir_intrinsic_load_ssbo
: {
587 assert(devinfo
->gen
>= 7);
589 nir_const_value
*const_uniform_block
=
590 nir_src_as_const_value(instr
->src
[0]);
593 if (const_uniform_block
) {
594 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
595 const_uniform_block
->u
[0];
596 surf_index
= brw_imm_ud(index
);
598 brw_mark_surface_used(&prog_data
->base
, index
);
600 surf_index
= src_reg(this, glsl_type::uint_type
);
601 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
602 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
603 surf_index
= emit_uniformize(surf_index
);
605 /* Assume this may touch any UBO. It would be nice to provide
606 * a tighter bound, but the array information is already lowered away.
608 brw_mark_surface_used(&prog_data
->base
,
609 prog_data
->base
.binding_table
.ssbo_start
+
610 nir
->info
.num_ssbos
- 1);
613 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
614 unsigned const_offset_bytes
= 0;
616 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[1], 1)));
618 const_offset_bytes
= instr
->const_index
[0];
619 emit(MOV(dst_reg(offset_reg
), brw_imm_ud((const_offset_bytes
))));
622 /* Read the vector */
623 const vec4_builder bld
= vec4_builder(this).at_end()
624 .annotate(current_annotation
, base_ir
);
626 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
627 1 /* dims */, 4 /* size*/,
629 dst_reg dest
= get_nir_dest(instr
->dest
);
630 read_result
.type
= dest
.type
;
631 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
632 emit(MOV(dest
, read_result
));
637 case nir_intrinsic_ssbo_atomic_add
:
638 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
640 case nir_intrinsic_ssbo_atomic_imin
:
641 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
643 case nir_intrinsic_ssbo_atomic_umin
:
644 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
646 case nir_intrinsic_ssbo_atomic_imax
:
647 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
649 case nir_intrinsic_ssbo_atomic_umax
:
650 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
652 case nir_intrinsic_ssbo_atomic_and
:
653 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
655 case nir_intrinsic_ssbo_atomic_or
:
656 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
658 case nir_intrinsic_ssbo_atomic_xor
:
659 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
661 case nir_intrinsic_ssbo_atomic_exchange
:
662 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
664 case nir_intrinsic_ssbo_atomic_comp_swap
:
665 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
668 case nir_intrinsic_load_vertex_id
:
669 unreachable("should be lowered by lower_vertex_id()");
671 case nir_intrinsic_load_vertex_id_zero_base
:
672 case nir_intrinsic_load_base_vertex
:
673 case nir_intrinsic_load_instance_id
: {
674 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
675 src_reg val
= src_reg(nir_system_values
[sv
]);
676 assert(val
.file
!= BAD_FILE
);
677 dest
= get_nir_dest(instr
->dest
, val
.type
);
678 emit(MOV(dest
, val
));
682 case nir_intrinsic_load_uniform_indirect
:
685 case nir_intrinsic_load_uniform
: {
686 dest
= get_nir_dest(instr
->dest
);
688 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0]));
689 src
.reg_offset
= instr
->const_index
[1];
692 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
693 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
696 emit(MOV(dest
, src
));
700 case nir_intrinsic_atomic_counter_read
:
701 case nir_intrinsic_atomic_counter_inc
:
702 case nir_intrinsic_atomic_counter_dec
: {
703 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
704 (unsigned) instr
->const_index
[0];
705 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
706 instr
->num_components
);
707 dest
= get_nir_dest(instr
->dest
);
709 switch (instr
->intrinsic
) {
710 case nir_intrinsic_atomic_counter_inc
:
711 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
712 src_reg(), src_reg());
714 case nir_intrinsic_atomic_counter_dec
:
715 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
716 src_reg(), src_reg());
718 case nir_intrinsic_atomic_counter_read
:
719 emit_untyped_surface_read(surf_index
, dest
, offset
);
722 unreachable("Unreachable");
725 brw_mark_surface_used(stage_prog_data
, surf_index
);
729 case nir_intrinsic_load_ubo_indirect
:
732 case nir_intrinsic_load_ubo
: {
733 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
736 dest
= get_nir_dest(instr
->dest
);
738 if (const_block_index
) {
739 /* The block index is a constant, so just emit the binding table entry
742 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
743 const_block_index
->u
[0];
744 surf_index
= brw_imm_ud(index
);
745 brw_mark_surface_used(&prog_data
->base
, index
);
747 /* The block index is not a constant. Evaluate the index expression
748 * per-channel and add the base UBO index; we have to select a value
749 * from any live channel.
751 surf_index
= src_reg(this, glsl_type::uint_type
);
752 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
753 instr
->num_components
),
754 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
755 surf_index
= emit_uniformize(surf_index
);
757 /* Assume this may touch any UBO. It would be nice to provide
758 * a tighter bound, but the array information is already lowered away.
760 brw_mark_surface_used(&prog_data
->base
,
761 prog_data
->base
.binding_table
.ubo_start
+
762 nir
->info
.num_ubos
- 1);
765 unsigned const_offset
= instr
->const_index
[0];
769 offset
= brw_imm_ud(const_offset
/ 16);
771 offset
= src_reg(this, glsl_type::uint_type
);
772 emit(SHR(dst_reg(offset
), get_nir_src(instr
->src
[1], nir_type_int
, 1),
776 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
777 packed_consts
.type
= dest
.type
;
779 emit_pull_constant_load_reg(dst_reg(packed_consts
),
782 NULL
, NULL
/* before_block/inst */);
784 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
785 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
786 const_offset
% 16 / 4,
787 const_offset
% 16 / 4,
788 const_offset
% 16 / 4);
790 emit(MOV(dest
, packed_consts
));
794 case nir_intrinsic_memory_barrier
: {
795 const vec4_builder bld
=
796 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
797 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
798 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
803 case nir_intrinsic_shader_clock
: {
804 /* We cannot do anything if there is an event, so ignore it for now */
805 const src_reg shader_clock
= get_timestamp();
806 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
808 dest
= get_nir_dest(instr
->dest
, type
);
809 emit(MOV(dest
, shader_clock
));
814 unreachable("Unknown intrinsic");
819 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
822 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
823 dest
= get_nir_dest(instr
->dest
);
826 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
828 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
830 surface
= brw_imm_ud(surf_index
);
831 brw_mark_surface_used(&prog_data
->base
, surf_index
);
833 surface
= src_reg(this, glsl_type::uint_type
);
834 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
835 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
837 /* Assume this may touch any UBO. This is the same we do for other
838 * UBO/SSBO accesses with non-constant surface.
840 brw_mark_surface_used(&prog_data
->base
,
841 prog_data
->base
.binding_table
.ssbo_start
+
842 nir
->info
.num_ssbos
- 1);
845 src_reg offset
= get_nir_src(instr
->src
[1], 1);
846 src_reg data1
= get_nir_src(instr
->src
[2], 1);
848 if (op
== BRW_AOP_CMPWR
)
849 data2
= get_nir_src(instr
->src
[3], 1);
851 /* Emit the actual atomic operation operation */
852 const vec4_builder bld
=
853 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
855 src_reg atomic_result
=
856 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
858 1 /* dims */, 1 /* rsize */,
861 dest
.type
= atomic_result
.type
;
862 bld
.MOV(dest
, atomic_result
);
866 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
868 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
871 static enum brw_conditional_mod
872 brw_conditional_for_nir_comparison(nir_op op
)
878 return BRW_CONDITIONAL_L
;
883 return BRW_CONDITIONAL_GE
;
887 case nir_op_ball_fequal2
:
888 case nir_op_ball_iequal2
:
889 case nir_op_ball_fequal3
:
890 case nir_op_ball_iequal3
:
891 case nir_op_ball_fequal4
:
892 case nir_op_ball_iequal4
:
893 return BRW_CONDITIONAL_Z
;
897 case nir_op_bany_fnequal2
:
898 case nir_op_bany_inequal2
:
899 case nir_op_bany_fnequal3
:
900 case nir_op_bany_inequal3
:
901 case nir_op_bany_fnequal4
:
902 case nir_op_bany_inequal4
:
903 return BRW_CONDITIONAL_NZ
;
906 unreachable("not reached: bad operation for comparison");
911 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
913 vec4_instruction
*inst
;
915 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
916 nir_op_infos
[instr
->op
].output_type
);
917 dst
.writemask
= instr
->dest
.write_mask
;
920 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
921 op
[i
] = get_nir_src(instr
->src
[i
].src
,
922 nir_op_infos
[instr
->op
].input_types
[i
], 4);
923 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
924 op
[i
].abs
= instr
->src
[i
].abs
;
925 op
[i
].negate
= instr
->src
[i
].negate
;
931 inst
= emit(MOV(dst
, op
[0]));
932 inst
->saturate
= instr
->dest
.saturate
;
938 unreachable("not reached: should be handled by lower_vec_to_movs()");
942 inst
= emit(MOV(dst
, op
[0]));
943 inst
->saturate
= instr
->dest
.saturate
;
948 inst
= emit(MOV(dst
, op
[0]));
954 inst
= emit(ADD(dst
, op
[0], op
[1]));
955 inst
->saturate
= instr
->dest
.saturate
;
959 inst
= emit(MUL(dst
, op
[0], op
[1]));
960 inst
->saturate
= instr
->dest
.saturate
;
964 if (devinfo
->gen
< 8) {
965 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
966 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
968 /* For integer multiplication, the MUL uses the low 16 bits of one of
969 * the operands (src0 through SNB, src1 on IVB and later). The MACH
970 * accumulates in the contribution of the upper 16 bits of that
971 * operand. If we can determine that one of the args is in the low
972 * 16 bits, though, we can just emit a single MUL.
974 if (value0
&& value0
->u
[0] < (1 << 16)) {
975 if (devinfo
->gen
< 7)
976 emit(MUL(dst
, op
[0], op
[1]));
978 emit(MUL(dst
, op
[1], op
[0]));
979 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
980 if (devinfo
->gen
< 7)
981 emit(MUL(dst
, op
[1], op
[0]));
983 emit(MUL(dst
, op
[0], op
[1]));
985 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
987 emit(MUL(acc
, op
[0], op
[1]));
988 emit(MACH(dst_null_d(), op
[0], op
[1]));
989 emit(MOV(dst
, src_reg(acc
)));
992 emit(MUL(dst
, op
[0], op
[1]));
997 case nir_op_imul_high
:
998 case nir_op_umul_high
: {
999 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1001 emit(MUL(acc
, op
[0], op
[1]));
1002 emit(MACH(dst
, op
[0], op
[1]));
1007 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1008 inst
->saturate
= instr
->dest
.saturate
;
1012 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1013 inst
->saturate
= instr
->dest
.saturate
;
1017 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1018 inst
->saturate
= instr
->dest
.saturate
;
1022 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1023 inst
->saturate
= instr
->dest
.saturate
;
1027 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1028 inst
->saturate
= instr
->dest
.saturate
;
1033 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1037 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1041 unreachable("not reached: should be handled by ldexp_to_arith()");
1044 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1045 inst
->saturate
= instr
->dest
.saturate
;
1049 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1050 inst
->saturate
= instr
->dest
.saturate
;
1054 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1055 inst
->saturate
= instr
->dest
.saturate
;
1058 case nir_op_uadd_carry
: {
1059 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1061 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1062 emit(MOV(dst
, src_reg(acc
)));
1066 case nir_op_usub_borrow
: {
1067 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1069 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1070 emit(MOV(dst
, src_reg(acc
)));
1075 inst
= emit(RNDZ(dst
, op
[0]));
1076 inst
->saturate
= instr
->dest
.saturate
;
1079 case nir_op_fceil
: {
1080 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1082 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1083 instr
->src
[0].src
.ssa
->num_components
:
1084 instr
->src
[0].src
.reg
.reg
->num_components
);
1086 op
[0].negate
= !op
[0].negate
;
1087 emit(RNDD(dst_reg(tmp
), op
[0]));
1089 inst
= emit(MOV(dst
, tmp
));
1090 inst
->saturate
= instr
->dest
.saturate
;
1095 inst
= emit(RNDD(dst
, op
[0]));
1096 inst
->saturate
= instr
->dest
.saturate
;
1100 inst
= emit(FRC(dst
, op
[0]));
1101 inst
->saturate
= instr
->dest
.saturate
;
1104 case nir_op_fround_even
:
1105 inst
= emit(RNDE(dst
, op
[0]));
1106 inst
->saturate
= instr
->dest
.saturate
;
1112 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1113 inst
->saturate
= instr
->dest
.saturate
;
1119 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1120 inst
->saturate
= instr
->dest
.saturate
;
1124 case nir_op_fddx_coarse
:
1125 case nir_op_fddx_fine
:
1127 case nir_op_fddy_coarse
:
1128 case nir_op_fddy_fine
:
1129 unreachable("derivatives are not valid in vertex shaders");
1141 emit(CMP(dst
, op
[0], op
[1],
1142 brw_conditional_for_nir_comparison(instr
->op
)));
1145 case nir_op_ball_fequal2
:
1146 case nir_op_ball_iequal2
:
1147 case nir_op_ball_fequal3
:
1148 case nir_op_ball_iequal3
:
1149 case nir_op_ball_fequal4
:
1150 case nir_op_ball_iequal4
: {
1152 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1154 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1155 brw_conditional_for_nir_comparison(instr
->op
)));
1156 emit(MOV(dst
, brw_imm_d(0)));
1157 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1158 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1162 case nir_op_bany_fnequal2
:
1163 case nir_op_bany_inequal2
:
1164 case nir_op_bany_fnequal3
:
1165 case nir_op_bany_inequal3
:
1166 case nir_op_bany_fnequal4
:
1167 case nir_op_bany_inequal4
: {
1169 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1171 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1172 brw_conditional_for_nir_comparison(instr
->op
)));
1174 emit(MOV(dst
, brw_imm_d(0)));
1175 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1176 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1181 if (devinfo
->gen
>= 8) {
1182 op
[0] = resolve_source_modifiers(op
[0]);
1184 emit(NOT(dst
, op
[0]));
1188 if (devinfo
->gen
>= 8) {
1189 op
[0] = resolve_source_modifiers(op
[0]);
1190 op
[1] = resolve_source_modifiers(op
[1]);
1192 emit(XOR(dst
, op
[0], op
[1]));
1196 if (devinfo
->gen
>= 8) {
1197 op
[0] = resolve_source_modifiers(op
[0]);
1198 op
[1] = resolve_source_modifiers(op
[1]);
1200 emit(OR(dst
, op
[0], op
[1]));
1204 if (devinfo
->gen
>= 8) {
1205 op
[0] = resolve_source_modifiers(op
[0]);
1206 op
[1] = resolve_source_modifiers(op
[1]);
1208 emit(AND(dst
, op
[0], op
[1]));
1213 emit(MOV(dst
, negate(op
[0])));
1217 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1221 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1224 case nir_op_fnoise1_1
:
1225 case nir_op_fnoise1_2
:
1226 case nir_op_fnoise1_3
:
1227 case nir_op_fnoise1_4
:
1228 case nir_op_fnoise2_1
:
1229 case nir_op_fnoise2_2
:
1230 case nir_op_fnoise2_3
:
1231 case nir_op_fnoise2_4
:
1232 case nir_op_fnoise3_1
:
1233 case nir_op_fnoise3_2
:
1234 case nir_op_fnoise3_3
:
1235 case nir_op_fnoise3_4
:
1236 case nir_op_fnoise4_1
:
1237 case nir_op_fnoise4_2
:
1238 case nir_op_fnoise4_3
:
1239 case nir_op_fnoise4_4
:
1240 unreachable("not reached: should be handled by lower_noise");
1242 case nir_op_unpack_half_2x16_split_x
:
1243 case nir_op_unpack_half_2x16_split_y
:
1244 case nir_op_pack_half_2x16_split
:
1245 unreachable("not reached: should not occur in vertex shader");
1247 case nir_op_unpack_snorm_2x16
:
1248 case nir_op_unpack_unorm_2x16
:
1249 case nir_op_pack_snorm_2x16
:
1250 case nir_op_pack_unorm_2x16
:
1251 unreachable("not reached: should be handled by lower_packing_builtins");
1253 case nir_op_unpack_half_2x16
:
1254 /* As NIR does not guarantee that we have a correct swizzle outside the
1255 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1256 * uses the source operand in an operation with WRITEMASK_Y while our
1257 * source operand has only size 1, it accessed incorrect data producing
1258 * regressions in Piglit. We repeat the swizzle of the first component on the
1259 * rest of components to avoid regressions. In the vec4_visitor IR code path
1260 * this is not needed because the operand has already the correct swizzle.
1262 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1263 emit_unpack_half_2x16(dst
, op
[0]);
1266 case nir_op_pack_half_2x16
:
1267 emit_pack_half_2x16(dst
, op
[0]);
1270 case nir_op_unpack_unorm_4x8
:
1271 emit_unpack_unorm_4x8(dst
, op
[0]);
1274 case nir_op_pack_unorm_4x8
:
1275 emit_pack_unorm_4x8(dst
, op
[0]);
1278 case nir_op_unpack_snorm_4x8
:
1279 emit_unpack_snorm_4x8(dst
, op
[0]);
1282 case nir_op_pack_snorm_4x8
:
1283 emit_pack_snorm_4x8(dst
, op
[0]);
1286 case nir_op_bitfield_reverse
:
1287 emit(BFREV(dst
, op
[0]));
1290 case nir_op_bit_count
:
1291 emit(CBIT(dst
, op
[0]));
1294 case nir_op_ufind_msb
:
1295 case nir_op_ifind_msb
: {
1296 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1298 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1299 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1300 * subtract the result from 31 to convert the MSB count into an LSB count.
1303 emit(CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
));
1305 inst
= emit(ADD(dst
, src
, brw_imm_d(31)));
1306 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1307 inst
->src
[0].negate
= true;
1311 case nir_op_find_lsb
:
1312 emit(FBL(dst
, op
[0]));
1315 case nir_op_ubitfield_extract
:
1316 case nir_op_ibitfield_extract
:
1317 op
[0] = fix_3src_operand(op
[0]);
1318 op
[1] = fix_3src_operand(op
[1]);
1319 op
[2] = fix_3src_operand(op
[2]);
1321 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1325 emit(BFI1(dst
, op
[0], op
[1]));
1329 op
[0] = fix_3src_operand(op
[0]);
1330 op
[1] = fix_3src_operand(op
[1]);
1331 op
[2] = fix_3src_operand(op
[2]);
1333 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1336 case nir_op_bitfield_insert
:
1337 unreachable("not reached: should be handled by "
1338 "lower_instructions::bitfield_insert_to_bfm_bfi");
1341 /* AND(val, 0x80000000) gives the sign bit.
1343 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1346 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1348 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1349 dst
.type
= BRW_REGISTER_TYPE_UD
;
1350 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1352 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1353 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1354 dst
.type
= BRW_REGISTER_TYPE_F
;
1356 if (instr
->dest
.saturate
) {
1357 inst
= emit(MOV(dst
, src_reg(dst
)));
1358 inst
->saturate
= true;
1363 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1364 * -> non-negative val generates 0x00000000.
1365 * Predicated OR sets 1 if val is positive.
1367 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1368 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1369 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1370 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1374 emit(SHL(dst
, op
[0], op
[1]));
1378 emit(ASR(dst
, op
[0], op
[1]));
1382 emit(SHR(dst
, op
[0], op
[1]));
1386 op
[0] = fix_3src_operand(op
[0]);
1387 op
[1] = fix_3src_operand(op
[1]);
1388 op
[2] = fix_3src_operand(op
[2]);
1390 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1391 inst
->saturate
= instr
->dest
.saturate
;
1395 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1396 inst
->saturate
= instr
->dest
.saturate
;
1400 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1401 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1402 switch (dst
.writemask
) {
1404 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1407 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1410 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1413 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1416 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1421 case nir_op_fdot_replicated2
:
1422 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1423 inst
->saturate
= instr
->dest
.saturate
;
1426 case nir_op_fdot_replicated3
:
1427 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1428 inst
->saturate
= instr
->dest
.saturate
;
1431 case nir_op_fdot_replicated4
:
1432 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1433 inst
->saturate
= instr
->dest
.saturate
;
1436 case nir_op_fdph_replicated
:
1437 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1438 inst
->saturate
= instr
->dest
.saturate
;
1443 case nir_op_bany4
: {
1445 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1447 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), brw_imm_d(0),
1448 BRW_CONDITIONAL_NZ
));
1449 emit(MOV(dst
, brw_imm_d(0)));
1450 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1451 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1460 unreachable("not reached: should be lowered by lower_source mods");
1463 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1466 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1470 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1473 unreachable("Unimplemented ALU operation");
1476 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1477 * to sign extend the low bit to 0/~0
1479 if (devinfo
->gen
<= 5 &&
1480 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1481 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1482 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1483 masked
.writemask
= dst
.writemask
;
1484 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1485 src_reg masked_neg
= src_reg(masked
);
1486 masked_neg
.negate
= true;
1487 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1492 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1494 switch (instr
->type
) {
1495 case nir_jump_break
:
1496 emit(BRW_OPCODE_BREAK
);
1499 case nir_jump_continue
:
1500 emit(BRW_OPCODE_CONTINUE
);
1503 case nir_jump_return
:
1506 unreachable("unknown jump");
1510 enum ir_texture_opcode
1511 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1513 enum ir_texture_opcode op
;
1516 case nir_texop_lod
: op
= ir_lod
; break;
1517 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1518 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1519 case nir_texop_tex
: op
= ir_tex
; break;
1520 case nir_texop_tg4
: op
= ir_tg4
; break;
1521 case nir_texop_txb
: op
= ir_txb
; break;
1522 case nir_texop_txd
: op
= ir_txd
; break;
1523 case nir_texop_txf
: op
= ir_txf
; break;
1524 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1525 case nir_texop_txl
: op
= ir_txl
; break;
1526 case nir_texop_txs
: op
= ir_txs
; break;
1527 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
1529 unreachable("unknown texture opcode");
1535 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1536 unsigned components
)
1539 case nir_type_float
:
1540 return glsl_type::vec(components
);
1542 return glsl_type::ivec(components
);
1544 return glsl_type::uvec(components
);
1546 return glsl_type::bvec(components
);
1548 return glsl_type::error_type
;
1551 return glsl_type::error_type
;
1555 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1557 unsigned sampler
= instr
->sampler_index
;
1558 src_reg sampler_reg
= brw_imm_ud(sampler
);
1560 const glsl_type
*coord_type
= NULL
;
1561 src_reg shadow_comparitor
;
1562 src_reg offset_value
;
1564 src_reg sample_index
;
1567 const glsl_type
*dest_type
=
1568 glsl_type_for_nir_alu_type(instr
->dest_type
,
1569 nir_tex_instr_dest_size(instr
));
1570 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1572 /* Load the texture operation sources */
1573 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1574 switch (instr
->src
[i
].src_type
) {
1575 case nir_tex_src_comparitor
:
1576 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1577 BRW_REGISTER_TYPE_F
, 1);
1580 case nir_tex_src_coord
: {
1581 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1583 switch (instr
->op
) {
1585 case nir_texop_txf_ms
:
1586 case nir_texop_samples_identical
:
1587 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1589 coord_type
= glsl_type::ivec(src_size
);
1593 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1595 coord_type
= glsl_type::vec(src_size
);
1601 case nir_tex_src_ddx
:
1602 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1603 nir_tex_instr_src_size(instr
, i
));
1606 case nir_tex_src_ddy
:
1607 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1608 nir_tex_instr_src_size(instr
, i
));
1611 case nir_tex_src_lod
:
1612 switch (instr
->op
) {
1615 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1619 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1624 case nir_tex_src_ms_index
: {
1625 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1629 case nir_tex_src_offset
:
1630 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1633 case nir_tex_src_sampler_offset
: {
1634 /* The highest sampler which may be used by this operation is
1635 * the last element of the array. Mark it here, because the generator
1636 * doesn't have enough information to determine the bound.
1638 uint32_t array_size
= instr
->sampler_array_size
;
1639 uint32_t max_used
= sampler
+ array_size
- 1;
1640 if (instr
->op
== nir_texop_tg4
) {
1641 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1643 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1646 brw_mark_surface_used(&prog_data
->base
, max_used
);
1648 /* Emit code to evaluate the actual indexing expression */
1649 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1650 src_reg
temp(this, glsl_type::uint_type
);
1651 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
1652 sampler_reg
= emit_uniformize(temp
);
1656 case nir_tex_src_projector
:
1657 unreachable("Should be lowered by do_lower_texture_projection");
1659 case nir_tex_src_bias
:
1660 unreachable("LOD bias is not valid for vertex shaders.\n");
1663 unreachable("unknown texture source");
1667 if (instr
->op
== nir_texop_txf_ms
||
1668 instr
->op
== nir_texop_samples_identical
) {
1669 assert(coord_type
!= NULL
);
1670 if (devinfo
->gen
>= 7 &&
1671 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1672 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1674 mcs
= brw_imm_ud(0u);
1678 uint32_t constant_offset
= 0;
1679 for (unsigned i
= 0; i
< 3; i
++) {
1680 if (instr
->const_offset
[i
] != 0) {
1681 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1686 /* Stuff the channel select bits in the top of the texture offset */
1687 if (instr
->op
== nir_texop_tg4
) {
1688 if (instr
->component
== 1 &&
1689 (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))) {
1690 /* gather4 sampler is broken for green channel on RG32F --
1691 * we must ask for blue instead.
1693 constant_offset
|= 2 << 16;
1695 constant_offset
|= instr
->component
<< 16;
1699 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1701 bool is_cube_array
=
1702 instr
->op
== nir_texop_txs
&&
1703 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1706 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1708 lod
, lod2
, sample_index
,
1709 constant_offset
, offset_value
,
1710 mcs
, is_cube_array
, sampler
, sampler_reg
);
1714 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1716 nir_ssa_values
[instr
->def
.index
] = dst_reg(VGRF
, alloc
.allocate(1));