2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_setup_system_values();
43 /* get the main function and emit it */
44 nir_foreach_overload(nir
, overload
) {
45 assert(strcmp(overload
->function
->name
, "main") == 0);
46 assert(overload
->impl
);
47 nir_emit_impl(overload
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
63 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
67 case nir_intrinsic_load_base_vertex
:
68 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
69 if (reg
->file
== BAD_FILE
)
70 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
74 case nir_intrinsic_load_instance_id
:
75 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
76 if (reg
->file
== BAD_FILE
)
77 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
87 setup_system_values_block(nir_block
*block
, void *void_visitor
)
89 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
91 nir_foreach_instr(block
, instr
) {
92 if (instr
->type
!= nir_instr_type_intrinsic
)
95 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
96 v
->nir_setup_system_value_intrinsic(intrin
);
103 vec4_visitor::nir_setup_system_values()
105 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
106 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
107 nir_system_values
[i
] = dst_reg();
110 nir_foreach_overload(nir
, overload
) {
111 assert(strcmp(overload
->function
->name
, "main") == 0);
112 assert(overload
->impl
);
113 nir_foreach_block(overload
->impl
, setup_system_values_block
, this);
118 vec4_visitor::nir_setup_uniforms()
120 uniforms
= nir
->num_uniforms
;
122 nir_foreach_variable(var
, &nir
->uniforms
) {
123 /* UBO's and atomics don't take up space in the uniform file */
124 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
127 if (type_size_vec4(var
->type
) > 0)
128 uniform_size
[var
->data
.driver_location
] = type_size_vec4(var
->type
);
133 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
135 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
136 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
137 nir_locals
[i
] = dst_reg();
140 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
141 unsigned array_elems
=
142 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
144 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(array_elems
));
147 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
149 nir_emit_cf_list(&impl
->body
);
153 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
155 exec_list_validate(list
);
156 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
157 switch (node
->type
) {
159 nir_emit_if(nir_cf_node_as_if(node
));
162 case nir_cf_node_loop
:
163 nir_emit_loop(nir_cf_node_as_loop(node
));
166 case nir_cf_node_block
:
167 nir_emit_block(nir_cf_node_as_block(node
));
171 unreachable("Invalid CFG node block");
177 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
179 /* First, put the condition in f0 */
180 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
181 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
182 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
184 /* We can just predicate based on the X channel, as the condition only
185 * goes on its own line */
186 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
188 nir_emit_cf_list(&if_stmt
->then_list
);
190 /* note: if the else is empty, dead CF elimination will remove it */
191 emit(BRW_OPCODE_ELSE
);
193 nir_emit_cf_list(&if_stmt
->else_list
);
195 emit(BRW_OPCODE_ENDIF
);
199 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
203 nir_emit_cf_list(&loop
->body
);
205 emit(BRW_OPCODE_WHILE
);
209 vec4_visitor::nir_emit_block(nir_block
*block
)
211 nir_foreach_instr(block
, instr
) {
212 nir_emit_instr(instr
);
217 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
221 switch (instr
->type
) {
222 case nir_instr_type_load_const
:
223 nir_emit_load_const(nir_instr_as_load_const(instr
));
226 case nir_instr_type_intrinsic
:
227 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
230 case nir_instr_type_alu
:
231 nir_emit_alu(nir_instr_as_alu(instr
));
234 case nir_instr_type_jump
:
235 nir_emit_jump(nir_instr_as_jump(instr
));
238 case nir_instr_type_tex
:
239 nir_emit_texture(nir_instr_as_tex(instr
));
242 case nir_instr_type_ssa_undef
:
243 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
247 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
253 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
254 unsigned base_offset
, nir_src
*indirect
)
258 reg
= v
->nir_locals
[nir_reg
->index
];
259 reg
= offset(reg
, base_offset
);
262 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
270 vec4_visitor::get_nir_dest(nir_dest dest
)
273 dst_reg dst
= dst_reg(VGRF
, alloc
.allocate(1));
274 nir_ssa_values
[dest
.ssa
.index
] = dst
;
277 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
283 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
285 return retype(get_nir_dest(dest
), type
);
289 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
291 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
295 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
296 unsigned num_components
)
301 assert(src
.ssa
!= NULL
);
302 reg
= nir_ssa_values
[src
.ssa
->index
];
305 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
309 reg
= retype(reg
, type
);
311 src_reg reg_as_src
= src_reg(reg
);
312 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
317 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
318 unsigned num_components
)
320 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
324 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
326 /* if type is not specified, default to signed int */
327 return get_nir_src(src
, nir_type_int
, num_components
);
331 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
333 dst_reg reg
= dst_reg(VGRF
, alloc
.allocate(1));
334 reg
.type
= BRW_REGISTER_TYPE_D
;
336 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
338 /* @FIXME: consider emitting vector operations to save some MOVs in
339 * cases where the components are representable in 8 bits.
340 * For now, we emit a MOV for each distinct value.
342 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
343 unsigned writemask
= 1 << i
;
345 if ((remaining
& writemask
) == 0)
348 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
349 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
354 reg
.writemask
= writemask
;
355 emit(MOV(reg
, brw_imm_d(instr
->value
.i
[i
])));
357 remaining
&= ~writemask
;
360 /* Set final writemask */
361 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
363 nir_ssa_values
[instr
->def
.index
] = reg
;
367 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
372 bool has_indirect
= false;
374 switch (instr
->intrinsic
) {
376 case nir_intrinsic_load_input_indirect
:
379 case nir_intrinsic_load_input
: {
380 int offset
= instr
->const_index
[0];
381 src
= src_reg(ATTR
, offset
, glsl_type::uvec4_type
);
384 dest
.reladdr
= new(mem_ctx
) src_reg(get_nir_src(instr
->src
[0],
388 dest
= get_nir_dest(instr
->dest
, src
.type
);
389 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
391 emit(MOV(dest
, src
));
395 case nir_intrinsic_store_output_indirect
:
396 unreachable("nir_lower_outputs_to_temporaries should prevent this");
398 case nir_intrinsic_store_output
: {
399 int varying
= instr
->const_index
[0];
401 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
402 instr
->num_components
);
404 output_reg
[varying
] = dst_reg(src
);
408 case nir_intrinsic_get_buffer_size
: {
409 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
410 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
412 const unsigned index
=
413 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
414 dst_reg result_dst
= get_nir_dest(instr
->dest
);
415 vec4_instruction
*inst
= new(mem_ctx
)
416 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
419 inst
->mlen
= 1; /* always at least one */
420 inst
->src
[1] = brw_imm_ud(index
);
422 /* MRF for the first parameter */
423 src_reg lod
= brw_imm_d(0);
424 int param_base
= inst
->base_mrf
;
425 int writemask
= WRITEMASK_X
;
426 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
430 brw_mark_surface_used(&prog_data
->base
, index
);
434 case nir_intrinsic_store_ssbo_indirect
:
437 case nir_intrinsic_store_ssbo
: {
438 assert(devinfo
->gen
>= 7);
442 nir_const_value
*const_uniform_block
=
443 nir_src_as_const_value(instr
->src
[1]);
444 if (const_uniform_block
) {
445 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
446 const_uniform_block
->u
[0];
447 surf_index
= brw_imm_ud(index
);
448 brw_mark_surface_used(&prog_data
->base
, index
);
450 surf_index
= src_reg(this, glsl_type::uint_type
);
451 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
452 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
453 surf_index
= emit_uniformize(surf_index
);
455 brw_mark_surface_used(&prog_data
->base
,
456 prog_data
->base
.binding_table
.ssbo_start
+
457 nir
->info
.num_ssbos
- 1);
461 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
462 unsigned const_offset_bytes
= 0;
464 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[2], 1)));
466 const_offset_bytes
= instr
->const_index
[0];
467 emit(MOV(dst_reg(offset_reg
), brw_imm_ud(const_offset_bytes
)));
471 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
474 unsigned write_mask
= instr
->const_index
[1];
476 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
477 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
478 * typed and untyped messages and across hardware platforms, the
479 * current implementation of the untyped messages will transparently convert
480 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
481 * and enabling only channel X on the SEND instruction.
483 * The above, works well for full vector writes, but not for partial writes
484 * where we want to write some channels and not others, like when we have
485 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
486 * quite restrictive with regards to the channel enables we can configure in
487 * the message descriptor (not all combinations are allowed) we cannot simply
488 * implement these scenarios with a single message while keeping the
489 * aforementioned symmetry in the implementation. For now we de decided that
490 * it is better to keep the symmetry to reduce complexity, so in situations
491 * such as the one described we end up emitting two untyped write messages
492 * (one for xy and another for w).
494 * The code below packs consecutive channels into a single write message,
495 * detects gaps in the vector write and if needed, sends a second message
496 * with the remaining channels. If in the future we decide that we want to
497 * emit a single message at the expense of losing the symmetry in the
498 * implementation we can:
500 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
501 * message payload. In this mode we can write up to 8 offsets and dwords
502 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
503 * and select which of the 8 channels carry data to write by setting the
504 * appropriate writemask in the dst register of the SEND instruction.
505 * It would require to write a new generator opcode specifically for
506 * IvyBridge since we would need to prepare a SIMD8 payload that could
507 * use any channel, not just X.
509 * 2) For Haswell+: Simply send a single write message but set the writemask
510 * on the dst of the SEND instruction to select the channels we want to
511 * write. It would require to modify the current messages to receive
512 * and honor the writemask provided.
514 const vec4_builder bld
= vec4_builder(this).at_end()
515 .annotate(current_annotation
, base_ir
);
517 int swizzle
[4] = { 0, 0, 0, 0};
518 int num_channels
= 0;
519 unsigned skipped_channels
= 0;
520 int num_components
= instr
->num_components
;
521 for (int i
= 0; i
< num_components
; i
++) {
522 /* Check if this channel needs to be written. If so, record the
523 * channel we need to take the data from in the swizzle array
525 int component_mask
= 1 << i
;
526 int write_test
= write_mask
& component_mask
;
528 swizzle
[num_channels
++] = i
;
530 /* If we don't have to write this channel it means we have a gap in the
531 * vector, so write the channels we accumulated until now, if any. Do
532 * the same if this was the last component in the vector.
534 if (!write_test
|| i
== num_components
- 1) {
535 if (num_channels
> 0) {
536 /* We have channels to write, so update the offset we need to
537 * write at to skip the channels we skipped, if any.
539 if (skipped_channels
> 0) {
541 const_offset_bytes
+= 4 * skipped_channels
;
542 offset_reg
= brw_imm_ud(const_offset_bytes
);
544 emit(ADD(dst_reg(offset_reg
), offset_reg
,
545 brw_imm_ud(4 * skipped_channels
)));
549 /* Swizzle the data register so we take the data from the channels
550 * we need to write and send the write message. This will write
551 * num_channels consecutive dwords starting at offset.
554 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
555 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
556 1 /* dims */, num_channels
/* size */,
559 /* If we have to do a second write we will have to update the
560 * offset so that we jump over the channels we have just written
563 skipped_channels
= num_channels
;
565 /* Restart the count for the next write message */
569 /* We did not write the current channel, so increase skipped count */
577 case nir_intrinsic_load_ssbo_indirect
:
580 case nir_intrinsic_load_ssbo
: {
581 assert(devinfo
->gen
>= 7);
583 nir_const_value
*const_uniform_block
=
584 nir_src_as_const_value(instr
->src
[0]);
587 if (const_uniform_block
) {
588 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
589 const_uniform_block
->u
[0];
590 surf_index
= brw_imm_ud(index
);
592 brw_mark_surface_used(&prog_data
->base
, index
);
594 surf_index
= src_reg(this, glsl_type::uint_type
);
595 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
596 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
597 surf_index
= emit_uniformize(surf_index
);
599 /* Assume this may touch any UBO. It would be nice to provide
600 * a tighter bound, but the array information is already lowered away.
602 brw_mark_surface_used(&prog_data
->base
,
603 prog_data
->base
.binding_table
.ssbo_start
+
604 nir
->info
.num_ssbos
- 1);
607 src_reg offset_reg
= src_reg(this, glsl_type::uint_type
);
608 unsigned const_offset_bytes
= 0;
610 emit(MOV(dst_reg(offset_reg
), get_nir_src(instr
->src
[1], 1)));
612 const_offset_bytes
= instr
->const_index
[0];
613 emit(MOV(dst_reg(offset_reg
), brw_imm_ud((const_offset_bytes
))));
616 /* Read the vector */
617 const vec4_builder bld
= vec4_builder(this).at_end()
618 .annotate(current_annotation
, base_ir
);
620 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
621 1 /* dims */, 4 /* size*/,
623 dst_reg dest
= get_nir_dest(instr
->dest
);
624 read_result
.type
= dest
.type
;
625 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
626 emit(MOV(dest
, read_result
));
631 case nir_intrinsic_ssbo_atomic_add
:
632 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
634 case nir_intrinsic_ssbo_atomic_imin
:
635 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
637 case nir_intrinsic_ssbo_atomic_umin
:
638 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
640 case nir_intrinsic_ssbo_atomic_imax
:
641 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
643 case nir_intrinsic_ssbo_atomic_umax
:
644 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
646 case nir_intrinsic_ssbo_atomic_and
:
647 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
649 case nir_intrinsic_ssbo_atomic_or
:
650 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
652 case nir_intrinsic_ssbo_atomic_xor
:
653 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
655 case nir_intrinsic_ssbo_atomic_exchange
:
656 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
658 case nir_intrinsic_ssbo_atomic_comp_swap
:
659 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
662 case nir_intrinsic_load_vertex_id
:
663 unreachable("should be lowered by lower_vertex_id()");
665 case nir_intrinsic_load_vertex_id_zero_base
:
666 case nir_intrinsic_load_base_vertex
:
667 case nir_intrinsic_load_instance_id
: {
668 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
669 src_reg val
= src_reg(nir_system_values
[sv
]);
670 assert(val
.file
!= BAD_FILE
);
671 dest
= get_nir_dest(instr
->dest
, val
.type
);
672 emit(MOV(dest
, val
));
676 case nir_intrinsic_load_uniform_indirect
:
679 case nir_intrinsic_load_uniform
: {
680 dest
= get_nir_dest(instr
->dest
);
682 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0]));
683 src
.reg_offset
= instr
->const_index
[1];
686 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
687 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
690 emit(MOV(dest
, src
));
694 case nir_intrinsic_atomic_counter_read
:
695 case nir_intrinsic_atomic_counter_inc
:
696 case nir_intrinsic_atomic_counter_dec
: {
697 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
698 (unsigned) instr
->const_index
[0];
699 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
700 instr
->num_components
);
701 dest
= get_nir_dest(instr
->dest
);
703 switch (instr
->intrinsic
) {
704 case nir_intrinsic_atomic_counter_inc
:
705 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
706 src_reg(), src_reg());
708 case nir_intrinsic_atomic_counter_dec
:
709 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
710 src_reg(), src_reg());
712 case nir_intrinsic_atomic_counter_read
:
713 emit_untyped_surface_read(surf_index
, dest
, offset
);
716 unreachable("Unreachable");
719 brw_mark_surface_used(stage_prog_data
, surf_index
);
723 case nir_intrinsic_load_ubo_indirect
:
726 case nir_intrinsic_load_ubo
: {
727 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
730 dest
= get_nir_dest(instr
->dest
);
732 if (const_block_index
) {
733 /* The block index is a constant, so just emit the binding table entry
736 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
737 const_block_index
->u
[0];
738 surf_index
= brw_imm_ud(index
);
739 brw_mark_surface_used(&prog_data
->base
, index
);
741 /* The block index is not a constant. Evaluate the index expression
742 * per-channel and add the base UBO index; we have to select a value
743 * from any live channel.
745 surf_index
= src_reg(this, glsl_type::uint_type
);
746 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
747 instr
->num_components
),
748 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
749 surf_index
= emit_uniformize(surf_index
);
751 /* Assume this may touch any UBO. It would be nice to provide
752 * a tighter bound, but the array information is already lowered away.
754 brw_mark_surface_used(&prog_data
->base
,
755 prog_data
->base
.binding_table
.ubo_start
+
756 nir
->info
.num_ubos
- 1);
759 unsigned const_offset
= instr
->const_index
[0];
763 offset
= brw_imm_ud(const_offset
/ 16);
765 offset
= src_reg(this, glsl_type::uint_type
);
766 emit(SHR(dst_reg(offset
), get_nir_src(instr
->src
[1], nir_type_int
, 1),
770 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
771 packed_consts
.type
= dest
.type
;
773 emit_pull_constant_load_reg(dst_reg(packed_consts
),
776 NULL
, NULL
/* before_block/inst */);
778 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
779 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
780 const_offset
% 16 / 4,
781 const_offset
% 16 / 4,
782 const_offset
% 16 / 4);
784 emit(MOV(dest
, packed_consts
));
788 case nir_intrinsic_memory_barrier
: {
789 const vec4_builder bld
=
790 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
791 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
792 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
797 case nir_intrinsic_shader_clock
: {
798 /* We cannot do anything if there is an event, so ignore it for now */
799 const src_reg shader_clock
= get_timestamp();
800 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
802 dest
= get_nir_dest(instr
->dest
, type
);
803 emit(MOV(dest
, shader_clock
));
808 unreachable("Unknown intrinsic");
813 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
816 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
817 dest
= get_nir_dest(instr
->dest
);
820 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
822 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
824 surface
= brw_imm_ud(surf_index
);
825 brw_mark_surface_used(&prog_data
->base
, surf_index
);
827 surface
= src_reg(this, glsl_type::uint_type
);
828 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
829 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
831 /* Assume this may touch any UBO. This is the same we do for other
832 * UBO/SSBO accesses with non-constant surface.
834 brw_mark_surface_used(&prog_data
->base
,
835 prog_data
->base
.binding_table
.ssbo_start
+
836 nir
->info
.num_ssbos
- 1);
839 src_reg offset
= get_nir_src(instr
->src
[1], 1);
840 src_reg data1
= get_nir_src(instr
->src
[2], 1);
842 if (op
== BRW_AOP_CMPWR
)
843 data2
= get_nir_src(instr
->src
[3], 1);
845 /* Emit the actual atomic operation operation */
846 const vec4_builder bld
=
847 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
849 src_reg atomic_result
=
850 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
852 1 /* dims */, 1 /* rsize */,
855 dest
.type
= atomic_result
.type
;
856 bld
.MOV(dest
, atomic_result
);
860 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
862 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
865 static enum brw_conditional_mod
866 brw_conditional_for_nir_comparison(nir_op op
)
872 return BRW_CONDITIONAL_L
;
877 return BRW_CONDITIONAL_GE
;
881 case nir_op_ball_fequal2
:
882 case nir_op_ball_iequal2
:
883 case nir_op_ball_fequal3
:
884 case nir_op_ball_iequal3
:
885 case nir_op_ball_fequal4
:
886 case nir_op_ball_iequal4
:
887 return BRW_CONDITIONAL_Z
;
891 case nir_op_bany_fnequal2
:
892 case nir_op_bany_inequal2
:
893 case nir_op_bany_fnequal3
:
894 case nir_op_bany_inequal3
:
895 case nir_op_bany_fnequal4
:
896 case nir_op_bany_inequal4
:
897 return BRW_CONDITIONAL_NZ
;
900 unreachable("not reached: bad operation for comparison");
905 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
907 vec4_instruction
*inst
;
909 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
910 nir_op_infos
[instr
->op
].output_type
);
911 dst
.writemask
= instr
->dest
.write_mask
;
914 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
915 op
[i
] = get_nir_src(instr
->src
[i
].src
,
916 nir_op_infos
[instr
->op
].input_types
[i
], 4);
917 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
918 op
[i
].abs
= instr
->src
[i
].abs
;
919 op
[i
].negate
= instr
->src
[i
].negate
;
925 inst
= emit(MOV(dst
, op
[0]));
926 inst
->saturate
= instr
->dest
.saturate
;
932 unreachable("not reached: should be handled by lower_vec_to_movs()");
936 inst
= emit(MOV(dst
, op
[0]));
937 inst
->saturate
= instr
->dest
.saturate
;
942 inst
= emit(MOV(dst
, op
[0]));
948 inst
= emit(ADD(dst
, op
[0], op
[1]));
949 inst
->saturate
= instr
->dest
.saturate
;
953 inst
= emit(MUL(dst
, op
[0], op
[1]));
954 inst
->saturate
= instr
->dest
.saturate
;
958 if (devinfo
->gen
< 8) {
959 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
960 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
962 /* For integer multiplication, the MUL uses the low 16 bits of one of
963 * the operands (src0 through SNB, src1 on IVB and later). The MACH
964 * accumulates in the contribution of the upper 16 bits of that
965 * operand. If we can determine that one of the args is in the low
966 * 16 bits, though, we can just emit a single MUL.
968 if (value0
&& value0
->u
[0] < (1 << 16)) {
969 if (devinfo
->gen
< 7)
970 emit(MUL(dst
, op
[0], op
[1]));
972 emit(MUL(dst
, op
[1], op
[0]));
973 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
974 if (devinfo
->gen
< 7)
975 emit(MUL(dst
, op
[1], op
[0]));
977 emit(MUL(dst
, op
[0], op
[1]));
979 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
981 emit(MUL(acc
, op
[0], op
[1]));
982 emit(MACH(dst_null_d(), op
[0], op
[1]));
983 emit(MOV(dst
, src_reg(acc
)));
986 emit(MUL(dst
, op
[0], op
[1]));
991 case nir_op_imul_high
:
992 case nir_op_umul_high
: {
993 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
995 emit(MUL(acc
, op
[0], op
[1]));
996 emit(MACH(dst
, op
[0], op
[1]));
1001 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1002 inst
->saturate
= instr
->dest
.saturate
;
1006 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1007 inst
->saturate
= instr
->dest
.saturate
;
1011 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1012 inst
->saturate
= instr
->dest
.saturate
;
1016 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1017 inst
->saturate
= instr
->dest
.saturate
;
1021 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1022 inst
->saturate
= instr
->dest
.saturate
;
1027 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1031 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1035 unreachable("not reached: should be handled by ldexp_to_arith()");
1038 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1039 inst
->saturate
= instr
->dest
.saturate
;
1043 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1048 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1049 inst
->saturate
= instr
->dest
.saturate
;
1052 case nir_op_uadd_carry
: {
1053 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1055 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1056 emit(MOV(dst
, src_reg(acc
)));
1060 case nir_op_usub_borrow
: {
1061 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1063 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1064 emit(MOV(dst
, src_reg(acc
)));
1069 inst
= emit(RNDZ(dst
, op
[0]));
1070 inst
->saturate
= instr
->dest
.saturate
;
1073 case nir_op_fceil
: {
1074 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1076 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1077 instr
->src
[0].src
.ssa
->num_components
:
1078 instr
->src
[0].src
.reg
.reg
->num_components
);
1080 op
[0].negate
= !op
[0].negate
;
1081 emit(RNDD(dst_reg(tmp
), op
[0]));
1083 inst
= emit(MOV(dst
, tmp
));
1084 inst
->saturate
= instr
->dest
.saturate
;
1089 inst
= emit(RNDD(dst
, op
[0]));
1090 inst
->saturate
= instr
->dest
.saturate
;
1094 inst
= emit(FRC(dst
, op
[0]));
1095 inst
->saturate
= instr
->dest
.saturate
;
1098 case nir_op_fround_even
:
1099 inst
= emit(RNDE(dst
, op
[0]));
1100 inst
->saturate
= instr
->dest
.saturate
;
1106 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1107 inst
->saturate
= instr
->dest
.saturate
;
1113 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1114 inst
->saturate
= instr
->dest
.saturate
;
1118 case nir_op_fddx_coarse
:
1119 case nir_op_fddx_fine
:
1121 case nir_op_fddy_coarse
:
1122 case nir_op_fddy_fine
:
1123 unreachable("derivatives are not valid in vertex shaders");
1135 emit(CMP(dst
, op
[0], op
[1],
1136 brw_conditional_for_nir_comparison(instr
->op
)));
1139 case nir_op_ball_fequal2
:
1140 case nir_op_ball_iequal2
:
1141 case nir_op_ball_fequal3
:
1142 case nir_op_ball_iequal3
:
1143 case nir_op_ball_fequal4
:
1144 case nir_op_ball_iequal4
: {
1146 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1148 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1149 brw_conditional_for_nir_comparison(instr
->op
)));
1150 emit(MOV(dst
, brw_imm_d(0)));
1151 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1152 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1156 case nir_op_bany_fnequal2
:
1157 case nir_op_bany_inequal2
:
1158 case nir_op_bany_fnequal3
:
1159 case nir_op_bany_inequal3
:
1160 case nir_op_bany_fnequal4
:
1161 case nir_op_bany_inequal4
: {
1163 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1165 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1166 brw_conditional_for_nir_comparison(instr
->op
)));
1168 emit(MOV(dst
, brw_imm_d(0)));
1169 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1170 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1175 if (devinfo
->gen
>= 8) {
1176 op
[0] = resolve_source_modifiers(op
[0]);
1178 emit(NOT(dst
, op
[0]));
1182 if (devinfo
->gen
>= 8) {
1183 op
[0] = resolve_source_modifiers(op
[0]);
1184 op
[1] = resolve_source_modifiers(op
[1]);
1186 emit(XOR(dst
, op
[0], op
[1]));
1190 if (devinfo
->gen
>= 8) {
1191 op
[0] = resolve_source_modifiers(op
[0]);
1192 op
[1] = resolve_source_modifiers(op
[1]);
1194 emit(OR(dst
, op
[0], op
[1]));
1198 if (devinfo
->gen
>= 8) {
1199 op
[0] = resolve_source_modifiers(op
[0]);
1200 op
[1] = resolve_source_modifiers(op
[1]);
1202 emit(AND(dst
, op
[0], op
[1]));
1207 emit(MOV(dst
, negate(op
[0])));
1211 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1215 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1218 case nir_op_fnoise1_1
:
1219 case nir_op_fnoise1_2
:
1220 case nir_op_fnoise1_3
:
1221 case nir_op_fnoise1_4
:
1222 case nir_op_fnoise2_1
:
1223 case nir_op_fnoise2_2
:
1224 case nir_op_fnoise2_3
:
1225 case nir_op_fnoise2_4
:
1226 case nir_op_fnoise3_1
:
1227 case nir_op_fnoise3_2
:
1228 case nir_op_fnoise3_3
:
1229 case nir_op_fnoise3_4
:
1230 case nir_op_fnoise4_1
:
1231 case nir_op_fnoise4_2
:
1232 case nir_op_fnoise4_3
:
1233 case nir_op_fnoise4_4
:
1234 unreachable("not reached: should be handled by lower_noise");
1236 case nir_op_unpack_half_2x16_split_x
:
1237 case nir_op_unpack_half_2x16_split_y
:
1238 case nir_op_pack_half_2x16_split
:
1239 unreachable("not reached: should not occur in vertex shader");
1241 case nir_op_unpack_snorm_2x16
:
1242 case nir_op_unpack_unorm_2x16
:
1243 case nir_op_pack_snorm_2x16
:
1244 case nir_op_pack_unorm_2x16
:
1245 unreachable("not reached: should be handled by lower_packing_builtins");
1247 case nir_op_unpack_half_2x16
:
1248 /* As NIR does not guarantee that we have a correct swizzle outside the
1249 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1250 * uses the source operand in an operation with WRITEMASK_Y while our
1251 * source operand has only size 1, it accessed incorrect data producing
1252 * regressions in Piglit. We repeat the swizzle of the first component on the
1253 * rest of components to avoid regressions. In the vec4_visitor IR code path
1254 * this is not needed because the operand has already the correct swizzle.
1256 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1257 emit_unpack_half_2x16(dst
, op
[0]);
1260 case nir_op_pack_half_2x16
:
1261 emit_pack_half_2x16(dst
, op
[0]);
1264 case nir_op_unpack_unorm_4x8
:
1265 emit_unpack_unorm_4x8(dst
, op
[0]);
1268 case nir_op_pack_unorm_4x8
:
1269 emit_pack_unorm_4x8(dst
, op
[0]);
1272 case nir_op_unpack_snorm_4x8
:
1273 emit_unpack_snorm_4x8(dst
, op
[0]);
1276 case nir_op_pack_snorm_4x8
:
1277 emit_pack_snorm_4x8(dst
, op
[0]);
1280 case nir_op_bitfield_reverse
:
1281 emit(BFREV(dst
, op
[0]));
1284 case nir_op_bit_count
:
1285 emit(CBIT(dst
, op
[0]));
1288 case nir_op_ufind_msb
:
1289 case nir_op_ifind_msb
: {
1290 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1292 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1293 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1294 * subtract the result from 31 to convert the MSB count into an LSB count.
1297 emit(CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
));
1299 inst
= emit(ADD(dst
, src
, brw_imm_d(31)));
1300 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1301 inst
->src
[0].negate
= true;
1305 case nir_op_find_lsb
:
1306 emit(FBL(dst
, op
[0]));
1309 case nir_op_ubitfield_extract
:
1310 case nir_op_ibitfield_extract
:
1311 op
[0] = fix_3src_operand(op
[0]);
1312 op
[1] = fix_3src_operand(op
[1]);
1313 op
[2] = fix_3src_operand(op
[2]);
1315 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1319 emit(BFI1(dst
, op
[0], op
[1]));
1323 op
[0] = fix_3src_operand(op
[0]);
1324 op
[1] = fix_3src_operand(op
[1]);
1325 op
[2] = fix_3src_operand(op
[2]);
1327 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1330 case nir_op_bitfield_insert
:
1331 unreachable("not reached: should be handled by "
1332 "lower_instructions::bitfield_insert_to_bfm_bfi");
1335 /* AND(val, 0x80000000) gives the sign bit.
1337 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1340 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1342 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1343 dst
.type
= BRW_REGISTER_TYPE_UD
;
1344 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1346 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1347 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1348 dst
.type
= BRW_REGISTER_TYPE_F
;
1350 if (instr
->dest
.saturate
) {
1351 inst
= emit(MOV(dst
, src_reg(dst
)));
1352 inst
->saturate
= true;
1357 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1358 * -> non-negative val generates 0x00000000.
1359 * Predicated OR sets 1 if val is positive.
1361 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1362 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1363 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1364 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1368 emit(SHL(dst
, op
[0], op
[1]));
1372 emit(ASR(dst
, op
[0], op
[1]));
1376 emit(SHR(dst
, op
[0], op
[1]));
1380 op
[0] = fix_3src_operand(op
[0]);
1381 op
[1] = fix_3src_operand(op
[1]);
1382 op
[2] = fix_3src_operand(op
[2]);
1384 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1385 inst
->saturate
= instr
->dest
.saturate
;
1389 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1390 inst
->saturate
= instr
->dest
.saturate
;
1394 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1395 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1396 switch (dst
.writemask
) {
1398 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1401 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1404 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1407 inst
->predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1410 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1415 case nir_op_fdot_replicated2
:
1416 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1417 inst
->saturate
= instr
->dest
.saturate
;
1420 case nir_op_fdot_replicated3
:
1421 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1422 inst
->saturate
= instr
->dest
.saturate
;
1425 case nir_op_fdot_replicated4
:
1426 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1427 inst
->saturate
= instr
->dest
.saturate
;
1430 case nir_op_fdph_replicated
:
1431 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1432 inst
->saturate
= instr
->dest
.saturate
;
1437 case nir_op_bany4
: {
1439 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1441 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), brw_imm_d(0),
1442 BRW_CONDITIONAL_NZ
));
1443 emit(MOV(dst
, brw_imm_d(0)));
1444 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1445 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1454 unreachable("not reached: should be lowered by lower_source mods");
1457 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1460 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1464 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1467 unreachable("Unimplemented ALU operation");
1470 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1471 * to sign extend the low bit to 0/~0
1473 if (devinfo
->gen
<= 5 &&
1474 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1475 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1476 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1477 masked
.writemask
= dst
.writemask
;
1478 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1479 src_reg masked_neg
= src_reg(masked
);
1480 masked_neg
.negate
= true;
1481 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1486 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1488 switch (instr
->type
) {
1489 case nir_jump_break
:
1490 emit(BRW_OPCODE_BREAK
);
1493 case nir_jump_continue
:
1494 emit(BRW_OPCODE_CONTINUE
);
1497 case nir_jump_return
:
1500 unreachable("unknown jump");
1504 enum ir_texture_opcode
1505 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1507 enum ir_texture_opcode op
;
1510 case nir_texop_lod
: op
= ir_lod
; break;
1511 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1512 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1513 case nir_texop_tex
: op
= ir_tex
; break;
1514 case nir_texop_tg4
: op
= ir_tg4
; break;
1515 case nir_texop_txb
: op
= ir_txb
; break;
1516 case nir_texop_txd
: op
= ir_txd
; break;
1517 case nir_texop_txf
: op
= ir_txf
; break;
1518 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1519 case nir_texop_txl
: op
= ir_txl
; break;
1520 case nir_texop_txs
: op
= ir_txs
; break;
1521 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
1523 unreachable("unknown texture opcode");
1529 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1530 unsigned components
)
1533 case nir_type_float
:
1534 return glsl_type::vec(components
);
1536 return glsl_type::ivec(components
);
1538 return glsl_type::uvec(components
);
1540 return glsl_type::bvec(components
);
1542 return glsl_type::error_type
;
1545 return glsl_type::error_type
;
1549 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1551 unsigned sampler
= instr
->sampler_index
;
1552 src_reg sampler_reg
= brw_imm_ud(sampler
);
1554 const glsl_type
*coord_type
= NULL
;
1555 src_reg shadow_comparitor
;
1556 src_reg offset_value
;
1558 src_reg sample_index
;
1561 const glsl_type
*dest_type
=
1562 glsl_type_for_nir_alu_type(instr
->dest_type
,
1563 nir_tex_instr_dest_size(instr
));
1564 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1566 /* Load the texture operation sources */
1567 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1568 switch (instr
->src
[i
].src_type
) {
1569 case nir_tex_src_comparitor
:
1570 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1571 BRW_REGISTER_TYPE_F
, 1);
1574 case nir_tex_src_coord
: {
1575 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1577 switch (instr
->op
) {
1579 case nir_texop_txf_ms
:
1580 case nir_texop_samples_identical
:
1581 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1583 coord_type
= glsl_type::ivec(src_size
);
1587 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1589 coord_type
= glsl_type::vec(src_size
);
1595 case nir_tex_src_ddx
:
1596 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1597 nir_tex_instr_src_size(instr
, i
));
1600 case nir_tex_src_ddy
:
1601 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1602 nir_tex_instr_src_size(instr
, i
));
1605 case nir_tex_src_lod
:
1606 switch (instr
->op
) {
1609 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1613 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1618 case nir_tex_src_ms_index
: {
1619 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1623 case nir_tex_src_offset
:
1624 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1627 case nir_tex_src_sampler_offset
: {
1628 /* The highest sampler which may be used by this operation is
1629 * the last element of the array. Mark it here, because the generator
1630 * doesn't have enough information to determine the bound.
1632 uint32_t array_size
= instr
->sampler_array_size
;
1633 uint32_t max_used
= sampler
+ array_size
- 1;
1634 if (instr
->op
== nir_texop_tg4
) {
1635 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1637 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1640 brw_mark_surface_used(&prog_data
->base
, max_used
);
1642 /* Emit code to evaluate the actual indexing expression */
1643 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1644 src_reg
temp(this, glsl_type::uint_type
);
1645 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
1646 sampler_reg
= emit_uniformize(temp
);
1650 case nir_tex_src_projector
:
1651 unreachable("Should be lowered by do_lower_texture_projection");
1653 case nir_tex_src_bias
:
1654 unreachable("LOD bias is not valid for vertex shaders.\n");
1657 unreachable("unknown texture source");
1661 if (instr
->op
== nir_texop_txf_ms
||
1662 instr
->op
== nir_texop_samples_identical
) {
1663 assert(coord_type
!= NULL
);
1664 if (devinfo
->gen
>= 7 &&
1665 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1666 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1668 mcs
= brw_imm_ud(0u);
1672 uint32_t constant_offset
= 0;
1673 for (unsigned i
= 0; i
< 3; i
++) {
1674 if (instr
->const_offset
[i
] != 0) {
1675 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1680 /* Stuff the channel select bits in the top of the texture offset */
1681 if (instr
->op
== nir_texop_tg4
) {
1682 if (instr
->component
== 1 &&
1683 (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))) {
1684 /* gather4 sampler is broken for green channel on RG32F --
1685 * we must ask for blue instead.
1687 constant_offset
|= 2 << 16;
1689 constant_offset
|= instr
->component
<< 16;
1693 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1695 bool is_cube_array
=
1696 instr
->op
== nir_texop_txs
&&
1697 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1700 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1702 lod
, lod2
, sample_index
,
1703 constant_offset
, offset_value
,
1704 mcs
, is_cube_array
, sampler
, sampler_reg
);
1708 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1710 nir_ssa_values
[instr
->def
.index
] = dst_reg(VGRF
, alloc
.allocate(1));