2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_setup_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(nir
, function
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
63 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
,
67 case nir_intrinsic_load_base_vertex
:
68 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
69 if (reg
->file
== BAD_FILE
)
70 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
,
74 case nir_intrinsic_load_instance_id
:
75 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
76 if (reg
->file
== BAD_FILE
)
77 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
,
87 setup_system_values_block(nir_block
*block
, void *void_visitor
)
89 vec4_visitor
*v
= (vec4_visitor
*)void_visitor
;
91 nir_foreach_instr(block
, instr
) {
92 if (instr
->type
!= nir_instr_type_intrinsic
)
95 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
96 v
->nir_setup_system_value_intrinsic(intrin
);
103 vec4_visitor::nir_setup_system_values()
105 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
106 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
107 nir_system_values
[i
] = dst_reg();
110 nir_foreach_function(nir
, function
) {
111 assert(strcmp(function
->name
, "main") == 0);
112 assert(function
->impl
);
113 nir_foreach_block(function
->impl
, setup_system_values_block
, this);
118 vec4_visitor::nir_setup_uniforms()
120 uniforms
= nir
->num_uniforms
/ 16;
122 nir_foreach_variable(var
, &nir
->uniforms
) {
123 /* UBO's and atomics don't take up space in the uniform file */
124 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
127 if (type_size_vec4(var
->type
) > 0)
128 uniform_size
[var
->data
.driver_location
/ 16] = type_size_vec4(var
->type
);
133 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
135 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
136 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
137 nir_locals
[i
] = dst_reg();
140 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
141 unsigned array_elems
=
142 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
144 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(array_elems
));
147 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
149 nir_emit_cf_list(&impl
->body
);
153 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
155 exec_list_validate(list
);
156 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
157 switch (node
->type
) {
159 nir_emit_if(nir_cf_node_as_if(node
));
162 case nir_cf_node_loop
:
163 nir_emit_loop(nir_cf_node_as_loop(node
));
166 case nir_cf_node_block
:
167 nir_emit_block(nir_cf_node_as_block(node
));
171 unreachable("Invalid CFG node block");
177 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
179 /* First, put the condition in f0 */
180 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
181 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
182 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
184 /* We can just predicate based on the X channel, as the condition only
185 * goes on its own line */
186 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
188 nir_emit_cf_list(&if_stmt
->then_list
);
190 /* note: if the else is empty, dead CF elimination will remove it */
191 emit(BRW_OPCODE_ELSE
);
193 nir_emit_cf_list(&if_stmt
->else_list
);
195 emit(BRW_OPCODE_ENDIF
);
199 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
203 nir_emit_cf_list(&loop
->body
);
205 emit(BRW_OPCODE_WHILE
);
209 vec4_visitor::nir_emit_block(nir_block
*block
)
211 nir_foreach_instr(block
, instr
) {
212 nir_emit_instr(instr
);
217 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
221 switch (instr
->type
) {
222 case nir_instr_type_load_const
:
223 nir_emit_load_const(nir_instr_as_load_const(instr
));
226 case nir_instr_type_intrinsic
:
227 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
230 case nir_instr_type_alu
:
231 nir_emit_alu(nir_instr_as_alu(instr
));
234 case nir_instr_type_jump
:
235 nir_emit_jump(nir_instr_as_jump(instr
));
238 case nir_instr_type_tex
:
239 nir_emit_texture(nir_instr_as_tex(instr
));
242 case nir_instr_type_ssa_undef
:
243 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
247 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
253 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
254 unsigned base_offset
, nir_src
*indirect
)
258 reg
= v
->nir_locals
[nir_reg
->index
];
259 reg
= offset(reg
, base_offset
);
262 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
270 vec4_visitor::get_nir_dest(nir_dest dest
)
273 dst_reg dst
= dst_reg(VGRF
, alloc
.allocate(1));
274 nir_ssa_values
[dest
.ssa
.index
] = dst
;
277 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
283 vec4_visitor::get_nir_dest(nir_dest dest
, enum brw_reg_type type
)
285 return retype(get_nir_dest(dest
), type
);
289 vec4_visitor::get_nir_dest(nir_dest dest
, nir_alu_type type
)
291 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
295 vec4_visitor::get_nir_src(nir_src src
, enum brw_reg_type type
,
296 unsigned num_components
)
301 assert(src
.ssa
!= NULL
);
302 reg
= nir_ssa_values
[src
.ssa
->index
];
305 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
309 reg
= retype(reg
, type
);
311 src_reg reg_as_src
= src_reg(reg
);
312 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
317 vec4_visitor::get_nir_src(nir_src src
, nir_alu_type type
,
318 unsigned num_components
)
320 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
324 vec4_visitor::get_nir_src(nir_src src
, unsigned num_components
)
326 /* if type is not specified, default to signed int */
327 return get_nir_src(src
, nir_type_int
, num_components
);
331 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
333 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
334 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
337 /* The only constant offset we should find is 0. brw_nir.c's
338 * add_const_offset_to_base() will fold other constant offsets
339 * into instr->const_index[0].
341 assert(const_value
->u
[0] == 0);
345 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
349 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
351 dst_reg reg
= dst_reg(VGRF
, alloc
.allocate(1));
352 reg
.type
= BRW_REGISTER_TYPE_D
;
354 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
356 /* @FIXME: consider emitting vector operations to save some MOVs in
357 * cases where the components are representable in 8 bits.
358 * For now, we emit a MOV for each distinct value.
360 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
361 unsigned writemask
= 1 << i
;
363 if ((remaining
& writemask
) == 0)
366 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
367 if (instr
->value
.u
[i
] == instr
->value
.u
[j
]) {
372 reg
.writemask
= writemask
;
373 emit(MOV(reg
, brw_imm_d(instr
->value
.i
[i
])));
375 remaining
&= ~writemask
;
378 /* Set final writemask */
379 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
381 nir_ssa_values
[instr
->def
.index
] = reg
;
385 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
390 switch (instr
->intrinsic
) {
392 case nir_intrinsic_load_input
: {
393 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
395 /* We set EmitNoIndirectInput for VS */
396 assert(const_offset
);
398 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u
[0],
399 glsl_type::uvec4_type
);
401 dest
= get_nir_dest(instr
->dest
, src
.type
);
402 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
404 emit(MOV(dest
, src
));
408 case nir_intrinsic_store_output
: {
409 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
410 assert(const_offset
);
412 int varying
= instr
->const_index
[0] + const_offset
->u
[0];
414 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
415 instr
->num_components
);
417 output_reg
[varying
] = dst_reg(src
);
421 case nir_intrinsic_get_buffer_size
: {
422 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
423 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
425 const unsigned index
=
426 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
427 dst_reg result_dst
= get_nir_dest(instr
->dest
);
428 vec4_instruction
*inst
= new(mem_ctx
)
429 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
432 inst
->mlen
= 1; /* always at least one */
433 inst
->src
[1] = brw_imm_ud(index
);
435 /* MRF for the first parameter */
436 src_reg lod
= brw_imm_d(0);
437 int param_base
= inst
->base_mrf
;
438 int writemask
= WRITEMASK_X
;
439 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
443 brw_mark_surface_used(&prog_data
->base
, index
);
447 case nir_intrinsic_store_ssbo
: {
448 assert(devinfo
->gen
>= 7);
452 nir_const_value
*const_uniform_block
=
453 nir_src_as_const_value(instr
->src
[1]);
454 if (const_uniform_block
) {
455 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
456 const_uniform_block
->u
[0];
457 surf_index
= brw_imm_ud(index
);
458 brw_mark_surface_used(&prog_data
->base
, index
);
460 surf_index
= src_reg(this, glsl_type::uint_type
);
461 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
462 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
463 surf_index
= emit_uniformize(surf_index
);
465 brw_mark_surface_used(&prog_data
->base
,
466 prog_data
->base
.binding_table
.ssbo_start
+
467 nir
->info
.num_ssbos
- 1);
472 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
474 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
476 offset_reg
= get_nir_src(instr
->src
[2], 1);
480 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
483 unsigned write_mask
= instr
->const_index
[0];
485 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
486 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
487 * typed and untyped messages and across hardware platforms, the
488 * current implementation of the untyped messages will transparently convert
489 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
490 * and enabling only channel X on the SEND instruction.
492 * The above, works well for full vector writes, but not for partial writes
493 * where we want to write some channels and not others, like when we have
494 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
495 * quite restrictive with regards to the channel enables we can configure in
496 * the message descriptor (not all combinations are allowed) we cannot simply
497 * implement these scenarios with a single message while keeping the
498 * aforementioned symmetry in the implementation. For now we de decided that
499 * it is better to keep the symmetry to reduce complexity, so in situations
500 * such as the one described we end up emitting two untyped write messages
501 * (one for xy and another for w).
503 * The code below packs consecutive channels into a single write message,
504 * detects gaps in the vector write and if needed, sends a second message
505 * with the remaining channels. If in the future we decide that we want to
506 * emit a single message at the expense of losing the symmetry in the
507 * implementation we can:
509 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
510 * message payload. In this mode we can write up to 8 offsets and dwords
511 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
512 * and select which of the 8 channels carry data to write by setting the
513 * appropriate writemask in the dst register of the SEND instruction.
514 * It would require to write a new generator opcode specifically for
515 * IvyBridge since we would need to prepare a SIMD8 payload that could
516 * use any channel, not just X.
518 * 2) For Haswell+: Simply send a single write message but set the writemask
519 * on the dst of the SEND instruction to select the channels we want to
520 * write. It would require to modify the current messages to receive
521 * and honor the writemask provided.
523 const vec4_builder bld
= vec4_builder(this).at_end()
524 .annotate(current_annotation
, base_ir
);
526 int swizzle
[4] = { 0, 0, 0, 0};
527 int num_channels
= 0;
528 unsigned skipped_channels
= 0;
529 int num_components
= instr
->num_components
;
530 for (int i
= 0; i
< num_components
; i
++) {
531 /* Check if this channel needs to be written. If so, record the
532 * channel we need to take the data from in the swizzle array
534 int component_mask
= 1 << i
;
535 int write_test
= write_mask
& component_mask
;
537 swizzle
[num_channels
++] = i
;
539 /* If we don't have to write this channel it means we have a gap in the
540 * vector, so write the channels we accumulated until now, if any. Do
541 * the same if this was the last component in the vector.
543 if (!write_test
|| i
== num_components
- 1) {
544 if (num_channels
> 0) {
545 /* We have channels to write, so update the offset we need to
546 * write at to skip the channels we skipped, if any.
548 if (skipped_channels
> 0) {
549 if (offset_reg
.file
== IMM
) {
550 offset_reg
.ud
+= 4 * skipped_channels
;
552 emit(ADD(dst_reg(offset_reg
), offset_reg
,
553 brw_imm_ud(4 * skipped_channels
)));
557 /* Swizzle the data register so we take the data from the channels
558 * we need to write and send the write message. This will write
559 * num_channels consecutive dwords starting at offset.
562 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
563 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
564 1 /* dims */, num_channels
/* size */,
567 /* If we have to do a second write we will have to update the
568 * offset so that we jump over the channels we have just written
571 skipped_channels
= num_channels
;
573 /* Restart the count for the next write message */
577 /* We did not write the current channel, so increase skipped count */
585 case nir_intrinsic_load_ssbo
: {
586 assert(devinfo
->gen
>= 7);
588 nir_const_value
*const_uniform_block
=
589 nir_src_as_const_value(instr
->src
[0]);
592 if (const_uniform_block
) {
593 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
594 const_uniform_block
->u
[0];
595 surf_index
= brw_imm_ud(index
);
597 brw_mark_surface_used(&prog_data
->base
, index
);
599 surf_index
= src_reg(this, glsl_type::uint_type
);
600 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
601 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
602 surf_index
= emit_uniformize(surf_index
);
604 /* Assume this may touch any UBO. It would be nice to provide
605 * a tighter bound, but the array information is already lowered away.
607 brw_mark_surface_used(&prog_data
->base
,
608 prog_data
->base
.binding_table
.ssbo_start
+
609 nir
->info
.num_ssbos
- 1);
613 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
615 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
617 offset_reg
= get_nir_src(instr
->src
[1], 1);
620 /* Read the vector */
621 const vec4_builder bld
= vec4_builder(this).at_end()
622 .annotate(current_annotation
, base_ir
);
624 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
625 1 /* dims */, 4 /* size*/,
627 dst_reg dest
= get_nir_dest(instr
->dest
);
628 read_result
.type
= dest
.type
;
629 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
630 emit(MOV(dest
, read_result
));
635 case nir_intrinsic_ssbo_atomic_add
:
636 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
638 case nir_intrinsic_ssbo_atomic_imin
:
639 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
641 case nir_intrinsic_ssbo_atomic_umin
:
642 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
644 case nir_intrinsic_ssbo_atomic_imax
:
645 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
647 case nir_intrinsic_ssbo_atomic_umax
:
648 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
650 case nir_intrinsic_ssbo_atomic_and
:
651 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
653 case nir_intrinsic_ssbo_atomic_or
:
654 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
656 case nir_intrinsic_ssbo_atomic_xor
:
657 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
659 case nir_intrinsic_ssbo_atomic_exchange
:
660 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
662 case nir_intrinsic_ssbo_atomic_comp_swap
:
663 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
666 case nir_intrinsic_load_vertex_id
:
667 unreachable("should be lowered by lower_vertex_id()");
669 case nir_intrinsic_load_vertex_id_zero_base
:
670 case nir_intrinsic_load_base_vertex
:
671 case nir_intrinsic_load_instance_id
:
672 case nir_intrinsic_load_invocation_id
:
673 case nir_intrinsic_load_tess_level_inner
:
674 case nir_intrinsic_load_tess_level_outer
: {
675 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
676 src_reg val
= src_reg(nir_system_values
[sv
]);
677 assert(val
.file
!= BAD_FILE
);
678 dest
= get_nir_dest(instr
->dest
, val
.type
);
679 emit(MOV(dest
, val
));
683 case nir_intrinsic_load_uniform
: {
684 /* Offsets are in bytes but they should always be multiples of 16 */
685 assert(instr
->const_index
[0] % 16 == 0);
687 dest
= get_nir_dest(instr
->dest
);
689 src
= src_reg(dst_reg(UNIFORM
, instr
->const_index
[0] / 16));
690 src
.type
= dest
.type
;
692 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
694 /* Offsets are in bytes but they should always be multiples of 16 */
695 assert(const_offset
->u
[0] % 16 == 0);
696 src
.reg_offset
= const_offset
->u
[0] / 16;
698 src_reg tmp
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_D
, 1);
699 src
.reladdr
= new(mem_ctx
) src_reg(tmp
);
702 emit(MOV(dest
, src
));
706 case nir_intrinsic_atomic_counter_read
:
707 case nir_intrinsic_atomic_counter_inc
:
708 case nir_intrinsic_atomic_counter_dec
: {
709 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
710 (unsigned) instr
->const_index
[0];
711 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int
,
712 instr
->num_components
);
713 dest
= get_nir_dest(instr
->dest
);
715 switch (instr
->intrinsic
) {
716 case nir_intrinsic_atomic_counter_inc
:
717 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
718 src_reg(), src_reg());
720 case nir_intrinsic_atomic_counter_dec
:
721 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
722 src_reg(), src_reg());
724 case nir_intrinsic_atomic_counter_read
:
725 emit_untyped_surface_read(surf_index
, dest
, offset
);
728 unreachable("Unreachable");
731 brw_mark_surface_used(stage_prog_data
, surf_index
);
735 case nir_intrinsic_load_ubo
: {
736 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
739 dest
= get_nir_dest(instr
->dest
);
741 if (const_block_index
) {
742 /* The block index is a constant, so just emit the binding table entry
745 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
746 const_block_index
->u
[0];
747 surf_index
= brw_imm_ud(index
);
748 brw_mark_surface_used(&prog_data
->base
, index
);
750 /* The block index is not a constant. Evaluate the index expression
751 * per-channel and add the base UBO index; we have to select a value
752 * from any live channel.
754 surf_index
= src_reg(this, glsl_type::uint_type
);
755 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int
,
756 instr
->num_components
),
757 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
758 surf_index
= emit_uniformize(surf_index
);
760 /* Assume this may touch any UBO. It would be nice to provide
761 * a tighter bound, but the array information is already lowered away.
763 brw_mark_surface_used(&prog_data
->base
,
764 prog_data
->base
.binding_table
.ubo_start
+
765 nir
->info
.num_ubos
- 1);
769 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
771 offset
= brw_imm_ud(const_offset
->u
[0] & ~15);
773 offset
= get_nir_src(instr
->src
[1], nir_type_int
, 1);
776 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
777 packed_consts
.type
= dest
.type
;
779 emit_pull_constant_load_reg(dst_reg(packed_consts
),
782 NULL
, NULL
/* before_block/inst */);
784 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
786 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
->u
[0] % 16 / 4,
787 const_offset
->u
[0] % 16 / 4,
788 const_offset
->u
[0] % 16 / 4,
789 const_offset
->u
[0] % 16 / 4);
792 emit(MOV(dest
, packed_consts
));
796 case nir_intrinsic_memory_barrier
: {
797 const vec4_builder bld
=
798 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
799 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
800 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
805 case nir_intrinsic_shader_clock
: {
806 /* We cannot do anything if there is an event, so ignore it for now */
807 const src_reg shader_clock
= get_timestamp();
808 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
810 dest
= get_nir_dest(instr
->dest
, type
);
811 emit(MOV(dest
, shader_clock
));
816 unreachable("Unknown intrinsic");
821 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
824 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
825 dest
= get_nir_dest(instr
->dest
);
828 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
830 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
832 surface
= brw_imm_ud(surf_index
);
833 brw_mark_surface_used(&prog_data
->base
, surf_index
);
835 surface
= src_reg(this, glsl_type::uint_type
);
836 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
837 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
839 /* Assume this may touch any UBO. This is the same we do for other
840 * UBO/SSBO accesses with non-constant surface.
842 brw_mark_surface_used(&prog_data
->base
,
843 prog_data
->base
.binding_table
.ssbo_start
+
844 nir
->info
.num_ssbos
- 1);
847 src_reg offset
= get_nir_src(instr
->src
[1], 1);
848 src_reg data1
= get_nir_src(instr
->src
[2], 1);
850 if (op
== BRW_AOP_CMPWR
)
851 data2
= get_nir_src(instr
->src
[3], 1);
853 /* Emit the actual atomic operation operation */
854 const vec4_builder bld
=
855 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
857 src_reg atomic_result
=
858 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
860 1 /* dims */, 1 /* rsize */,
863 dest
.type
= atomic_result
.type
;
864 bld
.MOV(dest
, atomic_result
);
868 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
870 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
873 static enum brw_conditional_mod
874 brw_conditional_for_nir_comparison(nir_op op
)
880 return BRW_CONDITIONAL_L
;
885 return BRW_CONDITIONAL_GE
;
889 case nir_op_ball_fequal2
:
890 case nir_op_ball_iequal2
:
891 case nir_op_ball_fequal3
:
892 case nir_op_ball_iequal3
:
893 case nir_op_ball_fequal4
:
894 case nir_op_ball_iequal4
:
895 return BRW_CONDITIONAL_Z
;
899 case nir_op_bany_fnequal2
:
900 case nir_op_bany_inequal2
:
901 case nir_op_bany_fnequal3
:
902 case nir_op_bany_inequal3
:
903 case nir_op_bany_fnequal4
:
904 case nir_op_bany_inequal4
:
905 return BRW_CONDITIONAL_NZ
;
908 unreachable("not reached: bad operation for comparison");
913 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
914 enum brw_predicate
*predicate
)
916 if (!instr
->src
[0].src
.is_ssa
||
917 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
920 nir_alu_instr
*cmp_instr
=
921 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
923 switch (cmp_instr
->op
) {
924 case nir_op_bany_fnequal2
:
925 case nir_op_bany_inequal2
:
926 case nir_op_bany_fnequal3
:
927 case nir_op_bany_inequal3
:
928 case nir_op_bany_fnequal4
:
929 case nir_op_bany_inequal4
:
930 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
932 case nir_op_ball_fequal2
:
933 case nir_op_ball_iequal2
:
934 case nir_op_ball_fequal3
:
935 case nir_op_ball_iequal3
:
936 case nir_op_ball_fequal4
:
937 case nir_op_ball_iequal4
:
938 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
944 unsigned size_swizzle
=
945 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
948 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
949 for (unsigned i
= 0; i
< 2; i
++) {
950 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
,
951 nir_op_infos
[cmp_instr
->op
].input_types
[i
], 4);
952 unsigned base_swizzle
=
953 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
954 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
955 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
956 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
959 emit(CMP(dst_null_d(), op
[0], op
[1],
960 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
966 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
968 vec4_instruction
*inst
;
970 dst_reg dst
= get_nir_dest(instr
->dest
.dest
,
971 nir_op_infos
[instr
->op
].output_type
);
972 dst
.writemask
= instr
->dest
.write_mask
;
975 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
976 op
[i
] = get_nir_src(instr
->src
[i
].src
,
977 nir_op_infos
[instr
->op
].input_types
[i
], 4);
978 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
979 op
[i
].abs
= instr
->src
[i
].abs
;
980 op
[i
].negate
= instr
->src
[i
].negate
;
986 inst
= emit(MOV(dst
, op
[0]));
987 inst
->saturate
= instr
->dest
.saturate
;
993 unreachable("not reached: should be handled by lower_vec_to_movs()");
997 inst
= emit(MOV(dst
, op
[0]));
998 inst
->saturate
= instr
->dest
.saturate
;
1003 inst
= emit(MOV(dst
, op
[0]));
1009 inst
= emit(ADD(dst
, op
[0], op
[1]));
1010 inst
->saturate
= instr
->dest
.saturate
;
1014 inst
= emit(MUL(dst
, op
[0], op
[1]));
1015 inst
->saturate
= instr
->dest
.saturate
;
1019 if (devinfo
->gen
< 8) {
1020 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1021 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1023 /* For integer multiplication, the MUL uses the low 16 bits of one of
1024 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1025 * accumulates in the contribution of the upper 16 bits of that
1026 * operand. If we can determine that one of the args is in the low
1027 * 16 bits, though, we can just emit a single MUL.
1029 if (value0
&& value0
->u
[0] < (1 << 16)) {
1030 if (devinfo
->gen
< 7)
1031 emit(MUL(dst
, op
[0], op
[1]));
1033 emit(MUL(dst
, op
[1], op
[0]));
1034 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
1035 if (devinfo
->gen
< 7)
1036 emit(MUL(dst
, op
[1], op
[0]));
1038 emit(MUL(dst
, op
[0], op
[1]));
1040 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1042 emit(MUL(acc
, op
[0], op
[1]));
1043 emit(MACH(dst_null_d(), op
[0], op
[1]));
1044 emit(MOV(dst
, src_reg(acc
)));
1047 emit(MUL(dst
, op
[0], op
[1]));
1052 case nir_op_imul_high
:
1053 case nir_op_umul_high
: {
1054 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1056 emit(MUL(acc
, op
[0], op
[1]));
1057 emit(MACH(dst
, op
[0], op
[1]));
1062 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1063 inst
->saturate
= instr
->dest
.saturate
;
1067 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1068 inst
->saturate
= instr
->dest
.saturate
;
1072 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1073 inst
->saturate
= instr
->dest
.saturate
;
1077 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1078 inst
->saturate
= instr
->dest
.saturate
;
1082 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1083 inst
->saturate
= instr
->dest
.saturate
;
1088 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1092 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1096 unreachable("not reached: should be handled by ldexp_to_arith()");
1099 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1100 inst
->saturate
= instr
->dest
.saturate
;
1104 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1105 inst
->saturate
= instr
->dest
.saturate
;
1109 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1110 inst
->saturate
= instr
->dest
.saturate
;
1113 case nir_op_uadd_carry
: {
1114 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1116 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1117 emit(MOV(dst
, src_reg(acc
)));
1121 case nir_op_usub_borrow
: {
1122 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1124 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1125 emit(MOV(dst
, src_reg(acc
)));
1130 inst
= emit(RNDZ(dst
, op
[0]));
1131 inst
->saturate
= instr
->dest
.saturate
;
1134 case nir_op_fceil
: {
1135 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1137 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1138 instr
->src
[0].src
.ssa
->num_components
:
1139 instr
->src
[0].src
.reg
.reg
->num_components
);
1141 op
[0].negate
= !op
[0].negate
;
1142 emit(RNDD(dst_reg(tmp
), op
[0]));
1144 inst
= emit(MOV(dst
, tmp
));
1145 inst
->saturate
= instr
->dest
.saturate
;
1150 inst
= emit(RNDD(dst
, op
[0]));
1151 inst
->saturate
= instr
->dest
.saturate
;
1155 inst
= emit(FRC(dst
, op
[0]));
1156 inst
->saturate
= instr
->dest
.saturate
;
1159 case nir_op_fround_even
:
1160 inst
= emit(RNDE(dst
, op
[0]));
1161 inst
->saturate
= instr
->dest
.saturate
;
1167 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1168 inst
->saturate
= instr
->dest
.saturate
;
1174 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1175 inst
->saturate
= instr
->dest
.saturate
;
1179 case nir_op_fddx_coarse
:
1180 case nir_op_fddx_fine
:
1182 case nir_op_fddy_coarse
:
1183 case nir_op_fddy_fine
:
1184 unreachable("derivatives are not valid in vertex shaders");
1196 emit(CMP(dst
, op
[0], op
[1],
1197 brw_conditional_for_nir_comparison(instr
->op
)));
1200 case nir_op_ball_fequal2
:
1201 case nir_op_ball_iequal2
:
1202 case nir_op_ball_fequal3
:
1203 case nir_op_ball_iequal3
:
1204 case nir_op_ball_fequal4
:
1205 case nir_op_ball_iequal4
: {
1207 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1209 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1210 brw_conditional_for_nir_comparison(instr
->op
)));
1211 emit(MOV(dst
, brw_imm_d(0)));
1212 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1213 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1217 case nir_op_bany_fnequal2
:
1218 case nir_op_bany_inequal2
:
1219 case nir_op_bany_fnequal3
:
1220 case nir_op_bany_inequal3
:
1221 case nir_op_bany_fnequal4
:
1222 case nir_op_bany_inequal4
: {
1224 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1226 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1227 brw_conditional_for_nir_comparison(instr
->op
)));
1229 emit(MOV(dst
, brw_imm_d(0)));
1230 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1231 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1236 if (devinfo
->gen
>= 8) {
1237 op
[0] = resolve_source_modifiers(op
[0]);
1239 emit(NOT(dst
, op
[0]));
1243 if (devinfo
->gen
>= 8) {
1244 op
[0] = resolve_source_modifiers(op
[0]);
1245 op
[1] = resolve_source_modifiers(op
[1]);
1247 emit(XOR(dst
, op
[0], op
[1]));
1251 if (devinfo
->gen
>= 8) {
1252 op
[0] = resolve_source_modifiers(op
[0]);
1253 op
[1] = resolve_source_modifiers(op
[1]);
1255 emit(OR(dst
, op
[0], op
[1]));
1259 if (devinfo
->gen
>= 8) {
1260 op
[0] = resolve_source_modifiers(op
[0]);
1261 op
[1] = resolve_source_modifiers(op
[1]);
1263 emit(AND(dst
, op
[0], op
[1]));
1268 emit(MOV(dst
, negate(op
[0])));
1272 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1276 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1279 case nir_op_fnoise1_1
:
1280 case nir_op_fnoise1_2
:
1281 case nir_op_fnoise1_3
:
1282 case nir_op_fnoise1_4
:
1283 case nir_op_fnoise2_1
:
1284 case nir_op_fnoise2_2
:
1285 case nir_op_fnoise2_3
:
1286 case nir_op_fnoise2_4
:
1287 case nir_op_fnoise3_1
:
1288 case nir_op_fnoise3_2
:
1289 case nir_op_fnoise3_3
:
1290 case nir_op_fnoise3_4
:
1291 case nir_op_fnoise4_1
:
1292 case nir_op_fnoise4_2
:
1293 case nir_op_fnoise4_3
:
1294 case nir_op_fnoise4_4
:
1295 unreachable("not reached: should be handled by lower_noise");
1297 case nir_op_unpack_half_2x16_split_x
:
1298 case nir_op_unpack_half_2x16_split_y
:
1299 case nir_op_pack_half_2x16_split
:
1300 unreachable("not reached: should not occur in vertex shader");
1302 case nir_op_unpack_snorm_2x16
:
1303 case nir_op_unpack_unorm_2x16
:
1304 case nir_op_pack_snorm_2x16
:
1305 case nir_op_pack_unorm_2x16
:
1306 unreachable("not reached: should be handled by lower_packing_builtins");
1308 case nir_op_unpack_half_2x16
:
1309 /* As NIR does not guarantee that we have a correct swizzle outside the
1310 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1311 * uses the source operand in an operation with WRITEMASK_Y while our
1312 * source operand has only size 1, it accessed incorrect data producing
1313 * regressions in Piglit. We repeat the swizzle of the first component on the
1314 * rest of components to avoid regressions. In the vec4_visitor IR code path
1315 * this is not needed because the operand has already the correct swizzle.
1317 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1318 emit_unpack_half_2x16(dst
, op
[0]);
1321 case nir_op_pack_half_2x16
:
1322 emit_pack_half_2x16(dst
, op
[0]);
1325 case nir_op_unpack_unorm_4x8
:
1326 emit_unpack_unorm_4x8(dst
, op
[0]);
1329 case nir_op_pack_unorm_4x8
:
1330 emit_pack_unorm_4x8(dst
, op
[0]);
1333 case nir_op_unpack_snorm_4x8
:
1334 emit_unpack_snorm_4x8(dst
, op
[0]);
1337 case nir_op_pack_snorm_4x8
:
1338 emit_pack_snorm_4x8(dst
, op
[0]);
1341 case nir_op_bitfield_reverse
:
1342 emit(BFREV(dst
, op
[0]));
1345 case nir_op_bit_count
:
1346 emit(CBIT(dst
, op
[0]));
1349 case nir_op_ufind_msb
:
1350 case nir_op_ifind_msb
: {
1351 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1353 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1354 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1355 * subtract the result from 31 to convert the MSB count into an LSB count.
1358 emit(CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
));
1360 inst
= emit(ADD(dst
, src
, brw_imm_d(31)));
1361 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1362 inst
->src
[0].negate
= true;
1366 case nir_op_find_lsb
:
1367 emit(FBL(dst
, op
[0]));
1370 case nir_op_ubitfield_extract
:
1371 case nir_op_ibitfield_extract
:
1372 op
[0] = fix_3src_operand(op
[0]);
1373 op
[1] = fix_3src_operand(op
[1]);
1374 op
[2] = fix_3src_operand(op
[2]);
1376 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1380 emit(BFI1(dst
, op
[0], op
[1]));
1384 op
[0] = fix_3src_operand(op
[0]);
1385 op
[1] = fix_3src_operand(op
[1]);
1386 op
[2] = fix_3src_operand(op
[2]);
1388 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1391 case nir_op_bitfield_insert
:
1392 unreachable("not reached: should be handled by "
1393 "lower_instructions::bitfield_insert_to_bfm_bfi");
1396 /* AND(val, 0x80000000) gives the sign bit.
1398 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1401 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1403 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1404 dst
.type
= BRW_REGISTER_TYPE_UD
;
1405 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1407 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1408 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1409 dst
.type
= BRW_REGISTER_TYPE_F
;
1411 if (instr
->dest
.saturate
) {
1412 inst
= emit(MOV(dst
, src_reg(dst
)));
1413 inst
->saturate
= true;
1418 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1419 * -> non-negative val generates 0x00000000.
1420 * Predicated OR sets 1 if val is positive.
1422 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1423 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1424 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1425 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1429 emit(SHL(dst
, op
[0], op
[1]));
1433 emit(ASR(dst
, op
[0], op
[1]));
1437 emit(SHR(dst
, op
[0], op
[1]));
1441 op
[0] = fix_3src_operand(op
[0]);
1442 op
[1] = fix_3src_operand(op
[1]);
1443 op
[2] = fix_3src_operand(op
[2]);
1445 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1446 inst
->saturate
= instr
->dest
.saturate
;
1450 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1451 inst
->saturate
= instr
->dest
.saturate
;
1455 enum brw_predicate predicate
;
1456 if (!optimize_predicate(instr
, &predicate
)) {
1457 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1458 switch (dst
.writemask
) {
1460 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1463 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1466 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1469 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1472 predicate
= BRW_PREDICATE_NORMAL
;
1476 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1477 inst
->predicate
= predicate
;
1480 case nir_op_fdot_replicated2
:
1481 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1482 inst
->saturate
= instr
->dest
.saturate
;
1485 case nir_op_fdot_replicated3
:
1486 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1487 inst
->saturate
= instr
->dest
.saturate
;
1490 case nir_op_fdot_replicated4
:
1491 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1492 inst
->saturate
= instr
->dest
.saturate
;
1495 case nir_op_fdph_replicated
:
1496 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1497 inst
->saturate
= instr
->dest
.saturate
;
1505 unreachable("not reached: should be lowered by lower_source mods");
1508 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1511 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1515 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1518 unreachable("Unimplemented ALU operation");
1521 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1522 * to sign extend the low bit to 0/~0
1524 if (devinfo
->gen
<= 5 &&
1525 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1526 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1527 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1528 masked
.writemask
= dst
.writemask
;
1529 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1530 src_reg masked_neg
= src_reg(masked
);
1531 masked_neg
.negate
= true;
1532 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1537 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1539 switch (instr
->type
) {
1540 case nir_jump_break
:
1541 emit(BRW_OPCODE_BREAK
);
1544 case nir_jump_continue
:
1545 emit(BRW_OPCODE_CONTINUE
);
1548 case nir_jump_return
:
1550 unreachable("unknown jump");
1554 enum ir_texture_opcode
1555 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1557 enum ir_texture_opcode op
;
1560 case nir_texop_lod
: op
= ir_lod
; break;
1561 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1562 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1563 case nir_texop_tex
: op
= ir_tex
; break;
1564 case nir_texop_tg4
: op
= ir_tg4
; break;
1565 case nir_texop_txb
: op
= ir_txb
; break;
1566 case nir_texop_txd
: op
= ir_txd
; break;
1567 case nir_texop_txf
: op
= ir_txf
; break;
1568 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1569 case nir_texop_txl
: op
= ir_txl
; break;
1570 case nir_texop_txs
: op
= ir_txs
; break;
1571 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
1573 unreachable("unknown texture opcode");
1579 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1580 unsigned components
)
1583 case nir_type_float
:
1584 return glsl_type::vec(components
);
1586 return glsl_type::ivec(components
);
1588 return glsl_type::uvec(components
);
1590 return glsl_type::bvec(components
);
1592 return glsl_type::error_type
;
1595 return glsl_type::error_type
;
1599 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1601 unsigned texture
= instr
->texture_index
;
1602 unsigned sampler
= instr
->sampler_index
;
1603 src_reg texture_reg
= brw_imm_ud(texture
);
1604 src_reg sampler_reg
= brw_imm_ud(sampler
);
1606 const glsl_type
*coord_type
= NULL
;
1607 src_reg shadow_comparitor
;
1608 src_reg offset_value
;
1610 src_reg sample_index
;
1613 const glsl_type
*dest_type
=
1614 glsl_type_for_nir_alu_type(instr
->dest_type
,
1615 nir_tex_instr_dest_size(instr
));
1616 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1618 /* Our hardware requires a LOD for buffer textures */
1619 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
1622 /* Load the texture operation sources */
1623 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1624 switch (instr
->src
[i
].src_type
) {
1625 case nir_tex_src_comparitor
:
1626 shadow_comparitor
= get_nir_src(instr
->src
[i
].src
,
1627 BRW_REGISTER_TYPE_F
, 1);
1630 case nir_tex_src_coord
: {
1631 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1633 switch (instr
->op
) {
1635 case nir_texop_txf_ms
:
1636 case nir_texop_samples_identical
:
1637 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1639 coord_type
= glsl_type::ivec(src_size
);
1643 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1645 coord_type
= glsl_type::vec(src_size
);
1651 case nir_tex_src_ddx
:
1652 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1653 nir_tex_instr_src_size(instr
, i
));
1656 case nir_tex_src_ddy
:
1657 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1658 nir_tex_instr_src_size(instr
, i
));
1661 case nir_tex_src_lod
:
1662 switch (instr
->op
) {
1665 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1669 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1674 case nir_tex_src_ms_index
: {
1675 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1679 case nir_tex_src_offset
:
1680 offset_value
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1683 case nir_tex_src_texture_offset
: {
1684 /* The highest texture which may be used by this operation is
1685 * the last element of the array. Mark it here, because the generator
1686 * doesn't have enough information to determine the bound.
1688 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
1689 if (instr
->op
== nir_texop_tg4
) {
1690 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1692 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1695 brw_mark_surface_used(&prog_data
->base
, max_used
);
1697 /* Emit code to evaluate the actual indexing expression */
1698 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1699 src_reg
temp(this, glsl_type::uint_type
);
1700 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
1701 texture_reg
= emit_uniformize(temp
);
1705 case nir_tex_src_sampler_offset
: {
1706 /* Emit code to evaluate the actual indexing expression */
1707 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1708 src_reg
temp(this, glsl_type::uint_type
);
1709 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
1710 sampler_reg
= emit_uniformize(temp
);
1714 case nir_tex_src_projector
:
1715 unreachable("Should be lowered by do_lower_texture_projection");
1717 case nir_tex_src_bias
:
1718 unreachable("LOD bias is not valid for vertex shaders.\n");
1721 unreachable("unknown texture source");
1725 if (instr
->op
== nir_texop_txf_ms
||
1726 instr
->op
== nir_texop_samples_identical
) {
1727 assert(coord_type
!= NULL
);
1728 if (devinfo
->gen
>= 7 &&
1729 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1730 mcs
= emit_mcs_fetch(coord_type
, coordinate
, sampler_reg
);
1732 mcs
= brw_imm_ud(0u);
1736 uint32_t constant_offset
= 0;
1737 for (unsigned i
= 0; i
< 3; i
++) {
1738 if (instr
->const_offset
[i
] != 0) {
1739 constant_offset
= brw_texture_offset(instr
->const_offset
, 3);
1744 /* Stuff the channel select bits in the top of the texture offset */
1745 if (instr
->op
== nir_texop_tg4
) {
1746 if (instr
->component
== 1 &&
1747 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
1748 /* gather4 sampler is broken for green channel on RG32F --
1749 * we must ask for blue instead.
1751 constant_offset
|= 2 << 16;
1753 constant_offset
|= instr
->component
<< 16;
1757 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1759 bool is_cube_array
=
1760 instr
->op
== nir_texop_txs
&&
1761 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1764 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1766 lod
, lod2
, sample_index
,
1767 constant_offset
, offset_value
,
1769 texture
, texture_reg
, sampler
, sampler_reg
);
1773 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1775 nir_ssa_values
[instr
->def
.index
] = dst_reg(VGRF
, alloc
.allocate(1));