2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_setup_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
56 switch (instr
->intrinsic
) {
57 case nir_intrinsic_load_vertex_id
:
58 unreachable("should be lowered by lower_vertex_id().");
60 case nir_intrinsic_load_vertex_id_zero_base
:
61 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
62 if (reg
->file
== BAD_FILE
)
63 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
66 case nir_intrinsic_load_base_vertex
:
67 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
68 if (reg
->file
== BAD_FILE
)
69 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
);
72 case nir_intrinsic_load_instance_id
:
73 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
74 if (reg
->file
== BAD_FILE
)
75 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
);
78 case nir_intrinsic_load_base_instance
:
79 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
80 if (reg
->file
== BAD_FILE
)
81 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
84 case nir_intrinsic_load_draw_id
:
85 reg
= &nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
86 if (reg
->file
== BAD_FILE
)
87 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_DRAW_ID
);
96 setup_system_values_block(nir_block
*block
, vec4_visitor
*v
)
98 nir_foreach_instr(instr
, block
) {
99 if (instr
->type
!= nir_instr_type_intrinsic
)
102 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
103 v
->nir_setup_system_value_intrinsic(intrin
);
110 vec4_visitor::nir_setup_system_values()
112 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
113 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
114 nir_system_values
[i
] = dst_reg();
117 nir_foreach_function(function
, nir
) {
118 assert(strcmp(function
->name
, "main") == 0);
119 assert(function
->impl
);
120 nir_foreach_block(block
, function
->impl
) {
121 setup_system_values_block(block
, this);
127 vec4_visitor::nir_setup_uniforms()
129 uniforms
= nir
->num_uniforms
/ 16;
133 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
135 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
136 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
137 nir_locals
[i
] = dst_reg();
140 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
141 unsigned array_elems
=
142 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
143 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
144 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
147 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
149 nir_emit_cf_list(&impl
->body
);
153 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
155 exec_list_validate(list
);
156 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
157 switch (node
->type
) {
159 nir_emit_if(nir_cf_node_as_if(node
));
162 case nir_cf_node_loop
:
163 nir_emit_loop(nir_cf_node_as_loop(node
));
166 case nir_cf_node_block
:
167 nir_emit_block(nir_cf_node_as_block(node
));
171 unreachable("Invalid CFG node block");
177 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
179 /* First, put the condition in f0 */
180 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
181 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
182 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
184 /* We can just predicate based on the X channel, as the condition only
185 * goes on its own line */
186 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
188 nir_emit_cf_list(&if_stmt
->then_list
);
190 /* note: if the else is empty, dead CF elimination will remove it */
191 emit(BRW_OPCODE_ELSE
);
193 nir_emit_cf_list(&if_stmt
->else_list
);
195 emit(BRW_OPCODE_ENDIF
);
199 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
203 nir_emit_cf_list(&loop
->body
);
205 emit(BRW_OPCODE_WHILE
);
209 vec4_visitor::nir_emit_block(nir_block
*block
)
211 nir_foreach_instr(instr
, block
) {
212 nir_emit_instr(instr
);
217 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
221 switch (instr
->type
) {
222 case nir_instr_type_load_const
:
223 nir_emit_load_const(nir_instr_as_load_const(instr
));
226 case nir_instr_type_intrinsic
:
227 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
230 case nir_instr_type_alu
:
231 nir_emit_alu(nir_instr_as_alu(instr
));
234 case nir_instr_type_jump
:
235 nir_emit_jump(nir_instr_as_jump(instr
));
238 case nir_instr_type_tex
:
239 nir_emit_texture(nir_instr_as_tex(instr
));
242 case nir_instr_type_ssa_undef
:
243 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
247 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
253 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
254 unsigned base_offset
, nir_src
*indirect
)
258 reg
= v
->nir_locals
[nir_reg
->index
];
259 reg
= offset(reg
, 8, base_offset
);
262 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
270 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
274 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
275 nir_ssa_values
[dest
.ssa
.index
] = dst
;
278 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
284 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
286 return retype(get_nir_dest(dest
), type
);
290 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
292 return get_nir_dest(dest
, brw_type_for_nir_type(type
));
296 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
297 unsigned num_components
)
302 assert(src
.ssa
!= NULL
);
303 reg
= nir_ssa_values
[src
.ssa
->index
];
306 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
310 reg
= retype(reg
, type
);
312 src_reg reg_as_src
= src_reg(reg
);
313 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
318 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
319 unsigned num_components
)
321 return get_nir_src(src
, brw_type_for_nir_type(type
), num_components
);
325 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
327 /* if type is not specified, default to signed int */
328 return get_nir_src(src
, nir_type_int32
, num_components
);
332 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
334 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
335 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
338 /* The only constant offset we should find is 0. brw_nir.c's
339 * add_const_offset_to_base() will fold other constant offsets
340 * into instr->const_index[0].
342 assert(const_value
->u32
[0] == 0);
346 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
350 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
352 dst_reg reg
= dst_reg(VGRF
, alloc
.allocate(1));
353 reg
.type
= BRW_REGISTER_TYPE_D
;
355 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
357 /* @FIXME: consider emitting vector operations to save some MOVs in
358 * cases where the components are representable in 8 bits.
359 * For now, we emit a MOV for each distinct value.
361 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
362 unsigned writemask
= 1 << i
;
364 if ((remaining
& writemask
) == 0)
367 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
368 if (instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) {
373 reg
.writemask
= writemask
;
374 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
376 remaining
&= ~writemask
;
379 /* Set final writemask */
380 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
382 nir_ssa_values
[instr
->def
.index
] = reg
;
386 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
391 switch (instr
->intrinsic
) {
393 case nir_intrinsic_load_input
: {
394 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
396 /* We set EmitNoIndirectInput for VS */
397 assert(const_offset
);
399 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
400 glsl_type::uvec4_type
);
401 /* Swizzle source based on component layout qualifier */
402 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
404 dest
= get_nir_dest(instr
->dest
, src
.type
);
405 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
407 emit(MOV(dest
, src
));
411 case nir_intrinsic_store_output
: {
412 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
413 assert(const_offset
);
415 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
417 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
418 instr
->num_components
);
420 unsigned c
= nir_intrinsic_component(instr
);
421 output_reg
[varying
][c
] = dst_reg(src
);
422 output_num_components
[varying
][c
] = instr
->num_components
;
426 case nir_intrinsic_get_buffer_size
: {
427 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
428 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
430 const unsigned index
=
431 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
432 dst_reg result_dst
= get_nir_dest(instr
->dest
);
433 vec4_instruction
*inst
= new(mem_ctx
)
434 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
437 inst
->mlen
= 1; /* always at least one */
438 inst
->src
[1] = brw_imm_ud(index
);
440 /* MRF for the first parameter */
441 src_reg lod
= brw_imm_d(0);
442 int param_base
= inst
->base_mrf
;
443 int writemask
= WRITEMASK_X
;
444 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
448 brw_mark_surface_used(&prog_data
->base
, index
);
452 case nir_intrinsic_store_ssbo
: {
453 assert(devinfo
->gen
>= 7);
457 nir_const_value
*const_uniform_block
=
458 nir_src_as_const_value(instr
->src
[1]);
459 if (const_uniform_block
) {
460 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
461 const_uniform_block
->u32
[0];
462 surf_index
= brw_imm_ud(index
);
463 brw_mark_surface_used(&prog_data
->base
, index
);
465 surf_index
= src_reg(this, glsl_type::uint_type
);
466 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
467 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
468 surf_index
= emit_uniformize(surf_index
);
470 brw_mark_surface_used(&prog_data
->base
,
471 prog_data
->base
.binding_table
.ssbo_start
+
472 nir
->info
->num_ssbos
- 1);
477 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
479 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
481 offset_reg
= get_nir_src(instr
->src
[2], 1);
485 src_reg val_reg
= get_nir_src(instr
->src
[0], 4);
488 unsigned write_mask
= instr
->const_index
[0];
490 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
491 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
492 * typed and untyped messages and across hardware platforms, the
493 * current implementation of the untyped messages will transparently convert
494 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
495 * and enabling only channel X on the SEND instruction.
497 * The above, works well for full vector writes, but not for partial writes
498 * where we want to write some channels and not others, like when we have
499 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
500 * quite restrictive with regards to the channel enables we can configure in
501 * the message descriptor (not all combinations are allowed) we cannot simply
502 * implement these scenarios with a single message while keeping the
503 * aforementioned symmetry in the implementation. For now we de decided that
504 * it is better to keep the symmetry to reduce complexity, so in situations
505 * such as the one described we end up emitting two untyped write messages
506 * (one for xy and another for w).
508 * The code below packs consecutive channels into a single write message,
509 * detects gaps in the vector write and if needed, sends a second message
510 * with the remaining channels. If in the future we decide that we want to
511 * emit a single message at the expense of losing the symmetry in the
512 * implementation we can:
514 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
515 * message payload. In this mode we can write up to 8 offsets and dwords
516 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
517 * and select which of the 8 channels carry data to write by setting the
518 * appropriate writemask in the dst register of the SEND instruction.
519 * It would require to write a new generator opcode specifically for
520 * IvyBridge since we would need to prepare a SIMD8 payload that could
521 * use any channel, not just X.
523 * 2) For Haswell+: Simply send a single write message but set the writemask
524 * on the dst of the SEND instruction to select the channels we want to
525 * write. It would require to modify the current messages to receive
526 * and honor the writemask provided.
528 const vec4_builder bld
= vec4_builder(this).at_end()
529 .annotate(current_annotation
, base_ir
);
531 int swizzle
[4] = { 0, 0, 0, 0};
532 int num_channels
= 0;
533 unsigned skipped_channels
= 0;
534 int num_components
= instr
->num_components
;
535 for (int i
= 0; i
< num_components
; i
++) {
536 /* Check if this channel needs to be written. If so, record the
537 * channel we need to take the data from in the swizzle array
539 int component_mask
= 1 << i
;
540 int write_test
= write_mask
& component_mask
;
542 swizzle
[num_channels
++] = i
;
544 /* If we don't have to write this channel it means we have a gap in the
545 * vector, so write the channels we accumulated until now, if any. Do
546 * the same if this was the last component in the vector.
548 if (!write_test
|| i
== num_components
- 1) {
549 if (num_channels
> 0) {
550 /* We have channels to write, so update the offset we need to
551 * write at to skip the channels we skipped, if any.
553 if (skipped_channels
> 0) {
554 if (offset_reg
.file
== IMM
) {
555 offset_reg
.ud
+= 4 * skipped_channels
;
557 emit(ADD(dst_reg(offset_reg
), offset_reg
,
558 brw_imm_ud(4 * skipped_channels
)));
562 /* Swizzle the data register so we take the data from the channels
563 * we need to write and send the write message. This will write
564 * num_channels consecutive dwords starting at offset.
567 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
568 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
569 1 /* dims */, num_channels
/* size */,
572 /* If we have to do a second write we will have to update the
573 * offset so that we jump over the channels we have just written
576 skipped_channels
= num_channels
;
578 /* Restart the count for the next write message */
582 /* We did not write the current channel, so increase skipped count */
590 case nir_intrinsic_load_ssbo
: {
591 assert(devinfo
->gen
>= 7);
593 nir_const_value
*const_uniform_block
=
594 nir_src_as_const_value(instr
->src
[0]);
597 if (const_uniform_block
) {
598 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
599 const_uniform_block
->u32
[0];
600 surf_index
= brw_imm_ud(index
);
602 brw_mark_surface_used(&prog_data
->base
, index
);
604 surf_index
= src_reg(this, glsl_type::uint_type
);
605 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
606 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
607 surf_index
= emit_uniformize(surf_index
);
609 /* Assume this may touch any UBO. It would be nice to provide
610 * a tighter bound, but the array information is already lowered away.
612 brw_mark_surface_used(&prog_data
->base
,
613 prog_data
->base
.binding_table
.ssbo_start
+
614 nir
->info
->num_ssbos
- 1);
618 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
620 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
622 offset_reg
= get_nir_src(instr
->src
[1], 1);
625 /* Read the vector */
626 const vec4_builder bld
= vec4_builder(this).at_end()
627 .annotate(current_annotation
, base_ir
);
629 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
630 1 /* dims */, 4 /* size*/,
632 dst_reg dest
= get_nir_dest(instr
->dest
);
633 read_result
.type
= dest
.type
;
634 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
635 emit(MOV(dest
, read_result
));
640 case nir_intrinsic_ssbo_atomic_add
:
641 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
643 case nir_intrinsic_ssbo_atomic_imin
:
644 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
646 case nir_intrinsic_ssbo_atomic_umin
:
647 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
649 case nir_intrinsic_ssbo_atomic_imax
:
650 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
652 case nir_intrinsic_ssbo_atomic_umax
:
653 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
655 case nir_intrinsic_ssbo_atomic_and
:
656 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
658 case nir_intrinsic_ssbo_atomic_or
:
659 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
661 case nir_intrinsic_ssbo_atomic_xor
:
662 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
664 case nir_intrinsic_ssbo_atomic_exchange
:
665 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
667 case nir_intrinsic_ssbo_atomic_comp_swap
:
668 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
671 case nir_intrinsic_load_vertex_id
:
672 unreachable("should be lowered by lower_vertex_id()");
674 case nir_intrinsic_load_vertex_id_zero_base
:
675 case nir_intrinsic_load_base_vertex
:
676 case nir_intrinsic_load_instance_id
:
677 case nir_intrinsic_load_base_instance
:
678 case nir_intrinsic_load_draw_id
:
679 case nir_intrinsic_load_invocation_id
: {
680 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
681 src_reg val
= src_reg(nir_system_values
[sv
]);
682 assert(val
.file
!= BAD_FILE
);
683 dest
= get_nir_dest(instr
->dest
, val
.type
);
684 emit(MOV(dest
, val
));
688 case nir_intrinsic_load_uniform
: {
689 /* Offsets are in bytes but they should always be multiples of 4 */
690 assert(nir_intrinsic_base(instr
) % 4 == 0);
692 dest
= get_nir_dest(instr
->dest
);
694 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
695 src
.type
= dest
.type
;
697 /* Uniforms don't actually have to be vec4 aligned. In the case that
698 * it isn't, we have to use a swizzle to shift things around. They
699 * do still have the std140 alignment requirement that vec2's have to
700 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
702 * The swizzle also works in the indirect case as the generator adds
703 * the swizzle to the offset for us.
705 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / 4;
706 assert(shift
+ instr
->num_components
<= 4);
708 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
710 /* Offsets are in bytes but they should always be multiples of 4 */
711 assert(const_offset
->u32
[0] % 4 == 0);
713 unsigned offset
= const_offset
->u32
[0] + shift
* 4;
714 src
.offset
= ROUND_DOWN_TO(offset
, 16);
715 shift
= (offset
% 16) / 4;
716 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
718 emit(MOV(dest
, src
));
720 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
722 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
724 /* MOV_INDIRECT is going to stomp the whole thing anyway */
725 dest
.writemask
= WRITEMASK_XYZW
;
727 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
728 indirect
, brw_imm_ud(instr
->const_index
[1]));
733 case nir_intrinsic_atomic_counter_read
:
734 case nir_intrinsic_atomic_counter_inc
:
735 case nir_intrinsic_atomic_counter_dec
: {
736 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
737 (unsigned) instr
->const_index
[0];
738 const vec4_builder bld
=
739 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
741 /* Get some metadata from the image intrinsic. */
742 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
744 /* Get the arguments of the atomic intrinsic. */
745 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int32
,
746 instr
->num_components
);
747 const src_reg surface
= brw_imm_ud(surf_index
);
748 const src_reg src0
= (info
->num_srcs
>= 2
749 ? get_nir_src(instr
->src
[1]) : src_reg());
750 const src_reg src1
= (info
->num_srcs
>= 3
751 ? get_nir_src(instr
->src
[2]) : src_reg());
755 dest
= get_nir_dest(instr
->dest
);
757 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
758 tmp
= emit_untyped_read(bld
, surface
, offset
, 1, 1);
760 tmp
= emit_untyped_atomic(bld
, surface
, offset
,
763 get_atomic_counter_op(instr
->intrinsic
));
766 bld
.MOV(retype(dest
, tmp
.type
), tmp
);
767 brw_mark_surface_used(stage_prog_data
, surf_index
);
771 case nir_intrinsic_load_ubo
: {
772 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
775 dest
= get_nir_dest(instr
->dest
);
777 if (const_block_index
) {
778 /* The block index is a constant, so just emit the binding table entry
781 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
782 const_block_index
->u32
[0];
783 surf_index
= brw_imm_ud(index
);
784 brw_mark_surface_used(&prog_data
->base
, index
);
786 /* The block index is not a constant. Evaluate the index expression
787 * per-channel and add the base UBO index; we have to select a value
788 * from any live channel.
790 surf_index
= src_reg(this, glsl_type::uint_type
);
791 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
792 instr
->num_components
),
793 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
794 surf_index
= emit_uniformize(surf_index
);
796 /* Assume this may touch any UBO. It would be nice to provide
797 * a tighter bound, but the array information is already lowered away.
799 brw_mark_surface_used(&prog_data
->base
,
800 prog_data
->base
.binding_table
.ubo_start
+
801 nir
->info
->num_ubos
- 1);
805 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
807 offset
= brw_imm_ud(const_offset
->u32
[0] & ~15);
809 offset
= get_nir_src(instr
->src
[1], nir_type_uint32
, 1);
812 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
813 packed_consts
.type
= dest
.type
;
815 emit_pull_constant_load_reg(dst_reg(packed_consts
),
818 NULL
, NULL
/* before_block/inst */);
820 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
822 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / 4,
823 const_offset
->u32
[0] % 16 / 4,
824 const_offset
->u32
[0] % 16 / 4,
825 const_offset
->u32
[0] % 16 / 4);
828 emit(MOV(dest
, packed_consts
));
832 case nir_intrinsic_memory_barrier
: {
833 const vec4_builder bld
=
834 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
835 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
836 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
837 ->size_written
= 2 * REG_SIZE
;
841 case nir_intrinsic_shader_clock
: {
842 /* We cannot do anything if there is an event, so ignore it for now */
843 const src_reg shader_clock
= get_timestamp();
844 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
846 dest
= get_nir_dest(instr
->dest
, type
);
847 emit(MOV(dest
, shader_clock
));
852 unreachable("Unknown intrinsic");
857 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
860 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
861 dest
= get_nir_dest(instr
->dest
);
864 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
866 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
867 const_surface
->u32
[0];
868 surface
= brw_imm_ud(surf_index
);
869 brw_mark_surface_used(&prog_data
->base
, surf_index
);
871 surface
= src_reg(this, glsl_type::uint_type
);
872 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
873 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
875 /* Assume this may touch any UBO. This is the same we do for other
876 * UBO/SSBO accesses with non-constant surface.
878 brw_mark_surface_used(&prog_data
->base
,
879 prog_data
->base
.binding_table
.ssbo_start
+
880 nir
->info
->num_ssbos
- 1);
883 src_reg offset
= get_nir_src(instr
->src
[1], 1);
884 src_reg data1
= get_nir_src(instr
->src
[2], 1);
886 if (op
== BRW_AOP_CMPWR
)
887 data2
= get_nir_src(instr
->src
[3], 1);
889 /* Emit the actual atomic operation operation */
890 const vec4_builder bld
=
891 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
893 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
895 1 /* dims */, 1 /* rsize */,
898 dest
.type
= atomic_result
.type
;
899 bld
.MOV(dest
, atomic_result
);
903 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
905 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
908 static enum brw_conditional_mod
909 brw_conditional_for_nir_comparison(nir_op op
)
915 return BRW_CONDITIONAL_L
;
920 return BRW_CONDITIONAL_GE
;
924 case nir_op_ball_fequal2
:
925 case nir_op_ball_iequal2
:
926 case nir_op_ball_fequal3
:
927 case nir_op_ball_iequal3
:
928 case nir_op_ball_fequal4
:
929 case nir_op_ball_iequal4
:
930 return BRW_CONDITIONAL_Z
;
934 case nir_op_bany_fnequal2
:
935 case nir_op_bany_inequal2
:
936 case nir_op_bany_fnequal3
:
937 case nir_op_bany_inequal3
:
938 case nir_op_bany_fnequal4
:
939 case nir_op_bany_inequal4
:
940 return BRW_CONDITIONAL_NZ
;
943 unreachable("not reached: bad operation for comparison");
948 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
949 enum brw_predicate
*predicate
)
951 if (!instr
->src
[0].src
.is_ssa
||
952 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
955 nir_alu_instr
*cmp_instr
=
956 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
958 switch (cmp_instr
->op
) {
959 case nir_op_bany_fnequal2
:
960 case nir_op_bany_inequal2
:
961 case nir_op_bany_fnequal3
:
962 case nir_op_bany_inequal3
:
963 case nir_op_bany_fnequal4
:
964 case nir_op_bany_inequal4
:
965 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
967 case nir_op_ball_fequal2
:
968 case nir_op_ball_iequal2
:
969 case nir_op_ball_fequal3
:
970 case nir_op_ball_iequal3
:
971 case nir_op_ball_fequal4
:
972 case nir_op_ball_iequal4
:
973 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
979 unsigned size_swizzle
=
980 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
983 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
984 for (unsigned i
= 0; i
< 2; i
++) {
985 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
,
986 nir_op_infos
[cmp_instr
->op
].input_types
[i
], 4);
987 unsigned base_swizzle
=
988 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
989 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
990 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
991 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
994 emit(CMP(dst_null_d(), op
[0], op
[1],
995 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1001 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1006 vec4_instruction
*inst
;
1010 /* LZD of an absolute value source almost always does the right
1011 * thing. There are two problem values:
1013 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1014 * 0. However, findMSB(int(0x80000000)) == 30.
1016 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1017 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1019 * For a value of zero or negative one, -1 will be returned.
1021 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1022 * findMSB(-(1<<x)) should return x-1.
1024 * For all negative number cases, including 0x80000000 and
1025 * 0xffffffff, the correct value is obtained from LZD if instead of
1026 * negating the (already negative) value the logical-not is used. A
1027 * conditonal logical-not can be achieved in two instructions.
1029 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1031 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1032 bld
.XOR(dst_reg(temp
), temp
, src
);
1035 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1036 retype(temp
, BRW_REGISTER_TYPE_UD
));
1038 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1039 * from the LSB side. Subtract the result from 31 to convert the MSB count
1040 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1041 * which is exactly what findMSB() is supposed to return.
1043 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1045 inst
->src
[0].negate
= true;
1049 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1051 vec4_instruction
*inst
;
1053 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1054 nir_dest_bit_size(instr
->dest
.dest
));
1055 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1056 dst
.writemask
= instr
->dest
.write_mask
;
1059 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1060 nir_alu_type src_type
= (nir_alu_type
)
1061 (nir_op_infos
[instr
->op
].input_types
[i
] |
1062 nir_src_bit_size(instr
->src
[i
].src
));
1063 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1064 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1065 op
[i
].abs
= instr
->src
[i
].abs
;
1066 op
[i
].negate
= instr
->src
[i
].negate
;
1069 switch (instr
->op
) {
1072 inst
= emit(MOV(dst
, op
[0]));
1073 inst
->saturate
= instr
->dest
.saturate
;
1079 unreachable("not reached: should be handled by lower_vec_to_movs()");
1083 inst
= emit(MOV(dst
, op
[0]));
1084 inst
->saturate
= instr
->dest
.saturate
;
1089 inst
= emit(MOV(dst
, op
[0]));
1095 inst
= emit(ADD(dst
, op
[0], op
[1]));
1096 inst
->saturate
= instr
->dest
.saturate
;
1100 inst
= emit(MUL(dst
, op
[0], op
[1]));
1101 inst
->saturate
= instr
->dest
.saturate
;
1105 if (devinfo
->gen
< 8) {
1106 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1107 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1109 /* For integer multiplication, the MUL uses the low 16 bits of one of
1110 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1111 * accumulates in the contribution of the upper 16 bits of that
1112 * operand. If we can determine that one of the args is in the low
1113 * 16 bits, though, we can just emit a single MUL.
1115 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1116 if (devinfo
->gen
< 7)
1117 emit(MUL(dst
, op
[0], op
[1]));
1119 emit(MUL(dst
, op
[1], op
[0]));
1120 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1121 if (devinfo
->gen
< 7)
1122 emit(MUL(dst
, op
[1], op
[0]));
1124 emit(MUL(dst
, op
[0], op
[1]));
1126 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1128 emit(MUL(acc
, op
[0], op
[1]));
1129 emit(MACH(dst_null_d(), op
[0], op
[1]));
1130 emit(MOV(dst
, src_reg(acc
)));
1133 emit(MUL(dst
, op
[0], op
[1]));
1138 case nir_op_imul_high
:
1139 case nir_op_umul_high
: {
1140 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1142 if (devinfo
->gen
>= 8)
1143 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1145 emit(MUL(acc
, op
[0], op
[1]));
1147 emit(MACH(dst
, op
[0], op
[1]));
1152 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1162 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1163 inst
->saturate
= instr
->dest
.saturate
;
1167 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1168 inst
->saturate
= instr
->dest
.saturate
;
1172 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1173 inst
->saturate
= instr
->dest
.saturate
;
1178 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1183 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1184 * appears that our hardware just does the right thing for signed
1187 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1191 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1192 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1194 /* Math instructions don't support conditional mod */
1195 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1196 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1198 /* Now, we need to determine if signs of the sources are different.
1199 * When we XOR the sources, the top bit is 0 if they are the same and 1
1200 * if they are different. We can then use a conditional modifier to
1201 * turn that into a predicate. This leads us to an XOR.l instruction.
1203 * Technically, according to the PRM, you're not allowed to use .l on a
1204 * XOR instruction. However, emperical experiments and Curro's reading
1205 * of the simulator source both indicate that it's safe.
1207 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1208 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1209 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1210 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1212 /* If the result of the initial remainder operation is non-zero and the
1213 * two sources have different signs, add in a copy of op[1] to get the
1214 * final integer modulus value.
1216 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1217 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1222 unreachable("not reached: should be handled by ldexp_to_arith()");
1225 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1226 inst
->saturate
= instr
->dest
.saturate
;
1230 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1231 inst
->saturate
= instr
->dest
.saturate
;
1235 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1236 inst
->saturate
= instr
->dest
.saturate
;
1239 case nir_op_uadd_carry
: {
1240 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1242 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1243 emit(MOV(dst
, src_reg(acc
)));
1247 case nir_op_usub_borrow
: {
1248 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1250 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1251 emit(MOV(dst
, src_reg(acc
)));
1256 inst
= emit(RNDZ(dst
, op
[0]));
1257 inst
->saturate
= instr
->dest
.saturate
;
1260 case nir_op_fceil
: {
1261 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1263 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1264 instr
->src
[0].src
.ssa
->num_components
:
1265 instr
->src
[0].src
.reg
.reg
->num_components
);
1267 op
[0].negate
= !op
[0].negate
;
1268 emit(RNDD(dst_reg(tmp
), op
[0]));
1270 inst
= emit(MOV(dst
, tmp
));
1271 inst
->saturate
= instr
->dest
.saturate
;
1276 inst
= emit(RNDD(dst
, op
[0]));
1277 inst
->saturate
= instr
->dest
.saturate
;
1281 inst
= emit(FRC(dst
, op
[0]));
1282 inst
->saturate
= instr
->dest
.saturate
;
1285 case nir_op_fround_even
:
1286 inst
= emit(RNDE(dst
, op
[0]));
1287 inst
->saturate
= instr
->dest
.saturate
;
1290 case nir_op_fquantize2f16
: {
1291 /* See also vec4_visitor::emit_pack_half_2x16() */
1292 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1293 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1294 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1296 /* Check for denormal */
1297 src_reg abs_src0
= op
[0];
1298 abs_src0
.abs
= true;
1299 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1300 BRW_CONDITIONAL_L
));
1301 /* Get the appropriately signed zero */
1302 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1303 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1304 brw_imm_ud(0x80000000)));
1305 /* Do the actual F32 -> F16 -> F32 conversion */
1306 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1307 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1308 /* Select that or zero based on normal status */
1309 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1310 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1311 inst
->saturate
= instr
->dest
.saturate
;
1318 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1319 inst
->saturate
= instr
->dest
.saturate
;
1325 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1326 inst
->saturate
= instr
->dest
.saturate
;
1330 case nir_op_fddx_coarse
:
1331 case nir_op_fddx_fine
:
1333 case nir_op_fddy_coarse
:
1334 case nir_op_fddy_fine
:
1335 unreachable("derivatives are not valid in vertex shaders");
1347 emit(CMP(dst
, op
[0], op
[1],
1348 brw_conditional_for_nir_comparison(instr
->op
)));
1351 case nir_op_ball_fequal2
:
1352 case nir_op_ball_iequal2
:
1353 case nir_op_ball_fequal3
:
1354 case nir_op_ball_iequal3
:
1355 case nir_op_ball_fequal4
:
1356 case nir_op_ball_iequal4
: {
1358 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1360 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1361 brw_conditional_for_nir_comparison(instr
->op
)));
1362 emit(MOV(dst
, brw_imm_d(0)));
1363 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1364 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1368 case nir_op_bany_fnequal2
:
1369 case nir_op_bany_inequal2
:
1370 case nir_op_bany_fnequal3
:
1371 case nir_op_bany_inequal3
:
1372 case nir_op_bany_fnequal4
:
1373 case nir_op_bany_inequal4
: {
1375 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1377 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1378 brw_conditional_for_nir_comparison(instr
->op
)));
1380 emit(MOV(dst
, brw_imm_d(0)));
1381 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1382 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1387 if (devinfo
->gen
>= 8) {
1388 op
[0] = resolve_source_modifiers(op
[0]);
1390 emit(NOT(dst
, op
[0]));
1394 if (devinfo
->gen
>= 8) {
1395 op
[0] = resolve_source_modifiers(op
[0]);
1396 op
[1] = resolve_source_modifiers(op
[1]);
1398 emit(XOR(dst
, op
[0], op
[1]));
1402 if (devinfo
->gen
>= 8) {
1403 op
[0] = resolve_source_modifiers(op
[0]);
1404 op
[1] = resolve_source_modifiers(op
[1]);
1406 emit(OR(dst
, op
[0], op
[1]));
1410 if (devinfo
->gen
>= 8) {
1411 op
[0] = resolve_source_modifiers(op
[0]);
1412 op
[1] = resolve_source_modifiers(op
[1]);
1414 emit(AND(dst
, op
[0], op
[1]));
1419 emit(MOV(dst
, negate(op
[0])));
1423 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1427 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1430 case nir_op_fnoise1_1
:
1431 case nir_op_fnoise1_2
:
1432 case nir_op_fnoise1_3
:
1433 case nir_op_fnoise1_4
:
1434 case nir_op_fnoise2_1
:
1435 case nir_op_fnoise2_2
:
1436 case nir_op_fnoise2_3
:
1437 case nir_op_fnoise2_4
:
1438 case nir_op_fnoise3_1
:
1439 case nir_op_fnoise3_2
:
1440 case nir_op_fnoise3_3
:
1441 case nir_op_fnoise3_4
:
1442 case nir_op_fnoise4_1
:
1443 case nir_op_fnoise4_2
:
1444 case nir_op_fnoise4_3
:
1445 case nir_op_fnoise4_4
:
1446 unreachable("not reached: should be handled by lower_noise");
1448 case nir_op_unpack_half_2x16_split_x
:
1449 case nir_op_unpack_half_2x16_split_y
:
1450 case nir_op_pack_half_2x16_split
:
1451 unreachable("not reached: should not occur in vertex shader");
1453 case nir_op_unpack_snorm_2x16
:
1454 case nir_op_unpack_unorm_2x16
:
1455 case nir_op_pack_snorm_2x16
:
1456 case nir_op_pack_unorm_2x16
:
1457 unreachable("not reached: should be handled by lower_packing_builtins");
1459 case nir_op_pack_uvec4_to_uint
:
1460 unreachable("not reached");
1462 case nir_op_pack_uvec2_to_uint
: {
1463 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1464 tmp1
.writemask
= WRITEMASK_X
;
1465 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1466 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1468 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1469 tmp2
.writemask
= WRITEMASK_X
;
1470 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1471 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1473 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1477 case nir_op_unpack_half_2x16
:
1478 /* As NIR does not guarantee that we have a correct swizzle outside the
1479 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1480 * uses the source operand in an operation with WRITEMASK_Y while our
1481 * source operand has only size 1, it accessed incorrect data producing
1482 * regressions in Piglit. We repeat the swizzle of the first component on the
1483 * rest of components to avoid regressions. In the vec4_visitor IR code path
1484 * this is not needed because the operand has already the correct swizzle.
1486 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1487 emit_unpack_half_2x16(dst
, op
[0]);
1490 case nir_op_pack_half_2x16
:
1491 emit_pack_half_2x16(dst
, op
[0]);
1494 case nir_op_unpack_unorm_4x8
:
1495 emit_unpack_unorm_4x8(dst
, op
[0]);
1498 case nir_op_pack_unorm_4x8
:
1499 emit_pack_unorm_4x8(dst
, op
[0]);
1502 case nir_op_unpack_snorm_4x8
:
1503 emit_unpack_snorm_4x8(dst
, op
[0]);
1506 case nir_op_pack_snorm_4x8
:
1507 emit_pack_snorm_4x8(dst
, op
[0]);
1510 case nir_op_bitfield_reverse
:
1511 emit(BFREV(dst
, op
[0]));
1514 case nir_op_bit_count
:
1515 emit(CBIT(dst
, op
[0]));
1518 case nir_op_ufind_msb
:
1519 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1522 case nir_op_ifind_msb
: {
1523 vec4_builder bld
= vec4_builder(this).at_end();
1526 if (devinfo
->gen
< 7) {
1527 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1529 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1531 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1532 * count from the LSB side. If FBH didn't return an error
1533 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1534 * count into an LSB count.
1536 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1538 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1539 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1540 inst
->src
[0].negate
= true;
1545 case nir_op_find_lsb
: {
1546 vec4_builder bld
= vec4_builder(this).at_end();
1548 if (devinfo
->gen
< 7) {
1549 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1551 /* (x & -x) generates a value that consists of only the LSB of x.
1552 * For all powers of 2, findMSB(y) == findLSB(y).
1554 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1555 src_reg negated_src
= src
;
1557 /* One must be negated, and the other must be non-negated. It
1558 * doesn't matter which is which.
1560 negated_src
.negate
= true;
1563 bld
.AND(temp
, src
, negated_src
);
1564 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1566 bld
.FBL(dst
, op
[0]);
1571 case nir_op_ubitfield_extract
:
1572 case nir_op_ibitfield_extract
:
1573 unreachable("should have been lowered");
1576 op
[0] = fix_3src_operand(op
[0]);
1577 op
[1] = fix_3src_operand(op
[1]);
1578 op
[2] = fix_3src_operand(op
[2]);
1580 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1584 emit(BFI1(dst
, op
[0], op
[1]));
1588 op
[0] = fix_3src_operand(op
[0]);
1589 op
[1] = fix_3src_operand(op
[1]);
1590 op
[2] = fix_3src_operand(op
[2]);
1592 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1595 case nir_op_bitfield_insert
:
1596 unreachable("not reached: should have been lowered");
1599 /* AND(val, 0x80000000) gives the sign bit.
1601 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1604 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1606 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1607 dst
.type
= BRW_REGISTER_TYPE_UD
;
1608 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1610 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1611 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1612 dst
.type
= BRW_REGISTER_TYPE_F
;
1614 if (instr
->dest
.saturate
) {
1615 inst
= emit(MOV(dst
, src_reg(dst
)));
1616 inst
->saturate
= true;
1621 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1622 * -> non-negative val generates 0x00000000.
1623 * Predicated OR sets 1 if val is positive.
1625 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1626 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1627 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1628 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1632 emit(SHL(dst
, op
[0], op
[1]));
1636 emit(ASR(dst
, op
[0], op
[1]));
1640 emit(SHR(dst
, op
[0], op
[1]));
1644 op
[0] = fix_3src_operand(op
[0]);
1645 op
[1] = fix_3src_operand(op
[1]);
1646 op
[2] = fix_3src_operand(op
[2]);
1648 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1649 inst
->saturate
= instr
->dest
.saturate
;
1653 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1654 inst
->saturate
= instr
->dest
.saturate
;
1658 enum brw_predicate predicate
;
1659 if (!optimize_predicate(instr
, &predicate
)) {
1660 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1661 switch (dst
.writemask
) {
1663 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1666 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1669 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1672 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1675 predicate
= BRW_PREDICATE_NORMAL
;
1679 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1680 inst
->predicate
= predicate
;
1683 case nir_op_fdot_replicated2
:
1684 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1685 inst
->saturate
= instr
->dest
.saturate
;
1688 case nir_op_fdot_replicated3
:
1689 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1690 inst
->saturate
= instr
->dest
.saturate
;
1693 case nir_op_fdot_replicated4
:
1694 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1695 inst
->saturate
= instr
->dest
.saturate
;
1698 case nir_op_fdph_replicated
:
1699 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1700 inst
->saturate
= instr
->dest
.saturate
;
1708 unreachable("not reached: should be lowered by lower_source mods");
1711 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1714 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1718 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1721 unreachable("Unimplemented ALU operation");
1724 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1725 * to sign extend the low bit to 0/~0
1727 if (devinfo
->gen
<= 5 &&
1728 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1729 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1730 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1731 masked
.writemask
= dst
.writemask
;
1732 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1733 src_reg masked_neg
= src_reg(masked
);
1734 masked_neg
.negate
= true;
1735 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1740 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1742 switch (instr
->type
) {
1743 case nir_jump_break
:
1744 emit(BRW_OPCODE_BREAK
);
1747 case nir_jump_continue
:
1748 emit(BRW_OPCODE_CONTINUE
);
1751 case nir_jump_return
:
1754 unreachable("unknown jump");
1758 enum ir_texture_opcode
1759 ir_texture_opcode_for_nir_texop(nir_texop texop
)
1761 enum ir_texture_opcode op
;
1764 case nir_texop_lod
: op
= ir_lod
; break;
1765 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1766 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
1767 case nir_texop_tex
: op
= ir_tex
; break;
1768 case nir_texop_tg4
: op
= ir_tg4
; break;
1769 case nir_texop_txb
: op
= ir_txb
; break;
1770 case nir_texop_txd
: op
= ir_txd
; break;
1771 case nir_texop_txf
: op
= ir_txf
; break;
1772 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1773 case nir_texop_txl
: op
= ir_txl
; break;
1774 case nir_texop_txs
: op
= ir_txs
; break;
1775 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
1777 unreachable("unknown texture opcode");
1783 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
1784 unsigned components
)
1786 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
1791 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1793 unsigned texture
= instr
->texture_index
;
1794 unsigned sampler
= instr
->sampler_index
;
1795 src_reg texture_reg
= brw_imm_ud(texture
);
1796 src_reg sampler_reg
= brw_imm_ud(sampler
);
1798 const glsl_type
*coord_type
= NULL
;
1799 src_reg shadow_comparator
;
1800 src_reg offset_value
;
1802 src_reg sample_index
;
1805 const glsl_type
*dest_type
=
1806 glsl_type_for_nir_alu_type(instr
->dest_type
,
1807 nir_tex_instr_dest_size(instr
));
1808 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
1810 /* The hardware requires a LOD for buffer textures */
1811 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
1814 /* Load the texture operation sources */
1815 uint32_t constant_offset
= 0;
1816 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1817 switch (instr
->src
[i
].src_type
) {
1818 case nir_tex_src_comparator
:
1819 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
1820 BRW_REGISTER_TYPE_F
, 1);
1823 case nir_tex_src_coord
: {
1824 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
1826 switch (instr
->op
) {
1828 case nir_texop_txf_ms
:
1829 case nir_texop_samples_identical
:
1830 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
1832 coord_type
= glsl_type::ivec(src_size
);
1836 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1838 coord_type
= glsl_type::vec(src_size
);
1844 case nir_tex_src_ddx
:
1845 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1846 nir_tex_instr_src_size(instr
, i
));
1849 case nir_tex_src_ddy
:
1850 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
1851 nir_tex_instr_src_size(instr
, i
));
1854 case nir_tex_src_lod
:
1855 switch (instr
->op
) {
1858 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1862 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
1867 case nir_tex_src_ms_index
: {
1868 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
1872 case nir_tex_src_offset
: {
1873 nir_const_value
*const_offset
=
1874 nir_src_as_const_value(instr
->src
[i
].src
);
1875 if (!const_offset
||
1876 !brw_texture_offset(const_offset
->i32
,
1877 nir_tex_instr_src_size(instr
, i
),
1878 &constant_offset
)) {
1880 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
1885 case nir_tex_src_texture_offset
: {
1886 /* The highest texture which may be used by this operation is
1887 * the last element of the array. Mark it here, because the generator
1888 * doesn't have enough information to determine the bound.
1890 uint32_t array_size
= instr
->texture_array_size
;
1891 uint32_t max_used
= texture
+ array_size
- 1;
1892 if (instr
->op
== nir_texop_tg4
) {
1893 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
1895 max_used
+= prog_data
->base
.binding_table
.texture_start
;
1898 brw_mark_surface_used(&prog_data
->base
, max_used
);
1900 /* Emit code to evaluate the actual indexing expression */
1901 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1902 src_reg
temp(this, glsl_type::uint_type
);
1903 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
1904 texture_reg
= emit_uniformize(temp
);
1908 case nir_tex_src_sampler_offset
: {
1909 /* Emit code to evaluate the actual indexing expression */
1910 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
1911 src_reg
temp(this, glsl_type::uint_type
);
1912 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
1913 sampler_reg
= emit_uniformize(temp
);
1917 case nir_tex_src_projector
:
1918 unreachable("Should be lowered by do_lower_texture_projection");
1920 case nir_tex_src_bias
:
1921 unreachable("LOD bias is not valid for vertex shaders.\n");
1924 unreachable("unknown texture source");
1928 if (instr
->op
== nir_texop_txf_ms
||
1929 instr
->op
== nir_texop_samples_identical
) {
1930 assert(coord_type
!= NULL
);
1931 if (devinfo
->gen
>= 7 &&
1932 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
1933 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
1935 mcs
= brw_imm_ud(0u);
1939 /* Stuff the channel select bits in the top of the texture offset */
1940 if (instr
->op
== nir_texop_tg4
) {
1941 if (instr
->component
== 1 &&
1942 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
1943 /* gather4 sampler is broken for green channel on RG32F --
1944 * we must ask for blue instead.
1946 constant_offset
|= 2 << 16;
1948 constant_offset
|= instr
->component
<< 16;
1952 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
1954 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
1956 lod
, lod2
, sample_index
,
1957 constant_offset
, offset_value
, mcs
,
1958 texture
, texture_reg
, sampler_reg
);
1962 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
1964 nir_ssa_values
[instr
->def
.index
] = dst_reg(VGRF
, alloc
.allocate(1));