01ca6b5dc897d214339cce8dff657072405f52d3
2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/macros.h"
26 #include "program/register_allocate.h"
30 #include "glsl/ir_print_visitor.h"
37 assign(unsigned int *reg_hw_locations
, reg
*reg
)
39 if (reg
->file
== GRF
) {
40 reg
->reg
= reg_hw_locations
[reg
->reg
];
45 vec4_visitor::reg_allocate_trivial()
47 unsigned int hw_reg_mapping
[this->virtual_grf_count
];
48 bool virtual_grf_used
[this->virtual_grf_count
];
52 /* Calculate which virtual GRFs are actually in use after whatever
53 * optimization passes have occurred.
55 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
56 virtual_grf_used
[i
] = false;
59 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
60 vec4_instruction
*inst
= (vec4_instruction
*)iter
.get();
62 if (inst
->dst
.file
== GRF
)
63 virtual_grf_used
[inst
->dst
.reg
] = true;
65 for (int i
= 0; i
< 3; i
++) {
66 if (inst
->src
[i
].file
== GRF
)
67 virtual_grf_used
[inst
->src
[i
].reg
] = true;
71 hw_reg_mapping
[0] = this->first_non_payload_grf
;
72 next
= hw_reg_mapping
[0] + this->virtual_grf_sizes
[0];
73 for (i
= 1; i
< this->virtual_grf_count
; i
++) {
74 if (virtual_grf_used
[i
]) {
75 hw_reg_mapping
[i
] = next
;
76 next
+= this->virtual_grf_sizes
[i
];
79 prog_data
->total_grf
= next
;
81 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
82 vec4_instruction
*inst
= (vec4_instruction
*)iter
.get();
84 assign(hw_reg_mapping
, &inst
->dst
);
85 assign(hw_reg_mapping
, &inst
->src
[0]);
86 assign(hw_reg_mapping
, &inst
->src
[1]);
87 assign(hw_reg_mapping
, &inst
->src
[2]);
90 if (prog_data
->total_grf
> max_grf
) {
91 fail("Ran out of regs on trivial allocator (%d/%d)\n",
92 prog_data
->total_grf
, max_grf
);
97 brw_alloc_reg_set_for_classes(struct brw_context
*brw
,
102 /* Compute the total number of registers across all classes. */
103 int ra_reg_count
= 0;
104 for (int i
= 0; i
< class_count
; i
++) {
105 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
108 ralloc_free(brw
->vs
.ra_reg_to_grf
);
109 brw
->vs
.ra_reg_to_grf
= ralloc_array(brw
, uint8_t, ra_reg_count
);
110 ralloc_free(brw
->vs
.regs
);
111 brw
->vs
.regs
= ra_alloc_reg_set(brw
, ra_reg_count
);
112 ralloc_free(brw
->vs
.classes
);
113 brw
->vs
.classes
= ralloc_array(brw
, int, class_count
+ 1);
115 /* Now, add the registers to their classes, and add the conflicts
116 * between them and the base GRF registers (and also each other).
119 for (int i
= 0; i
< class_count
; i
++) {
120 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
121 brw
->vs
.classes
[i
] = ra_alloc_reg_class(brw
->vs
.regs
);
123 for (int j
= 0; j
< class_reg_count
; j
++) {
124 ra_class_add_reg(brw
->vs
.regs
, brw
->vs
.classes
[i
], reg
);
126 brw
->vs
.ra_reg_to_grf
[reg
] = j
;
128 for (int base_reg
= j
;
129 base_reg
< j
+ class_sizes
[i
];
131 ra_add_transitive_reg_conflict(brw
->vs
.regs
, base_reg
, reg
);
137 assert(reg
== ra_reg_count
);
139 ra_set_finalize(brw
->vs
.regs
, NULL
);
143 vec4_visitor::reg_allocate()
145 unsigned int hw_reg_mapping
[virtual_grf_count
];
146 int first_assigned_grf
= this->first_non_payload_grf
;
147 int base_reg_count
= max_grf
- first_assigned_grf
;
148 int class_sizes
[base_reg_count
];
151 /* Using the trivial allocator can be useful in debugging undefined
152 * register access as a result of broken optimization passes.
155 reg_allocate_trivial();
159 calculate_live_intervals();
161 /* Set up the register classes.
163 * The base registers store a vec4. However, we'll need larger
164 * storage for arrays, structures, and matrices, which will be sets
165 * of contiguous registers.
167 class_sizes
[class_count
++] = 1;
169 for (int r
= 0; r
< virtual_grf_count
; r
++) {
172 for (i
= 0; i
< class_count
; i
++) {
173 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
176 if (i
== class_count
) {
177 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
178 fail("Object too large to register allocate.\n");
181 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
185 brw_alloc_reg_set_for_classes(brw
, class_sizes
, class_count
, base_reg_count
);
187 struct ra_graph
*g
= ra_alloc_interference_graph(brw
->vs
.regs
,
190 for (int i
= 0; i
< virtual_grf_count
; i
++) {
191 for (int c
= 0; c
< class_count
; c
++) {
192 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
193 ra_set_node_class(g
, i
, brw
->vs
.classes
[c
]);
198 for (int j
= 0; j
< i
; j
++) {
199 if (virtual_grf_interferes(i
, j
)) {
200 ra_add_node_interference(g
, i
, j
);
205 if (!ra_allocate_no_spills(g
)) {
206 /* Failed to allocate registers. Spill a reg, and the caller will
207 * loop back into here to try again.
209 int reg
= choose_spill_reg(g
);
211 fail("no register to spill\n");
219 /* Get the chosen virtual registers for each node, and map virtual
220 * regs in the register classes back down to real hardware reg
223 prog_data
->total_grf
= first_assigned_grf
;
224 for (int i
= 0; i
< virtual_grf_count
; i
++) {
225 int reg
= ra_get_node_reg(g
, i
);
227 hw_reg_mapping
[i
] = first_assigned_grf
+ brw
->vs
.ra_reg_to_grf
[reg
];
228 prog_data
->total_grf
= MAX2(prog_data
->total_grf
,
229 hw_reg_mapping
[i
] + virtual_grf_sizes
[i
]);
232 foreach_list(node
, &this->instructions
) {
233 vec4_instruction
*inst
= (vec4_instruction
*)node
;
235 assign(hw_reg_mapping
, &inst
->dst
);
236 assign(hw_reg_mapping
, &inst
->src
[0]);
237 assign(hw_reg_mapping
, &inst
->src
[1]);
238 assign(hw_reg_mapping
, &inst
->src
[2]);
245 vec4_visitor::evaluate_spill_costs(float *spill_costs
, bool *no_spill
)
247 float loop_scale
= 1.0;
249 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
250 spill_costs
[i
] = 0.0;
251 no_spill
[i
] = virtual_grf_sizes
[i
] != 1;
254 /* Calculate costs for spilling nodes. Call it a cost of 1 per
255 * spill/unspill we'll have to do, and guess that the insides of
256 * loops run 10 times.
258 foreach_list(node
, &this->instructions
) {
259 vec4_instruction
*inst
= (vec4_instruction
*) node
;
261 for (unsigned int i
= 0; i
< 3; i
++) {
262 if (inst
->src
[i
].file
== GRF
) {
263 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
264 if (inst
->src
[i
].reladdr
)
265 no_spill
[inst
->src
[i
].reg
] = true;
269 if (inst
->dst
.file
== GRF
) {
270 spill_costs
[inst
->dst
.reg
] += loop_scale
;
271 if (inst
->dst
.reladdr
)
272 no_spill
[inst
->dst
.reg
] = true;
275 switch (inst
->opcode
) {
281 case BRW_OPCODE_WHILE
:
285 case VS_OPCODE_SCRATCH_READ
:
286 case VS_OPCODE_SCRATCH_WRITE
:
287 for (int i
= 0; i
< 3; i
++) {
288 if (inst
->src
[i
].file
== GRF
)
289 no_spill
[inst
->src
[i
].reg
] = true;
291 if (inst
->dst
.file
== GRF
)
292 no_spill
[inst
->dst
.reg
] = true;
302 vec4_visitor::choose_spill_reg(struct ra_graph
*g
)
304 float spill_costs
[this->virtual_grf_count
];
305 bool no_spill
[this->virtual_grf_count
];
307 evaluate_spill_costs(spill_costs
, no_spill
);
309 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
311 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
314 return ra_get_best_spill_node(g
);
318 vec4_visitor::spill_reg(int spill_reg_nr
)
320 assert(virtual_grf_sizes
[spill_reg_nr
] == 1);
321 unsigned int spill_offset
= c
->last_scratch
++;
323 /* Generate spill/unspill instructions for the objects being spilled. */
324 foreach_list(node
, &this->instructions
) {
325 vec4_instruction
*inst
= (vec4_instruction
*) node
;
327 for (unsigned int i
= 0; i
< 3; i
++) {
328 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
== spill_reg_nr
) {
329 src_reg spill_reg
= inst
->src
[i
];
330 inst
->src
[i
].reg
= virtual_grf_alloc(1);
331 dst_reg temp
= dst_reg(inst
->src
[i
]);
333 /* Only read the necessary channels, to avoid overwriting the rest
334 * with data that may not have been written to scratch.
337 for (int c
= 0; c
< 4; c
++)
338 temp
.writemask
|= (1 << BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
));
339 assert(temp
.writemask
!= 0);
341 emit_scratch_read(inst
, temp
, spill_reg
, spill_offset
);
345 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
== spill_reg_nr
) {
346 dst_reg spill_reg
= inst
->dst
;
347 inst
->dst
.reg
= virtual_grf_alloc(1);
349 /* We don't want a swizzle when reading from the source; read the
350 * whole register and use spill_reg's writemask to select which
353 src_reg temp
= src_reg(inst
->dst
);
354 temp
.swizzle
= BRW_SWIZZLE_XYZW
;
355 emit_scratch_write(inst
, temp
, spill_reg
, spill_offset
);
359 this->live_intervals_valid
= false;
362 } /* namespace brw */