src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "program/register_allocate.h"
  27 } /* extern "C" */
  28
  29 #include "brw_vec4.h"
  30 #include "brw_vs.h"
  31
  32 using namespace brw;
  33
  34 namespace brw {
  35
  36 static void
  37 assign(unsigned int *reg_hw_locations, reg *reg)
  38 {
  39    if (reg->file == GRF) {
  40       reg->reg = reg_hw_locations[reg->reg];
  41    }
  42 }
  43
  44 bool
  45 vec4_visitor::reg_allocate_trivial()
  46 {
  47    unsigned int hw_reg_mapping[this->virtual_grf_count];
  48    bool virtual_grf_used[this->virtual_grf_count];
  49    int i;
  50    int next;
  51
  52    /* Calculate which virtual GRFs are actually in use after whatever
  53     * optimization passes have occurred.
  54     */
  55    for (int i = 0; i < this->virtual_grf_count; i++) {
  56       virtual_grf_used[i] = false;
  57    }
  58
  59    foreach_iter(exec_list_iterator, iter, this->instructions) {
  60       vec4_instruction *inst = (vec4_instruction *)iter.get();
  61
  62       if (inst->dst.file == GRF)
  63          virtual_grf_used[inst->dst.reg] = true;
  64
  65       for (int i = 0; i < 3; i++) {
  66          if (inst->src[i].file == GRF)
  67             virtual_grf_used[inst->src[i].reg] = true;
  68       }
  69    }
  70
  71    hw_reg_mapping[0] = this->first_non_payload_grf;
  72    next = hw_reg_mapping[0] + this->virtual_grf_sizes[0];
  73    for (i = 1; i < this->virtual_grf_count; i++) {
  74       if (virtual_grf_used[i]) {
  75          hw_reg_mapping[i] = next;
  76          next += this->virtual_grf_sizes[i];
  77       }
  78    }
  79    prog_data->total_grf = next;
  80
  81    foreach_iter(exec_list_iterator, iter, this->instructions) {
  82       vec4_instruction *inst = (vec4_instruction *)iter.get();
  83
  84       assign(hw_reg_mapping, &inst->dst);
  85       assign(hw_reg_mapping, &inst->src[0]);
  86       assign(hw_reg_mapping, &inst->src[1]);
  87       assign(hw_reg_mapping, &inst->src[2]);
  88    }
  89
  90    if (prog_data->total_grf > max_grf) {
  91       fail("Ran out of regs on trivial allocator (%d/%d)\n",
  92            prog_data->total_grf, max_grf);
  93       return false;
  94    }
  95
  96    return true;
  97 }
  98
  99 static void
 100 brw_alloc_reg_set_for_classes(struct brw_context *brw,
 101                               int *class_sizes,
 102                               int class_count,
 103                               int base_reg_count)
 104 {
 105    /* Compute the total number of registers across all classes. */
 106    int ra_reg_count = 0;
 107    for (int i = 0; i < class_count; i++) {
 108       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
 109    }
 110
 111    ralloc_free(brw->vs.ra_reg_to_grf);
 112    brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
 113    ralloc_free(brw->vs.regs);
 114    brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
 115    if (brw->gen >= 6)
 116       ra_set_allocate_round_robin(brw->vs.regs);
 117    ralloc_free(brw->vs.classes);
 118    brw->vs.classes = ralloc_array(brw, int, class_count + 1);
 119
 120    /* Now, add the registers to their classes, and add the conflicts
 121     * between them and the base GRF registers (and also each other).
 122     */
 123    int reg = 0;
 124    for (int i = 0; i < class_count; i++) {
 125       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
 126       brw->vs.classes[i] = ra_alloc_reg_class(brw->vs.regs);
 127
 128       for (int j = 0; j < class_reg_count; j++) {
 129          ra_class_add_reg(brw->vs.regs, brw->vs.classes[i], reg);
 130
 131          brw->vs.ra_reg_to_grf[reg] = j;
 132
 133          for (int base_reg = j;
 134               base_reg < j + class_sizes[i];
 135               base_reg++) {
 136             ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
 137          }
 138
 139          reg++;
 140       }
 141    }
 142    assert(reg == ra_reg_count);
 143
 144    ra_set_finalize(brw->vs.regs, NULL);
 145 }
 146
 147 bool
 148 vec4_visitor::reg_allocate()
 149 {
 150    unsigned int hw_reg_mapping[virtual_grf_count];
 151    int first_assigned_grf = this->first_non_payload_grf;
 152    int base_reg_count = max_grf - first_assigned_grf;
 153    int class_sizes[base_reg_count];
 154    int class_count = 0;
 155
 156    /* Using the trivial allocator can be useful in debugging undefined
 157     * register access as a result of broken optimization passes.
 158     */
 159    if (0)
 160       return reg_allocate_trivial();
 161
 162    calculate_live_intervals();
 163
 164    /* Set up the register classes.
 165     *
 166     * The base registers store a vec4.  However, we'll need larger
 167     * storage for arrays, structures, and matrices, which will be sets
 168     * of contiguous registers.
 169     */
 170    class_sizes[class_count++] = 1;
 171
 172    for (int r = 0; r < virtual_grf_count; r++) {
 173       int i;
 174
 175       for (i = 0; i < class_count; i++) {
 176          if (class_sizes[i] == this->virtual_grf_sizes[r])
 177             break;
 178       }
 179       if (i == class_count) {
 180          if (this->virtual_grf_sizes[r] >= base_reg_count) {
 181             fail("Object too large to register allocate.\n");
 182          }
 183
 184          class_sizes[class_count++] = this->virtual_grf_sizes[r];
 185       }
 186    }
 187
 188    brw_alloc_reg_set_for_classes(brw, class_sizes, class_count, base_reg_count);
 189
 190    struct ra_graph *g = ra_alloc_interference_graph(brw->vs.regs,
 191                                                     virtual_grf_count);
 192
 193    for (int i = 0; i < virtual_grf_count; i++) {
 194       for (int c = 0; c < class_count; c++) {
 195          if (class_sizes[c] == this->virtual_grf_sizes[i]) {
 196             ra_set_node_class(g, i, brw->vs.classes[c]);
 197             break;
 198          }
 199       }
 200
 201       for (int j = 0; j < i; j++) {
 202          if (virtual_grf_interferes(i, j)) {
 203             ra_add_node_interference(g, i, j);
 204          }
 205       }
 206    }
 207
 208    if (!ra_allocate_no_spills(g)) {
 209       /* Failed to allocate registers.  Spill a reg, and the caller will
 210        * loop back into here to try again.
 211        */
 212       int reg = choose_spill_reg(g);
 213       if (reg == -1) {
 214          fail("no register to spill\n");
 215       } else {
 216          spill_reg(reg);
 217       }
 218       ralloc_free(g);
 219       return false;
 220    }
 221
 222    /* Get the chosen virtual registers for each node, and map virtual
 223     * regs in the register classes back down to real hardware reg
 224     * numbers.
 225     */
 226    prog_data->total_grf = first_assigned_grf;
 227    for (int i = 0; i < virtual_grf_count; i++) {
 228       int reg = ra_get_node_reg(g, i);
 229
 230       hw_reg_mapping[i] = first_assigned_grf + brw->vs.ra_reg_to_grf[reg];
 231       prog_data->total_grf = MAX2(prog_data->total_grf,
 232                                   hw_reg_mapping[i] + virtual_grf_sizes[i]);
 233    }
 234
 235    foreach_list(node, &this->instructions) {
 236       vec4_instruction *inst = (vec4_instruction *)node;
 237
 238       assign(hw_reg_mapping, &inst->dst);
 239       assign(hw_reg_mapping, &inst->src[0]);
 240       assign(hw_reg_mapping, &inst->src[1]);
 241       assign(hw_reg_mapping, &inst->src[2]);
 242    }
 243
 244    ralloc_free(g);
 245
 246    return true;
 247 }
 248
 249 void
 250 vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
 251 {
 252    float loop_scale = 1.0;
 253
 254    for (int i = 0; i < this->virtual_grf_count; i++) {
 255       spill_costs[i] = 0.0;
 256       no_spill[i] = virtual_grf_sizes[i] != 1;
 257    }
 258
 259    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 260     * spill/unspill we'll have to do, and guess that the insides of
 261     * loops run 10 times.
 262     */
 263    foreach_list(node, &this->instructions) {
 264       vec4_instruction *inst = (vec4_instruction *) node;
 265
 266       for (unsigned int i = 0; i < 3; i++) {
 267          if (inst->src[i].file == GRF) {
 268             spill_costs[inst->src[i].reg] += loop_scale;
 269             if (inst->src[i].reladdr)
 270                no_spill[inst->src[i].reg] = true;
 271          }
 272       }
 273
 274       if (inst->dst.file == GRF) {
 275          spill_costs[inst->dst.reg] += loop_scale;
 276          if (inst->dst.reladdr)
 277             no_spill[inst->dst.reg] = true;
 278       }
 279
 280       switch (inst->opcode) {
 281
 282       case BRW_OPCODE_DO:
 283          loop_scale *= 10;
 284          break;
 285
 286       case BRW_OPCODE_WHILE:
 287          loop_scale /= 10;
 288          break;
 289
 290       case VS_OPCODE_SCRATCH_READ:
 291       case VS_OPCODE_SCRATCH_WRITE:
 292          for (int i = 0; i < 3; i++) {
 293             if (inst->src[i].file == GRF)
 294                no_spill[inst->src[i].reg] = true;
 295          }
 296          if (inst->dst.file == GRF)
 297             no_spill[inst->dst.reg] = true;
 298          break;
 299
 300       default:
 301          break;
 302       }
 303    }
 304 }
 305
 306 int
 307 vec4_visitor::choose_spill_reg(struct ra_graph *g)
 308 {
 309    float spill_costs[this->virtual_grf_count];
 310    bool no_spill[this->virtual_grf_count];
 311
 312    evaluate_spill_costs(spill_costs, no_spill);
 313
 314    for (int i = 0; i < this->virtual_grf_count; i++) {
 315       if (!no_spill[i])
 316          ra_set_node_spill_cost(g, i, spill_costs[i]);
 317    }
 318
 319    return ra_get_best_spill_node(g);
 320 }
 321
 322 void
 323 vec4_visitor::spill_reg(int spill_reg_nr)
 324 {
 325    assert(virtual_grf_sizes[spill_reg_nr] == 1);
 326    unsigned int spill_offset = c->last_scratch++;
 327
 328    /* Generate spill/unspill instructions for the objects being spilled. */
 329    foreach_list(node, &this->instructions) {
 330       vec4_instruction *inst = (vec4_instruction *) node;
 331
 332       for (unsigned int i = 0; i < 3; i++) {
 333          if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
 334             src_reg spill_reg = inst->src[i];
 335             inst->src[i].reg = virtual_grf_alloc(1);
 336             dst_reg temp = dst_reg(inst->src[i]);
 337
 338             /* Only read the necessary channels, to avoid overwriting the rest
 339              * with data that may not have been written to scratch.
 340              */
 341             temp.writemask = 0;
 342             for (int c = 0; c < 4; c++)
 343                temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
 344             assert(temp.writemask != 0);
 345
 346             emit_scratch_read(inst, temp, spill_reg, spill_offset);
 347          }
 348       }
 349
 350       if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
 351          emit_scratch_write(inst, spill_offset);
 352       }
 353    }
 354
 355    this->live_intervals_valid = false;
 356 }
 357
 358 } /* namespace brw */