2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/macros.h"
26 #include "program/register_allocate.h"
37 assign(unsigned int *reg_hw_locations
, backend_reg
*reg
)
39 if (reg
->file
== GRF
) {
40 reg
->reg
= reg_hw_locations
[reg
->reg
];
45 vec4_visitor::reg_allocate_trivial()
47 unsigned int hw_reg_mapping
[this->virtual_grf_count
];
48 bool virtual_grf_used
[this->virtual_grf_count
];
52 /* Calculate which virtual GRFs are actually in use after whatever
53 * optimization passes have occurred.
55 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
56 virtual_grf_used
[i
] = false;
59 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
60 if (inst
->dst
.file
== GRF
)
61 virtual_grf_used
[inst
->dst
.reg
] = true;
63 for (int i
= 0; i
< 3; i
++) {
64 if (inst
->src
[i
].file
== GRF
)
65 virtual_grf_used
[inst
->src
[i
].reg
] = true;
69 hw_reg_mapping
[0] = this->first_non_payload_grf
;
70 next
= hw_reg_mapping
[0] + this->virtual_grf_sizes
[0];
71 for (i
= 1; i
< this->virtual_grf_count
; i
++) {
72 if (virtual_grf_used
[i
]) {
73 hw_reg_mapping
[i
] = next
;
74 next
+= this->virtual_grf_sizes
[i
];
77 prog_data
->total_grf
= next
;
79 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
80 assign(hw_reg_mapping
, &inst
->dst
);
81 assign(hw_reg_mapping
, &inst
->src
[0]);
82 assign(hw_reg_mapping
, &inst
->src
[1]);
83 assign(hw_reg_mapping
, &inst
->src
[2]);
86 if (prog_data
->total_grf
> max_grf
) {
87 fail("Ran out of regs on trivial allocator (%d/%d)\n",
88 prog_data
->total_grf
, max_grf
);
96 brw_vec4_alloc_reg_set(struct intel_screen
*screen
)
99 screen
->devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
101 /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
102 * SEND-from-GRF sources cannot be split, so we also need classes for each
103 * potential message length.
105 const int class_count
= 2;
106 const int class_sizes
[class_count
] = {1, 2};
108 /* Compute the total number of registers across all classes. */
109 int ra_reg_count
= 0;
110 for (int i
= 0; i
< class_count
; i
++) {
111 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
114 ralloc_free(screen
->vec4_reg_set
.ra_reg_to_grf
);
115 screen
->vec4_reg_set
.ra_reg_to_grf
= ralloc_array(screen
, uint8_t, ra_reg_count
);
116 ralloc_free(screen
->vec4_reg_set
.regs
);
117 screen
->vec4_reg_set
.regs
= ra_alloc_reg_set(screen
, ra_reg_count
);
118 if (screen
->devinfo
->gen
>= 6)
119 ra_set_allocate_round_robin(screen
->vec4_reg_set
.regs
);
120 ralloc_free(screen
->vec4_reg_set
.classes
);
121 screen
->vec4_reg_set
.classes
= ralloc_array(screen
, int, class_count
);
123 /* Now, add the registers to their classes, and add the conflicts
124 * between them and the base GRF registers (and also each other).
127 for (int i
= 0; i
< class_count
; i
++) {
128 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
129 screen
->vec4_reg_set
.classes
[i
] = ra_alloc_reg_class(screen
->vec4_reg_set
.regs
);
131 for (int j
= 0; j
< class_reg_count
; j
++) {
132 ra_class_add_reg(screen
->vec4_reg_set
.regs
, screen
->vec4_reg_set
.classes
[i
], reg
);
134 screen
->vec4_reg_set
.ra_reg_to_grf
[reg
] = j
;
136 for (int base_reg
= j
;
137 base_reg
< j
+ class_sizes
[i
];
139 ra_add_transitive_reg_conflict(screen
->vec4_reg_set
.regs
, base_reg
, reg
);
145 assert(reg
== ra_reg_count
);
147 ra_set_finalize(screen
->vec4_reg_set
.regs
, NULL
);
151 vec4_visitor::setup_payload_interference(struct ra_graph
*g
,
152 int first_payload_node
,
155 int payload_node_count
= this->first_non_payload_grf
;
157 for (int i
= 0; i
< payload_node_count
; i
++) {
158 /* Mark each payload reg node as being allocated to its physical register.
160 * The alternative would be to have per-physical register classes, which
161 * would just be silly.
163 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
165 /* For now, just mark each payload node as interfering with every other
166 * node to be allocated.
168 for (int j
= 0; j
< reg_node_count
; j
++) {
169 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
175 vec4_visitor::reg_allocate()
177 struct intel_screen
*screen
= brw
->intelScreen
;
178 unsigned int hw_reg_mapping
[virtual_grf_count
];
179 int payload_reg_count
= this->first_non_payload_grf
;
181 /* Using the trivial allocator can be useful in debugging undefined
182 * register access as a result of broken optimization passes.
185 return reg_allocate_trivial();
187 calculate_live_intervals();
189 int node_count
= virtual_grf_count
;
190 int first_payload_node
= node_count
;
191 node_count
+= payload_reg_count
;
193 ra_alloc_interference_graph(screen
->vec4_reg_set
.regs
, node_count
);
195 for (int i
= 0; i
< virtual_grf_count
; i
++) {
196 int size
= this->virtual_grf_sizes
[i
];
197 assert(size
>= 1 && size
<= 2 &&
198 "Register allocation relies on split_virtual_grfs().");
199 ra_set_node_class(g
, i
, screen
->vec4_reg_set
.classes
[size
- 1]);
201 for (int j
= 0; j
< i
; j
++) {
202 if (virtual_grf_interferes(i
, j
)) {
203 ra_add_node_interference(g
, i
, j
);
208 setup_payload_interference(g
, first_payload_node
, node_count
);
210 if (!ra_allocate_no_spills(g
)) {
211 /* Failed to allocate registers. Spill a reg, and the caller will
212 * loop back into here to try again.
214 int reg
= choose_spill_reg(g
);
215 if (this->no_spills
) {
216 fail("Failure to register allocate. Reduce number of live "
217 "values to avoid this.");
218 } else if (reg
== -1) {
219 fail("no register to spill\n");
227 /* Get the chosen virtual registers for each node, and map virtual
228 * regs in the register classes back down to real hardware reg
231 prog_data
->total_grf
= payload_reg_count
;
232 for (int i
= 0; i
< virtual_grf_count
; i
++) {
233 int reg
= ra_get_node_reg(g
, i
);
235 hw_reg_mapping
[i
] = screen
->vec4_reg_set
.ra_reg_to_grf
[reg
];
236 prog_data
->total_grf
= MAX2(prog_data
->total_grf
,
237 hw_reg_mapping
[i
] + virtual_grf_sizes
[i
]);
240 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
241 assign(hw_reg_mapping
, &inst
->dst
);
242 assign(hw_reg_mapping
, &inst
->src
[0]);
243 assign(hw_reg_mapping
, &inst
->src
[1]);
244 assign(hw_reg_mapping
, &inst
->src
[2]);
253 vec4_visitor::evaluate_spill_costs(float *spill_costs
, bool *no_spill
)
255 float loop_scale
= 1.0;
257 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
258 spill_costs
[i
] = 0.0;
259 no_spill
[i
] = virtual_grf_sizes
[i
] != 1;
262 /* Calculate costs for spilling nodes. Call it a cost of 1 per
263 * spill/unspill we'll have to do, and guess that the insides of
264 * loops run 10 times.
266 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
267 for (unsigned int i
= 0; i
< 3; i
++) {
268 if (inst
->src
[i
].file
== GRF
) {
269 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
270 if (inst
->src
[i
].reladdr
)
271 no_spill
[inst
->src
[i
].reg
] = true;
275 if (inst
->dst
.file
== GRF
) {
276 spill_costs
[inst
->dst
.reg
] += loop_scale
;
277 if (inst
->dst
.reladdr
)
278 no_spill
[inst
->dst
.reg
] = true;
281 switch (inst
->opcode
) {
287 case BRW_OPCODE_WHILE
:
291 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
292 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
293 for (int i
= 0; i
< 3; i
++) {
294 if (inst
->src
[i
].file
== GRF
)
295 no_spill
[inst
->src
[i
].reg
] = true;
297 if (inst
->dst
.file
== GRF
)
298 no_spill
[inst
->dst
.reg
] = true;
308 vec4_visitor::choose_spill_reg(struct ra_graph
*g
)
310 float spill_costs
[this->virtual_grf_count
];
311 bool no_spill
[this->virtual_grf_count
];
313 evaluate_spill_costs(spill_costs
, no_spill
);
315 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
317 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
320 return ra_get_best_spill_node(g
);
324 vec4_visitor::spill_reg(int spill_reg_nr
)
326 assert(virtual_grf_sizes
[spill_reg_nr
] == 1);
327 unsigned int spill_offset
= c
->last_scratch
++;
329 /* Generate spill/unspill instructions for the objects being spilled. */
330 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
331 for (unsigned int i
= 0; i
< 3; i
++) {
332 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
== spill_reg_nr
) {
333 src_reg spill_reg
= inst
->src
[i
];
334 inst
->src
[i
].reg
= virtual_grf_alloc(1);
335 dst_reg temp
= dst_reg(inst
->src
[i
]);
337 /* Only read the necessary channels, to avoid overwriting the rest
338 * with data that may not have been written to scratch.
341 for (int c
= 0; c
< 4; c
++)
342 temp
.writemask
|= (1 << BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
));
343 assert(temp
.writemask
!= 0);
345 emit_scratch_read(inst
, temp
, spill_reg
, spill_offset
);
349 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
== spill_reg_nr
) {
350 emit_scratch_write(inst
, spill_offset
);
354 invalidate_live_intervals();
357 } /* namespace brw */