src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "program/register_allocate.h"
  27 } /* extern "C" */
  28
  29 #include "brw_vec4.h"
  30
  31 using namespace brw;
  32
  33 namespace brw {
  34
  35 static void
  36 assign(unsigned int *reg_hw_locations, reg *reg)
  37 {
  38    if (reg->file == GRF) {
  39       reg->reg = reg_hw_locations[reg->reg];
  40    }
  41 }
  42
  43 bool
  44 vec4_visitor::reg_allocate_trivial()
  45 {
  46    unsigned int hw_reg_mapping[this->virtual_grf_count];
  47    bool virtual_grf_used[this->virtual_grf_count];
  48    int i;
  49    int next;
  50
  51    /* Calculate which virtual GRFs are actually in use after whatever
  52     * optimization passes have occurred.
  53     */
  54    for (int i = 0; i < this->virtual_grf_count; i++) {
  55       virtual_grf_used[i] = false;
  56    }
  57
  58    foreach_iter(exec_list_iterator, iter, this->instructions) {
  59       vec4_instruction *inst = (vec4_instruction *)iter.get();
  60
  61       if (inst->dst.file == GRF)
  62          virtual_grf_used[inst->dst.reg] = true;
  63
  64       for (int i = 0; i < 3; i++) {
  65          if (inst->src[i].file == GRF)
  66             virtual_grf_used[inst->src[i].reg] = true;
  67       }
  68    }
  69
  70    hw_reg_mapping[0] = this->first_non_payload_grf;
  71    next = hw_reg_mapping[0] + this->virtual_grf_sizes[0];
  72    for (i = 1; i < this->virtual_grf_count; i++) {
  73       if (virtual_grf_used[i]) {
  74          hw_reg_mapping[i] = next;
  75          next += this->virtual_grf_sizes[i];
  76       }
  77    }
  78    prog_data->total_grf = next;
  79
  80    foreach_iter(exec_list_iterator, iter, this->instructions) {
  81       vec4_instruction *inst = (vec4_instruction *)iter.get();
  82
  83       assign(hw_reg_mapping, &inst->dst);
  84       assign(hw_reg_mapping, &inst->src[0]);
  85       assign(hw_reg_mapping, &inst->src[1]);
  86       assign(hw_reg_mapping, &inst->src[2]);
  87    }
  88
  89    if (prog_data->total_grf > max_grf) {
  90       fail("Ran out of regs on trivial allocator (%d/%d)\n",
  91            prog_data->total_grf, max_grf);
  92       return false;
  93    }
  94
  95    return true;
  96 }
  97
  98 static void
  99 brw_alloc_reg_set_for_classes(struct brw_context *brw,
 100                               int *class_sizes,
 101                               int class_count,
 102                               int base_reg_count)
 103 {
 104    struct intel_context *intel = &brw->intel;
 105
 106    /* Compute the total number of registers across all classes. */
 107    int ra_reg_count = 0;
 108    for (int i = 0; i < class_count; i++) {
 109       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
 110    }
 111
 112    ralloc_free(brw->vs.ra_reg_to_grf);
 113    brw->vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
 114    ralloc_free(brw->vs.regs);
 115    brw->vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
 116    if (intel->gen >= 6)
 117       ra_set_allocate_round_robin(brw->vs.regs);
 118    ralloc_free(brw->vs.classes);
 119    brw->vs.classes = ralloc_array(brw, int, class_count + 1);
 120
 121    /* Now, add the registers to their classes, and add the conflicts
 122     * between them and the base GRF registers (and also each other).
 123     */
 124    int reg = 0;
 125    for (int i = 0; i < class_count; i++) {
 126       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
 127       brw->vs.classes[i] = ra_alloc_reg_class(brw->vs.regs);
 128
 129       for (int j = 0; j < class_reg_count; j++) {
 130          ra_class_add_reg(brw->vs.regs, brw->vs.classes[i], reg);
 131
 132          brw->vs.ra_reg_to_grf[reg] = j;
 133
 134          for (int base_reg = j;
 135               base_reg < j + class_sizes[i];
 136               base_reg++) {
 137             ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
 138          }
 139
 140          reg++;
 141       }
 142    }
 143    assert(reg == ra_reg_count);
 144
 145    ra_set_finalize(brw->vs.regs, NULL);
 146 }
 147
 148 bool
 149 vec4_visitor::reg_allocate()
 150 {
 151    unsigned int hw_reg_mapping[virtual_grf_count];
 152    int first_assigned_grf = this->first_non_payload_grf;
 153    int base_reg_count = max_grf - first_assigned_grf;
 154    int class_sizes[base_reg_count];
 155    int class_count = 0;
 156
 157    /* Using the trivial allocator can be useful in debugging undefined
 158     * register access as a result of broken optimization passes.
 159     */
 160    if (0)
 161       return reg_allocate_trivial();
 162
 163    calculate_live_intervals();
 164
 165    /* Set up the register classes.
 166     *
 167     * The base registers store a vec4.  However, we'll need larger
 168     * storage for arrays, structures, and matrices, which will be sets
 169     * of contiguous registers.
 170     */
 171    class_sizes[class_count++] = 1;
 172
 173    for (int r = 0; r < virtual_grf_count; r++) {
 174       int i;
 175
 176       for (i = 0; i < class_count; i++) {
 177          if (class_sizes[i] == this->virtual_grf_sizes[r])
 178             break;
 179       }
 180       if (i == class_count) {
 181          if (this->virtual_grf_sizes[r] >= base_reg_count) {
 182             fail("Object too large to register allocate.\n");
 183          }
 184
 185          class_sizes[class_count++] = this->virtual_grf_sizes[r];
 186       }
 187    }
 188
 189    brw_alloc_reg_set_for_classes(brw, class_sizes, class_count, base_reg_count);
 190
 191    struct ra_graph *g = ra_alloc_interference_graph(brw->vs.regs,
 192                                                     virtual_grf_count);
 193
 194    for (int i = 0; i < virtual_grf_count; i++) {
 195       for (int c = 0; c < class_count; c++) {
 196          if (class_sizes[c] == this->virtual_grf_sizes[i]) {
 197             ra_set_node_class(g, i, brw->vs.classes[c]);
 198             break;
 199          }
 200       }
 201
 202       for (int j = 0; j < i; j++) {
 203          if (virtual_grf_interferes(i, j)) {
 204             ra_add_node_interference(g, i, j);
 205          }
 206       }
 207    }
 208
 209    if (!ra_allocate_no_spills(g)) {
 210       /* Failed to allocate registers.  Spill a reg, and the caller will
 211        * loop back into here to try again.
 212        */
 213       int reg = choose_spill_reg(g);
 214       if (reg == -1) {
 215          fail("no register to spill\n");
 216       } else {
 217          spill_reg(reg);
 218       }
 219       ralloc_free(g);
 220       return false;
 221    }
 222
 223    /* Get the chosen virtual registers for each node, and map virtual
 224     * regs in the register classes back down to real hardware reg
 225     * numbers.
 226     */
 227    prog_data->total_grf = first_assigned_grf;
 228    for (int i = 0; i < virtual_grf_count; i++) {
 229       int reg = ra_get_node_reg(g, i);
 230
 231       hw_reg_mapping[i] = first_assigned_grf + brw->vs.ra_reg_to_grf[reg];
 232       prog_data->total_grf = MAX2(prog_data->total_grf,
 233                                   hw_reg_mapping[i] + virtual_grf_sizes[i]);
 234    }
 235
 236    foreach_list(node, &this->instructions) {
 237       vec4_instruction *inst = (vec4_instruction *)node;
 238
 239       assign(hw_reg_mapping, &inst->dst);
 240       assign(hw_reg_mapping, &inst->src[0]);
 241       assign(hw_reg_mapping, &inst->src[1]);
 242       assign(hw_reg_mapping, &inst->src[2]);
 243    }
 244
 245    ralloc_free(g);
 246
 247    return true;
 248 }
 249
 250 void
 251 vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
 252 {
 253    float loop_scale = 1.0;
 254
 255    for (int i = 0; i < this->virtual_grf_count; i++) {
 256       spill_costs[i] = 0.0;
 257       no_spill[i] = virtual_grf_sizes[i] != 1;
 258    }
 259
 260    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 261     * spill/unspill we'll have to do, and guess that the insides of
 262     * loops run 10 times.
 263     */
 264    foreach_list(node, &this->instructions) {
 265       vec4_instruction *inst = (vec4_instruction *) node;
 266
 267       for (unsigned int i = 0; i < 3; i++) {
 268          if (inst->src[i].file == GRF) {
 269             spill_costs[inst->src[i].reg] += loop_scale;
 270             if (inst->src[i].reladdr)
 271                no_spill[inst->src[i].reg] = true;
 272          }
 273       }
 274
 275       if (inst->dst.file == GRF) {
 276          spill_costs[inst->dst.reg] += loop_scale;
 277          if (inst->dst.reladdr)
 278             no_spill[inst->dst.reg] = true;
 279       }
 280
 281       switch (inst->opcode) {
 282
 283       case BRW_OPCODE_DO:
 284          loop_scale *= 10;
 285          break;
 286
 287       case BRW_OPCODE_WHILE:
 288          loop_scale /= 10;
 289          break;
 290
 291       case VS_OPCODE_SCRATCH_READ:
 292       case VS_OPCODE_SCRATCH_WRITE:
 293          for (int i = 0; i < 3; i++) {
 294             if (inst->src[i].file == GRF)
 295                no_spill[inst->src[i].reg] = true;
 296          }
 297          if (inst->dst.file == GRF)
 298             no_spill[inst->dst.reg] = true;
 299          break;
 300
 301       default:
 302          break;
 303       }
 304    }
 305 }
 306
 307 int
 308 vec4_visitor::choose_spill_reg(struct ra_graph *g)
 309 {
 310    float spill_costs[this->virtual_grf_count];
 311    bool no_spill[this->virtual_grf_count];
 312
 313    evaluate_spill_costs(spill_costs, no_spill);
 314
 315    for (int i = 0; i < this->virtual_grf_count; i++) {
 316       if (!no_spill[i])
 317          ra_set_node_spill_cost(g, i, spill_costs[i]);
 318    }
 319
 320    return ra_get_best_spill_node(g);
 321 }
 322
 323 void
 324 vec4_visitor::spill_reg(int spill_reg_nr)
 325 {
 326    assert(virtual_grf_sizes[spill_reg_nr] == 1);
 327    unsigned int spill_offset = c->last_scratch++;
 328
 329    /* Generate spill/unspill instructions for the objects being spilled. */
 330    foreach_list(node, &this->instructions) {
 331       vec4_instruction *inst = (vec4_instruction *) node;
 332
 333       for (unsigned int i = 0; i < 3; i++) {
 334          if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
 335             src_reg spill_reg = inst->src[i];
 336             inst->src[i].reg = virtual_grf_alloc(1);
 337             dst_reg temp = dst_reg(inst->src[i]);
 338
 339             /* Only read the necessary channels, to avoid overwriting the rest
 340              * with data that may not have been written to scratch.
 341              */
 342             temp.writemask = 0;
 343             for (int c = 0; c < 4; c++)
 344                temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
 345             assert(temp.writemask != 0);
 346
 347             emit_scratch_read(inst, temp, spill_reg, spill_offset);
 348          }
 349       }
 350
 351       if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
 352          emit_scratch_write(inst, spill_offset);
 353       }
 354    }
 355
 356    this->live_intervals_valid = false;
 357 }
 358
 359 } /* namespace brw */