2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/macros.h"
26 #include "program/register_allocate.h"
37 assign(unsigned int *reg_hw_locations
, reg
*reg
)
39 if (reg
->file
== GRF
) {
40 reg
->reg
= reg_hw_locations
[reg
->reg
];
45 vec4_visitor::reg_allocate_trivial()
47 unsigned int hw_reg_mapping
[this->virtual_grf_count
];
48 bool virtual_grf_used
[this->virtual_grf_count
];
52 /* Calculate which virtual GRFs are actually in use after whatever
53 * optimization passes have occurred.
55 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
56 virtual_grf_used
[i
] = false;
59 foreach_list(node
, &this->instructions
) {
60 vec4_instruction
*inst
= (vec4_instruction
*) node
;
62 if (inst
->dst
.file
== GRF
)
63 virtual_grf_used
[inst
->dst
.reg
] = true;
65 for (int i
= 0; i
< 3; i
++) {
66 if (inst
->src
[i
].file
== GRF
)
67 virtual_grf_used
[inst
->src
[i
].reg
] = true;
71 hw_reg_mapping
[0] = this->first_non_payload_grf
;
72 next
= hw_reg_mapping
[0] + this->virtual_grf_sizes
[0];
73 for (i
= 1; i
< this->virtual_grf_count
; i
++) {
74 if (virtual_grf_used
[i
]) {
75 hw_reg_mapping
[i
] = next
;
76 next
+= this->virtual_grf_sizes
[i
];
79 prog_data
->total_grf
= next
;
81 foreach_list(node
, &this->instructions
) {
82 vec4_instruction
*inst
= (vec4_instruction
*) node
;
84 assign(hw_reg_mapping
, &inst
->dst
);
85 assign(hw_reg_mapping
, &inst
->src
[0]);
86 assign(hw_reg_mapping
, &inst
->src
[1]);
87 assign(hw_reg_mapping
, &inst
->src
[2]);
90 if (prog_data
->total_grf
> max_grf
) {
91 fail("Ran out of regs on trivial allocator (%d/%d)\n",
92 prog_data
->total_grf
, max_grf
);
100 brw_vec4_alloc_reg_set(struct brw_context
*brw
)
102 int base_reg_count
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
104 /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
105 * SEND-from-GRF sources cannot be split, so we also need classes for each
106 * potential message length.
108 const int class_count
= 2;
109 const int class_sizes
[class_count
] = {1, 2};
111 /* Compute the total number of registers across all classes. */
112 int ra_reg_count
= 0;
113 for (int i
= 0; i
< class_count
; i
++) {
114 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
117 ralloc_free(brw
->vec4
.ra_reg_to_grf
);
118 brw
->vec4
.ra_reg_to_grf
= ralloc_array(brw
, uint8_t, ra_reg_count
);
119 ralloc_free(brw
->vec4
.regs
);
120 brw
->vec4
.regs
= ra_alloc_reg_set(brw
, ra_reg_count
);
122 ra_set_allocate_round_robin(brw
->vec4
.regs
);
123 ralloc_free(brw
->vec4
.classes
);
124 brw
->vec4
.classes
= ralloc_array(brw
, int, class_count
);
126 /* Now, add the registers to their classes, and add the conflicts
127 * between them and the base GRF registers (and also each other).
130 for (int i
= 0; i
< class_count
; i
++) {
131 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
132 brw
->vec4
.classes
[i
] = ra_alloc_reg_class(brw
->vec4
.regs
);
134 for (int j
= 0; j
< class_reg_count
; j
++) {
135 ra_class_add_reg(brw
->vec4
.regs
, brw
->vec4
.classes
[i
], reg
);
137 brw
->vec4
.ra_reg_to_grf
[reg
] = j
;
139 for (int base_reg
= j
;
140 base_reg
< j
+ class_sizes
[i
];
142 ra_add_transitive_reg_conflict(brw
->vec4
.regs
, base_reg
, reg
);
148 assert(reg
== ra_reg_count
);
150 ra_set_finalize(brw
->vec4
.regs
, NULL
);
154 vec4_visitor::setup_payload_interference(struct ra_graph
*g
,
155 int first_payload_node
,
158 int payload_node_count
= this->first_non_payload_grf
;
160 for (int i
= 0; i
< payload_node_count
; i
++) {
161 /* Mark each payload reg node as being allocated to its physical register.
163 * The alternative would be to have per-physical register classes, which
164 * would just be silly.
166 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
168 /* For now, just mark each payload node as interfering with every other
169 * node to be allocated.
171 for (int j
= 0; j
< reg_node_count
; j
++) {
172 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
178 vec4_visitor::reg_allocate()
180 unsigned int hw_reg_mapping
[virtual_grf_count
];
181 int payload_reg_count
= this->first_non_payload_grf
;
183 /* Using the trivial allocator can be useful in debugging undefined
184 * register access as a result of broken optimization passes.
187 return reg_allocate_trivial();
189 calculate_live_intervals();
191 int node_count
= virtual_grf_count
;
192 int first_payload_node
= node_count
;
193 node_count
+= payload_reg_count
;
195 ra_alloc_interference_graph(brw
->vec4
.regs
, node_count
);
197 for (int i
= 0; i
< virtual_grf_count
; i
++) {
198 int size
= this->virtual_grf_sizes
[i
];
199 assert(size
>= 1 && size
<= 2 &&
200 "Register allocation relies on split_virtual_grfs().");
201 ra_set_node_class(g
, i
, brw
->vec4
.classes
[size
- 1]);
203 for (int j
= 0; j
< i
; j
++) {
204 if (virtual_grf_interferes(i
, j
)) {
205 ra_add_node_interference(g
, i
, j
);
210 setup_payload_interference(g
, first_payload_node
, node_count
);
212 if (!ra_allocate_no_spills(g
)) {
213 /* Failed to allocate registers. Spill a reg, and the caller will
214 * loop back into here to try again.
216 int reg
= choose_spill_reg(g
);
217 if (this->no_spills
) {
218 fail("Failure to register allocate. Reduce number of live "
219 "values to avoid this.");
220 } else if (reg
== -1) {
221 fail("no register to spill\n");
229 /* Get the chosen virtual registers for each node, and map virtual
230 * regs in the register classes back down to real hardware reg
233 prog_data
->total_grf
= payload_reg_count
;
234 for (int i
= 0; i
< virtual_grf_count
; i
++) {
235 int reg
= ra_get_node_reg(g
, i
);
237 hw_reg_mapping
[i
] = brw
->vec4
.ra_reg_to_grf
[reg
];
238 prog_data
->total_grf
= MAX2(prog_data
->total_grf
,
239 hw_reg_mapping
[i
] + virtual_grf_sizes
[i
]);
242 foreach_list(node
, &this->instructions
) {
243 vec4_instruction
*inst
= (vec4_instruction
*)node
;
245 assign(hw_reg_mapping
, &inst
->dst
);
246 assign(hw_reg_mapping
, &inst
->src
[0]);
247 assign(hw_reg_mapping
, &inst
->src
[1]);
248 assign(hw_reg_mapping
, &inst
->src
[2]);
257 vec4_visitor::evaluate_spill_costs(float *spill_costs
, bool *no_spill
)
259 float loop_scale
= 1.0;
261 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
262 spill_costs
[i
] = 0.0;
263 no_spill
[i
] = virtual_grf_sizes
[i
] != 1;
266 /* Calculate costs for spilling nodes. Call it a cost of 1 per
267 * spill/unspill we'll have to do, and guess that the insides of
268 * loops run 10 times.
270 foreach_list(node
, &this->instructions
) {
271 vec4_instruction
*inst
= (vec4_instruction
*) node
;
273 for (unsigned int i
= 0; i
< 3; i
++) {
274 if (inst
->src
[i
].file
== GRF
) {
275 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
276 if (inst
->src
[i
].reladdr
)
277 no_spill
[inst
->src
[i
].reg
] = true;
281 if (inst
->dst
.file
== GRF
) {
282 spill_costs
[inst
->dst
.reg
] += loop_scale
;
283 if (inst
->dst
.reladdr
)
284 no_spill
[inst
->dst
.reg
] = true;
287 switch (inst
->opcode
) {
293 case BRW_OPCODE_WHILE
:
297 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
298 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
299 for (int i
= 0; i
< 3; i
++) {
300 if (inst
->src
[i
].file
== GRF
)
301 no_spill
[inst
->src
[i
].reg
] = true;
303 if (inst
->dst
.file
== GRF
)
304 no_spill
[inst
->dst
.reg
] = true;
314 vec4_visitor::choose_spill_reg(struct ra_graph
*g
)
316 float spill_costs
[this->virtual_grf_count
];
317 bool no_spill
[this->virtual_grf_count
];
319 evaluate_spill_costs(spill_costs
, no_spill
);
321 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
323 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
326 return ra_get_best_spill_node(g
);
330 vec4_visitor::spill_reg(int spill_reg_nr
)
332 assert(virtual_grf_sizes
[spill_reg_nr
] == 1);
333 unsigned int spill_offset
= c
->last_scratch
++;
335 /* Generate spill/unspill instructions for the objects being spilled. */
336 foreach_list(node
, &this->instructions
) {
337 vec4_instruction
*inst
= (vec4_instruction
*) node
;
339 for (unsigned int i
= 0; i
< 3; i
++) {
340 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
== spill_reg_nr
) {
341 src_reg spill_reg
= inst
->src
[i
];
342 inst
->src
[i
].reg
= virtual_grf_alloc(1);
343 dst_reg temp
= dst_reg(inst
->src
[i
]);
345 /* Only read the necessary channels, to avoid overwriting the rest
346 * with data that may not have been written to scratch.
349 for (int c
= 0; c
< 4; c
++)
350 temp
.writemask
|= (1 << BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
));
351 assert(temp
.writemask
!= 0);
353 emit_scratch_read(inst
, temp
, spill_reg
, spill_offset
);
357 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
== spill_reg_nr
) {
358 emit_scratch_write(inst
, spill_offset
);
362 invalidate_live_intervals();
365 } /* namespace brw */