src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "util/register_allocate.h"
  27 } /* extern "C" */
  28
  29 #include "brw_vec4.h"
  30 #include "brw_vs.h"
  31 #include "brw_cfg.h"
  32
  33 using namespace brw;
  34
  35 namespace brw {
  36
  37 static void
  38 assign(unsigned int *reg_hw_locations, backend_reg *reg)
  39 {
  40    if (reg->file == GRF) {
  41       reg->reg = reg_hw_locations[reg->reg];
  42    }
  43 }
  44
  45 bool
  46 vec4_visitor::reg_allocate_trivial()
  47 {
  48    unsigned int hw_reg_mapping[this->virtual_grf_count];
  49    bool virtual_grf_used[this->virtual_grf_count];
  50    int i;
  51    int next;
  52
  53    /* Calculate which virtual GRFs are actually in use after whatever
  54     * optimization passes have occurred.
  55     */
  56    for (int i = 0; i < this->virtual_grf_count; i++) {
  57       virtual_grf_used[i] = false;
  58    }
  59
  60    foreach_in_list(vec4_instruction, inst, &instructions) {
  61       if (inst->dst.file == GRF)
  62          virtual_grf_used[inst->dst.reg] = true;
  63
  64       for (int i = 0; i < 3; i++) {
  65          if (inst->src[i].file == GRF)
  66             virtual_grf_used[inst->src[i].reg] = true;
  67       }
  68    }
  69
  70    hw_reg_mapping[0] = this->first_non_payload_grf;
  71    next = hw_reg_mapping[0] + this->virtual_grf_sizes[0];
  72    for (i = 1; i < this->virtual_grf_count; i++) {
  73       if (virtual_grf_used[i]) {
  74          hw_reg_mapping[i] = next;
  75          next += this->virtual_grf_sizes[i];
  76       }
  77    }
  78    prog_data->total_grf = next;
  79
  80    foreach_in_list(vec4_instruction, inst, &instructions) {
  81       assign(hw_reg_mapping, &inst->dst);
  82       assign(hw_reg_mapping, &inst->src[0]);
  83       assign(hw_reg_mapping, &inst->src[1]);
  84       assign(hw_reg_mapping, &inst->src[2]);
  85    }
  86
  87    if (prog_data->total_grf > max_grf) {
  88       fail("Ran out of regs on trivial allocator (%d/%d)\n",
  89            prog_data->total_grf, max_grf);
  90       return false;
  91    }
  92
  93    return true;
  94 }
  95
  96 extern "C" void
  97 brw_vec4_alloc_reg_set(struct intel_screen *screen)
  98 {
  99    int base_reg_count =
 100       screen->devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 101
 102    /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
 103     * SEND-from-GRF sources cannot be split, so we also need classes for each
 104     * potential message length.
 105     */
 106    const int class_count = 2;
 107    const int class_sizes[class_count] = {1, 2};
 108
 109    /* Compute the total number of registers across all classes. */
 110    int ra_reg_count = 0;
 111    for (int i = 0; i < class_count; i++) {
 112       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
 113    }
 114
 115    ralloc_free(screen->vec4_reg_set.ra_reg_to_grf);
 116    screen->vec4_reg_set.ra_reg_to_grf = ralloc_array(screen, uint8_t, ra_reg_count);
 117    ralloc_free(screen->vec4_reg_set.regs);
 118    screen->vec4_reg_set.regs = ra_alloc_reg_set(screen, ra_reg_count);
 119    if (screen->devinfo->gen >= 6)
 120       ra_set_allocate_round_robin(screen->vec4_reg_set.regs);
 121    ralloc_free(screen->vec4_reg_set.classes);
 122    screen->vec4_reg_set.classes = ralloc_array(screen, int, class_count);
 123
 124    /* Now, add the registers to their classes, and add the conflicts
 125     * between them and the base GRF registers (and also each other).
 126     */
 127    int reg = 0;
 128    for (int i = 0; i < class_count; i++) {
 129       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
 130       screen->vec4_reg_set.classes[i] = ra_alloc_reg_class(screen->vec4_reg_set.regs);
 131
 132       for (int j = 0; j < class_reg_count; j++) {
 133          ra_class_add_reg(screen->vec4_reg_set.regs, screen->vec4_reg_set.classes[i], reg);
 134
 135          screen->vec4_reg_set.ra_reg_to_grf[reg] = j;
 136
 137          for (int base_reg = j;
 138               base_reg < j + class_sizes[i];
 139               base_reg++) {
 140             ra_add_transitive_reg_conflict(screen->vec4_reg_set.regs, base_reg, reg);
 141          }
 142
 143          reg++;
 144       }
 145    }
 146    assert(reg == ra_reg_count);
 147
 148    ra_set_finalize(screen->vec4_reg_set.regs, NULL);
 149 }
 150
 151 void
 152 vec4_visitor::setup_payload_interference(struct ra_graph *g,
 153                                          int first_payload_node,
 154                                          int reg_node_count)
 155 {
 156    int payload_node_count = this->first_non_payload_grf;
 157
 158    for (int i = 0; i < payload_node_count; i++) {
 159       /* Mark each payload reg node as being allocated to its physical register.
 160        *
 161        * The alternative would be to have per-physical register classes, which
 162        * would just be silly.
 163        */
 164       ra_set_node_reg(g, first_payload_node + i, i);
 165
 166       /* For now, just mark each payload node as interfering with every other
 167        * node to be allocated.
 168        */
 169       for (int j = 0; j < reg_node_count; j++) {
 170          ra_add_node_interference(g, first_payload_node + i, j);
 171       }
 172    }
 173 }
 174
 175 bool
 176 vec4_visitor::reg_allocate()
 177 {
 178    struct intel_screen *screen = brw->intelScreen;
 179    unsigned int hw_reg_mapping[virtual_grf_count];
 180    int payload_reg_count = this->first_non_payload_grf;
 181
 182    /* Using the trivial allocator can be useful in debugging undefined
 183     * register access as a result of broken optimization passes.
 184     */
 185    if (0)
 186       return reg_allocate_trivial();
 187
 188    calculate_live_intervals();
 189
 190    int node_count = virtual_grf_count;
 191    int first_payload_node = node_count;
 192    node_count += payload_reg_count;
 193    struct ra_graph *g =
 194       ra_alloc_interference_graph(screen->vec4_reg_set.regs, node_count);
 195
 196    for (int i = 0; i < virtual_grf_count; i++) {
 197       int size = this->virtual_grf_sizes[i];
 198       assert(size >= 1 && size <= 2 &&
 199              "Register allocation relies on split_virtual_grfs().");
 200       ra_set_node_class(g, i, screen->vec4_reg_set.classes[size - 1]);
 201
 202       for (int j = 0; j < i; j++) {
 203          if (virtual_grf_interferes(i, j)) {
 204             ra_add_node_interference(g, i, j);
 205          }
 206       }
 207    }
 208
 209    setup_payload_interference(g, first_payload_node, node_count);
 210
 211    if (!ra_allocate(g)) {
 212       /* Failed to allocate registers.  Spill a reg, and the caller will
 213        * loop back into here to try again.
 214        */
 215       int reg = choose_spill_reg(g);
 216       if (this->no_spills) {
 217          fail("Failure to register allocate.  Reduce number of live "
 218               "values to avoid this.");
 219       } else if (reg == -1) {
 220          fail("no register to spill\n");
 221       } else {
 222          spill_reg(reg);
 223       }
 224       ralloc_free(g);
 225       return false;
 226    }
 227
 228    /* Get the chosen virtual registers for each node, and map virtual
 229     * regs in the register classes back down to real hardware reg
 230     * numbers.
 231     */
 232    prog_data->total_grf = payload_reg_count;
 233    for (int i = 0; i < virtual_grf_count; i++) {
 234       int reg = ra_get_node_reg(g, i);
 235
 236       hw_reg_mapping[i] = screen->vec4_reg_set.ra_reg_to_grf[reg];
 237       prog_data->total_grf = MAX2(prog_data->total_grf,
 238                                   hw_reg_mapping[i] + virtual_grf_sizes[i]);
 239    }
 240
 241    foreach_in_list(vec4_instruction, inst, &instructions) {
 242       assign(hw_reg_mapping, &inst->dst);
 243       assign(hw_reg_mapping, &inst->src[0]);
 244       assign(hw_reg_mapping, &inst->src[1]);
 245       assign(hw_reg_mapping, &inst->src[2]);
 246    }
 247
 248    ralloc_free(g);
 249
 250    return true;
 251 }
 252
 253 void
 254 vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
 255 {
 256    float loop_scale = 1.0;
 257
 258    for (int i = 0; i < this->virtual_grf_count; i++) {
 259       spill_costs[i] = 0.0;
 260       no_spill[i] = virtual_grf_sizes[i] != 1;
 261    }
 262
 263    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 264     * spill/unspill we'll have to do, and guess that the insides of
 265     * loops run 10 times.
 266     */
 267    foreach_in_list(vec4_instruction, inst, &instructions) {
 268       for (unsigned int i = 0; i < 3; i++) {
 269          if (inst->src[i].file == GRF) {
 270             spill_costs[inst->src[i].reg] += loop_scale;
 271             if (inst->src[i].reladdr)
 272                no_spill[inst->src[i].reg] = true;
 273          }
 274       }
 275
 276       if (inst->dst.file == GRF) {
 277          spill_costs[inst->dst.reg] += loop_scale;
 278          if (inst->dst.reladdr)
 279             no_spill[inst->dst.reg] = true;
 280       }
 281
 282       switch (inst->opcode) {
 283
 284       case BRW_OPCODE_DO:
 285          loop_scale *= 10;
 286          break;
 287
 288       case BRW_OPCODE_WHILE:
 289          loop_scale /= 10;
 290          break;
 291
 292       case SHADER_OPCODE_GEN4_SCRATCH_READ:
 293       case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 294          for (int i = 0; i < 3; i++) {
 295             if (inst->src[i].file == GRF)
 296                no_spill[inst->src[i].reg] = true;
 297          }
 298          if (inst->dst.file == GRF)
 299             no_spill[inst->dst.reg] = true;
 300          break;
 301
 302       default:
 303          break;
 304       }
 305    }
 306 }
 307
 308 int
 309 vec4_visitor::choose_spill_reg(struct ra_graph *g)
 310 {
 311    float spill_costs[this->virtual_grf_count];
 312    bool no_spill[this->virtual_grf_count];
 313
 314    evaluate_spill_costs(spill_costs, no_spill);
 315
 316    for (int i = 0; i < this->virtual_grf_count; i++) {
 317       if (!no_spill[i])
 318          ra_set_node_spill_cost(g, i, spill_costs[i]);
 319    }
 320
 321    return ra_get_best_spill_node(g);
 322 }
 323
 324 void
 325 vec4_visitor::spill_reg(int spill_reg_nr)
 326 {
 327    assert(virtual_grf_sizes[spill_reg_nr] == 1);
 328    unsigned int spill_offset = c->last_scratch++;
 329
 330    calculate_cfg();
 331
 332    /* Generate spill/unspill instructions for the objects being spilled. */
 333    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 334       for (unsigned int i = 0; i < 3; i++) {
 335          if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
 336             src_reg spill_reg = inst->src[i];
 337             inst->src[i].reg = virtual_grf_alloc(1);
 338             dst_reg temp = dst_reg(inst->src[i]);
 339
 340             /* Only read the necessary channels, to avoid overwriting the rest
 341              * with data that may not have been written to scratch.
 342              */
 343             temp.writemask = 0;
 344             for (int c = 0; c < 4; c++)
 345                temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
 346             assert(temp.writemask != 0);
 347
 348             emit_scratch_read(block, inst, temp, spill_reg, spill_offset);
 349          }
 350       }
 351
 352       if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
 353          emit_scratch_write(block, inst, spill_offset);
 354       }
 355    }
 356
 357    invalidate_live_intervals();
 358 }
 359
 360 } /* namespace brw */