src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "program/register_allocate.h"
  27 } /* extern "C" */
  28
  29 #include "brw_vec4.h"
  30 #include "brw_vs.h"
  31
  32 using namespace brw;
  33
  34 namespace brw {
  35
  36 static void
  37 assign(unsigned int *reg_hw_locations, reg *reg)
  38 {
  39    if (reg->file == GRF) {
  40       reg->reg = reg_hw_locations[reg->reg];
  41    }
  42 }
  43
  44 bool
  45 vec4_visitor::reg_allocate_trivial()
  46 {
  47    unsigned int hw_reg_mapping[this->virtual_grf_count];
  48    bool virtual_grf_used[this->virtual_grf_count];
  49    int i;
  50    int next;
  51
  52    /* Calculate which virtual GRFs are actually in use after whatever
  53     * optimization passes have occurred.
  54     */
  55    for (int i = 0; i < this->virtual_grf_count; i++) {
  56       virtual_grf_used[i] = false;
  57    }
  58
  59    foreach_list(node, &this->instructions) {
  60       vec4_instruction *inst = (vec4_instruction *) node;
  61
  62       if (inst->dst.file == GRF)
  63          virtual_grf_used[inst->dst.reg] = true;
  64
  65       for (int i = 0; i < 3; i++) {
  66          if (inst->src[i].file == GRF)
  67             virtual_grf_used[inst->src[i].reg] = true;
  68       }
  69    }
  70
  71    hw_reg_mapping[0] = this->first_non_payload_grf;
  72    next = hw_reg_mapping[0] + this->virtual_grf_sizes[0];
  73    for (i = 1; i < this->virtual_grf_count; i++) {
  74       if (virtual_grf_used[i]) {
  75          hw_reg_mapping[i] = next;
  76          next += this->virtual_grf_sizes[i];
  77       }
  78    }
  79    prog_data->total_grf = next;
  80
  81    foreach_list(node, &this->instructions) {
  82       vec4_instruction *inst = (vec4_instruction *) node;
  83
  84       assign(hw_reg_mapping, &inst->dst);
  85       assign(hw_reg_mapping, &inst->src[0]);
  86       assign(hw_reg_mapping, &inst->src[1]);
  87       assign(hw_reg_mapping, &inst->src[2]);
  88    }
  89
  90    if (prog_data->total_grf > max_grf) {
  91       fail("Ran out of regs on trivial allocator (%d/%d)\n",
  92            prog_data->total_grf, max_grf);
  93       return false;
  94    }
  95
  96    return true;
  97 }
  98
  99 extern "C" void
 100 brw_vec4_alloc_reg_set(struct intel_screen *screen)
 101 {
 102    int base_reg_count =
 103       screen->devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 104
 105    /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
 106     * SEND-from-GRF sources cannot be split, so we also need classes for each
 107     * potential message length.
 108     */
 109    const int class_count = 2;
 110    const int class_sizes[class_count] = {1, 2};
 111
 112    /* Compute the total number of registers across all classes. */
 113    int ra_reg_count = 0;
 114    for (int i = 0; i < class_count; i++) {
 115       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
 116    }
 117
 118    ralloc_free(screen->vec4_reg_set.ra_reg_to_grf);
 119    screen->vec4_reg_set.ra_reg_to_grf = ralloc_array(screen, uint8_t, ra_reg_count);
 120    ralloc_free(screen->vec4_reg_set.regs);
 121    screen->vec4_reg_set.regs = ra_alloc_reg_set(screen, ra_reg_count);
 122    if (screen->devinfo->gen >= 6)
 123       ra_set_allocate_round_robin(screen->vec4_reg_set.regs);
 124    ralloc_free(screen->vec4_reg_set.classes);
 125    screen->vec4_reg_set.classes = ralloc_array(screen, int, class_count);
 126
 127    /* Now, add the registers to their classes, and add the conflicts
 128     * between them and the base GRF registers (and also each other).
 129     */
 130    int reg = 0;
 131    for (int i = 0; i < class_count; i++) {
 132       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
 133       screen->vec4_reg_set.classes[i] = ra_alloc_reg_class(screen->vec4_reg_set.regs);
 134
 135       for (int j = 0; j < class_reg_count; j++) {
 136          ra_class_add_reg(screen->vec4_reg_set.regs, screen->vec4_reg_set.classes[i], reg);
 137
 138          screen->vec4_reg_set.ra_reg_to_grf[reg] = j;
 139
 140          for (int base_reg = j;
 141               base_reg < j + class_sizes[i];
 142               base_reg++) {
 143             ra_add_transitive_reg_conflict(screen->vec4_reg_set.regs, base_reg, reg);
 144          }
 145
 146          reg++;
 147       }
 148    }
 149    assert(reg == ra_reg_count);
 150
 151    ra_set_finalize(screen->vec4_reg_set.regs, NULL);
 152 }
 153
 154 void
 155 vec4_visitor::setup_payload_interference(struct ra_graph *g,
 156                                          int first_payload_node,
 157                                          int reg_node_count)
 158 {
 159    int payload_node_count = this->first_non_payload_grf;
 160
 161    for (int i = 0; i < payload_node_count; i++) {
 162       /* Mark each payload reg node as being allocated to its physical register.
 163        *
 164        * The alternative would be to have per-physical register classes, which
 165        * would just be silly.
 166        */
 167       ra_set_node_reg(g, first_payload_node + i, i);
 168
 169       /* For now, just mark each payload node as interfering with every other
 170        * node to be allocated.
 171        */
 172       for (int j = 0; j < reg_node_count; j++) {
 173          ra_add_node_interference(g, first_payload_node + i, j);
 174       }
 175    }
 176 }
 177
 178 bool
 179 vec4_visitor::reg_allocate()
 180 {
 181    struct intel_screen *screen = brw->intelScreen;
 182    unsigned int hw_reg_mapping[virtual_grf_count];
 183    int payload_reg_count = this->first_non_payload_grf;
 184
 185    /* Using the trivial allocator can be useful in debugging undefined
 186     * register access as a result of broken optimization passes.
 187     */
 188    if (0)
 189       return reg_allocate_trivial();
 190
 191    calculate_live_intervals();
 192
 193    int node_count = virtual_grf_count;
 194    int first_payload_node = node_count;
 195    node_count += payload_reg_count;
 196    struct ra_graph *g =
 197       ra_alloc_interference_graph(screen->vec4_reg_set.regs, node_count);
 198
 199    for (int i = 0; i < virtual_grf_count; i++) {
 200       int size = this->virtual_grf_sizes[i];
 201       assert(size >= 1 && size <= 2 &&
 202              "Register allocation relies on split_virtual_grfs().");
 203       ra_set_node_class(g, i, screen->vec4_reg_set.classes[size - 1]);
 204
 205       for (int j = 0; j < i; j++) {
 206          if (virtual_grf_interferes(i, j)) {
 207             ra_add_node_interference(g, i, j);
 208          }
 209       }
 210    }
 211
 212    setup_payload_interference(g, first_payload_node, node_count);
 213
 214    if (!ra_allocate_no_spills(g)) {
 215       /* Failed to allocate registers.  Spill a reg, and the caller will
 216        * loop back into here to try again.
 217        */
 218       int reg = choose_spill_reg(g);
 219       if (this->no_spills) {
 220          fail("Failure to register allocate.  Reduce number of live "
 221               "values to avoid this.");
 222       } else if (reg == -1) {
 223          fail("no register to spill\n");
 224       } else {
 225          spill_reg(reg);
 226       }
 227       ralloc_free(g);
 228       return false;
 229    }
 230
 231    /* Get the chosen virtual registers for each node, and map virtual
 232     * regs in the register classes back down to real hardware reg
 233     * numbers.
 234     */
 235    prog_data->total_grf = payload_reg_count;
 236    for (int i = 0; i < virtual_grf_count; i++) {
 237       int reg = ra_get_node_reg(g, i);
 238
 239       hw_reg_mapping[i] = screen->vec4_reg_set.ra_reg_to_grf[reg];
 240       prog_data->total_grf = MAX2(prog_data->total_grf,
 241                                   hw_reg_mapping[i] + virtual_grf_sizes[i]);
 242    }
 243
 244    foreach_list(node, &this->instructions) {
 245       vec4_instruction *inst = (vec4_instruction *)node;
 246
 247       assign(hw_reg_mapping, &inst->dst);
 248       assign(hw_reg_mapping, &inst->src[0]);
 249       assign(hw_reg_mapping, &inst->src[1]);
 250       assign(hw_reg_mapping, &inst->src[2]);
 251    }
 252
 253    ralloc_free(g);
 254
 255    return true;
 256 }
 257
 258 void
 259 vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
 260 {
 261    float loop_scale = 1.0;
 262
 263    for (int i = 0; i < this->virtual_grf_count; i++) {
 264       spill_costs[i] = 0.0;
 265       no_spill[i] = virtual_grf_sizes[i] != 1;
 266    }
 267
 268    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 269     * spill/unspill we'll have to do, and guess that the insides of
 270     * loops run 10 times.
 271     */
 272    foreach_list(node, &this->instructions) {
 273       vec4_instruction *inst = (vec4_instruction *) node;
 274
 275       for (unsigned int i = 0; i < 3; i++) {
 276          if (inst->src[i].file == GRF) {
 277             spill_costs[inst->src[i].reg] += loop_scale;
 278             if (inst->src[i].reladdr)
 279                no_spill[inst->src[i].reg] = true;
 280          }
 281       }
 282
 283       if (inst->dst.file == GRF) {
 284          spill_costs[inst->dst.reg] += loop_scale;
 285          if (inst->dst.reladdr)
 286             no_spill[inst->dst.reg] = true;
 287       }
 288
 289       switch (inst->opcode) {
 290
 291       case BRW_OPCODE_DO:
 292          loop_scale *= 10;
 293          break;
 294
 295       case BRW_OPCODE_WHILE:
 296          loop_scale /= 10;
 297          break;
 298
 299       case SHADER_OPCODE_GEN4_SCRATCH_READ:
 300       case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 301          for (int i = 0; i < 3; i++) {
 302             if (inst->src[i].file == GRF)
 303                no_spill[inst->src[i].reg] = true;
 304          }
 305          if (inst->dst.file == GRF)
 306             no_spill[inst->dst.reg] = true;
 307          break;
 308
 309       default:
 310          break;
 311       }
 312    }
 313 }
 314
 315 int
 316 vec4_visitor::choose_spill_reg(struct ra_graph *g)
 317 {
 318    float spill_costs[this->virtual_grf_count];
 319    bool no_spill[this->virtual_grf_count];
 320
 321    evaluate_spill_costs(spill_costs, no_spill);
 322
 323    for (int i = 0; i < this->virtual_grf_count; i++) {
 324       if (!no_spill[i])
 325          ra_set_node_spill_cost(g, i, spill_costs[i]);
 326    }
 327
 328    return ra_get_best_spill_node(g);
 329 }
 330
 331 void
 332 vec4_visitor::spill_reg(int spill_reg_nr)
 333 {
 334    assert(virtual_grf_sizes[spill_reg_nr] == 1);
 335    unsigned int spill_offset = c->last_scratch++;
 336
 337    /* Generate spill/unspill instructions for the objects being spilled. */
 338    foreach_list(node, &this->instructions) {
 339       vec4_instruction *inst = (vec4_instruction *) node;
 340
 341       for (unsigned int i = 0; i < 3; i++) {
 342          if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
 343             src_reg spill_reg = inst->src[i];
 344             inst->src[i].reg = virtual_grf_alloc(1);
 345             dst_reg temp = dst_reg(inst->src[i]);
 346
 347             /* Only read the necessary channels, to avoid overwriting the rest
 348              * with data that may not have been written to scratch.
 349              */
 350             temp.writemask = 0;
 351             for (int c = 0; c < 4; c++)
 352                temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
 353             assert(temp.writemask != 0);
 354
 355             emit_scratch_read(inst, temp, spill_reg, spill_offset);
 356          }
 357       }
 358
 359       if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
 360          emit_scratch_write(inst, spill_offset);
 361       }
 362    }
 363
 364    invalidate_live_intervals();
 365 }
 366
 367 } /* namespace brw */