src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 extern "C" {
  25 #include "main/macros.h"
  26 #include "program/register_allocate.h"
  27 } /* extern "C" */
  28
  29 #include "brw_vec4.h"
  30 #include "brw_vs.h"
  31
  32 using namespace brw;
  33
  34 namespace brw {
  35
  36 static void
  37 assign(unsigned int *reg_hw_locations, reg *reg)
  38 {
  39    if (reg->file == GRF) {
  40       reg->reg = reg_hw_locations[reg->reg];
  41    }
  42 }
  43
  44 bool
  45 vec4_visitor::reg_allocate_trivial()
  46 {
  47    unsigned int hw_reg_mapping[this->virtual_grf_count];
  48    bool virtual_grf_used[this->virtual_grf_count];
  49    int i;
  50    int next;
  51
  52    /* Calculate which virtual GRFs are actually in use after whatever
  53     * optimization passes have occurred.
  54     */
  55    for (int i = 0; i < this->virtual_grf_count; i++) {
  56       virtual_grf_used[i] = false;
  57    }
  58
  59    foreach_iter(exec_list_iterator, iter, this->instructions) {
  60       vec4_instruction *inst = (vec4_instruction *)iter.get();
  61
  62       if (inst->dst.file == GRF)
  63          virtual_grf_used[inst->dst.reg] = true;
  64
  65       for (int i = 0; i < 3; i++) {
  66          if (inst->src[i].file == GRF)
  67             virtual_grf_used[inst->src[i].reg] = true;
  68       }
  69    }
  70
  71    hw_reg_mapping[0] = this->first_non_payload_grf;
  72    next = hw_reg_mapping[0] + this->virtual_grf_sizes[0];
  73    for (i = 1; i < this->virtual_grf_count; i++) {
  74       if (virtual_grf_used[i]) {
  75          hw_reg_mapping[i] = next;
  76          next += this->virtual_grf_sizes[i];
  77       }
  78    }
  79    prog_data->total_grf = next;
  80
  81    foreach_iter(exec_list_iterator, iter, this->instructions) {
  82       vec4_instruction *inst = (vec4_instruction *)iter.get();
  83
  84       assign(hw_reg_mapping, &inst->dst);
  85       assign(hw_reg_mapping, &inst->src[0]);
  86       assign(hw_reg_mapping, &inst->src[1]);
  87       assign(hw_reg_mapping, &inst->src[2]);
  88    }
  89
  90    if (prog_data->total_grf > max_grf) {
  91       fail("Ran out of regs on trivial allocator (%d/%d)\n",
  92            prog_data->total_grf, max_grf);
  93       return false;
  94    }
  95
  96    return true;
  97 }
  98
  99 extern "C" void
 100 brw_vec4_alloc_reg_set(struct brw_context *brw)
 101 {
 102    int base_reg_count = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 103
 104    /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
 105     * SEND-from-GRF sources cannot be split, so we also need classes for each
 106     * potential message length.
 107     */
 108    const int class_count = 2;
 109    const int class_sizes[class_count] = {1, 2};
 110
 111    /* Compute the total number of registers across all classes. */
 112    int ra_reg_count = 0;
 113    for (int i = 0; i < class_count; i++) {
 114       ra_reg_count += base_reg_count - (class_sizes[i] - 1);
 115    }
 116
 117    ralloc_free(brw->vec4.ra_reg_to_grf);
 118    brw->vec4.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
 119    ralloc_free(brw->vec4.regs);
 120    brw->vec4.regs = ra_alloc_reg_set(brw, ra_reg_count);
 121    if (brw->gen >= 6)
 122       ra_set_allocate_round_robin(brw->vec4.regs);
 123    ralloc_free(brw->vec4.classes);
 124    brw->vec4.classes = ralloc_array(brw, int, class_count + 1);
 125
 126    /* Now, add the registers to their classes, and add the conflicts
 127     * between them and the base GRF registers (and also each other).
 128     */
 129    int reg = 0;
 130    for (int i = 0; i < class_count; i++) {
 131       int class_reg_count = base_reg_count - (class_sizes[i] - 1);
 132       brw->vec4.classes[i] = ra_alloc_reg_class(brw->vec4.regs);
 133
 134       for (int j = 0; j < class_reg_count; j++) {
 135          ra_class_add_reg(brw->vec4.regs, brw->vec4.classes[i], reg);
 136
 137          brw->vec4.ra_reg_to_grf[reg] = j;
 138
 139          for (int base_reg = j;
 140               base_reg < j + class_sizes[i];
 141               base_reg++) {
 142             ra_add_transitive_reg_conflict(brw->vec4.regs, base_reg, reg);
 143          }
 144
 145          reg++;
 146       }
 147    }
 148    assert(reg == ra_reg_count);
 149
 150    ra_set_finalize(brw->vec4.regs, NULL);
 151 }
 152
 153 void
 154 vec4_visitor::setup_payload_interference(struct ra_graph *g,
 155                                          int first_payload_node,
 156                                          int reg_node_count)
 157 {
 158    int payload_node_count = this->first_non_payload_grf;
 159
 160    for (int i = 0; i < payload_node_count; i++) {
 161       /* Mark each payload reg node as being allocated to its physical register.
 162        *
 163        * The alternative would be to have per-physical register classes, which
 164        * would just be silly.
 165        */
 166       ra_set_node_reg(g, first_payload_node + i, i);
 167
 168       /* For now, just mark each payload node as interfering with every other
 169        * node to be allocated.
 170        */
 171       for (int j = 0; j < reg_node_count; j++) {
 172          ra_add_node_interference(g, first_payload_node + i, j);
 173       }
 174    }
 175 }
 176
 177 bool
 178 vec4_visitor::reg_allocate()
 179 {
 180    unsigned int hw_reg_mapping[virtual_grf_count];
 181    int payload_reg_count = this->first_non_payload_grf;
 182
 183    /* Using the trivial allocator can be useful in debugging undefined
 184     * register access as a result of broken optimization passes.
 185     */
 186    if (0)
 187       return reg_allocate_trivial();
 188
 189    calculate_live_intervals();
 190
 191    int node_count = virtual_grf_count;
 192    int first_payload_node = node_count;
 193    node_count += payload_reg_count;
 194    struct ra_graph *g =
 195       ra_alloc_interference_graph(brw->vec4.regs, node_count);
 196
 197    for (int i = 0; i < virtual_grf_count; i++) {
 198       int size = this->virtual_grf_sizes[i];
 199       assert(size >= 1 && size <= 2 &&
 200              "Register allocation relies on split_virtual_grfs().");
 201       ra_set_node_class(g, i, brw->vec4.classes[size - 1]);
 202
 203       for (int j = 0; j < i; j++) {
 204          if (virtual_grf_interferes(i, j)) {
 205             ra_add_node_interference(g, i, j);
 206          }
 207       }
 208    }
 209
 210    setup_payload_interference(g, first_payload_node, node_count);
 211
 212    if (!ra_allocate_no_spills(g)) {
 213       /* Failed to allocate registers.  Spill a reg, and the caller will
 214        * loop back into here to try again.
 215        */
 216       int reg = choose_spill_reg(g);
 217       if (reg == -1) {
 218          fail("no register to spill\n");
 219       } else {
 220          spill_reg(reg);
 221       }
 222       ralloc_free(g);
 223       return false;
 224    }
 225
 226    /* Get the chosen virtual registers for each node, and map virtual
 227     * regs in the register classes back down to real hardware reg
 228     * numbers.
 229     */
 230    prog_data->total_grf = payload_reg_count;
 231    for (int i = 0; i < virtual_grf_count; i++) {
 232       int reg = ra_get_node_reg(g, i);
 233
 234       hw_reg_mapping[i] = brw->vec4.ra_reg_to_grf[reg];
 235       prog_data->total_grf = MAX2(prog_data->total_grf,
 236                                   hw_reg_mapping[i] + virtual_grf_sizes[i]);
 237    }
 238
 239    foreach_list(node, &this->instructions) {
 240       vec4_instruction *inst = (vec4_instruction *)node;
 241
 242       assign(hw_reg_mapping, &inst->dst);
 243       assign(hw_reg_mapping, &inst->src[0]);
 244       assign(hw_reg_mapping, &inst->src[1]);
 245       assign(hw_reg_mapping, &inst->src[2]);
 246    }
 247
 248    ralloc_free(g);
 249
 250    return true;
 251 }
 252
 253 void
 254 vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill)
 255 {
 256    float loop_scale = 1.0;
 257
 258    for (int i = 0; i < this->virtual_grf_count; i++) {
 259       spill_costs[i] = 0.0;
 260       no_spill[i] = virtual_grf_sizes[i] != 1;
 261    }
 262
 263    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 264     * spill/unspill we'll have to do, and guess that the insides of
 265     * loops run 10 times.
 266     */
 267    foreach_list(node, &this->instructions) {
 268       vec4_instruction *inst = (vec4_instruction *) node;
 269
 270       for (unsigned int i = 0; i < 3; i++) {
 271          if (inst->src[i].file == GRF) {
 272             spill_costs[inst->src[i].reg] += loop_scale;
 273             if (inst->src[i].reladdr)
 274                no_spill[inst->src[i].reg] = true;
 275          }
 276       }
 277
 278       if (inst->dst.file == GRF) {
 279          spill_costs[inst->dst.reg] += loop_scale;
 280          if (inst->dst.reladdr)
 281             no_spill[inst->dst.reg] = true;
 282       }
 283
 284       switch (inst->opcode) {
 285
 286       case BRW_OPCODE_DO:
 287          loop_scale *= 10;
 288          break;
 289
 290       case BRW_OPCODE_WHILE:
 291          loop_scale /= 10;
 292          break;
 293
 294       case VS_OPCODE_SCRATCH_READ:
 295       case VS_OPCODE_SCRATCH_WRITE:
 296          for (int i = 0; i < 3; i++) {
 297             if (inst->src[i].file == GRF)
 298                no_spill[inst->src[i].reg] = true;
 299          }
 300          if (inst->dst.file == GRF)
 301             no_spill[inst->dst.reg] = true;
 302          break;
 303
 304       default:
 305          break;
 306       }
 307    }
 308 }
 309
 310 int
 311 vec4_visitor::choose_spill_reg(struct ra_graph *g)
 312 {
 313    float spill_costs[this->virtual_grf_count];
 314    bool no_spill[this->virtual_grf_count];
 315
 316    evaluate_spill_costs(spill_costs, no_spill);
 317
 318    for (int i = 0; i < this->virtual_grf_count; i++) {
 319       if (!no_spill[i])
 320          ra_set_node_spill_cost(g, i, spill_costs[i]);
 321    }
 322
 323    return ra_get_best_spill_node(g);
 324 }
 325
 326 void
 327 vec4_visitor::spill_reg(int spill_reg_nr)
 328 {
 329    assert(virtual_grf_sizes[spill_reg_nr] == 1);
 330    unsigned int spill_offset = c->last_scratch++;
 331
 332    /* Generate spill/unspill instructions for the objects being spilled. */
 333    foreach_list(node, &this->instructions) {
 334       vec4_instruction *inst = (vec4_instruction *) node;
 335
 336       for (unsigned int i = 0; i < 3; i++) {
 337          if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) {
 338             src_reg spill_reg = inst->src[i];
 339             inst->src[i].reg = virtual_grf_alloc(1);
 340             dst_reg temp = dst_reg(inst->src[i]);
 341
 342             /* Only read the necessary channels, to avoid overwriting the rest
 343              * with data that may not have been written to scratch.
 344              */
 345             temp.writemask = 0;
 346             for (int c = 0; c < 4; c++)
 347                temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c));
 348             assert(temp.writemask != 0);
 349
 350             emit_scratch_read(inst, temp, spill_reg, spill_offset);
 351          }
 352       }
 353
 354       if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
 355          emit_scratch_write(inst, spill_offset);
 356       }
 357    }
 358
 359    this->live_intervals_valid = false;
 360 }
 361
 362 } /* namespace brw */