src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32 #include "brw_fs.h"
  33
  34 namespace brw {
  35
  36 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  37                                    void *log_data,
  38                                    const struct brw_tcs_prog_key *key,
  39                                    struct brw_tcs_prog_data *prog_data,
  40                                    const nir_shader *nir,
  41                                    void *mem_ctx,
  42                                    int shader_time_index,
  43                                    const struct brw_vue_map *input_vue_map)
  44    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  45                   nir, mem_ctx, false, shader_time_index),
  46      input_vue_map(input_vue_map), key(key)
  47 {
  48 }
  49
  50
  51 void
  52 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
  53 {
  54 }
  55
  56 dst_reg *
  57 vec4_tcs_visitor::make_reg_for_system_value(int location)
  58 {
  59    return NULL;
  60 }
  61
  62
  63 void
  64 vec4_tcs_visitor::setup_payload()
  65 {
  66    int reg = 0;
  67
  68    /* The payload always contains important data in r0, which contains
  69     * the URB handles that are passed on to the URB write at the end
  70     * of the thread.
  71     */
  72    reg++;
  73
  74    /* r1.0 - r4.7 may contain the input control point URB handles,
  75     * which we use to pull vertex data.
  76     */
  77    reg += 4;
  78
  79    /* Push constants may start at r5.0 */
  80    reg = setup_uniforms(reg);
  81
  82    this->first_non_payload_grf = reg;
  83 }
  84
  85
  86 void
  87 vec4_tcs_visitor::emit_prolog()
  88 {
  89    invocation_id = src_reg(this, glsl_type::uint_type);
  90    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
  91
  92    /* HS threads are dispatched with the dispatch mask set to 0xFF.
  93     * If there are an odd number of output vertices, then the final
  94     * HS instance dispatched will only have its bottom half doing real
  95     * work, and so we need to disable the upper half:
  96     */
  97    if (nir->info->tess.tcs_vertices_out % 2) {
  98       emit(CMP(dst_null_d(), invocation_id,
  99                brw_imm_ud(nir->info->tess.tcs_vertices_out),
 100                BRW_CONDITIONAL_L));
 101
 102       /* Matching ENDIF is in emit_thread_end() */
 103       emit(IF(BRW_PREDICATE_NORMAL));
 104    }
 105 }
 106
 107
 108 void
 109 vec4_tcs_visitor::emit_thread_end()
 110 {
 111    vec4_instruction *inst;
 112    current_annotation = "thread end";
 113
 114    if (nir->info->tess.tcs_vertices_out % 2) {
 115       emit(BRW_OPCODE_ENDIF);
 116    }
 117
 118    if (devinfo->gen == 7) {
 119       struct brw_tcs_prog_data *tcs_prog_data =
 120          (struct brw_tcs_prog_data *) prog_data;
 121
 122       current_annotation = "release input vertices";
 123
 124       /* Synchronize all threads, so we know that no one is still
 125        * using the input URB handles.
 126        */
 127       if (tcs_prog_data->instances > 1) {
 128          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 129          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 130          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 131       }
 132
 133       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 134        * We want to compare the bottom half of invocation_id with 0, but
 135        * use that truth value for the top half as well.  Unfortunately,
 136        * we don't have stride in the vec4 world, nor UV immediates in
 137        * align16, so we need an opcode to get invocation_id<0,4,0>.
 138        */
 139       set_condmod(BRW_CONDITIONAL_Z,
 140                   emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
 141                        invocation_id));
 142       emit(IF(BRW_PREDICATE_NORMAL));
 143       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 144          /* If we have an odd number of input vertices, the last will be
 145           * unpaired.  We don't want to use an interleaved URB write in
 146           * that case.
 147           */
 148          const bool is_unpaired = i == key->input_vertices - 1;
 149
 150          dst_reg header(this, glsl_type::uvec4_type);
 151          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 152               brw_imm_ud(is_unpaired));
 153       }
 154       emit(BRW_OPCODE_ENDIF);
 155    }
 156
 157    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 158       emit_shader_time_end();
 159
 160    inst = emit(TCS_OPCODE_THREAD_END);
 161    inst->base_mrf = 14;
 162    inst->mlen = 2;
 163 }
 164
 165
 166 void
 167 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 168                                       const src_reg &vertex_index,
 169                                       unsigned base_offset,
 170                                       unsigned first_component,
 171                                       const src_reg &indirect_offset)
 172 {
 173    vec4_instruction *inst;
 174    dst_reg temp(this, glsl_type::ivec4_type);
 175    temp.type = dst.type;
 176
 177    /* Set up the message header to reference the proper parts of the URB */
 178    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 179    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 180                indirect_offset);
 181    inst->force_writemask_all = true;
 182
 183    /* Read into a temporary, ignoring writemasking. */
 184    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 185    inst->offset = base_offset;
 186    inst->mlen = 1;
 187    inst->base_mrf = -1;
 188
 189    /* Copy the temporary to the destination to deal with writemasking.
 190     *
 191     * Also attempt to deal with gl_PointSize being in the .w component.
 192     */
 193    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 194       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 195    } else {
 196       src_reg src = src_reg(temp);
 197       src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
 198       emit(MOV(dst, src));
 199    }
 200 }
 201
 202 void
 203 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 204                                        unsigned base_offset,
 205                                        unsigned first_component,
 206                                        const src_reg &indirect_offset)
 207 {
 208    vec4_instruction *inst;
 209
 210    /* Set up the message header to reference the proper parts of the URB */
 211    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 212    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 213                brw_imm_ud(dst.writemask << first_component), indirect_offset);
 214    inst->force_writemask_all = true;
 215
 216    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 217    read->offset = base_offset;
 218    read->mlen = 1;
 219    read->base_mrf = -1;
 220
 221    if (first_component) {
 222       /* Read into a temporary and copy with a swizzle and writemask. */
 223       read->dst = retype(dst_reg(this, glsl_type::ivec4_type), dst.type);
 224       emit(MOV(dst, swizzle(src_reg(read->dst),
 225                             BRW_SWZ_COMP_INPUT(first_component))));
 226    }
 227 }
 228
 229 void
 230 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 231                                  unsigned writemask,
 232                                  unsigned base_offset,
 233                                  const src_reg &indirect_offset)
 234 {
 235    if (writemask == 0)
 236       return;
 237
 238    src_reg message(this, glsl_type::uvec4_type, 2);
 239    vec4_instruction *inst;
 240
 241    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 242                brw_imm_ud(writemask), indirect_offset);
 243    inst->force_writemask_all = true;
 244    inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE),
 245                    value));
 246    inst->force_writemask_all = true;
 247
 248    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 249    inst->offset = base_offset;
 250    inst->mlen = 2;
 251    inst->base_mrf = -1;
 252 }
 253
 254 void
 255 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 256 {
 257    switch (instr->intrinsic) {
 258    case nir_intrinsic_load_invocation_id:
 259       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 260                invocation_id));
 261       break;
 262    case nir_intrinsic_load_primitive_id:
 263       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 264            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 265       break;
 266    case nir_intrinsic_load_patch_vertices_in:
 267       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 268                brw_imm_d(key->input_vertices)));
 269       break;
 270    case nir_intrinsic_load_per_vertex_input: {
 271       src_reg indirect_offset = get_indirect_offset(instr);
 272       unsigned imm_offset = instr->const_index[0];
 273
 274       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 275       src_reg vertex_index =
 276          vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
 277                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 278
 279       unsigned first_component = nir_intrinsic_component(instr);
 280       if (nir_dest_bit_size(instr->dest) == 64) {
 281          /* We need to emit up to two 32-bit URB reads, then shuffle
 282           * the result into a temporary, then move to the destination
 283           * honoring the writemask
 284           *
 285           * We don't need to divide first_component by 2 because
 286           * emit_input_urb_read takes a 32-bit type.
 287           */
 288          dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
 289          dst_reg tmp_d = retype(tmp, BRW_REGISTER_TYPE_D);
 290          emit_input_urb_read(tmp_d, vertex_index, imm_offset,
 291                              first_component, indirect_offset);
 292          if (instr->num_components > 2) {
 293             emit_input_urb_read(byte_offset(tmp_d, REG_SIZE), vertex_index,
 294                                 imm_offset + 1, 0, indirect_offset);
 295          }
 296
 297          src_reg tmp_src = retype(src_reg(tmp_d), BRW_REGISTER_TYPE_DF);
 298          dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
 299          shuffle_64bit_data(shuffled, tmp_src, false);
 300
 301          dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF);
 302          dst.writemask = brw_writemask_for_size(instr->num_components);
 303          emit(MOV(dst, src_reg(shuffled)));
 304       } else {
 305          dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 306          dst.writemask = brw_writemask_for_size(instr->num_components);
 307          emit_input_urb_read(dst, vertex_index, imm_offset,
 308                              first_component, indirect_offset);
 309       }
 310       break;
 311    }
 312    case nir_intrinsic_load_input:
 313       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 314       break;
 315    case nir_intrinsic_load_output:
 316    case nir_intrinsic_load_per_vertex_output: {
 317       src_reg indirect_offset = get_indirect_offset(instr);
 318       unsigned imm_offset = instr->const_index[0];
 319
 320       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 321       dst.writemask = brw_writemask_for_size(instr->num_components);
 322
 323       emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr),
 324                            indirect_offset);
 325       break;
 326    }
 327    case nir_intrinsic_store_output:
 328    case nir_intrinsic_store_per_vertex_output: {
 329       src_reg value = get_nir_src(instr->src[0]);
 330       unsigned mask = instr->const_index[1];
 331       unsigned swiz = BRW_SWIZZLE_XYZW;
 332
 333       src_reg indirect_offset = get_indirect_offset(instr);
 334       unsigned imm_offset = instr->const_index[0];
 335
 336       unsigned first_component = nir_intrinsic_component(instr);
 337       if (first_component) {
 338          if (nir_src_bit_size(instr->src[0]) == 64)
 339             first_component /= 2;
 340          assert(swiz == BRW_SWIZZLE_XYZW);
 341          swiz = BRW_SWZ_COMP_OUTPUT(first_component);
 342          mask = mask << first_component;
 343       }
 344
 345       if (nir_src_bit_size(instr->src[0]) == 64) {
 346          /* For 64-bit data we need to shuffle the data before we write and
 347           * emit two messages. Also, since each channel is twice as large we
 348           * need to fix the writemask in each 32-bit message to account for it.
 349           */
 350          value = swizzle(retype(value, BRW_REGISTER_TYPE_DF), swiz);
 351          dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type);
 352          shuffle_64bit_data(shuffled, value, true);
 353          src_reg shuffled_float = src_reg(retype(shuffled, BRW_REGISTER_TYPE_F));
 354
 355          for (int n = 0; n < 2; n++) {
 356             unsigned fixed_mask = 0;
 357             if (mask & WRITEMASK_X)
 358                fixed_mask |= WRITEMASK_XY;
 359             if (mask & WRITEMASK_Y)
 360                fixed_mask |= WRITEMASK_ZW;
 361             emit_urb_write(shuffled_float, fixed_mask,
 362                            imm_offset, indirect_offset);
 363
 364             shuffled_float = byte_offset(shuffled_float, REG_SIZE);
 365             mask >>= 2;
 366             imm_offset++;
 367          }
 368       } else {
 369          emit_urb_write(swizzle(value, swiz), mask,
 370                         imm_offset, indirect_offset);
 371       }
 372       break;
 373    }
 374
 375    case nir_intrinsic_barrier: {
 376       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 377       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 378       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 379       break;
 380    }
 381
 382    default:
 383       vec4_visitor::nir_emit_intrinsic(instr);
 384    }
 385 }
 386
 387
 388 extern "C" const unsigned *
 389 brw_compile_tcs(const struct brw_compiler *compiler,
 390                 void *log_data,
 391                 void *mem_ctx,
 392                 const struct brw_tcs_prog_key *key,
 393                 struct brw_tcs_prog_data *prog_data,
 394                 const nir_shader *src_shader,
 395                 int shader_time_index,
 396                 unsigned *final_assembly_size,
 397                 char **error_str)
 398 {
 399    const struct gen_device_info *devinfo = compiler->devinfo;
 400    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 401    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 402
 403    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 404    nir->info->outputs_written = key->outputs_written;
 405    nir->info->patch_outputs_written = key->patch_outputs_written;
 406
 407    struct brw_vue_map input_vue_map;
 408    brw_compute_vue_map(devinfo, &input_vue_map, nir->info->inputs_read,
 409                        nir->info->separate_shader);
 410    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 411                             nir->info->outputs_written,
 412                             nir->info->patch_outputs_written);
 413
 414    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
 415    brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
 416    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
 417                              key->tes_primitive_mode);
 418    if (key->quads_workaround)
 419       brw_nir_apply_tcs_quads_workaround(nir);
 420
 421    nir = brw_postprocess_nir(nir, compiler, is_scalar);
 422
 423    if (is_scalar)
 424       prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 8);
 425    else
 426       prog_data->instances = DIV_ROUND_UP(nir->info->tess.tcs_vertices_out, 2);
 427
 428    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 429     * That divides up as follows:
 430     *
 431     *     32 bytes for the patch header (tessellation factors)
 432     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 433     *              gl_MaxTessPatchComponents = 120)
 434     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 435     *              gl_MaxPatchVertices = 32 and
 436     *              gl_MaxTessControlOutputComponents = 128)
 437     *
 438     *  15808 bytes left for varying packing overhead
 439     */
 440    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 441    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 442    unsigned output_size_bytes = 0;
 443    /* Note that the patch header is counted in num_per_patch_slots. */
 444    output_size_bytes += num_per_patch_slots * 16;
 445    output_size_bytes += nir->info->tess.tcs_vertices_out *
 446                         num_per_vertex_slots * 16;
 447
 448    assert(output_size_bytes >= 1);
 449    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 450       return NULL;
 451
 452    /* URB entry sizes are stored as a multiple of 64 bytes. */
 453    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 454
 455    /* HS does not use the usual payload pushing from URB to GRFs,
 456     * because we don't have enough registers for a full-size payload, and
 457     * the hardware is broken on Haswell anyway.
 458     */
 459    vue_prog_data->urb_read_length = 0;
 460
 461    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 462       fprintf(stderr, "TCS Input ");
 463       brw_print_vue_map(stderr, &input_vue_map);
 464       fprintf(stderr, "TCS Output ");
 465       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 466    }
 467
 468    if (is_scalar) {
 469       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
 470                    &prog_data->base.base, NULL, nir, 8,
 471                    shader_time_index, &input_vue_map);
 472       if (!v.run_tcs_single_patch()) {
 473          if (error_str)
 474             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 475          return NULL;
 476       }
 477
 478       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
 479       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
 480
 481       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
 482                      &prog_data->base.base, v.promoted_constants, false,
 483                      MESA_SHADER_TESS_CTRL);
 484       if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 485          g.enable_debug(ralloc_asprintf(mem_ctx,
 486                                         "%s tessellation control shader %s",
 487                                         nir->info->label ? nir->info->label
 488                                                         : "unnamed",
 489                                         nir->info->name));
 490       }
 491
 492       g.generate_code(v.cfg, 8);
 493
 494       return g.get_assembly(final_assembly_size);
 495    } else {
 496       vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 497                          nir, mem_ctx, shader_time_index, &input_vue_map);
 498       if (!v.run()) {
 499          if (error_str)
 500             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 501          return NULL;
 502       }
 503
 504       if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 505          v.dump_instructions();
 506
 507
 508       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 509                                         &prog_data->base, v.cfg,
 510                                         final_assembly_size);
 511    }
 512 }
 513
 514
 515 } /* namespace brw */