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25 * \file brw_vec4_tcs.cpp
27 * Tessellaton control shader specific code derived from the vec4_visitor class.
31 #include "brw_vec4_tcs.h"
35 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler
*compiler
,
37 const struct brw_tcs_prog_key
*key
,
38 struct brw_tcs_prog_data
*prog_data
,
39 const nir_shader
*nir
,
41 int shader_time_index
,
42 const struct brw_vue_map
*input_vue_map
)
43 : vec4_visitor(compiler
, log_data
, &key
->tex
, &prog_data
->base
,
44 nir
, mem_ctx
, false, shader_time_index
),
45 input_vue_map(input_vue_map
), key(key
)
51 vec4_tcs_visitor::emit_nir_code()
53 if (key
->program_string_id
!= 0) {
54 /* We have a real application-supplied TCS, emit real code. */
55 vec4_visitor::emit_nir_code();
57 /* There is no TCS; automatically generate a passthrough shader
58 * that writes the API-specified default tessellation levels and
59 * copies VS outputs to TES inputs.
65 uint64_t varyings
= key
->outputs_written
;
67 src_reg
vertex_offset(this, glsl_type::uint_type
);
68 emit(MUL(dst_reg(vertex_offset
), invocation_id
,
69 brw_imm_ud(prog_data
->vue_map
.num_per_vertex_slots
)));
71 while (varyings
!= 0) {
72 const int varying
= ffsll(varyings
) - 1;
74 unsigned in_offset
= input_vue_map
->varying_to_slot
[varying
];
75 unsigned out_offset
= prog_data
->vue_map
.varying_to_slot
[varying
];
76 assert(out_offset
>= 2);
78 dst_reg
val(this, glsl_type::vec4_type
);
79 emit_input_urb_read(val
, invocation_id
, in_offset
, src_reg());
80 emit_urb_write(src_reg(val
), WRITEMASK_XYZW
, out_offset
,
83 varyings
&= ~BITFIELD64_BIT(varying
);
86 /* Only write the tessellation factors from invocation 0.
87 * There's no point in making other threads do redundant work.
89 emit(CMP(dst_null_d(), invocation_id
, brw_imm_ud(0),
91 emit(IF(BRW_PREDICATE_NORMAL
));
92 emit_urb_write(src_reg(UNIFORM
, 0, glsl_type::vec4_type
),
93 WRITEMASK_XYZW
, 0, src_reg());
94 emit_urb_write(src_reg(UNIFORM
, 1, glsl_type::vec4_type
),
95 WRITEMASK_XYZW
, 1, src_reg());
96 emit(BRW_OPCODE_ENDIF
);
101 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
106 vec4_tcs_visitor::make_reg_for_system_value(int location
, const glsl_type
*type
)
113 vec4_tcs_visitor::setup_payload()
117 /* The payload always contains important data in r0, which contains
118 * the URB handles that are passed on to the URB write at the end
123 /* r1.0 - r4.7 may contain the input control point URB handles,
124 * which we use to pull vertex data.
128 /* Push constants may start at r5.0 */
129 reg
= setup_uniforms(reg
);
131 this->first_non_payload_grf
= reg
;
136 vec4_tcs_visitor::emit_prolog()
138 invocation_id
= src_reg(this, glsl_type::uint_type
);
139 emit(TCS_OPCODE_GET_INSTANCE_ID
, dst_reg(invocation_id
));
141 /* HS threads are dispatched with the dispatch mask set to 0xFF.
142 * If there are an odd number of output vertices, then the final
143 * HS instance dispatched will only have its bottom half doing real
144 * work, and so we need to disable the upper half:
146 if (nir
->info
.tcs
.vertices_out
% 2) {
147 emit(CMP(dst_null_d(), invocation_id
,
148 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
));
150 /* Matching ENDIF is in emit_thread_end() */
151 emit(IF(BRW_PREDICATE_NORMAL
));
157 vec4_tcs_visitor::emit_thread_end()
159 current_annotation
= "thread end";
161 if (nir
->info
.tcs
.vertices_out
% 2) {
162 emit(BRW_OPCODE_ENDIF
);
165 if (unlikely(INTEL_DEBUG
& DEBUG_SHADER_TIME
))
166 emit_shader_time_end();
168 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
169 inst
->mlen
= 1; /* just the header, no data. */
170 inst
->urb_write_flags
= BRW_URB_WRITE_EOT_COMPLETE
;
175 vec4_tcs_visitor::emit_input_urb_read(const dst_reg
&dst
,
176 const src_reg
&vertex_index
,
177 unsigned base_offset
,
178 const src_reg
&indirect_offset
)
180 vec4_instruction
*inst
;
181 dst_reg
temp(this, glsl_type::ivec4_type
);
182 temp
.type
= dst
.type
;
184 /* Set up the message header to reference the proper parts of the URB */
185 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
186 inst
= emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS
, header
, vertex_index
,
188 inst
->force_writemask_all
= true;
190 /* Read into a temporary, ignoring writemasking. */
191 inst
= emit(VEC4_OPCODE_URB_READ
, temp
, src_reg(header
));
192 inst
->offset
= base_offset
;
196 /* Copy the temporary to the destination to deal with writemasking.
198 * Also attempt to deal with gl_PointSize being in the .w component.
200 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
201 emit(MOV(dst
, swizzle(src_reg(temp
), BRW_SWIZZLE_WWWW
)));
203 emit(MOV(dst
, src_reg(temp
)));
208 vec4_tcs_visitor::emit_output_urb_read(const dst_reg
&dst
,
209 unsigned base_offset
,
210 const src_reg
&indirect_offset
)
212 vec4_instruction
*inst
;
214 /* Set up the message header to reference the proper parts of the URB */
215 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
216 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, header
,
217 brw_imm_ud(dst
.writemask
), indirect_offset
);
218 inst
->force_writemask_all
= true;
220 /* Read into a temporary, ignoring writemasking. */
221 vec4_instruction
*read
= emit(VEC4_OPCODE_URB_READ
, dst
, src_reg(header
));
222 read
->offset
= base_offset
;
228 vec4_tcs_visitor::emit_urb_write(const src_reg
&value
,
230 unsigned base_offset
,
231 const src_reg
&indirect_offset
)
236 src_reg
message(this, glsl_type::uvec4_type
, 2);
237 vec4_instruction
*inst
;
239 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, dst_reg(message
),
240 brw_imm_ud(writemask
), indirect_offset
);
241 inst
->force_writemask_all
= true;
242 inst
= emit(MOV(offset(dst_reg(retype(message
, value
.type
)), 1), value
));
243 inst
->force_writemask_all
= true;
245 inst
= emit(TCS_OPCODE_URB_WRITE
, dst_null_f(), message
);
246 inst
->offset
= base_offset
;
252 tesslevel_outer_components(GLenum tes_primitive_mode
)
254 switch (tes_primitive_mode
) {
262 unreachable("Bogus tessellation domain");
268 tesslevel_inner_components(GLenum tes_primitive_mode
)
270 switch (tes_primitive_mode
) {
278 unreachable("Bogus tessellation domain");
284 * Given a normal .xyzw writemask, convert it to a writemask for a vector
285 * that's stored backwards, i.e. .wzyx.
288 writemask_for_backwards_vector(unsigned mask
)
290 unsigned new_mask
= 0;
292 for (int i
= 0; i
< 4; i
++)
293 new_mask
|= ((mask
>> i
) & 1) << (3 - i
);
299 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
301 switch (instr
->intrinsic
) {
302 case nir_intrinsic_load_invocation_id
:
303 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
),
306 case nir_intrinsic_load_primitive_id
:
307 emit(TCS_OPCODE_GET_PRIMITIVE_ID
,
308 get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
));
310 case nir_intrinsic_load_patch_vertices_in
:
311 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
),
312 brw_imm_d(key
->input_vertices
)));
314 case nir_intrinsic_load_per_vertex_input
: {
315 src_reg indirect_offset
= get_indirect_offset(instr
);
316 unsigned imm_offset
= instr
->const_index
[0];
318 nir_const_value
*vertex_const
= nir_src_as_const_value(instr
->src
[0]);
319 src_reg vertex_index
=
320 vertex_const
? src_reg(brw_imm_ud(vertex_const
->u
[0]))
321 : get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
323 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
324 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
326 emit_input_urb_read(dst
, vertex_index
, imm_offset
, indirect_offset
);
329 case nir_intrinsic_load_input
:
330 unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
332 case nir_intrinsic_load_output
:
333 case nir_intrinsic_load_per_vertex_output
: {
334 src_reg indirect_offset
= get_indirect_offset(instr
);
335 unsigned imm_offset
= instr
->const_index
[0];;
337 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
338 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
340 if (imm_offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
341 dst
.type
= BRW_REGISTER_TYPE_F
;
343 /* This is a read of gl_TessLevelInner[], which lives in the
344 * Patch URB header. The layout depends on the domain.
346 switch (key
->tes_primitive_mode
) {
348 /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
349 dst_reg
tmp(this, glsl_type::vec4_type
);
350 emit_output_urb_read(tmp
, 0, src_reg());
351 emit(MOV(writemask(dst
, WRITEMASK_XY
),
352 swizzle(src_reg(tmp
), BRW_SWIZZLE_WZYX
)));
356 /* DWord 4; use offset 1 but normal swizzle/writemask. */
357 emit_output_urb_read(writemask(dst
, WRITEMASK_X
), 1, src_reg());
360 /* All channels are undefined. */
363 unreachable("Bogus tessellation domain");
365 } else if (imm_offset
== 1 && indirect_offset
.file
== BAD_FILE
) {
366 dst
.type
= BRW_REGISTER_TYPE_F
;
368 /* This is a read of gl_TessLevelOuter[], which lives in the
369 * high 4 DWords of the Patch URB header, in reverse order.
371 switch (key
->tes_primitive_mode
) {
373 dst
.writemask
= WRITEMASK_XYZW
;
376 dst
.writemask
= WRITEMASK_XYZ
;
379 dst
.writemask
= WRITEMASK_XY
;
382 unreachable("Bogus tessellation domain");
385 dst_reg
tmp(this, glsl_type::vec4_type
);
386 emit_output_urb_read(tmp
, 1, src_reg());
387 emit(MOV(dst
, swizzle(src_reg(tmp
), BRW_SWIZZLE_WZYX
)));
389 emit_output_urb_read(dst
, imm_offset
, indirect_offset
);
393 case nir_intrinsic_store_output
:
394 case nir_intrinsic_store_per_vertex_output
: {
395 src_reg value
= get_nir_src(instr
->src
[0]);
396 unsigned mask
= instr
->const_index
[1];
397 unsigned swiz
= BRW_SWIZZLE_XYZW
;
399 src_reg indirect_offset
= get_indirect_offset(instr
);
400 unsigned imm_offset
= instr
->const_index
[0];
402 if (imm_offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
403 value
.type
= BRW_REGISTER_TYPE_F
;
405 mask
&= (1 << tesslevel_inner_components(key
->tes_primitive_mode
)) - 1;
407 /* This is a write to gl_TessLevelInner[], which lives in the
408 * Patch URB header. The layout depends on the domain.
410 switch (key
->tes_primitive_mode
) {
412 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
413 * We use an XXYX swizzle to reverse put .xy in the .wz
414 * channels, and use a .zw writemask.
416 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
417 mask
= writemask_for_backwards_vector(mask
);
420 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
421 * writemask to X and bump the URB offset by 1.
426 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
429 unreachable("Bogus tessellation domain");
431 } else if (imm_offset
== 1 && indirect_offset
.file
== BAD_FILE
) {
432 value
.type
= BRW_REGISTER_TYPE_F
;
434 mask
&= (1 << tesslevel_outer_components(key
->tes_primitive_mode
)) - 1;
436 /* This is a write to gl_TessLevelOuter[] which lives in the
437 * Patch URB Header at DWords 4-7. However, it's reversed, so
438 * instead of .xyzw we have .wzyx.
440 swiz
= BRW_SWIZZLE_WZYX
;
441 mask
= writemask_for_backwards_vector(mask
);
444 emit_urb_write(swizzle(value
, swiz
), mask
,
445 imm_offset
, indirect_offset
);
449 case nir_intrinsic_barrier
: {
450 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
451 emit(TCS_OPCODE_CREATE_BARRIER_HEADER
, header
);
452 emit(SHADER_OPCODE_BARRIER
, dst_null_ud(), src_reg(header
));
457 vec4_visitor::nir_emit_intrinsic(instr
);
462 extern "C" const unsigned *
463 brw_compile_tcs(const struct brw_compiler
*compiler
,
466 const struct brw_tcs_prog_key
*key
,
467 struct brw_tcs_prog_data
*prog_data
,
468 const nir_shader
*src_shader
,
469 int shader_time_index
,
470 unsigned *final_assembly_size
,
473 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
474 struct brw_vue_prog_data
*vue_prog_data
= &prog_data
->base
;
475 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
];
477 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
478 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
479 nir
->info
.outputs_written
= key
->outputs_written
;
480 nir
->info
.patch_outputs_written
= key
->patch_outputs_written
;
481 nir
= brw_nir_lower_io(nir
, compiler
->devinfo
, is_scalar
);
482 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
484 prog_data
->instances
= DIV_ROUND_UP(nir
->info
.tcs
.vertices_out
, 2);
486 brw_compute_tess_vue_map(&vue_prog_data
->vue_map
,
487 nir
->info
.outputs_written
,
488 nir
->info
.patch_outputs_written
);
490 /* Compute URB entry size. The maximum allowed URB entry size is 32k.
491 * That divides up as follows:
493 * 32 bytes for the patch header (tessellation factors)
494 * 480 bytes for per-patch varyings (a varying component is 4 bytes and
495 * gl_MaxTessPatchComponents = 120)
496 * 16384 bytes for per-vertex varyings (a varying component is 4 bytes,
497 * gl_MaxPatchVertices = 32 and
498 * gl_MaxTessControlOutputComponents = 128)
500 * 15808 bytes left for varying packing overhead
502 const int num_per_patch_slots
= vue_prog_data
->vue_map
.num_per_patch_slots
;
503 const int num_per_vertex_slots
= vue_prog_data
->vue_map
.num_per_vertex_slots
;
504 unsigned output_size_bytes
= 0;
505 /* Note that the patch header is counted in num_per_patch_slots. */
506 output_size_bytes
+= num_per_patch_slots
* 16;
507 output_size_bytes
+= nir
->info
.tcs
.vertices_out
* num_per_vertex_slots
* 16;
509 assert(output_size_bytes
>= 1);
510 if (output_size_bytes
> GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES
)
513 /* URB entry sizes are stored as a multiple of 64 bytes. */
514 vue_prog_data
->urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
516 struct brw_vue_map input_vue_map
;
517 brw_compute_vue_map(devinfo
, &input_vue_map
,
518 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
521 /* HS does not use the usual payload pushing from URB to GRFs,
522 * because we don't have enough registers for a full-size payload, and
523 * the hardware is broken on Haswell anyway.
525 vue_prog_data
->urb_read_length
= 0;
527 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
)) {
528 fprintf(stderr
, "TCS Input ");
529 brw_print_vue_map(stderr
, &input_vue_map
);
530 fprintf(stderr
, "TCS Output ");
531 brw_print_vue_map(stderr
, &vue_prog_data
->vue_map
);
534 vec4_tcs_visitor
v(compiler
, log_data
, key
, prog_data
,
535 nir
, mem_ctx
, shader_time_index
, &input_vue_map
);
538 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
542 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
))
543 v
.dump_instructions();
545 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
546 &prog_data
->base
, v
.cfg
,
547 final_assembly_size
);
551 } /* namespace brw */