2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * \file brw_vec4_tcs.cpp
27 * Tessellaton control shader specific code derived from the vec4_visitor class.
31 #include "brw_vec4_tcs.h"
35 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler
*compiler
,
37 const struct brw_tcs_prog_key
*key
,
38 struct brw_tcs_prog_data
*prog_data
,
39 const nir_shader
*nir
,
41 int shader_time_index
,
42 const struct brw_vue_map
*input_vue_map
)
43 : vec4_visitor(compiler
, log_data
, &key
->tex
, &prog_data
->base
,
44 nir
, mem_ctx
, false, shader_time_index
),
45 input_vue_map(input_vue_map
), key(key
)
51 vec4_tcs_visitor::emit_nir_code()
53 if (key
->program_string_id
!= 0) {
54 /* We have a real application-supplied TCS, emit real code. */
55 vec4_visitor::emit_nir_code();
57 /* There is no TCS; automatically generate a passthrough shader
58 * that writes the API-specified default tessellation levels and
59 * copies VS outputs to TES inputs.
65 uint64_t varyings
= key
->outputs_written
;
67 src_reg
vertex_offset(this, glsl_type::uint_type
);
68 emit(MUL(dst_reg(vertex_offset
), invocation_id
,
69 brw_imm_ud(prog_data
->vue_map
.num_per_vertex_slots
)));
71 while (varyings
!= 0) {
72 const int varying
= ffsll(varyings
) - 1;
74 unsigned in_offset
= input_vue_map
->varying_to_slot
[varying
];
75 unsigned out_offset
= prog_data
->vue_map
.varying_to_slot
[varying
];
76 assert(out_offset
>= 2);
78 dst_reg
val(this, glsl_type::vec4_type
);
79 emit_input_urb_read(val
, invocation_id
, in_offset
, src_reg());
80 emit_urb_write(src_reg(val
), WRITEMASK_XYZW
, out_offset
,
83 varyings
&= ~BITFIELD64_BIT(varying
);
86 /* Only write the tessellation factors from invocation 0.
87 * There's no point in making other threads do redundant work.
89 emit(CMP(dst_null_d(), invocation_id
, brw_imm_ud(0),
91 emit(IF(BRW_PREDICATE_NORMAL
));
92 emit_urb_write(src_reg(UNIFORM
, 0, glsl_type::vec4_type
),
93 WRITEMASK_XYZW
, 0, src_reg());
94 emit_urb_write(src_reg(UNIFORM
, 1, glsl_type::vec4_type
),
95 WRITEMASK_XYZW
, 1, src_reg());
96 emit(BRW_OPCODE_ENDIF
);
101 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
106 vec4_tcs_visitor::make_reg_for_system_value(int location
, const glsl_type
*type
)
113 vec4_tcs_visitor::setup_payload()
117 /* The payload always contains important data in r0, which contains
118 * the URB handles that are passed on to the URB write at the end
123 /* r1.0 - r4.7 may contain the input control point URB handles,
124 * which we use to pull vertex data.
128 /* Push constants may start at r5.0 */
129 reg
= setup_uniforms(reg
);
131 this->first_non_payload_grf
= reg
;
136 vec4_tcs_visitor::emit_prolog()
138 invocation_id
= src_reg(this, glsl_type::uint_type
);
139 emit(TCS_OPCODE_GET_INSTANCE_ID
, dst_reg(invocation_id
));
141 /* HS threads are dispatched with the dispatch mask set to 0xFF.
142 * If there are an odd number of output vertices, then the final
143 * HS instance dispatched will only have its bottom half doing real
144 * work, and so we need to disable the upper half:
146 if (nir
->info
.tcs
.vertices_out
% 2) {
147 emit(CMP(dst_null_d(), invocation_id
,
148 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
));
150 /* Matching ENDIF is in emit_thread_end() */
151 emit(IF(BRW_PREDICATE_NORMAL
));
157 vec4_tcs_visitor::emit_thread_end()
159 vec4_instruction
*inst
;
160 current_annotation
= "thread end";
162 if (nir
->info
.tcs
.vertices_out
% 2) {
163 emit(BRW_OPCODE_ENDIF
);
166 if (devinfo
->gen
== 7) {
167 struct brw_tcs_prog_data
*tcs_prog_data
=
168 (struct brw_tcs_prog_data
*) prog_data
;
170 current_annotation
= "release input vertices";
172 /* Synchronize all threads, so we know that no one is still
173 * using the input URB handles.
175 if (tcs_prog_data
->instances
> 1) {
176 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
177 emit(TCS_OPCODE_CREATE_BARRIER_HEADER
, header
);
178 emit(SHADER_OPCODE_BARRIER
, dst_null_ud(), src_reg(header
));
181 /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
182 * We want to compare the bottom half of invocation_id with 0, but
183 * use that truth value for the top half as well. Unfortunately,
184 * we don't have stride in the vec4 world, nor UV immediates in
185 * align16, so we need an opcode to get invocation_id<0,4,0>.
187 set_condmod(BRW_CONDITIONAL_Z
,
188 emit(TCS_OPCODE_SRC0_010_IS_ZERO
, dst_null_d(),
190 emit(IF(BRW_PREDICATE_NORMAL
));
191 for (unsigned i
= 0; i
< key
->input_vertices
; i
+= 2) {
192 /* If we have an odd number of input vertices, the last will be
193 * unpaired. We don't want to use an interleaved URB write in
196 const bool is_unpaired
= i
== key
->input_vertices
- 1;
198 dst_reg
header(this, glsl_type::uvec4_type
);
199 emit(TCS_OPCODE_RELEASE_INPUT
, header
, brw_imm_ud(i
),
200 brw_imm_ud(is_unpaired
));
202 emit(BRW_OPCODE_ENDIF
);
205 if (unlikely(INTEL_DEBUG
& DEBUG_SHADER_TIME
))
206 emit_shader_time_end();
208 inst
= emit(TCS_OPCODE_THREAD_END
);
215 vec4_tcs_visitor::emit_input_urb_read(const dst_reg
&dst
,
216 const src_reg
&vertex_index
,
217 unsigned base_offset
,
218 const src_reg
&indirect_offset
)
220 vec4_instruction
*inst
;
221 dst_reg
temp(this, glsl_type::ivec4_type
);
222 temp
.type
= dst
.type
;
224 /* Set up the message header to reference the proper parts of the URB */
225 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
226 inst
= emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS
, header
, vertex_index
,
228 inst
->force_writemask_all
= true;
230 /* Read into a temporary, ignoring writemasking. */
231 inst
= emit(VEC4_OPCODE_URB_READ
, temp
, src_reg(header
));
232 inst
->offset
= base_offset
;
236 /* Copy the temporary to the destination to deal with writemasking.
238 * Also attempt to deal with gl_PointSize being in the .w component.
240 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
241 emit(MOV(dst
, swizzle(src_reg(temp
), BRW_SWIZZLE_WWWW
)));
243 emit(MOV(dst
, src_reg(temp
)));
248 vec4_tcs_visitor::emit_output_urb_read(const dst_reg
&dst
,
249 unsigned base_offset
,
250 const src_reg
&indirect_offset
)
252 vec4_instruction
*inst
;
254 /* Set up the message header to reference the proper parts of the URB */
255 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
256 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, header
,
257 brw_imm_ud(dst
.writemask
), indirect_offset
);
258 inst
->force_writemask_all
= true;
260 /* Read into a temporary, ignoring writemasking. */
261 vec4_instruction
*read
= emit(VEC4_OPCODE_URB_READ
, dst
, src_reg(header
));
262 read
->offset
= base_offset
;
268 vec4_tcs_visitor::emit_urb_write(const src_reg
&value
,
270 unsigned base_offset
,
271 const src_reg
&indirect_offset
)
276 src_reg
message(this, glsl_type::uvec4_type
, 2);
277 vec4_instruction
*inst
;
279 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, dst_reg(message
),
280 brw_imm_ud(writemask
), indirect_offset
);
281 inst
->force_writemask_all
= true;
282 inst
= emit(MOV(offset(dst_reg(retype(message
, value
.type
)), 1), value
));
283 inst
->force_writemask_all
= true;
285 inst
= emit(TCS_OPCODE_URB_WRITE
, dst_null_f(), message
);
286 inst
->offset
= base_offset
;
292 tesslevel_outer_components(GLenum tes_primitive_mode
)
294 switch (tes_primitive_mode
) {
302 unreachable("Bogus tessellation domain");
308 tesslevel_inner_components(GLenum tes_primitive_mode
)
310 switch (tes_primitive_mode
) {
318 unreachable("Bogus tessellation domain");
324 * Given a normal .xyzw writemask, convert it to a writemask for a vector
325 * that's stored backwards, i.e. .wzyx.
328 writemask_for_backwards_vector(unsigned mask
)
330 unsigned new_mask
= 0;
332 for (int i
= 0; i
< 4; i
++)
333 new_mask
|= ((mask
>> i
) & 1) << (3 - i
);
339 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
341 switch (instr
->intrinsic
) {
342 case nir_intrinsic_load_invocation_id
:
343 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
),
346 case nir_intrinsic_load_primitive_id
:
347 emit(TCS_OPCODE_GET_PRIMITIVE_ID
,
348 get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
));
350 case nir_intrinsic_load_patch_vertices_in
:
351 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
),
352 brw_imm_d(key
->input_vertices
)));
354 case nir_intrinsic_load_per_vertex_input
: {
355 src_reg indirect_offset
= get_indirect_offset(instr
);
356 unsigned imm_offset
= instr
->const_index
[0];
358 nir_const_value
*vertex_const
= nir_src_as_const_value(instr
->src
[0]);
359 src_reg vertex_index
=
360 vertex_const
? src_reg(brw_imm_ud(vertex_const
->u32
[0]))
361 : get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
363 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
364 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
366 emit_input_urb_read(dst
, vertex_index
, imm_offset
, indirect_offset
);
369 case nir_intrinsic_load_input
:
370 unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
372 case nir_intrinsic_load_output
:
373 case nir_intrinsic_load_per_vertex_output
: {
374 src_reg indirect_offset
= get_indirect_offset(instr
);
375 unsigned imm_offset
= instr
->const_index
[0];;
377 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
378 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
380 if (imm_offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
381 dst
.type
= BRW_REGISTER_TYPE_F
;
383 /* This is a read of gl_TessLevelInner[], which lives in the
384 * Patch URB header. The layout depends on the domain.
386 switch (key
->tes_primitive_mode
) {
388 /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
389 dst_reg
tmp(this, glsl_type::vec4_type
);
390 emit_output_urb_read(tmp
, 0, src_reg());
391 emit(MOV(writemask(dst
, WRITEMASK_XY
),
392 swizzle(src_reg(tmp
), BRW_SWIZZLE_WZYX
)));
396 /* DWord 4; use offset 1 but normal swizzle/writemask. */
397 emit_output_urb_read(writemask(dst
, WRITEMASK_X
), 1, src_reg());
400 /* All channels are undefined. */
403 unreachable("Bogus tessellation domain");
405 } else if (imm_offset
== 1 && indirect_offset
.file
== BAD_FILE
) {
406 dst
.type
= BRW_REGISTER_TYPE_F
;
407 unsigned swiz
= BRW_SWIZZLE_WZYX
;
409 /* This is a read of gl_TessLevelOuter[], which lives in the
410 * high 4 DWords of the Patch URB header, in reverse order.
412 switch (key
->tes_primitive_mode
) {
414 dst
.writemask
= WRITEMASK_XYZW
;
417 dst
.writemask
= WRITEMASK_XYZ
;
420 /* Isolines are not reversed; swizzle .zw -> .xy */
421 swiz
= BRW_SWIZZLE_ZWZW
;
422 dst
.writemask
= WRITEMASK_XY
;
425 unreachable("Bogus tessellation domain");
428 dst_reg
tmp(this, glsl_type::vec4_type
);
429 emit_output_urb_read(tmp
, 1, src_reg());
430 emit(MOV(dst
, swizzle(src_reg(tmp
), swiz
)));
432 emit_output_urb_read(dst
, imm_offset
, indirect_offset
);
436 case nir_intrinsic_store_output
:
437 case nir_intrinsic_store_per_vertex_output
: {
438 src_reg value
= get_nir_src(instr
->src
[0]);
439 unsigned mask
= instr
->const_index
[1];
440 unsigned swiz
= BRW_SWIZZLE_XYZW
;
442 src_reg indirect_offset
= get_indirect_offset(instr
);
443 unsigned imm_offset
= instr
->const_index
[0];
445 if (imm_offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
446 value
.type
= BRW_REGISTER_TYPE_F
;
448 mask
&= (1 << tesslevel_inner_components(key
->tes_primitive_mode
)) - 1;
450 /* This is a write to gl_TessLevelInner[], which lives in the
451 * Patch URB header. The layout depends on the domain.
453 switch (key
->tes_primitive_mode
) {
455 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
456 * We use an XXYX swizzle to reverse put .xy in the .wz
457 * channels, and use a .zw writemask.
459 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
460 mask
= writemask_for_backwards_vector(mask
);
463 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
464 * writemask to X and bump the URB offset by 1.
469 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
472 unreachable("Bogus tessellation domain");
474 } else if (imm_offset
== 1 && indirect_offset
.file
== BAD_FILE
) {
475 value
.type
= BRW_REGISTER_TYPE_F
;
477 mask
&= (1 << tesslevel_outer_components(key
->tes_primitive_mode
)) - 1;
479 /* This is a write to gl_TessLevelOuter[] which lives in the
480 * Patch URB Header at DWords 4-7. However, it's reversed, so
481 * instead of .xyzw we have .wzyx.
483 if (key
->tes_primitive_mode
== GL_ISOLINES
) {
484 /* Isolines .xy should be stored in .zw, in order. */
485 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
488 /* Other domains are reversed; store .wzyx instead of .xyzw. */
489 swiz
= BRW_SWIZZLE_WZYX
;
490 mask
= writemask_for_backwards_vector(mask
);
494 emit_urb_write(swizzle(value
, swiz
), mask
,
495 imm_offset
, indirect_offset
);
499 case nir_intrinsic_barrier
: {
500 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
501 emit(TCS_OPCODE_CREATE_BARRIER_HEADER
, header
);
502 emit(SHADER_OPCODE_BARRIER
, dst_null_ud(), src_reg(header
));
507 vec4_visitor::nir_emit_intrinsic(instr
);
512 extern "C" const unsigned *
513 brw_compile_tcs(const struct brw_compiler
*compiler
,
516 const struct brw_tcs_prog_key
*key
,
517 struct brw_tcs_prog_data
*prog_data
,
518 const nir_shader
*src_shader
,
519 int shader_time_index
,
520 unsigned *final_assembly_size
,
523 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
524 struct brw_vue_prog_data
*vue_prog_data
= &prog_data
->base
;
525 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
];
527 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
528 nir
->info
.outputs_written
= key
->outputs_written
;
529 nir
->info
.patch_outputs_written
= key
->patch_outputs_written
;
531 struct brw_vue_map input_vue_map
;
532 brw_compute_vue_map(devinfo
, &input_vue_map
,
533 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
,
536 brw_compute_tess_vue_map(&vue_prog_data
->vue_map
,
537 nir
->info
.outputs_written
,
538 nir
->info
.patch_outputs_written
);
540 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
541 brw_nir_lower_vue_inputs(nir
, is_scalar
, &input_vue_map
);
542 brw_nir_lower_tcs_outputs(nir
, &vue_prog_data
->vue_map
);
543 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
545 prog_data
->instances
= DIV_ROUND_UP(nir
->info
.tcs
.vertices_out
, 2);
547 /* Compute URB entry size. The maximum allowed URB entry size is 32k.
548 * That divides up as follows:
550 * 32 bytes for the patch header (tessellation factors)
551 * 480 bytes for per-patch varyings (a varying component is 4 bytes and
552 * gl_MaxTessPatchComponents = 120)
553 * 16384 bytes for per-vertex varyings (a varying component is 4 bytes,
554 * gl_MaxPatchVertices = 32 and
555 * gl_MaxTessControlOutputComponents = 128)
557 * 15808 bytes left for varying packing overhead
559 const int num_per_patch_slots
= vue_prog_data
->vue_map
.num_per_patch_slots
;
560 const int num_per_vertex_slots
= vue_prog_data
->vue_map
.num_per_vertex_slots
;
561 unsigned output_size_bytes
= 0;
562 /* Note that the patch header is counted in num_per_patch_slots. */
563 output_size_bytes
+= num_per_patch_slots
* 16;
564 output_size_bytes
+= nir
->info
.tcs
.vertices_out
* num_per_vertex_slots
* 16;
566 assert(output_size_bytes
>= 1);
567 if (output_size_bytes
> GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES
)
570 /* URB entry sizes are stored as a multiple of 64 bytes. */
571 vue_prog_data
->urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
573 /* HS does not use the usual payload pushing from URB to GRFs,
574 * because we don't have enough registers for a full-size payload, and
575 * the hardware is broken on Haswell anyway.
577 vue_prog_data
->urb_read_length
= 0;
579 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
)) {
580 fprintf(stderr
, "TCS Input ");
581 brw_print_vue_map(stderr
, &input_vue_map
);
582 fprintf(stderr
, "TCS Output ");
583 brw_print_vue_map(stderr
, &vue_prog_data
->vue_map
);
586 vec4_tcs_visitor
v(compiler
, log_data
, key
, prog_data
,
587 nir
, mem_ctx
, shader_time_index
, &input_vue_map
);
590 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
594 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
))
595 v
.dump_instructions();
597 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
598 &prog_data
->base
, v
.cfg
,
599 final_assembly_size
);
603 } /* namespace brw */