2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 * DEALINGS IN THE SOFTWARE.
25 * \file brw_vec4_tcs.cpp
27 * Tessellaton control shader specific code derived from the vec4_visitor class.
31 #include "brw_vec4_tcs.h"
36 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler
*compiler
,
38 const struct brw_tcs_prog_key
*key
,
39 struct brw_tcs_prog_data
*prog_data
,
40 const nir_shader
*nir
,
42 int shader_time_index
,
43 const struct brw_vue_map
*input_vue_map
)
44 : vec4_visitor(compiler
, log_data
, &key
->tex
, &prog_data
->base
,
45 nir
, mem_ctx
, false, shader_time_index
),
46 input_vue_map(input_vue_map
), key(key
)
52 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
57 vec4_tcs_visitor::make_reg_for_system_value(int location
)
64 vec4_tcs_visitor::setup_payload()
68 /* The payload always contains important data in r0, which contains
69 * the URB handles that are passed on to the URB write at the end
74 /* r1.0 - r4.7 may contain the input control point URB handles,
75 * which we use to pull vertex data.
79 /* Push constants may start at r5.0 */
80 reg
= setup_uniforms(reg
);
82 this->first_non_payload_grf
= reg
;
87 vec4_tcs_visitor::emit_prolog()
89 invocation_id
= src_reg(this, glsl_type::uint_type
);
90 emit(TCS_OPCODE_GET_INSTANCE_ID
, dst_reg(invocation_id
));
92 /* HS threads are dispatched with the dispatch mask set to 0xFF.
93 * If there are an odd number of output vertices, then the final
94 * HS instance dispatched will only have its bottom half doing real
95 * work, and so we need to disable the upper half:
97 if (nir
->info
->tcs
.vertices_out
% 2) {
98 emit(CMP(dst_null_d(), invocation_id
,
99 brw_imm_ud(nir
->info
->tcs
.vertices_out
), BRW_CONDITIONAL_L
));
101 /* Matching ENDIF is in emit_thread_end() */
102 emit(IF(BRW_PREDICATE_NORMAL
));
108 vec4_tcs_visitor::emit_thread_end()
110 vec4_instruction
*inst
;
111 current_annotation
= "thread end";
113 if (nir
->info
->tcs
.vertices_out
% 2) {
114 emit(BRW_OPCODE_ENDIF
);
117 if (devinfo
->gen
== 7) {
118 struct brw_tcs_prog_data
*tcs_prog_data
=
119 (struct brw_tcs_prog_data
*) prog_data
;
121 current_annotation
= "release input vertices";
123 /* Synchronize all threads, so we know that no one is still
124 * using the input URB handles.
126 if (tcs_prog_data
->instances
> 1) {
127 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
128 emit(TCS_OPCODE_CREATE_BARRIER_HEADER
, header
);
129 emit(SHADER_OPCODE_BARRIER
, dst_null_ud(), src_reg(header
));
132 /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
133 * We want to compare the bottom half of invocation_id with 0, but
134 * use that truth value for the top half as well. Unfortunately,
135 * we don't have stride in the vec4 world, nor UV immediates in
136 * align16, so we need an opcode to get invocation_id<0,4,0>.
138 set_condmod(BRW_CONDITIONAL_Z
,
139 emit(TCS_OPCODE_SRC0_010_IS_ZERO
, dst_null_d(),
141 emit(IF(BRW_PREDICATE_NORMAL
));
142 for (unsigned i
= 0; i
< key
->input_vertices
; i
+= 2) {
143 /* If we have an odd number of input vertices, the last will be
144 * unpaired. We don't want to use an interleaved URB write in
147 const bool is_unpaired
= i
== key
->input_vertices
- 1;
149 dst_reg
header(this, glsl_type::uvec4_type
);
150 emit(TCS_OPCODE_RELEASE_INPUT
, header
, brw_imm_ud(i
),
151 brw_imm_ud(is_unpaired
));
153 emit(BRW_OPCODE_ENDIF
);
156 if (unlikely(INTEL_DEBUG
& DEBUG_SHADER_TIME
))
157 emit_shader_time_end();
159 inst
= emit(TCS_OPCODE_THREAD_END
);
166 vec4_tcs_visitor::emit_input_urb_read(const dst_reg
&dst
,
167 const src_reg
&vertex_index
,
168 unsigned base_offset
,
169 unsigned first_component
,
170 const src_reg
&indirect_offset
)
172 vec4_instruction
*inst
;
173 dst_reg
temp(this, glsl_type::ivec4_type
);
174 temp
.type
= dst
.type
;
176 /* Set up the message header to reference the proper parts of the URB */
177 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
178 inst
= emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS
, header
, vertex_index
,
180 inst
->force_writemask_all
= true;
182 /* Read into a temporary, ignoring writemasking. */
183 inst
= emit(VEC4_OPCODE_URB_READ
, temp
, src_reg(header
));
184 inst
->offset
= base_offset
;
188 /* Copy the temporary to the destination to deal with writemasking.
190 * Also attempt to deal with gl_PointSize being in the .w component.
192 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
193 emit(MOV(dst
, swizzle(src_reg(temp
), BRW_SWIZZLE_WWWW
)));
195 src_reg src
= src_reg(temp
);
196 src
.swizzle
= BRW_SWZ_COMP_INPUT(first_component
);
202 vec4_tcs_visitor::emit_output_urb_read(const dst_reg
&dst
,
203 unsigned base_offset
,
204 unsigned first_component
,
205 const src_reg
&indirect_offset
)
207 vec4_instruction
*inst
;
209 /* Set up the message header to reference the proper parts of the URB */
210 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
211 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, header
,
212 brw_imm_ud(dst
.writemask
<< first_component
), indirect_offset
);
213 inst
->force_writemask_all
= true;
215 vec4_instruction
*read
= emit(VEC4_OPCODE_URB_READ
, dst
, src_reg(header
));
216 read
->offset
= base_offset
;
220 if (first_component
) {
221 /* Read into a temporary and copy with a swizzle and writemask. */
222 read
->dst
= retype(dst_reg(this, glsl_type::ivec4_type
), dst
.type
);
223 emit(MOV(dst
, swizzle(src_reg(read
->dst
),
224 BRW_SWZ_COMP_INPUT(first_component
))));
229 vec4_tcs_visitor::emit_urb_write(const src_reg
&value
,
231 unsigned base_offset
,
232 const src_reg
&indirect_offset
)
237 src_reg
message(this, glsl_type::uvec4_type
, 2);
238 vec4_instruction
*inst
;
240 inst
= emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
, dst_reg(message
),
241 brw_imm_ud(writemask
), indirect_offset
);
242 inst
->force_writemask_all
= true;
243 inst
= emit(MOV(byte_offset(dst_reg(retype(message
, value
.type
)), REG_SIZE
),
245 inst
->force_writemask_all
= true;
247 inst
= emit(TCS_OPCODE_URB_WRITE
, dst_null_f(), message
);
248 inst
->offset
= base_offset
;
254 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
256 switch (instr
->intrinsic
) {
257 case nir_intrinsic_load_invocation_id
:
258 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
),
261 case nir_intrinsic_load_primitive_id
:
262 emit(TCS_OPCODE_GET_PRIMITIVE_ID
,
263 get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
));
265 case nir_intrinsic_load_patch_vertices_in
:
266 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
),
267 brw_imm_d(key
->input_vertices
)));
269 case nir_intrinsic_load_per_vertex_input
: {
270 src_reg indirect_offset
= get_indirect_offset(instr
);
271 unsigned imm_offset
= instr
->const_index
[0];
273 nir_const_value
*vertex_const
= nir_src_as_const_value(instr
->src
[0]);
274 src_reg vertex_index
=
275 vertex_const
? src_reg(brw_imm_ud(vertex_const
->u32
[0]))
276 : get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
278 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
279 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
281 emit_input_urb_read(dst
, vertex_index
, imm_offset
,
282 nir_intrinsic_component(instr
), indirect_offset
);
285 case nir_intrinsic_load_input
:
286 unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
288 case nir_intrinsic_load_output
:
289 case nir_intrinsic_load_per_vertex_output
: {
290 src_reg indirect_offset
= get_indirect_offset(instr
);
291 unsigned imm_offset
= instr
->const_index
[0];
293 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
294 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
296 if (imm_offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
297 dst
.type
= BRW_REGISTER_TYPE_F
;
299 /* This is a read of gl_TessLevelInner[], which lives in the
300 * Patch URB header. The layout depends on the domain.
302 switch (key
->tes_primitive_mode
) {
304 /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
305 dst_reg
tmp(this, glsl_type::vec4_type
);
306 emit_output_urb_read(tmp
, 0, 0, src_reg());
307 emit(MOV(writemask(dst
, WRITEMASK_XY
),
308 swizzle(src_reg(tmp
), BRW_SWIZZLE_WZYX
)));
312 /* DWord 4; use offset 1 but normal swizzle/writemask. */
313 emit_output_urb_read(writemask(dst
, WRITEMASK_X
), 1, 0,
317 /* All channels are undefined. */
320 unreachable("Bogus tessellation domain");
322 } else if (imm_offset
== 1 && indirect_offset
.file
== BAD_FILE
) {
323 dst
.type
= BRW_REGISTER_TYPE_F
;
324 unsigned swiz
= BRW_SWIZZLE_WZYX
;
326 /* This is a read of gl_TessLevelOuter[], which lives in the
327 * high 4 DWords of the Patch URB header, in reverse order.
329 switch (key
->tes_primitive_mode
) {
331 dst
.writemask
= WRITEMASK_XYZW
;
334 dst
.writemask
= WRITEMASK_XYZ
;
337 /* Isolines are not reversed; swizzle .zw -> .xy */
338 swiz
= BRW_SWIZZLE_ZWZW
;
339 dst
.writemask
= WRITEMASK_XY
;
342 unreachable("Bogus tessellation domain");
345 dst_reg
tmp(this, glsl_type::vec4_type
);
346 emit_output_urb_read(tmp
, 1, 0, src_reg());
347 emit(MOV(dst
, swizzle(src_reg(tmp
), swiz
)));
349 emit_output_urb_read(dst
, imm_offset
, nir_intrinsic_component(instr
),
354 case nir_intrinsic_store_output
:
355 case nir_intrinsic_store_per_vertex_output
: {
356 src_reg value
= get_nir_src(instr
->src
[0]);
357 unsigned mask
= instr
->const_index
[1];
358 unsigned swiz
= BRW_SWIZZLE_XYZW
;
360 src_reg indirect_offset
= get_indirect_offset(instr
);
361 unsigned imm_offset
= instr
->const_index
[0];
363 /* The passthrough shader writes the whole patch header as two vec4s;
364 * skip all the gl_TessLevelInner/Outer swizzling.
366 if (indirect_offset
.file
== BAD_FILE
&& !is_passthrough_shader
) {
367 if (imm_offset
== 0) {
368 value
.type
= BRW_REGISTER_TYPE_F
;
371 (1 << tesslevel_inner_components(key
->tes_primitive_mode
)) - 1;
373 /* This is a write to gl_TessLevelInner[], which lives in the
374 * Patch URB header. The layout depends on the domain.
376 switch (key
->tes_primitive_mode
) {
378 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
379 * We use an XXYX swizzle to reverse put .xy in the .wz
380 * channels, and use a .zw writemask.
382 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
383 mask
= writemask_for_backwards_vector(mask
);
386 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
387 * writemask to X and bump the URB offset by 1.
392 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
395 unreachable("Bogus tessellation domain");
397 } else if (imm_offset
== 1) {
398 value
.type
= BRW_REGISTER_TYPE_F
;
401 (1 << tesslevel_outer_components(key
->tes_primitive_mode
)) - 1;
403 /* This is a write to gl_TessLevelOuter[] which lives in the
404 * Patch URB Header at DWords 4-7. However, it's reversed, so
405 * instead of .xyzw we have .wzyx.
407 if (key
->tes_primitive_mode
== GL_ISOLINES
) {
408 /* Isolines .xy should be stored in .zw, in order. */
409 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
412 /* Other domains are reversed; store .wzyx instead of .xyzw. */
413 swiz
= BRW_SWIZZLE_WZYX
;
414 mask
= writemask_for_backwards_vector(mask
);
419 unsigned first_component
= nir_intrinsic_component(instr
);
420 if (first_component
) {
421 assert(swiz
== BRW_SWIZZLE_XYZW
);
422 swiz
= BRW_SWZ_COMP_OUTPUT(first_component
);
423 mask
= mask
<< first_component
;
426 emit_urb_write(swizzle(value
, swiz
), mask
,
427 imm_offset
, indirect_offset
);
431 case nir_intrinsic_barrier
: {
432 dst_reg header
= dst_reg(this, glsl_type::uvec4_type
);
433 emit(TCS_OPCODE_CREATE_BARRIER_HEADER
, header
);
434 emit(SHADER_OPCODE_BARRIER
, dst_null_ud(), src_reg(header
));
439 vec4_visitor::nir_emit_intrinsic(instr
);
444 extern "C" const unsigned *
445 brw_compile_tcs(const struct brw_compiler
*compiler
,
448 const struct brw_tcs_prog_key
*key
,
449 struct brw_tcs_prog_data
*prog_data
,
450 const nir_shader
*src_shader
,
451 int shader_time_index
,
452 unsigned *final_assembly_size
,
455 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
456 struct brw_vue_prog_data
*vue_prog_data
= &prog_data
->base
;
457 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
];
459 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
460 nir
->info
->outputs_written
= key
->outputs_written
;
461 nir
->info
->patch_outputs_written
= key
->patch_outputs_written
;
463 struct brw_vue_map input_vue_map
;
464 brw_compute_vue_map(devinfo
, &input_vue_map
, nir
->info
->inputs_read
,
465 nir
->info
->separate_shader
);
466 brw_compute_tess_vue_map(&vue_prog_data
->vue_map
,
467 nir
->info
->outputs_written
,
468 nir
->info
->patch_outputs_written
);
470 nir
= brw_nir_apply_sampler_key(nir
, devinfo
, &key
->tex
, is_scalar
);
471 brw_nir_lower_vue_inputs(nir
, is_scalar
, &input_vue_map
);
472 brw_nir_lower_tcs_outputs(nir
, &vue_prog_data
->vue_map
);
473 if (key
->quads_workaround
)
474 brw_nir_apply_tcs_quads_workaround(nir
);
476 nir
= brw_postprocess_nir(nir
, compiler
->devinfo
, is_scalar
);
479 prog_data
->instances
= DIV_ROUND_UP(nir
->info
->tcs
.vertices_out
, 8);
481 prog_data
->instances
= DIV_ROUND_UP(nir
->info
->tcs
.vertices_out
, 2);
483 /* Compute URB entry size. The maximum allowed URB entry size is 32k.
484 * That divides up as follows:
486 * 32 bytes for the patch header (tessellation factors)
487 * 480 bytes for per-patch varyings (a varying component is 4 bytes and
488 * gl_MaxTessPatchComponents = 120)
489 * 16384 bytes for per-vertex varyings (a varying component is 4 bytes,
490 * gl_MaxPatchVertices = 32 and
491 * gl_MaxTessControlOutputComponents = 128)
493 * 15808 bytes left for varying packing overhead
495 const int num_per_patch_slots
= vue_prog_data
->vue_map
.num_per_patch_slots
;
496 const int num_per_vertex_slots
= vue_prog_data
->vue_map
.num_per_vertex_slots
;
497 unsigned output_size_bytes
= 0;
498 /* Note that the patch header is counted in num_per_patch_slots. */
499 output_size_bytes
+= num_per_patch_slots
* 16;
500 output_size_bytes
+= nir
->info
->tcs
.vertices_out
* num_per_vertex_slots
* 16;
502 assert(output_size_bytes
>= 1);
503 if (output_size_bytes
> GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES
)
506 /* URB entry sizes are stored as a multiple of 64 bytes. */
507 vue_prog_data
->urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
509 /* HS does not use the usual payload pushing from URB to GRFs,
510 * because we don't have enough registers for a full-size payload, and
511 * the hardware is broken on Haswell anyway.
513 vue_prog_data
->urb_read_length
= 0;
515 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
)) {
516 fprintf(stderr
, "TCS Input ");
517 brw_print_vue_map(stderr
, &input_vue_map
);
518 fprintf(stderr
, "TCS Output ");
519 brw_print_vue_map(stderr
, &vue_prog_data
->vue_map
);
523 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
524 &prog_data
->base
.base
, NULL
, nir
, 8,
525 shader_time_index
, &input_vue_map
);
526 if (!v
.run_tcs_single_patch()) {
528 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
532 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
533 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
535 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
536 &prog_data
->base
.base
, v
.promoted_constants
, false,
537 MESA_SHADER_TESS_CTRL
);
538 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
)) {
539 g
.enable_debug(ralloc_asprintf(mem_ctx
,
540 "%s tessellation control shader %s",
541 nir
->info
->label
? nir
->info
->label
546 g
.generate_code(v
.cfg
, 8);
548 return g
.get_assembly(final_assembly_size
);
550 vec4_tcs_visitor
v(compiler
, log_data
, key
, prog_data
,
551 nir
, mem_ctx
, shader_time_index
, &input_vue_map
);
554 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
558 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
))
559 v
.dump_instructions();
562 return brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
563 &prog_data
->base
, v
.cfg
,
564 final_assembly_size
);
569 } /* namespace brw */