src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32
  33 namespace brw {
  34
  35 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  36                                    void *log_data,
  37                                    const struct brw_tcs_prog_key *key,
  38                                    struct brw_tcs_prog_data *prog_data,
  39                                    const nir_shader *nir,
  40                                    void *mem_ctx,
  41                                    int shader_time_index,
  42                                    const struct brw_vue_map *input_vue_map)
  43    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  44                   nir, mem_ctx, false, shader_time_index),
  45      input_vue_map(input_vue_map), key(key)
  46 {
  47 }
  48
  49
  50 void
  51 vec4_tcs_visitor::emit_nir_code()
  52 {
  53    if (key->program_string_id != 0) {
  54       /* We have a real application-supplied TCS, emit real code. */
  55       vec4_visitor::emit_nir_code();
  56    } else {
  57       /* There is no TCS; automatically generate a passthrough shader
  58        * that writes the API-specified default tessellation levels and
  59        * copies VS outputs to TES inputs.
  60        */
  61       uniforms = 2;
  62       uniform_size[0] = 1;
  63       uniform_size[1] = 1;
  64
  65       uint64_t varyings = key->outputs_written;
  66
  67       src_reg vertex_offset(this, glsl_type::uint_type);
  68       emit(MUL(dst_reg(vertex_offset), invocation_id,
  69                brw_imm_ud(prog_data->vue_map.num_per_vertex_slots)));
  70
  71       while (varyings != 0) {
  72          const int varying = ffsll(varyings) - 1;
  73
  74          unsigned in_offset = input_vue_map->varying_to_slot[varying];
  75          unsigned out_offset = prog_data->vue_map.varying_to_slot[varying];
  76          assert(out_offset >= 2);
  77
  78          dst_reg val(this, glsl_type::vec4_type);
  79          emit_input_urb_read(val, invocation_id, in_offset, src_reg());
  80          emit_urb_write(src_reg(val), WRITEMASK_XYZW, out_offset,
  81                         vertex_offset);
  82
  83          varyings &= ~BITFIELD64_BIT(varying);
  84       }
  85
  86       /* Only write the tessellation factors from invocation 0.
  87        * There's no point in making other threads do redundant work.
  88        */
  89       emit(CMP(dst_null_d(), invocation_id, brw_imm_ud(0),
  90                BRW_CONDITIONAL_EQ));
  91       emit(IF(BRW_PREDICATE_NORMAL));
  92       emit_urb_write(src_reg(UNIFORM, 0, glsl_type::vec4_type),
  93                      WRITEMASK_XYZW, 0, src_reg());
  94       emit_urb_write(src_reg(UNIFORM, 1, glsl_type::vec4_type),
  95                      WRITEMASK_XYZW, 1, src_reg());
  96       emit(BRW_OPCODE_ENDIF);
  97    }
  98 }
  99
 100 void
 101 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
 102 {
 103 }
 104
 105 dst_reg *
 106 vec4_tcs_visitor::make_reg_for_system_value(int location, const glsl_type *type)
 107 {
 108    return NULL;
 109 }
 110
 111
 112 void
 113 vec4_tcs_visitor::setup_payload()
 114 {
 115    int reg = 0;
 116
 117    /* The payload always contains important data in r0, which contains
 118     * the URB handles that are passed on to the URB write at the end
 119     * of the thread.
 120     */
 121    reg++;
 122
 123    /* r1.0 - r4.7 may contain the input control point URB handles,
 124     * which we use to pull vertex data.
 125     */
 126    reg += 4;
 127
 128    /* Push constants may start at r5.0 */
 129    reg = setup_uniforms(reg);
 130
 131    this->first_non_payload_grf = reg;
 132 }
 133
 134
 135 void
 136 vec4_tcs_visitor::emit_prolog()
 137 {
 138    invocation_id = src_reg(this, glsl_type::uint_type);
 139    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
 140
 141    /* HS threads are dispatched with the dispatch mask set to 0xFF.
 142     * If there are an odd number of output vertices, then the final
 143     * HS instance dispatched will only have its bottom half doing real
 144     * work, and so we need to disable the upper half:
 145     */
 146    if (nir->info.tcs.vertices_out % 2) {
 147       emit(CMP(dst_null_d(), invocation_id,
 148                brw_imm_ud(nir->info.tcs.vertices_out), BRW_CONDITIONAL_L));
 149
 150       /* Matching ENDIF is in emit_thread_end() */
 151       emit(IF(BRW_PREDICATE_NORMAL));
 152    }
 153 }
 154
 155
 156 void
 157 vec4_tcs_visitor::emit_thread_end()
 158 {
 159    current_annotation = "thread end";
 160
 161    if (nir->info.tcs.vertices_out % 2) {
 162       emit(BRW_OPCODE_ENDIF);
 163    }
 164
 165    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 166       emit_shader_time_end();
 167
 168    vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
 169    inst->mlen = 1;   /* just the header, no data. */
 170    inst->urb_write_flags = BRW_URB_WRITE_EOT_COMPLETE;
 171 }
 172
 173
 174 void
 175 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 176                                       const src_reg &vertex_index,
 177                                       unsigned base_offset,
 178                                       const src_reg &indirect_offset)
 179 {
 180    vec4_instruction *inst;
 181    dst_reg temp(this, glsl_type::ivec4_type);
 182    temp.type = dst.type;
 183
 184    /* Set up the message header to reference the proper parts of the URB */
 185    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 186    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 187                indirect_offset);
 188    inst->force_writemask_all = true;
 189
 190    /* Read into a temporary, ignoring writemasking. */
 191    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 192    inst->offset = base_offset;
 193    inst->mlen = 1;
 194    inst->base_mrf = -1;
 195
 196    /* Copy the temporary to the destination to deal with writemasking.
 197     *
 198     * Also attempt to deal with gl_PointSize being in the .w component.
 199     */
 200    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 201       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 202    } else {
 203       emit(MOV(dst, src_reg(temp)));
 204    }
 205 }
 206
 207 void
 208 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 209                                        unsigned base_offset,
 210                                        const src_reg &indirect_offset)
 211 {
 212    vec4_instruction *inst;
 213
 214    /* Set up the message header to reference the proper parts of the URB */
 215    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 216    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 217                brw_imm_ud(dst.writemask), indirect_offset);
 218    inst->force_writemask_all = true;
 219
 220    /* Read into a temporary, ignoring writemasking. */
 221    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 222    read->offset = base_offset;
 223    read->mlen = 1;
 224    read->base_mrf = -1;
 225 }
 226
 227 void
 228 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 229                                  unsigned writemask,
 230                                  unsigned base_offset,
 231                                  const src_reg &indirect_offset)
 232 {
 233    if (writemask == 0)
 234       return;
 235
 236    src_reg message(this, glsl_type::uvec4_type, 2);
 237    vec4_instruction *inst;
 238
 239    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 240                brw_imm_ud(writemask), indirect_offset);
 241    inst->force_writemask_all = true;
 242    inst = emit(MOV(offset(dst_reg(retype(message, value.type)), 1), value));
 243    inst->force_writemask_all = true;
 244
 245    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 246    inst->offset = base_offset;
 247    inst->mlen = 2;
 248    inst->base_mrf = -1;
 249 }
 250
 251 static unsigned
 252 tesslevel_outer_components(GLenum tes_primitive_mode)
 253 {
 254    switch (tes_primitive_mode) {
 255    case GL_QUADS:
 256       return 4;
 257    case GL_TRIANGLES:
 258       return 3;
 259    case GL_ISOLINES:
 260       return 2;
 261    default:
 262       unreachable("Bogus tessellation domain");
 263    }
 264    return 0;
 265 }
 266
 267 static unsigned
 268 tesslevel_inner_components(GLenum tes_primitive_mode)
 269 {
 270    switch (tes_primitive_mode) {
 271    case GL_QUADS:
 272       return 2;
 273    case GL_TRIANGLES:
 274       return 1;
 275    case GL_ISOLINES:
 276       return 0;
 277    default:
 278       unreachable("Bogus tessellation domain");
 279    }
 280    return 0;
 281 }
 282
 283 /**
 284  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 285  * that's stored backwards, i.e. .wzyx.
 286  */
 287 static unsigned
 288 writemask_for_backwards_vector(unsigned mask)
 289 {
 290    unsigned new_mask = 0;
 291
 292    for (int i = 0; i < 4; i++)
 293       new_mask |= ((mask >> i) & 1) << (3 - i);
 294
 295    return new_mask;
 296 }
 297
 298 void
 299 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 300 {
 301    switch (instr->intrinsic) {
 302    case nir_intrinsic_load_invocation_id:
 303       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 304                invocation_id));
 305       break;
 306    case nir_intrinsic_load_primitive_id:
 307       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 308            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 309       break;
 310    case nir_intrinsic_load_patch_vertices_in:
 311       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 312                brw_imm_d(key->input_vertices)));
 313       break;
 314    case nir_intrinsic_load_per_vertex_input: {
 315       src_reg indirect_offset = get_indirect_offset(instr);
 316       unsigned imm_offset = instr->const_index[0];
 317
 318       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 319       src_reg vertex_index =
 320          vertex_const ? src_reg(brw_imm_ud(vertex_const->u[0]))
 321                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 322
 323       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 324       dst.writemask = brw_writemask_for_size(instr->num_components);
 325
 326       emit_input_urb_read(dst, vertex_index, imm_offset, indirect_offset);
 327       break;
 328    }
 329    case nir_intrinsic_load_input:
 330       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 331       break;
 332    case nir_intrinsic_load_output:
 333    case nir_intrinsic_load_per_vertex_output: {
 334       src_reg indirect_offset = get_indirect_offset(instr);
 335       unsigned imm_offset = instr->const_index[0];;
 336
 337       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 338       dst.writemask = brw_writemask_for_size(instr->num_components);
 339
 340       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 341          dst.type = BRW_REGISTER_TYPE_F;
 342
 343          /* This is a read of gl_TessLevelInner[], which lives in the
 344           * Patch URB header.  The layout depends on the domain.
 345           */
 346          switch (key->tes_primitive_mode) {
 347          case GL_QUADS: {
 348             /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
 349             dst_reg tmp(this, glsl_type::vec4_type);
 350             emit_output_urb_read(tmp, 0, src_reg());
 351             emit(MOV(writemask(dst, WRITEMASK_XY),
 352                      swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 353             break;
 354          }
 355          case GL_TRIANGLES:
 356             /* DWord 4; use offset 1 but normal swizzle/writemask. */
 357             emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, src_reg());
 358             break;
 359          case GL_ISOLINES:
 360             /* All channels are undefined. */
 361             return;
 362          default:
 363             unreachable("Bogus tessellation domain");
 364          }
 365       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 366          dst.type = BRW_REGISTER_TYPE_F;
 367
 368          /* This is a read of gl_TessLevelOuter[], which lives in the
 369           * high 4 DWords of the Patch URB header, in reverse order.
 370           */
 371          switch (key->tes_primitive_mode) {
 372          case GL_QUADS:
 373             dst.writemask = WRITEMASK_XYZW;
 374             break;
 375          case GL_TRIANGLES:
 376             dst.writemask = WRITEMASK_XYZ;
 377             break;
 378          case GL_ISOLINES:
 379             dst.writemask = WRITEMASK_XY;
 380             return;
 381          default:
 382             unreachable("Bogus tessellation domain");
 383          }
 384
 385          dst_reg tmp(this, glsl_type::vec4_type);
 386          emit_output_urb_read(tmp, 1, src_reg());
 387          emit(MOV(dst, swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 388       } else {
 389          emit_output_urb_read(dst, imm_offset, indirect_offset);
 390       }
 391       break;
 392    }
 393    case nir_intrinsic_store_output:
 394    case nir_intrinsic_store_per_vertex_output: {
 395       src_reg value = get_nir_src(instr->src[0]);
 396       unsigned mask = instr->const_index[1];
 397       unsigned swiz = BRW_SWIZZLE_XYZW;
 398
 399       src_reg indirect_offset = get_indirect_offset(instr);
 400       unsigned imm_offset = instr->const_index[0];
 401
 402       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 403          value.type = BRW_REGISTER_TYPE_F;
 404
 405          mask &= (1 << tesslevel_inner_components(key->tes_primitive_mode)) - 1;
 406
 407          /* This is a write to gl_TessLevelInner[], which lives in the
 408           * Patch URB header.  The layout depends on the domain.
 409           */
 410          switch (key->tes_primitive_mode) {
 411          case GL_QUADS:
 412             /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
 413              * We use an XXYX swizzle to reverse put .xy in the .wz
 414              * channels, and use a .zw writemask.
 415              */
 416             swiz = BRW_SWIZZLE4(0, 0, 1, 0);
 417             mask = writemask_for_backwards_vector(mask);
 418             break;
 419          case GL_TRIANGLES:
 420             /* gl_TessLevelInner[].x lives at DWord 4, so we set the
 421              * writemask to X and bump the URB offset by 1.
 422              */
 423             imm_offset = 1;
 424             break;
 425          case GL_ISOLINES:
 426             /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
 427             return;
 428          default:
 429             unreachable("Bogus tessellation domain");
 430          }
 431       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 432          value.type = BRW_REGISTER_TYPE_F;
 433
 434          mask &= (1 << tesslevel_outer_components(key->tes_primitive_mode)) - 1;
 435
 436          /* This is a write to gl_TessLevelOuter[] which lives in the
 437           * Patch URB Header at DWords 4-7.  However, it's reversed, so
 438           * instead of .xyzw we have .wzyx.
 439           */
 440          swiz = BRW_SWIZZLE_WZYX;
 441          mask = writemask_for_backwards_vector(mask);
 442       }
 443
 444       emit_urb_write(swizzle(value, swiz), mask,
 445                      imm_offset, indirect_offset);
 446       break;
 447    }
 448
 449    case nir_intrinsic_barrier: {
 450       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 451       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 452       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 453       break;
 454    }
 455
 456    default:
 457       vec4_visitor::nir_emit_intrinsic(instr);
 458    }
 459 }
 460
 461
 462 extern "C" const unsigned *
 463 brw_compile_tcs(const struct brw_compiler *compiler,
 464                 void *log_data,
 465                 void *mem_ctx,
 466                 const struct brw_tcs_prog_key *key,
 467                 struct brw_tcs_prog_data *prog_data,
 468                 const nir_shader *src_shader,
 469                 int shader_time_index,
 470                 unsigned *final_assembly_size,
 471                 char **error_str)
 472 {
 473    const struct brw_device_info *devinfo = compiler->devinfo;
 474    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 475    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 476
 477    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 478    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
 479    nir = brw_nir_lower_io(nir, compiler->devinfo, is_scalar);
 480    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
 481
 482    prog_data->instances = DIV_ROUND_UP(nir->info.tcs.vertices_out, 2);
 483
 484    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 485                             nir->info.outputs_written,
 486                             nir->info.patch_outputs_written);
 487
 488    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 489     * That divides up as follows:
 490     *
 491     *     32 bytes for the patch header (tessellation factors)
 492     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 493     *              gl_MaxTessPatchComponents = 120)
 494     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 495     *              gl_MaxPatchVertices = 32 and
 496     *              gl_MaxTessControlOutputComponents = 128)
 497     *
 498     *  15808 bytes left for varying packing overhead
 499     */
 500    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 501    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 502    unsigned output_size_bytes = 0;
 503    /* Note that the patch header is counted in num_per_patch_slots. */
 504    output_size_bytes += num_per_patch_slots * 16;
 505    output_size_bytes += nir->info.tcs.vertices_out * num_per_vertex_slots * 16;
 506
 507    assert(output_size_bytes >= 1);
 508    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 509       return false;
 510
 511    /* URB entry sizes are stored as a multiple of 64 bytes. */
 512    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 513
 514    struct brw_vue_map input_vue_map;
 515    brw_compute_vue_map(devinfo, &input_vue_map,
 516                        nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
 517                        true);
 518
 519    /* HS does not use the usual payload pushing from URB to GRFs,
 520     * because we don't have enough registers for a full-size payload, and
 521     * the hardware is broken on Haswell anyway.
 522     */
 523    vue_prog_data->urb_read_length = 0;
 524
 525    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 526       fprintf(stderr, "TCS Input ");
 527       brw_print_vue_map(stderr, &input_vue_map);
 528       fprintf(stderr, "TCS Output ");
 529       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 530    }
 531
 532    vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 533                       nir, mem_ctx, shader_time_index, &input_vue_map);
 534    if (!v.run()) {
 535       if (error_str)
 536          *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 537       return NULL;
 538    }
 539
 540    if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 541       v.dump_instructions();
 542
 543    return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 544                                      &prog_data->base, v.cfg,
 545                                      final_assembly_size);
 546 }
 547
 548
 549 } /* namespace brw */