src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32 #include "brw_fs.h"
  33
  34 namespace brw {
  35
  36 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  37                                    void *log_data,
  38                                    const struct brw_tcs_prog_key *key,
  39                                    struct brw_tcs_prog_data *prog_data,
  40                                    const nir_shader *nir,
  41                                    void *mem_ctx,
  42                                    int shader_time_index,
  43                                    const struct brw_vue_map *input_vue_map)
  44    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  45                   nir, mem_ctx, false, shader_time_index),
  46      input_vue_map(input_vue_map), key(key)
  47 {
  48 }
  49
  50
  51 void
  52 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
  53 {
  54 }
  55
  56 dst_reg *
  57 vec4_tcs_visitor::make_reg_for_system_value(int location, const glsl_type *type)
  58 {
  59    return NULL;
  60 }
  61
  62
  63 void
  64 vec4_tcs_visitor::setup_payload()
  65 {
  66    int reg = 0;
  67
  68    /* The payload always contains important data in r0, which contains
  69     * the URB handles that are passed on to the URB write at the end
  70     * of the thread.
  71     */
  72    reg++;
  73
  74    /* r1.0 - r4.7 may contain the input control point URB handles,
  75     * which we use to pull vertex data.
  76     */
  77    reg += 4;
  78
  79    /* Push constants may start at r5.0 */
  80    reg = setup_uniforms(reg);
  81
  82    this->first_non_payload_grf = reg;
  83 }
  84
  85
  86 void
  87 vec4_tcs_visitor::emit_prolog()
  88 {
  89    invocation_id = src_reg(this, glsl_type::uint_type);
  90    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
  91
  92    /* HS threads are dispatched with the dispatch mask set to 0xFF.
  93     * If there are an odd number of output vertices, then the final
  94     * HS instance dispatched will only have its bottom half doing real
  95     * work, and so we need to disable the upper half:
  96     */
  97    if (nir->info.tcs.vertices_out % 2) {
  98       emit(CMP(dst_null_d(), invocation_id,
  99                brw_imm_ud(nir->info.tcs.vertices_out), BRW_CONDITIONAL_L));
 100
 101       /* Matching ENDIF is in emit_thread_end() */
 102       emit(IF(BRW_PREDICATE_NORMAL));
 103    }
 104 }
 105
 106
 107 void
 108 vec4_tcs_visitor::emit_thread_end()
 109 {
 110    vec4_instruction *inst;
 111    current_annotation = "thread end";
 112
 113    if (nir->info.tcs.vertices_out % 2) {
 114       emit(BRW_OPCODE_ENDIF);
 115    }
 116
 117    if (devinfo->gen == 7) {
 118       struct brw_tcs_prog_data *tcs_prog_data =
 119          (struct brw_tcs_prog_data *) prog_data;
 120
 121       current_annotation = "release input vertices";
 122
 123       /* Synchronize all threads, so we know that no one is still
 124        * using the input URB handles.
 125        */
 126       if (tcs_prog_data->instances > 1) {
 127          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 128          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 129          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 130       }
 131
 132       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 133        * We want to compare the bottom half of invocation_id with 0, but
 134        * use that truth value for the top half as well.  Unfortunately,
 135        * we don't have stride in the vec4 world, nor UV immediates in
 136        * align16, so we need an opcode to get invocation_id<0,4,0>.
 137        */
 138       set_condmod(BRW_CONDITIONAL_Z,
 139                   emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
 140                        invocation_id));
 141       emit(IF(BRW_PREDICATE_NORMAL));
 142       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 143          /* If we have an odd number of input vertices, the last will be
 144           * unpaired.  We don't want to use an interleaved URB write in
 145           * that case.
 146           */
 147          const bool is_unpaired = i == key->input_vertices - 1;
 148
 149          dst_reg header(this, glsl_type::uvec4_type);
 150          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 151               brw_imm_ud(is_unpaired));
 152       }
 153       emit(BRW_OPCODE_ENDIF);
 154    }
 155
 156    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 157       emit_shader_time_end();
 158
 159    inst = emit(TCS_OPCODE_THREAD_END);
 160    inst->base_mrf = 14;
 161    inst->mlen = 2;
 162 }
 163
 164
 165 void
 166 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 167                                       const src_reg &vertex_index,
 168                                       unsigned base_offset,
 169                                       const src_reg &indirect_offset)
 170 {
 171    vec4_instruction *inst;
 172    dst_reg temp(this, glsl_type::ivec4_type);
 173    temp.type = dst.type;
 174
 175    /* Set up the message header to reference the proper parts of the URB */
 176    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 177    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 178                indirect_offset);
 179    inst->force_writemask_all = true;
 180
 181    /* Read into a temporary, ignoring writemasking. */
 182    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 183    inst->offset = base_offset;
 184    inst->mlen = 1;
 185    inst->base_mrf = -1;
 186
 187    /* Copy the temporary to the destination to deal with writemasking.
 188     *
 189     * Also attempt to deal with gl_PointSize being in the .w component.
 190     */
 191    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 192       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 193    } else {
 194       emit(MOV(dst, src_reg(temp)));
 195    }
 196 }
 197
 198 void
 199 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 200                                        unsigned base_offset,
 201                                        const src_reg &indirect_offset)
 202 {
 203    vec4_instruction *inst;
 204
 205    /* Set up the message header to reference the proper parts of the URB */
 206    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 207    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 208                brw_imm_ud(dst.writemask), indirect_offset);
 209    inst->force_writemask_all = true;
 210
 211    /* Read into a temporary, ignoring writemasking. */
 212    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 213    read->offset = base_offset;
 214    read->mlen = 1;
 215    read->base_mrf = -1;
 216 }
 217
 218 void
 219 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 220                                  unsigned writemask,
 221                                  unsigned base_offset,
 222                                  const src_reg &indirect_offset)
 223 {
 224    if (writemask == 0)
 225       return;
 226
 227    src_reg message(this, glsl_type::uvec4_type, 2);
 228    vec4_instruction *inst;
 229
 230    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 231                brw_imm_ud(writemask), indirect_offset);
 232    inst->force_writemask_all = true;
 233    inst = emit(MOV(offset(dst_reg(retype(message, value.type)), 1), value));
 234    inst->force_writemask_all = true;
 235
 236    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 237    inst->offset = base_offset;
 238    inst->mlen = 2;
 239    inst->base_mrf = -1;
 240 }
 241
 242 void
 243 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 244 {
 245    switch (instr->intrinsic) {
 246    case nir_intrinsic_load_invocation_id:
 247       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 248                invocation_id));
 249       break;
 250    case nir_intrinsic_load_primitive_id:
 251       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 252            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 253       break;
 254    case nir_intrinsic_load_patch_vertices_in:
 255       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 256                brw_imm_d(key->input_vertices)));
 257       break;
 258    case nir_intrinsic_load_per_vertex_input: {
 259       src_reg indirect_offset = get_indirect_offset(instr);
 260       unsigned imm_offset = instr->const_index[0];
 261
 262       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 263       src_reg vertex_index =
 264          vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
 265                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 266
 267       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 268       dst.writemask = brw_writemask_for_size(instr->num_components);
 269
 270       emit_input_urb_read(dst, vertex_index, imm_offset, indirect_offset);
 271       break;
 272    }
 273    case nir_intrinsic_load_input:
 274       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 275       break;
 276    case nir_intrinsic_load_output:
 277    case nir_intrinsic_load_per_vertex_output: {
 278       src_reg indirect_offset = get_indirect_offset(instr);
 279       unsigned imm_offset = instr->const_index[0];
 280
 281       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 282       dst.writemask = brw_writemask_for_size(instr->num_components);
 283
 284       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 285          dst.type = BRW_REGISTER_TYPE_F;
 286
 287          /* This is a read of gl_TessLevelInner[], which lives in the
 288           * Patch URB header.  The layout depends on the domain.
 289           */
 290          switch (key->tes_primitive_mode) {
 291          case GL_QUADS: {
 292             /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
 293             dst_reg tmp(this, glsl_type::vec4_type);
 294             emit_output_urb_read(tmp, 0, src_reg());
 295             emit(MOV(writemask(dst, WRITEMASK_XY),
 296                      swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 297             break;
 298          }
 299          case GL_TRIANGLES:
 300             /* DWord 4; use offset 1 but normal swizzle/writemask. */
 301             emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, src_reg());
 302             break;
 303          case GL_ISOLINES:
 304             /* All channels are undefined. */
 305             return;
 306          default:
 307             unreachable("Bogus tessellation domain");
 308          }
 309       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 310          dst.type = BRW_REGISTER_TYPE_F;
 311          unsigned swiz = BRW_SWIZZLE_WZYX;
 312
 313          /* This is a read of gl_TessLevelOuter[], which lives in the
 314           * high 4 DWords of the Patch URB header, in reverse order.
 315           */
 316          switch (key->tes_primitive_mode) {
 317          case GL_QUADS:
 318             dst.writemask = WRITEMASK_XYZW;
 319             break;
 320          case GL_TRIANGLES:
 321             dst.writemask = WRITEMASK_XYZ;
 322             break;
 323          case GL_ISOLINES:
 324             /* Isolines are not reversed; swizzle .zw -> .xy */
 325             swiz = BRW_SWIZZLE_ZWZW;
 326             dst.writemask = WRITEMASK_XY;
 327             return;
 328          default:
 329             unreachable("Bogus tessellation domain");
 330          }
 331
 332          dst_reg tmp(this, glsl_type::vec4_type);
 333          emit_output_urb_read(tmp, 1, src_reg());
 334          emit(MOV(dst, swizzle(src_reg(tmp), swiz)));
 335       } else {
 336          emit_output_urb_read(dst, imm_offset, indirect_offset);
 337       }
 338       break;
 339    }
 340    case nir_intrinsic_store_output:
 341    case nir_intrinsic_store_per_vertex_output: {
 342       src_reg value = get_nir_src(instr->src[0]);
 343       unsigned mask = instr->const_index[1];
 344       unsigned swiz = BRW_SWIZZLE_XYZW;
 345
 346       src_reg indirect_offset = get_indirect_offset(instr);
 347       unsigned imm_offset = instr->const_index[0];
 348
 349       /* The passthrough shader writes the whole patch header as two vec4s;
 350        * skip all the gl_TessLevelInner/Outer swizzling.
 351        */
 352       if (indirect_offset.file == BAD_FILE && !is_passthrough_shader) {
 353          if (imm_offset == 0) {
 354             value.type = BRW_REGISTER_TYPE_F;
 355
 356             mask &=
 357                (1 << tesslevel_inner_components(key->tes_primitive_mode)) - 1;
 358
 359             /* This is a write to gl_TessLevelInner[], which lives in the
 360              * Patch URB header.  The layout depends on the domain.
 361              */
 362             switch (key->tes_primitive_mode) {
 363             case GL_QUADS:
 364                /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
 365                 * We use an XXYX swizzle to reverse put .xy in the .wz
 366                 * channels, and use a .zw writemask.
 367                 */
 368                swiz = BRW_SWIZZLE4(0, 0, 1, 0);
 369                mask = writemask_for_backwards_vector(mask);
 370                break;
 371             case GL_TRIANGLES:
 372                /* gl_TessLevelInner[].x lives at DWord 4, so we set the
 373                 * writemask to X and bump the URB offset by 1.
 374                 */
 375                imm_offset = 1;
 376                break;
 377             case GL_ISOLINES:
 378                /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
 379                return;
 380             default:
 381                unreachable("Bogus tessellation domain");
 382             }
 383          } else if (imm_offset == 1) {
 384             value.type = BRW_REGISTER_TYPE_F;
 385
 386             mask &=
 387                (1 << tesslevel_outer_components(key->tes_primitive_mode)) - 1;
 388
 389             /* This is a write to gl_TessLevelOuter[] which lives in the
 390              * Patch URB Header at DWords 4-7.  However, it's reversed, so
 391              * instead of .xyzw we have .wzyx.
 392              */
 393             if (key->tes_primitive_mode == GL_ISOLINES) {
 394                /* Isolines .xy should be stored in .zw, in order. */
 395                swiz = BRW_SWIZZLE4(0, 0, 0, 1);
 396                mask <<= 2;
 397             } else {
 398                /* Other domains are reversed; store .wzyx instead of .xyzw. */
 399                swiz = BRW_SWIZZLE_WZYX;
 400                mask = writemask_for_backwards_vector(mask);
 401             }
 402          }
 403       }
 404
 405       emit_urb_write(swizzle(value, swiz), mask,
 406                      imm_offset, indirect_offset);
 407       break;
 408    }
 409
 410    case nir_intrinsic_barrier: {
 411       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 412       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 413       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 414       break;
 415    }
 416
 417    default:
 418       vec4_visitor::nir_emit_intrinsic(instr);
 419    }
 420 }
 421
 422
 423 extern "C" const unsigned *
 424 brw_compile_tcs(const struct brw_compiler *compiler,
 425                 void *log_data,
 426                 void *mem_ctx,
 427                 const struct brw_tcs_prog_key *key,
 428                 struct brw_tcs_prog_data *prog_data,
 429                 const nir_shader *src_shader,
 430                 int shader_time_index,
 431                 unsigned *final_assembly_size,
 432                 char **error_str)
 433 {
 434    const struct brw_device_info *devinfo = compiler->devinfo;
 435    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 436    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 437
 438    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 439    nir->info.outputs_written = key->outputs_written;
 440    nir->info.patch_outputs_written = key->patch_outputs_written;
 441
 442    struct brw_vue_map input_vue_map;
 443    brw_compute_vue_map(devinfo, &input_vue_map,
 444                        nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
 445                        true);
 446
 447    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 448                             nir->info.outputs_written,
 449                             nir->info.patch_outputs_written);
 450
 451    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
 452    brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
 453    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map);
 454    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
 455
 456    if (is_scalar)
 457       prog_data->instances = DIV_ROUND_UP(nir->info.tcs.vertices_out, 8);
 458    else
 459       prog_data->instances = DIV_ROUND_UP(nir->info.tcs.vertices_out, 2);
 460
 461    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 462     * That divides up as follows:
 463     *
 464     *     32 bytes for the patch header (tessellation factors)
 465     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 466     *              gl_MaxTessPatchComponents = 120)
 467     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 468     *              gl_MaxPatchVertices = 32 and
 469     *              gl_MaxTessControlOutputComponents = 128)
 470     *
 471     *  15808 bytes left for varying packing overhead
 472     */
 473    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 474    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 475    unsigned output_size_bytes = 0;
 476    /* Note that the patch header is counted in num_per_patch_slots. */
 477    output_size_bytes += num_per_patch_slots * 16;
 478    output_size_bytes += nir->info.tcs.vertices_out * num_per_vertex_slots * 16;
 479
 480    assert(output_size_bytes >= 1);
 481    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 482       return NULL;
 483
 484    /* URB entry sizes are stored as a multiple of 64 bytes. */
 485    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 486
 487    /* HS does not use the usual payload pushing from URB to GRFs,
 488     * because we don't have enough registers for a full-size payload, and
 489     * the hardware is broken on Haswell anyway.
 490     */
 491    vue_prog_data->urb_read_length = 0;
 492
 493    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 494       fprintf(stderr, "TCS Input ");
 495       brw_print_vue_map(stderr, &input_vue_map);
 496       fprintf(stderr, "TCS Output ");
 497       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 498    }
 499
 500    if (is_scalar) {
 501       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
 502                    &prog_data->base.base, NULL, nir, 8,
 503                    shader_time_index, &input_vue_map);
 504       if (!v.run_tcs_single_patch()) {
 505          if (error_str)
 506             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 507          return NULL;
 508       }
 509
 510       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
 511       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
 512
 513       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
 514                      &prog_data->base.base, v.promoted_constants, false,
 515                      MESA_SHADER_TESS_CTRL);
 516       if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 517          g.enable_debug(ralloc_asprintf(mem_ctx,
 518                                         "%s tessellation control shader %s",
 519                                         nir->info.label ? nir->info.label
 520                                                         : "unnamed",
 521                                         nir->info.name));
 522       }
 523
 524       g.generate_code(v.cfg, 8);
 525
 526       return g.get_assembly(final_assembly_size);
 527    } else {
 528       vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 529                          nir, mem_ctx, shader_time_index, &input_vue_map);
 530       if (!v.run()) {
 531          if (error_str)
 532             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 533          return NULL;
 534       }
 535
 536       if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 537          v.dump_instructions();
 538
 539
 540       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 541                                         &prog_data->base, v.cfg,
 542                                         final_assembly_size);
 543    }
 544 }
 545
 546
 547 } /* namespace brw */