src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32
  33 namespace brw {
  34
  35 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  36                                    void *log_data,
  37                                    const struct brw_tcs_prog_key *key,
  38                                    struct brw_tcs_prog_data *prog_data,
  39                                    const nir_shader *nir,
  40                                    void *mem_ctx,
  41                                    int shader_time_index,
  42                                    const struct brw_vue_map *input_vue_map)
  43    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  44                   nir, mem_ctx, false, shader_time_index),
  45      input_vue_map(input_vue_map), key(key)
  46 {
  47 }
  48
  49
  50 void
  51 vec4_tcs_visitor::emit_nir_code()
  52 {
  53    if (key->program_string_id != 0) {
  54       /* We have a real application-supplied TCS, emit real code. */
  55       vec4_visitor::emit_nir_code();
  56    } else {
  57       /* There is no TCS; automatically generate a passthrough shader
  58        * that writes the API-specified default tessellation levels and
  59        * copies VS outputs to TES inputs.
  60        */
  61       uniforms = 2;
  62
  63       uint64_t varyings = key->outputs_written;
  64
  65       src_reg vertex_offset(this, glsl_type::uint_type);
  66       emit(MUL(dst_reg(vertex_offset), invocation_id,
  67                brw_imm_ud(prog_data->vue_map.num_per_vertex_slots)));
  68
  69       while (varyings != 0) {
  70          const int varying = ffsll(varyings) - 1;
  71
  72          unsigned in_offset = input_vue_map->varying_to_slot[varying];
  73          unsigned out_offset = prog_data->vue_map.varying_to_slot[varying];
  74          assert(out_offset >= 2);
  75
  76          dst_reg val(this, glsl_type::vec4_type);
  77          emit_input_urb_read(val, invocation_id, in_offset, src_reg());
  78          emit_urb_write(src_reg(val), WRITEMASK_XYZW, out_offset,
  79                         vertex_offset);
  80
  81          varyings &= ~BITFIELD64_BIT(varying);
  82       }
  83
  84       /* Only write the tessellation factors from invocation 0.
  85        * There's no point in making other threads do redundant work.
  86        */
  87       emit(CMP(dst_null_d(), invocation_id, brw_imm_ud(0),
  88                BRW_CONDITIONAL_EQ));
  89       emit(IF(BRW_PREDICATE_NORMAL));
  90       emit_urb_write(src_reg(UNIFORM, 0, glsl_type::vec4_type),
  91                      WRITEMASK_XYZW, 0, src_reg());
  92       emit_urb_write(src_reg(UNIFORM, 1, glsl_type::vec4_type),
  93                      WRITEMASK_XYZW, 1, src_reg());
  94       emit(BRW_OPCODE_ENDIF);
  95    }
  96 }
  97
  98 void
  99 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
 100 {
 101 }
 102
 103 dst_reg *
 104 vec4_tcs_visitor::make_reg_for_system_value(int location, const glsl_type *type)
 105 {
 106    return NULL;
 107 }
 108
 109
 110 void
 111 vec4_tcs_visitor::setup_payload()
 112 {
 113    int reg = 0;
 114
 115    /* The payload always contains important data in r0, which contains
 116     * the URB handles that are passed on to the URB write at the end
 117     * of the thread.
 118     */
 119    reg++;
 120
 121    /* r1.0 - r4.7 may contain the input control point URB handles,
 122     * which we use to pull vertex data.
 123     */
 124    reg += 4;
 125
 126    /* Push constants may start at r5.0 */
 127    reg = setup_uniforms(reg);
 128
 129    this->first_non_payload_grf = reg;
 130 }
 131
 132
 133 void
 134 vec4_tcs_visitor::emit_prolog()
 135 {
 136    invocation_id = src_reg(this, glsl_type::uint_type);
 137    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
 138
 139    /* HS threads are dispatched with the dispatch mask set to 0xFF.
 140     * If there are an odd number of output vertices, then the final
 141     * HS instance dispatched will only have its bottom half doing real
 142     * work, and so we need to disable the upper half:
 143     */
 144    if (nir->info.tcs.vertices_out % 2) {
 145       emit(CMP(dst_null_d(), invocation_id,
 146                brw_imm_ud(nir->info.tcs.vertices_out), BRW_CONDITIONAL_L));
 147
 148       /* Matching ENDIF is in emit_thread_end() */
 149       emit(IF(BRW_PREDICATE_NORMAL));
 150    }
 151 }
 152
 153
 154 void
 155 vec4_tcs_visitor::emit_thread_end()
 156 {
 157    vec4_instruction *inst;
 158    current_annotation = "thread end";
 159
 160    if (nir->info.tcs.vertices_out % 2) {
 161       emit(BRW_OPCODE_ENDIF);
 162    }
 163
 164    if (devinfo->gen == 7) {
 165       struct brw_tcs_prog_data *tcs_prog_data =
 166          (struct brw_tcs_prog_data *) prog_data;
 167
 168       current_annotation = "release input vertices";
 169
 170       /* Synchronize all threads, so we know that no one is still
 171        * using the input URB handles.
 172        */
 173       if (tcs_prog_data->instances > 1) {
 174          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 175          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 176          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 177       }
 178
 179       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 180        * We want to compare the bottom half of invocation_id with 0, but
 181        * use that truth value for the top half as well.  Unfortunately,
 182        * we don't have stride in the vec4 world, nor UV immediates in
 183        * align16, so we need an opcode to get invocation_id<0,4,0>.
 184        */
 185       emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(), invocation_id);
 186       emit(IF(BRW_PREDICATE_NORMAL));
 187       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 188          /* If we have an odd number of input vertices, the last will be
 189           * unpaired.  We don't want to use an interleaved URB write in
 190           * that case.
 191           */
 192          const bool is_unpaired = i == key->input_vertices - 1;
 193
 194          dst_reg header(this, glsl_type::uvec4_type);
 195          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 196               brw_imm_ud(is_unpaired));
 197       }
 198       emit(BRW_OPCODE_ENDIF);
 199    }
 200
 201    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 202       emit_shader_time_end();
 203
 204    inst = emit(TCS_OPCODE_THREAD_END);
 205    inst->base_mrf = 14;
 206    inst->mlen = 2;
 207 }
 208
 209
 210 void
 211 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 212                                       const src_reg &vertex_index,
 213                                       unsigned base_offset,
 214                                       const src_reg &indirect_offset)
 215 {
 216    vec4_instruction *inst;
 217    dst_reg temp(this, glsl_type::ivec4_type);
 218    temp.type = dst.type;
 219
 220    /* Set up the message header to reference the proper parts of the URB */
 221    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 222    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 223                indirect_offset);
 224    inst->force_writemask_all = true;
 225
 226    /* Read into a temporary, ignoring writemasking. */
 227    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 228    inst->offset = base_offset;
 229    inst->mlen = 1;
 230    inst->base_mrf = -1;
 231
 232    /* Copy the temporary to the destination to deal with writemasking.
 233     *
 234     * Also attempt to deal with gl_PointSize being in the .w component.
 235     */
 236    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 237       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 238    } else {
 239       emit(MOV(dst, src_reg(temp)));
 240    }
 241 }
 242
 243 void
 244 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 245                                        unsigned base_offset,
 246                                        const src_reg &indirect_offset)
 247 {
 248    vec4_instruction *inst;
 249
 250    /* Set up the message header to reference the proper parts of the URB */
 251    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 252    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 253                brw_imm_ud(dst.writemask), indirect_offset);
 254    inst->force_writemask_all = true;
 255
 256    /* Read into a temporary, ignoring writemasking. */
 257    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 258    read->offset = base_offset;
 259    read->mlen = 1;
 260    read->base_mrf = -1;
 261 }
 262
 263 void
 264 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 265                                  unsigned writemask,
 266                                  unsigned base_offset,
 267                                  const src_reg &indirect_offset)
 268 {
 269    if (writemask == 0)
 270       return;
 271
 272    src_reg message(this, glsl_type::uvec4_type, 2);
 273    vec4_instruction *inst;
 274
 275    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 276                brw_imm_ud(writemask), indirect_offset);
 277    inst->force_writemask_all = true;
 278    inst = emit(MOV(offset(dst_reg(retype(message, value.type)), 1), value));
 279    inst->force_writemask_all = true;
 280
 281    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 282    inst->offset = base_offset;
 283    inst->mlen = 2;
 284    inst->base_mrf = -1;
 285 }
 286
 287 static unsigned
 288 tesslevel_outer_components(GLenum tes_primitive_mode)
 289 {
 290    switch (tes_primitive_mode) {
 291    case GL_QUADS:
 292       return 4;
 293    case GL_TRIANGLES:
 294       return 3;
 295    case GL_ISOLINES:
 296       return 2;
 297    default:
 298       unreachable("Bogus tessellation domain");
 299    }
 300    return 0;
 301 }
 302
 303 static unsigned
 304 tesslevel_inner_components(GLenum tes_primitive_mode)
 305 {
 306    switch (tes_primitive_mode) {
 307    case GL_QUADS:
 308       return 2;
 309    case GL_TRIANGLES:
 310       return 1;
 311    case GL_ISOLINES:
 312       return 0;
 313    default:
 314       unreachable("Bogus tessellation domain");
 315    }
 316    return 0;
 317 }
 318
 319 /**
 320  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 321  * that's stored backwards, i.e. .wzyx.
 322  */
 323 static unsigned
 324 writemask_for_backwards_vector(unsigned mask)
 325 {
 326    unsigned new_mask = 0;
 327
 328    for (int i = 0; i < 4; i++)
 329       new_mask |= ((mask >> i) & 1) << (3 - i);
 330
 331    return new_mask;
 332 }
 333
 334 void
 335 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 336 {
 337    switch (instr->intrinsic) {
 338    case nir_intrinsic_load_invocation_id:
 339       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 340                invocation_id));
 341       break;
 342    case nir_intrinsic_load_primitive_id:
 343       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 344            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 345       break;
 346    case nir_intrinsic_load_patch_vertices_in:
 347       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 348                brw_imm_d(key->input_vertices)));
 349       break;
 350    case nir_intrinsic_load_per_vertex_input: {
 351       src_reg indirect_offset = get_indirect_offset(instr);
 352       unsigned imm_offset = instr->const_index[0];
 353
 354       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 355       src_reg vertex_index =
 356          vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
 357                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 358
 359       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 360       dst.writemask = brw_writemask_for_size(instr->num_components);
 361
 362       emit_input_urb_read(dst, vertex_index, imm_offset, indirect_offset);
 363       break;
 364    }
 365    case nir_intrinsic_load_input:
 366       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 367       break;
 368    case nir_intrinsic_load_output:
 369    case nir_intrinsic_load_per_vertex_output: {
 370       src_reg indirect_offset = get_indirect_offset(instr);
 371       unsigned imm_offset = instr->const_index[0];;
 372
 373       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 374       dst.writemask = brw_writemask_for_size(instr->num_components);
 375
 376       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 377          dst.type = BRW_REGISTER_TYPE_F;
 378
 379          /* This is a read of gl_TessLevelInner[], which lives in the
 380           * Patch URB header.  The layout depends on the domain.
 381           */
 382          switch (key->tes_primitive_mode) {
 383          case GL_QUADS: {
 384             /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
 385             dst_reg tmp(this, glsl_type::vec4_type);
 386             emit_output_urb_read(tmp, 0, src_reg());
 387             emit(MOV(writemask(dst, WRITEMASK_XY),
 388                      swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 389             break;
 390          }
 391          case GL_TRIANGLES:
 392             /* DWord 4; use offset 1 but normal swizzle/writemask. */
 393             emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, src_reg());
 394             break;
 395          case GL_ISOLINES:
 396             /* All channels are undefined. */
 397             return;
 398          default:
 399             unreachable("Bogus tessellation domain");
 400          }
 401       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 402          dst.type = BRW_REGISTER_TYPE_F;
 403          unsigned swiz = BRW_SWIZZLE_WZYX;
 404
 405          /* This is a read of gl_TessLevelOuter[], which lives in the
 406           * high 4 DWords of the Patch URB header, in reverse order.
 407           */
 408          switch (key->tes_primitive_mode) {
 409          case GL_QUADS:
 410             dst.writemask = WRITEMASK_XYZW;
 411             break;
 412          case GL_TRIANGLES:
 413             dst.writemask = WRITEMASK_XYZ;
 414             break;
 415          case GL_ISOLINES:
 416             /* Isolines are not reversed; swizzle .zw -> .xy */
 417             swiz = BRW_SWIZZLE_ZWZW;
 418             dst.writemask = WRITEMASK_XY;
 419             return;
 420          default:
 421             unreachable("Bogus tessellation domain");
 422          }
 423
 424          dst_reg tmp(this, glsl_type::vec4_type);
 425          emit_output_urb_read(tmp, 1, src_reg());
 426          emit(MOV(dst, swizzle(src_reg(tmp), swiz)));
 427       } else {
 428          emit_output_urb_read(dst, imm_offset, indirect_offset);
 429       }
 430       break;
 431    }
 432    case nir_intrinsic_store_output:
 433    case nir_intrinsic_store_per_vertex_output: {
 434       src_reg value = get_nir_src(instr->src[0]);
 435       unsigned mask = instr->const_index[1];
 436       unsigned swiz = BRW_SWIZZLE_XYZW;
 437
 438       src_reg indirect_offset = get_indirect_offset(instr);
 439       unsigned imm_offset = instr->const_index[0];
 440
 441       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 442          value.type = BRW_REGISTER_TYPE_F;
 443
 444          mask &= (1 << tesslevel_inner_components(key->tes_primitive_mode)) - 1;
 445
 446          /* This is a write to gl_TessLevelInner[], which lives in the
 447           * Patch URB header.  The layout depends on the domain.
 448           */
 449          switch (key->tes_primitive_mode) {
 450          case GL_QUADS:
 451             /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
 452              * We use an XXYX swizzle to reverse put .xy in the .wz
 453              * channels, and use a .zw writemask.
 454              */
 455             swiz = BRW_SWIZZLE4(0, 0, 1, 0);
 456             mask = writemask_for_backwards_vector(mask);
 457             break;
 458          case GL_TRIANGLES:
 459             /* gl_TessLevelInner[].x lives at DWord 4, so we set the
 460              * writemask to X and bump the URB offset by 1.
 461              */
 462             imm_offset = 1;
 463             break;
 464          case GL_ISOLINES:
 465             /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
 466             return;
 467          default:
 468             unreachable("Bogus tessellation domain");
 469          }
 470       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 471          value.type = BRW_REGISTER_TYPE_F;
 472
 473          mask &= (1 << tesslevel_outer_components(key->tes_primitive_mode)) - 1;
 474
 475          /* This is a write to gl_TessLevelOuter[] which lives in the
 476           * Patch URB Header at DWords 4-7.  However, it's reversed, so
 477           * instead of .xyzw we have .wzyx.
 478           */
 479          if (key->tes_primitive_mode == GL_ISOLINES) {
 480             /* Isolines .xy should be stored in .zw, in order. */
 481             swiz = BRW_SWIZZLE4(0, 0, 0, 1);
 482             mask <<= 2;
 483          } else {
 484             /* Other domains are reversed; store .wzyx instead of .xyzw. */
 485             swiz = BRW_SWIZZLE_WZYX;
 486             mask = writemask_for_backwards_vector(mask);
 487          }
 488       }
 489
 490       emit_urb_write(swizzle(value, swiz), mask,
 491                      imm_offset, indirect_offset);
 492       break;
 493    }
 494
 495    case nir_intrinsic_barrier: {
 496       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 497       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 498       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 499       break;
 500    }
 501
 502    default:
 503       vec4_visitor::nir_emit_intrinsic(instr);
 504    }
 505 }
 506
 507
 508 extern "C" const unsigned *
 509 brw_compile_tcs(const struct brw_compiler *compiler,
 510                 void *log_data,
 511                 void *mem_ctx,
 512                 const struct brw_tcs_prog_key *key,
 513                 struct brw_tcs_prog_data *prog_data,
 514                 const nir_shader *src_shader,
 515                 int shader_time_index,
 516                 unsigned *final_assembly_size,
 517                 char **error_str)
 518 {
 519    const struct brw_device_info *devinfo = compiler->devinfo;
 520    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 521    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 522
 523    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 524    nir->info.outputs_written = key->outputs_written;
 525    nir->info.patch_outputs_written = key->patch_outputs_written;
 526
 527    struct brw_vue_map input_vue_map;
 528    brw_compute_vue_map(devinfo, &input_vue_map,
 529                        nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
 530                        true);
 531
 532    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 533                             nir->info.outputs_written,
 534                             nir->info.patch_outputs_written);
 535
 536    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
 537    brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
 538    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map);
 539    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
 540
 541    prog_data->instances = DIV_ROUND_UP(nir->info.tcs.vertices_out, 2);
 542
 543    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 544     * That divides up as follows:
 545     *
 546     *     32 bytes for the patch header (tessellation factors)
 547     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 548     *              gl_MaxTessPatchComponents = 120)
 549     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 550     *              gl_MaxPatchVertices = 32 and
 551     *              gl_MaxTessControlOutputComponents = 128)
 552     *
 553     *  15808 bytes left for varying packing overhead
 554     */
 555    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 556    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 557    unsigned output_size_bytes = 0;
 558    /* Note that the patch header is counted in num_per_patch_slots. */
 559    output_size_bytes += num_per_patch_slots * 16;
 560    output_size_bytes += nir->info.tcs.vertices_out * num_per_vertex_slots * 16;
 561
 562    assert(output_size_bytes >= 1);
 563    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 564       return NULL;
 565
 566    /* URB entry sizes are stored as a multiple of 64 bytes. */
 567    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 568
 569    /* HS does not use the usual payload pushing from URB to GRFs,
 570     * because we don't have enough registers for a full-size payload, and
 571     * the hardware is broken on Haswell anyway.
 572     */
 573    vue_prog_data->urb_read_length = 0;
 574
 575    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 576       fprintf(stderr, "TCS Input ");
 577       brw_print_vue_map(stderr, &input_vue_map);
 578       fprintf(stderr, "TCS Output ");
 579       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 580    }
 581
 582    vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 583                       nir, mem_ctx, shader_time_index, &input_vue_map);
 584    if (!v.run()) {
 585       if (error_str)
 586          *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 587       return NULL;
 588    }
 589
 590    if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 591       v.dump_instructions();
 592
 593    return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 594                                      &prog_data->base, v.cfg,
 595                                      final_assembly_size);
 596 }
 597
 598
 599 } /* namespace brw */