src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32
  33 namespace brw {
  34
  35 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  36                                    void *log_data,
  37                                    const struct brw_tcs_prog_key *key,
  38                                    struct brw_tcs_prog_data *prog_data,
  39                                    const nir_shader *nir,
  40                                    void *mem_ctx,
  41                                    int shader_time_index,
  42                                    const struct brw_vue_map *input_vue_map)
  43    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  44                   nir, mem_ctx, false, shader_time_index),
  45      input_vue_map(input_vue_map), key(key)
  46 {
  47 }
  48
  49
  50 void
  51 vec4_tcs_visitor::emit_nir_code()
  52 {
  53    if (key->program_string_id != 0) {
  54       /* We have a real application-supplied TCS, emit real code. */
  55       vec4_visitor::emit_nir_code();
  56    } else {
  57       /* There is no TCS; automatically generate a passthrough shader
  58        * that writes the API-specified default tessellation levels and
  59        * copies VS outputs to TES inputs.
  60        */
  61       uniforms = 2;
  62
  63       uint64_t varyings = key->outputs_written;
  64
  65       src_reg vertex_offset(this, glsl_type::uint_type);
  66       emit(MUL(dst_reg(vertex_offset), invocation_id,
  67                brw_imm_ud(prog_data->vue_map.num_per_vertex_slots)));
  68
  69       while (varyings != 0) {
  70          const int varying = ffsll(varyings) - 1;
  71
  72          unsigned in_offset = input_vue_map->varying_to_slot[varying];
  73          unsigned out_offset = prog_data->vue_map.varying_to_slot[varying];
  74          assert(out_offset >= 2);
  75
  76          dst_reg val(this, glsl_type::vec4_type);
  77          emit_input_urb_read(val, invocation_id, in_offset, src_reg());
  78          emit_urb_write(src_reg(val), WRITEMASK_XYZW, out_offset,
  79                         vertex_offset);
  80
  81          varyings &= ~BITFIELD64_BIT(varying);
  82       }
  83
  84       /* Only write the tessellation factors from invocation 0.
  85        * There's no point in making other threads do redundant work.
  86        */
  87       emit(CMP(dst_null_d(), invocation_id, brw_imm_ud(0),
  88                BRW_CONDITIONAL_EQ));
  89       emit(IF(BRW_PREDICATE_NORMAL));
  90       emit_urb_write(src_reg(UNIFORM, 0, glsl_type::vec4_type),
  91                      WRITEMASK_XYZW, 0, src_reg());
  92       emit_urb_write(src_reg(UNIFORM, 1, glsl_type::vec4_type),
  93                      WRITEMASK_XYZW, 1, src_reg());
  94       emit(BRW_OPCODE_ENDIF);
  95    }
  96 }
  97
  98 void
  99 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
 100 {
 101 }
 102
 103 dst_reg *
 104 vec4_tcs_visitor::make_reg_for_system_value(int location, const glsl_type *type)
 105 {
 106    return NULL;
 107 }
 108
 109
 110 void
 111 vec4_tcs_visitor::setup_payload()
 112 {
 113    int reg = 0;
 114
 115    /* The payload always contains important data in r0, which contains
 116     * the URB handles that are passed on to the URB write at the end
 117     * of the thread.
 118     */
 119    reg++;
 120
 121    /* r1.0 - r4.7 may contain the input control point URB handles,
 122     * which we use to pull vertex data.
 123     */
 124    reg += 4;
 125
 126    /* Push constants may start at r5.0 */
 127    reg = setup_uniforms(reg);
 128
 129    this->first_non_payload_grf = reg;
 130 }
 131
 132
 133 void
 134 vec4_tcs_visitor::emit_prolog()
 135 {
 136    invocation_id = src_reg(this, glsl_type::uint_type);
 137    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
 138
 139    /* HS threads are dispatched with the dispatch mask set to 0xFF.
 140     * If there are an odd number of output vertices, then the final
 141     * HS instance dispatched will only have its bottom half doing real
 142     * work, and so we need to disable the upper half:
 143     */
 144    if (nir->info.tcs.vertices_out % 2) {
 145       emit(CMP(dst_null_d(), invocation_id,
 146                brw_imm_ud(nir->info.tcs.vertices_out), BRW_CONDITIONAL_L));
 147
 148       /* Matching ENDIF is in emit_thread_end() */
 149       emit(IF(BRW_PREDICATE_NORMAL));
 150    }
 151 }
 152
 153
 154 void
 155 vec4_tcs_visitor::emit_thread_end()
 156 {
 157    vec4_instruction *inst;
 158    current_annotation = "thread end";
 159
 160    if (nir->info.tcs.vertices_out % 2) {
 161       emit(BRW_OPCODE_ENDIF);
 162    }
 163
 164    if (devinfo->gen == 7) {
 165       struct brw_tcs_prog_data *tcs_prog_data =
 166          (struct brw_tcs_prog_data *) prog_data;
 167
 168       current_annotation = "release input vertices";
 169
 170       /* Synchronize all threads, so we know that no one is still
 171        * using the input URB handles.
 172        */
 173       if (tcs_prog_data->instances > 1) {
 174          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 175          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 176          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 177       }
 178
 179       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 180        * We want to compare the bottom half of invocation_id with 0, but
 181        * use that truth value for the top half as well.  Unfortunately,
 182        * we don't have stride in the vec4 world, nor UV immediates in
 183        * align16, so we need an opcode to get invocation_id<0,4,0>.
 184        */
 185       set_condmod(BRW_CONDITIONAL_Z,
 186                   emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
 187                        invocation_id));
 188       emit(IF(BRW_PREDICATE_NORMAL));
 189       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 190          /* If we have an odd number of input vertices, the last will be
 191           * unpaired.  We don't want to use an interleaved URB write in
 192           * that case.
 193           */
 194          const bool is_unpaired = i == key->input_vertices - 1;
 195
 196          dst_reg header(this, glsl_type::uvec4_type);
 197          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 198               brw_imm_ud(is_unpaired));
 199       }
 200       emit(BRW_OPCODE_ENDIF);
 201    }
 202
 203    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 204       emit_shader_time_end();
 205
 206    inst = emit(TCS_OPCODE_THREAD_END);
 207    inst->base_mrf = 14;
 208    inst->mlen = 2;
 209 }
 210
 211
 212 void
 213 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 214                                       const src_reg &vertex_index,
 215                                       unsigned base_offset,
 216                                       const src_reg &indirect_offset)
 217 {
 218    vec4_instruction *inst;
 219    dst_reg temp(this, glsl_type::ivec4_type);
 220    temp.type = dst.type;
 221
 222    /* Set up the message header to reference the proper parts of the URB */
 223    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 224    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 225                indirect_offset);
 226    inst->force_writemask_all = true;
 227
 228    /* Read into a temporary, ignoring writemasking. */
 229    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 230    inst->offset = base_offset;
 231    inst->mlen = 1;
 232    inst->base_mrf = -1;
 233
 234    /* Copy the temporary to the destination to deal with writemasking.
 235     *
 236     * Also attempt to deal with gl_PointSize being in the .w component.
 237     */
 238    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 239       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 240    } else {
 241       emit(MOV(dst, src_reg(temp)));
 242    }
 243 }
 244
 245 void
 246 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 247                                        unsigned base_offset,
 248                                        const src_reg &indirect_offset)
 249 {
 250    vec4_instruction *inst;
 251
 252    /* Set up the message header to reference the proper parts of the URB */
 253    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 254    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 255                brw_imm_ud(dst.writemask), indirect_offset);
 256    inst->force_writemask_all = true;
 257
 258    /* Read into a temporary, ignoring writemasking. */
 259    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 260    read->offset = base_offset;
 261    read->mlen = 1;
 262    read->base_mrf = -1;
 263 }
 264
 265 void
 266 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 267                                  unsigned writemask,
 268                                  unsigned base_offset,
 269                                  const src_reg &indirect_offset)
 270 {
 271    if (writemask == 0)
 272       return;
 273
 274    src_reg message(this, glsl_type::uvec4_type, 2);
 275    vec4_instruction *inst;
 276
 277    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 278                brw_imm_ud(writemask), indirect_offset);
 279    inst->force_writemask_all = true;
 280    inst = emit(MOV(offset(dst_reg(retype(message, value.type)), 1), value));
 281    inst->force_writemask_all = true;
 282
 283    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 284    inst->offset = base_offset;
 285    inst->mlen = 2;
 286    inst->base_mrf = -1;
 287 }
 288
 289 void
 290 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 291 {
 292    switch (instr->intrinsic) {
 293    case nir_intrinsic_load_invocation_id:
 294       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 295                invocation_id));
 296       break;
 297    case nir_intrinsic_load_primitive_id:
 298       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 299            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 300       break;
 301    case nir_intrinsic_load_patch_vertices_in:
 302       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 303                brw_imm_d(key->input_vertices)));
 304       break;
 305    case nir_intrinsic_load_per_vertex_input: {
 306       src_reg indirect_offset = get_indirect_offset(instr);
 307       unsigned imm_offset = instr->const_index[0];
 308
 309       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 310       src_reg vertex_index =
 311          vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
 312                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 313
 314       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 315       dst.writemask = brw_writemask_for_size(instr->num_components);
 316
 317       emit_input_urb_read(dst, vertex_index, imm_offset, indirect_offset);
 318       break;
 319    }
 320    case nir_intrinsic_load_input:
 321       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 322       break;
 323    case nir_intrinsic_load_output:
 324    case nir_intrinsic_load_per_vertex_output: {
 325       src_reg indirect_offset = get_indirect_offset(instr);
 326       unsigned imm_offset = instr->const_index[0];
 327
 328       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 329       dst.writemask = brw_writemask_for_size(instr->num_components);
 330
 331       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 332          dst.type = BRW_REGISTER_TYPE_F;
 333
 334          /* This is a read of gl_TessLevelInner[], which lives in the
 335           * Patch URB header.  The layout depends on the domain.
 336           */
 337          switch (key->tes_primitive_mode) {
 338          case GL_QUADS: {
 339             /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
 340             dst_reg tmp(this, glsl_type::vec4_type);
 341             emit_output_urb_read(tmp, 0, src_reg());
 342             emit(MOV(writemask(dst, WRITEMASK_XY),
 343                      swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 344             break;
 345          }
 346          case GL_TRIANGLES:
 347             /* DWord 4; use offset 1 but normal swizzle/writemask. */
 348             emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, src_reg());
 349             break;
 350          case GL_ISOLINES:
 351             /* All channels are undefined. */
 352             return;
 353          default:
 354             unreachable("Bogus tessellation domain");
 355          }
 356       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 357          dst.type = BRW_REGISTER_TYPE_F;
 358          unsigned swiz = BRW_SWIZZLE_WZYX;
 359
 360          /* This is a read of gl_TessLevelOuter[], which lives in the
 361           * high 4 DWords of the Patch URB header, in reverse order.
 362           */
 363          switch (key->tes_primitive_mode) {
 364          case GL_QUADS:
 365             dst.writemask = WRITEMASK_XYZW;
 366             break;
 367          case GL_TRIANGLES:
 368             dst.writemask = WRITEMASK_XYZ;
 369             break;
 370          case GL_ISOLINES:
 371             /* Isolines are not reversed; swizzle .zw -> .xy */
 372             swiz = BRW_SWIZZLE_ZWZW;
 373             dst.writemask = WRITEMASK_XY;
 374             return;
 375          default:
 376             unreachable("Bogus tessellation domain");
 377          }
 378
 379          dst_reg tmp(this, glsl_type::vec4_type);
 380          emit_output_urb_read(tmp, 1, src_reg());
 381          emit(MOV(dst, swizzle(src_reg(tmp), swiz)));
 382       } else {
 383          emit_output_urb_read(dst, imm_offset, indirect_offset);
 384       }
 385       break;
 386    }
 387    case nir_intrinsic_store_output:
 388    case nir_intrinsic_store_per_vertex_output: {
 389       src_reg value = get_nir_src(instr->src[0]);
 390       unsigned mask = instr->const_index[1];
 391       unsigned swiz = BRW_SWIZZLE_XYZW;
 392
 393       src_reg indirect_offset = get_indirect_offset(instr);
 394       unsigned imm_offset = instr->const_index[0];
 395
 396       if (indirect_offset.file == BAD_FILE) {
 397          if (imm_offset == 0) {
 398             value.type = BRW_REGISTER_TYPE_F;
 399
 400             mask &=
 401                (1 << tesslevel_inner_components(key->tes_primitive_mode)) - 1;
 402
 403             /* This is a write to gl_TessLevelInner[], which lives in the
 404              * Patch URB header.  The layout depends on the domain.
 405              */
 406             switch (key->tes_primitive_mode) {
 407             case GL_QUADS:
 408                /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
 409                 * We use an XXYX swizzle to reverse put .xy in the .wz
 410                 * channels, and use a .zw writemask.
 411                 */
 412                swiz = BRW_SWIZZLE4(0, 0, 1, 0);
 413                mask = writemask_for_backwards_vector(mask);
 414                break;
 415             case GL_TRIANGLES:
 416                /* gl_TessLevelInner[].x lives at DWord 4, so we set the
 417                 * writemask to X and bump the URB offset by 1.
 418                 */
 419                imm_offset = 1;
 420                break;
 421             case GL_ISOLINES:
 422                /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
 423                return;
 424             default:
 425                unreachable("Bogus tessellation domain");
 426             }
 427          } else if (imm_offset == 1) {
 428             value.type = BRW_REGISTER_TYPE_F;
 429
 430             mask &=
 431                (1 << tesslevel_outer_components(key->tes_primitive_mode)) - 1;
 432
 433             /* This is a write to gl_TessLevelOuter[] which lives in the
 434              * Patch URB Header at DWords 4-7.  However, it's reversed, so
 435              * instead of .xyzw we have .wzyx.
 436              */
 437             if (key->tes_primitive_mode == GL_ISOLINES) {
 438                /* Isolines .xy should be stored in .zw, in order. */
 439                swiz = BRW_SWIZZLE4(0, 0, 0, 1);
 440                mask <<= 2;
 441             } else {
 442                /* Other domains are reversed; store .wzyx instead of .xyzw. */
 443                swiz = BRW_SWIZZLE_WZYX;
 444                mask = writemask_for_backwards_vector(mask);
 445             }
 446          }
 447       }
 448
 449       emit_urb_write(swizzle(value, swiz), mask,
 450                      imm_offset, indirect_offset);
 451       break;
 452    }
 453
 454    case nir_intrinsic_barrier: {
 455       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 456       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 457       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 458       break;
 459    }
 460
 461    default:
 462       vec4_visitor::nir_emit_intrinsic(instr);
 463    }
 464 }
 465
 466
 467 extern "C" const unsigned *
 468 brw_compile_tcs(const struct brw_compiler *compiler,
 469                 void *log_data,
 470                 void *mem_ctx,
 471                 const struct brw_tcs_prog_key *key,
 472                 struct brw_tcs_prog_data *prog_data,
 473                 const nir_shader *src_shader,
 474                 int shader_time_index,
 475                 unsigned *final_assembly_size,
 476                 char **error_str)
 477 {
 478    const struct brw_device_info *devinfo = compiler->devinfo;
 479    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 480    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 481
 482    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 483    nir->info.outputs_written = key->outputs_written;
 484    nir->info.patch_outputs_written = key->patch_outputs_written;
 485
 486    struct brw_vue_map input_vue_map;
 487    brw_compute_vue_map(devinfo, &input_vue_map,
 488                        nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
 489                        true);
 490
 491    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 492                             nir->info.outputs_written,
 493                             nir->info.patch_outputs_written);
 494
 495    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
 496    brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
 497    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map);
 498    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
 499
 500    prog_data->instances = DIV_ROUND_UP(nir->info.tcs.vertices_out, 2);
 501
 502    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 503     * That divides up as follows:
 504     *
 505     *     32 bytes for the patch header (tessellation factors)
 506     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 507     *              gl_MaxTessPatchComponents = 120)
 508     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 509     *              gl_MaxPatchVertices = 32 and
 510     *              gl_MaxTessControlOutputComponents = 128)
 511     *
 512     *  15808 bytes left for varying packing overhead
 513     */
 514    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 515    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 516    unsigned output_size_bytes = 0;
 517    /* Note that the patch header is counted in num_per_patch_slots. */
 518    output_size_bytes += num_per_patch_slots * 16;
 519    output_size_bytes += nir->info.tcs.vertices_out * num_per_vertex_slots * 16;
 520
 521    assert(output_size_bytes >= 1);
 522    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 523       return NULL;
 524
 525    /* URB entry sizes are stored as a multiple of 64 bytes. */
 526    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 527
 528    /* HS does not use the usual payload pushing from URB to GRFs,
 529     * because we don't have enough registers for a full-size payload, and
 530     * the hardware is broken on Haswell anyway.
 531     */
 532    vue_prog_data->urb_read_length = 0;
 533
 534    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 535       fprintf(stderr, "TCS Input ");
 536       brw_print_vue_map(stderr, &input_vue_map);
 537       fprintf(stderr, "TCS Output ");
 538       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 539    }
 540
 541    vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 542                       nir, mem_ctx, shader_time_index, &input_vue_map);
 543    if (!v.run()) {
 544       if (error_str)
 545          *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 546       return NULL;
 547    }
 548
 549    if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 550       v.dump_instructions();
 551
 552    return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 553                                      &prog_data->base, v.cfg,
 554                                      final_assembly_size);
 555 }
 556
 557
 558 } /* namespace brw */