src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32
  33 namespace brw {
  34
  35 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  36                                    void *log_data,
  37                                    const struct brw_tcs_prog_key *key,
  38                                    struct brw_tcs_prog_data *prog_data,
  39                                    const nir_shader *nir,
  40                                    void *mem_ctx,
  41                                    int shader_time_index,
  42                                    const struct brw_vue_map *input_vue_map)
  43    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  44                   nir, mem_ctx, false, shader_time_index),
  45      input_vue_map(input_vue_map), key(key)
  46 {
  47 }
  48
  49
  50 void
  51 vec4_tcs_visitor::emit_nir_code()
  52 {
  53    if (key->program_string_id != 0) {
  54       /* We have a real application-supplied TCS, emit real code. */
  55       vec4_visitor::emit_nir_code();
  56    } else {
  57       /* There is no TCS; automatically generate a passthrough shader
  58        * that writes the API-specified default tessellation levels and
  59        * copies VS outputs to TES inputs.
  60        */
  61       uniforms = 2;
  62       uniform_size[0] = 1;
  63       uniform_size[1] = 1;
  64
  65       uint64_t varyings = key->outputs_written;
  66
  67       src_reg vertex_offset(this, glsl_type::uint_type);
  68       emit(MUL(dst_reg(vertex_offset), invocation_id,
  69                brw_imm_ud(prog_data->vue_map.num_per_vertex_slots)));
  70
  71       while (varyings != 0) {
  72          const int varying = ffsll(varyings) - 1;
  73
  74          unsigned in_offset = input_vue_map->varying_to_slot[varying];
  75          unsigned out_offset = prog_data->vue_map.varying_to_slot[varying];
  76          assert(out_offset >= 2);
  77
  78          dst_reg val(this, glsl_type::vec4_type);
  79          emit_input_urb_read(val, invocation_id, in_offset, src_reg());
  80          emit_urb_write(src_reg(val), WRITEMASK_XYZW, out_offset,
  81                         vertex_offset);
  82
  83          varyings &= ~BITFIELD64_BIT(varying);
  84       }
  85
  86       /* Only write the tessellation factors from invocation 0.
  87        * There's no point in making other threads do redundant work.
  88        */
  89       emit(CMP(dst_null_d(), invocation_id, brw_imm_ud(0),
  90                BRW_CONDITIONAL_EQ));
  91       emit(IF(BRW_PREDICATE_NORMAL));
  92       emit_urb_write(src_reg(UNIFORM, 0, glsl_type::vec4_type),
  93                      WRITEMASK_XYZW, 0, src_reg());
  94       emit_urb_write(src_reg(UNIFORM, 1, glsl_type::vec4_type),
  95                      WRITEMASK_XYZW, 1, src_reg());
  96       emit(BRW_OPCODE_ENDIF);
  97    }
  98 }
  99
 100 void
 101 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
 102 {
 103 }
 104
 105 dst_reg *
 106 vec4_tcs_visitor::make_reg_for_system_value(int location, const glsl_type *type)
 107 {
 108    return NULL;
 109 }
 110
 111
 112 void
 113 vec4_tcs_visitor::setup_payload()
 114 {
 115    int reg = 0;
 116
 117    /* The payload always contains important data in r0, which contains
 118     * the URB handles that are passed on to the URB write at the end
 119     * of the thread.
 120     */
 121    reg++;
 122
 123    /* r1.0 - r4.7 may contain the input control point URB handles,
 124     * which we use to pull vertex data.
 125     */
 126    reg += 4;
 127
 128    /* Push constants may start at r5.0 */
 129    reg = setup_uniforms(reg);
 130
 131    this->first_non_payload_grf = reg;
 132 }
 133
 134
 135 void
 136 vec4_tcs_visitor::emit_prolog()
 137 {
 138    invocation_id = src_reg(this, glsl_type::uint_type);
 139    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
 140
 141    /* HS threads are dispatched with the dispatch mask set to 0xFF.
 142     * If there are an odd number of output vertices, then the final
 143     * HS instance dispatched will only have its bottom half doing real
 144     * work, and so we need to disable the upper half:
 145     */
 146    if (nir->info.tcs.vertices_out % 2) {
 147       emit(CMP(dst_null_d(), invocation_id,
 148                brw_imm_ud(nir->info.tcs.vertices_out), BRW_CONDITIONAL_L));
 149
 150       /* Matching ENDIF is in emit_thread_end() */
 151       emit(IF(BRW_PREDICATE_NORMAL));
 152    }
 153 }
 154
 155
 156 void
 157 vec4_tcs_visitor::emit_thread_end()
 158 {
 159    vec4_instruction *inst;
 160    current_annotation = "thread end";
 161
 162    if (nir->info.tcs.vertices_out % 2) {
 163       emit(BRW_OPCODE_ENDIF);
 164    }
 165
 166    if (devinfo->gen == 7) {
 167       struct brw_tcs_prog_data *tcs_prog_data =
 168          (struct brw_tcs_prog_data *) prog_data;
 169
 170       current_annotation = "release input vertices";
 171
 172       /* Synchronize all threads, so we know that no one is still
 173        * using the input URB handles.
 174        */
 175       if (tcs_prog_data->instances > 1) {
 176          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 177          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 178          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 179       }
 180
 181       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 182        * We want to compare the bottom half of invocation_id with 0, but
 183        * use that truth value for the top half as well.  Unfortunately,
 184        * we don't have stride in the vec4 world, nor UV immediates in
 185        * align16, so we need an opcode to get invocation_id<0,4,0>.
 186        */
 187       emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(), invocation_id);
 188       emit(IF(BRW_PREDICATE_NORMAL));
 189       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 190          /* If we have an odd number of input vertices, the last will be
 191           * unpaired.  We don't want to use an interleaved URB write in
 192           * that case.
 193           */
 194          const bool is_unpaired = i == key->input_vertices - 1;
 195
 196          dst_reg header(this, glsl_type::uvec4_type);
 197          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 198               brw_imm_ud(is_unpaired));
 199       }
 200       emit(BRW_OPCODE_ENDIF);
 201    }
 202
 203    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 204       emit_shader_time_end();
 205
 206    inst = emit(TCS_OPCODE_THREAD_END);
 207    inst->base_mrf = 14;
 208    inst->mlen = 2;
 209 }
 210
 211
 212 void
 213 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 214                                       const src_reg &vertex_index,
 215                                       unsigned base_offset,
 216                                       const src_reg &indirect_offset)
 217 {
 218    vec4_instruction *inst;
 219    dst_reg temp(this, glsl_type::ivec4_type);
 220    temp.type = dst.type;
 221
 222    /* Set up the message header to reference the proper parts of the URB */
 223    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 224    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 225                indirect_offset);
 226    inst->force_writemask_all = true;
 227
 228    /* Read into a temporary, ignoring writemasking. */
 229    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 230    inst->offset = base_offset;
 231    inst->mlen = 1;
 232    inst->base_mrf = -1;
 233
 234    /* Copy the temporary to the destination to deal with writemasking.
 235     *
 236     * Also attempt to deal with gl_PointSize being in the .w component.
 237     */
 238    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 239       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 240    } else {
 241       emit(MOV(dst, src_reg(temp)));
 242    }
 243 }
 244
 245 void
 246 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 247                                        unsigned base_offset,
 248                                        const src_reg &indirect_offset)
 249 {
 250    vec4_instruction *inst;
 251
 252    /* Set up the message header to reference the proper parts of the URB */
 253    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 254    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 255                brw_imm_ud(dst.writemask), indirect_offset);
 256    inst->force_writemask_all = true;
 257
 258    /* Read into a temporary, ignoring writemasking. */
 259    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 260    read->offset = base_offset;
 261    read->mlen = 1;
 262    read->base_mrf = -1;
 263 }
 264
 265 void
 266 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 267                                  unsigned writemask,
 268                                  unsigned base_offset,
 269                                  const src_reg &indirect_offset)
 270 {
 271    if (writemask == 0)
 272       return;
 273
 274    src_reg message(this, glsl_type::uvec4_type, 2);
 275    vec4_instruction *inst;
 276
 277    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 278                brw_imm_ud(writemask), indirect_offset);
 279    inst->force_writemask_all = true;
 280    inst = emit(MOV(offset(dst_reg(retype(message, value.type)), 1), value));
 281    inst->force_writemask_all = true;
 282
 283    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 284    inst->offset = base_offset;
 285    inst->mlen = 2;
 286    inst->base_mrf = -1;
 287 }
 288
 289 static unsigned
 290 tesslevel_outer_components(GLenum tes_primitive_mode)
 291 {
 292    switch (tes_primitive_mode) {
 293    case GL_QUADS:
 294       return 4;
 295    case GL_TRIANGLES:
 296       return 3;
 297    case GL_ISOLINES:
 298       return 2;
 299    default:
 300       unreachable("Bogus tessellation domain");
 301    }
 302    return 0;
 303 }
 304
 305 static unsigned
 306 tesslevel_inner_components(GLenum tes_primitive_mode)
 307 {
 308    switch (tes_primitive_mode) {
 309    case GL_QUADS:
 310       return 2;
 311    case GL_TRIANGLES:
 312       return 1;
 313    case GL_ISOLINES:
 314       return 0;
 315    default:
 316       unreachable("Bogus tessellation domain");
 317    }
 318    return 0;
 319 }
 320
 321 /**
 322  * Given a normal .xyzw writemask, convert it to a writemask for a vector
 323  * that's stored backwards, i.e. .wzyx.
 324  */
 325 static unsigned
 326 writemask_for_backwards_vector(unsigned mask)
 327 {
 328    unsigned new_mask = 0;
 329
 330    for (int i = 0; i < 4; i++)
 331       new_mask |= ((mask >> i) & 1) << (3 - i);
 332
 333    return new_mask;
 334 }
 335
 336 void
 337 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 338 {
 339    switch (instr->intrinsic) {
 340    case nir_intrinsic_load_invocation_id:
 341       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 342                invocation_id));
 343       break;
 344    case nir_intrinsic_load_primitive_id:
 345       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 346            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 347       break;
 348    case nir_intrinsic_load_patch_vertices_in:
 349       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 350                brw_imm_d(key->input_vertices)));
 351       break;
 352    case nir_intrinsic_load_per_vertex_input: {
 353       src_reg indirect_offset = get_indirect_offset(instr);
 354       unsigned imm_offset = instr->const_index[0];
 355
 356       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 357       src_reg vertex_index =
 358          vertex_const ? src_reg(brw_imm_ud(vertex_const->u[0]))
 359                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 360
 361       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 362       dst.writemask = brw_writemask_for_size(instr->num_components);
 363
 364       emit_input_urb_read(dst, vertex_index, imm_offset, indirect_offset);
 365       break;
 366    }
 367    case nir_intrinsic_load_input:
 368       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 369       break;
 370    case nir_intrinsic_load_output:
 371    case nir_intrinsic_load_per_vertex_output: {
 372       src_reg indirect_offset = get_indirect_offset(instr);
 373       unsigned imm_offset = instr->const_index[0];;
 374
 375       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 376       dst.writemask = brw_writemask_for_size(instr->num_components);
 377
 378       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 379          dst.type = BRW_REGISTER_TYPE_F;
 380
 381          /* This is a read of gl_TessLevelInner[], which lives in the
 382           * Patch URB header.  The layout depends on the domain.
 383           */
 384          switch (key->tes_primitive_mode) {
 385          case GL_QUADS: {
 386             /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
 387             dst_reg tmp(this, glsl_type::vec4_type);
 388             emit_output_urb_read(tmp, 0, src_reg());
 389             emit(MOV(writemask(dst, WRITEMASK_XY),
 390                      swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 391             break;
 392          }
 393          case GL_TRIANGLES:
 394             /* DWord 4; use offset 1 but normal swizzle/writemask. */
 395             emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, src_reg());
 396             break;
 397          case GL_ISOLINES:
 398             /* All channels are undefined. */
 399             return;
 400          default:
 401             unreachable("Bogus tessellation domain");
 402          }
 403       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 404          dst.type = BRW_REGISTER_TYPE_F;
 405
 406          /* This is a read of gl_TessLevelOuter[], which lives in the
 407           * high 4 DWords of the Patch URB header, in reverse order.
 408           */
 409          switch (key->tes_primitive_mode) {
 410          case GL_QUADS:
 411             dst.writemask = WRITEMASK_XYZW;
 412             break;
 413          case GL_TRIANGLES:
 414             dst.writemask = WRITEMASK_XYZ;
 415             break;
 416          case GL_ISOLINES:
 417             dst.writemask = WRITEMASK_XY;
 418             return;
 419          default:
 420             unreachable("Bogus tessellation domain");
 421          }
 422
 423          dst_reg tmp(this, glsl_type::vec4_type);
 424          emit_output_urb_read(tmp, 1, src_reg());
 425          emit(MOV(dst, swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 426       } else {
 427          emit_output_urb_read(dst, imm_offset, indirect_offset);
 428       }
 429       break;
 430    }
 431    case nir_intrinsic_store_output:
 432    case nir_intrinsic_store_per_vertex_output: {
 433       src_reg value = get_nir_src(instr->src[0]);
 434       unsigned mask = instr->const_index[1];
 435       unsigned swiz = BRW_SWIZZLE_XYZW;
 436
 437       src_reg indirect_offset = get_indirect_offset(instr);
 438       unsigned imm_offset = instr->const_index[0];
 439
 440       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 441          value.type = BRW_REGISTER_TYPE_F;
 442
 443          mask &= (1 << tesslevel_inner_components(key->tes_primitive_mode)) - 1;
 444
 445          /* This is a write to gl_TessLevelInner[], which lives in the
 446           * Patch URB header.  The layout depends on the domain.
 447           */
 448          switch (key->tes_primitive_mode) {
 449          case GL_QUADS:
 450             /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
 451              * We use an XXYX swizzle to reverse put .xy in the .wz
 452              * channels, and use a .zw writemask.
 453              */
 454             swiz = BRW_SWIZZLE4(0, 0, 1, 0);
 455             mask = writemask_for_backwards_vector(mask);
 456             break;
 457          case GL_TRIANGLES:
 458             /* gl_TessLevelInner[].x lives at DWord 4, so we set the
 459              * writemask to X and bump the URB offset by 1.
 460              */
 461             imm_offset = 1;
 462             break;
 463          case GL_ISOLINES:
 464             /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
 465             return;
 466          default:
 467             unreachable("Bogus tessellation domain");
 468          }
 469       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 470          value.type = BRW_REGISTER_TYPE_F;
 471
 472          mask &= (1 << tesslevel_outer_components(key->tes_primitive_mode)) - 1;
 473
 474          /* This is a write to gl_TessLevelOuter[] which lives in the
 475           * Patch URB Header at DWords 4-7.  However, it's reversed, so
 476           * instead of .xyzw we have .wzyx.
 477           */
 478          swiz = BRW_SWIZZLE_WZYX;
 479          mask = writemask_for_backwards_vector(mask);
 480       }
 481
 482       emit_urb_write(swizzle(value, swiz), mask,
 483                      imm_offset, indirect_offset);
 484       break;
 485    }
 486
 487    case nir_intrinsic_barrier: {
 488       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 489       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 490       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 491       break;
 492    }
 493
 494    default:
 495       vec4_visitor::nir_emit_intrinsic(instr);
 496    }
 497 }
 498
 499
 500 extern "C" const unsigned *
 501 brw_compile_tcs(const struct brw_compiler *compiler,
 502                 void *log_data,
 503                 void *mem_ctx,
 504                 const struct brw_tcs_prog_key *key,
 505                 struct brw_tcs_prog_data *prog_data,
 506                 const nir_shader *src_shader,
 507                 int shader_time_index,
 508                 unsigned *final_assembly_size,
 509                 char **error_str)
 510 {
 511    const struct brw_device_info *devinfo = compiler->devinfo;
 512    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 513    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 514
 515    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 516    nir->info.outputs_written = key->outputs_written;
 517    nir->info.patch_outputs_written = key->patch_outputs_written;
 518
 519    struct brw_vue_map input_vue_map;
 520    brw_compute_vue_map(devinfo, &input_vue_map,
 521                        nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
 522                        true);
 523
 524    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 525                             nir->info.outputs_written,
 526                             nir->info.patch_outputs_written);
 527
 528    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
 529    brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
 530    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map);
 531    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
 532
 533    prog_data->instances = DIV_ROUND_UP(nir->info.tcs.vertices_out, 2);
 534
 535    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 536     * That divides up as follows:
 537     *
 538     *     32 bytes for the patch header (tessellation factors)
 539     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 540     *              gl_MaxTessPatchComponents = 120)
 541     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 542     *              gl_MaxPatchVertices = 32 and
 543     *              gl_MaxTessControlOutputComponents = 128)
 544     *
 545     *  15808 bytes left for varying packing overhead
 546     */
 547    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 548    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 549    unsigned output_size_bytes = 0;
 550    /* Note that the patch header is counted in num_per_patch_slots. */
 551    output_size_bytes += num_per_patch_slots * 16;
 552    output_size_bytes += nir->info.tcs.vertices_out * num_per_vertex_slots * 16;
 553
 554    assert(output_size_bytes >= 1);
 555    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 556       return NULL;
 557
 558    /* URB entry sizes are stored as a multiple of 64 bytes. */
 559    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 560
 561    /* HS does not use the usual payload pushing from URB to GRFs,
 562     * because we don't have enough registers for a full-size payload, and
 563     * the hardware is broken on Haswell anyway.
 564     */
 565    vue_prog_data->urb_read_length = 0;
 566
 567    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 568       fprintf(stderr, "TCS Input ");
 569       brw_print_vue_map(stderr, &input_vue_map);
 570       fprintf(stderr, "TCS Output ");
 571       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 572    }
 573
 574    vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 575                       nir, mem_ctx, shader_time_index, &input_vue_map);
 576    if (!v.run()) {
 577       if (error_str)
 578          *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 579       return NULL;
 580    }
 581
 582    if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 583       v.dump_instructions();
 584
 585    return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 586                                      &prog_data->base, v.cfg,
 587                                      final_assembly_size);
 588 }
 589
 590
 591 } /* namespace brw */