src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tcs.cpp
  26  *
  27  * Tessellaton control shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_nir.h"
  31 #include "brw_vec4_tcs.h"
  32 #include "brw_fs.h"
  33
  34 namespace brw {
  35
  36 vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler,
  37                                    void *log_data,
  38                                    const struct brw_tcs_prog_key *key,
  39                                    struct brw_tcs_prog_data *prog_data,
  40                                    const nir_shader *nir,
  41                                    void *mem_ctx,
  42                                    int shader_time_index,
  43                                    const struct brw_vue_map *input_vue_map)
  44    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  45                   nir, mem_ctx, false, shader_time_index),
  46      input_vue_map(input_vue_map), key(key)
  47 {
  48 }
  49
  50
  51 void
  52 vec4_tcs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
  53 {
  54 }
  55
  56 dst_reg *
  57 vec4_tcs_visitor::make_reg_for_system_value(int location)
  58 {
  59    return NULL;
  60 }
  61
  62
  63 void
  64 vec4_tcs_visitor::setup_payload()
  65 {
  66    int reg = 0;
  67
  68    /* The payload always contains important data in r0, which contains
  69     * the URB handles that are passed on to the URB write at the end
  70     * of the thread.
  71     */
  72    reg++;
  73
  74    /* r1.0 - r4.7 may contain the input control point URB handles,
  75     * which we use to pull vertex data.
  76     */
  77    reg += 4;
  78
  79    /* Push constants may start at r5.0 */
  80    reg = setup_uniforms(reg);
  81
  82    this->first_non_payload_grf = reg;
  83 }
  84
  85
  86 void
  87 vec4_tcs_visitor::emit_prolog()
  88 {
  89    invocation_id = src_reg(this, glsl_type::uint_type);
  90    emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id));
  91
  92    /* HS threads are dispatched with the dispatch mask set to 0xFF.
  93     * If there are an odd number of output vertices, then the final
  94     * HS instance dispatched will only have its bottom half doing real
  95     * work, and so we need to disable the upper half:
  96     */
  97    if (nir->info->tcs.vertices_out % 2) {
  98       emit(CMP(dst_null_d(), invocation_id,
  99                brw_imm_ud(nir->info->tcs.vertices_out), BRW_CONDITIONAL_L));
 100
 101       /* Matching ENDIF is in emit_thread_end() */
 102       emit(IF(BRW_PREDICATE_NORMAL));
 103    }
 104 }
 105
 106
 107 void
 108 vec4_tcs_visitor::emit_thread_end()
 109 {
 110    vec4_instruction *inst;
 111    current_annotation = "thread end";
 112
 113    if (nir->info->tcs.vertices_out % 2) {
 114       emit(BRW_OPCODE_ENDIF);
 115    }
 116
 117    if (devinfo->gen == 7) {
 118       struct brw_tcs_prog_data *tcs_prog_data =
 119          (struct brw_tcs_prog_data *) prog_data;
 120
 121       current_annotation = "release input vertices";
 122
 123       /* Synchronize all threads, so we know that no one is still
 124        * using the input URB handles.
 125        */
 126       if (tcs_prog_data->instances > 1) {
 127          dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 128          emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 129          emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 130       }
 131
 132       /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles.
 133        * We want to compare the bottom half of invocation_id with 0, but
 134        * use that truth value for the top half as well.  Unfortunately,
 135        * we don't have stride in the vec4 world, nor UV immediates in
 136        * align16, so we need an opcode to get invocation_id<0,4,0>.
 137        */
 138       set_condmod(BRW_CONDITIONAL_Z,
 139                   emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(),
 140                        invocation_id));
 141       emit(IF(BRW_PREDICATE_NORMAL));
 142       for (unsigned i = 0; i < key->input_vertices; i += 2) {
 143          /* If we have an odd number of input vertices, the last will be
 144           * unpaired.  We don't want to use an interleaved URB write in
 145           * that case.
 146           */
 147          const bool is_unpaired = i == key->input_vertices - 1;
 148
 149          dst_reg header(this, glsl_type::uvec4_type);
 150          emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i),
 151               brw_imm_ud(is_unpaired));
 152       }
 153       emit(BRW_OPCODE_ENDIF);
 154    }
 155
 156    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 157       emit_shader_time_end();
 158
 159    inst = emit(TCS_OPCODE_THREAD_END);
 160    inst->base_mrf = 14;
 161    inst->mlen = 2;
 162 }
 163
 164
 165 void
 166 vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
 167                                       const src_reg &vertex_index,
 168                                       unsigned base_offset,
 169                                       unsigned first_component,
 170                                       const src_reg &indirect_offset)
 171 {
 172    vec4_instruction *inst;
 173    dst_reg temp(this, glsl_type::ivec4_type);
 174    temp.type = dst.type;
 175
 176    /* Set up the message header to reference the proper parts of the URB */
 177    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 178    inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
 179                indirect_offset);
 180    inst->force_writemask_all = true;
 181
 182    /* Read into a temporary, ignoring writemasking. */
 183    inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 184    inst->offset = base_offset;
 185    inst->mlen = 1;
 186    inst->base_mrf = -1;
 187
 188    /* Copy the temporary to the destination to deal with writemasking.
 189     *
 190     * Also attempt to deal with gl_PointSize being in the .w component.
 191     */
 192    if (inst->offset == 0 && indirect_offset.file == BAD_FILE) {
 193       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW)));
 194    } else {
 195       src_reg src = src_reg(temp);
 196       src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
 197       emit(MOV(dst, src));
 198    }
 199 }
 200
 201 void
 202 vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
 203                                        unsigned base_offset,
 204                                        unsigned first_component,
 205                                        const src_reg &indirect_offset)
 206 {
 207    vec4_instruction *inst;
 208
 209    /* Set up the message header to reference the proper parts of the URB */
 210    dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 211    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
 212                brw_imm_ud(dst.writemask), indirect_offset);
 213    inst->force_writemask_all = true;
 214
 215    /* Read into a temporary, ignoring writemasking. */
 216    vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header));
 217    read->offset = base_offset;
 218    read->mlen = 1;
 219    read->base_mrf = -1;
 220
 221    if (first_component) {
 222       src_reg src = src_reg(dst);
 223       src.swizzle = BRW_SWZ_COMP_INPUT(first_component);
 224       emit(MOV(dst, src));
 225    }
 226 }
 227
 228 void
 229 vec4_tcs_visitor::emit_urb_write(const src_reg &value,
 230                                  unsigned writemask,
 231                                  unsigned base_offset,
 232                                  const src_reg &indirect_offset)
 233 {
 234    if (writemask == 0)
 235       return;
 236
 237    src_reg message(this, glsl_type::uvec4_type, 2);
 238    vec4_instruction *inst;
 239
 240    inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
 241                brw_imm_ud(writemask), indirect_offset);
 242    inst->force_writemask_all = true;
 243    inst = emit(MOV(offset(dst_reg(retype(message, value.type)), 1), value));
 244    inst->force_writemask_all = true;
 245
 246    inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
 247    inst->offset = base_offset;
 248    inst->mlen = 2;
 249    inst->base_mrf = -1;
 250 }
 251
 252 void
 253 vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 254 {
 255    switch (instr->intrinsic) {
 256    case nir_intrinsic_load_invocation_id:
 257       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD),
 258                invocation_id));
 259       break;
 260    case nir_intrinsic_load_primitive_id:
 261       emit(TCS_OPCODE_GET_PRIMITIVE_ID,
 262            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 263       break;
 264    case nir_intrinsic_load_patch_vertices_in:
 265       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D),
 266                brw_imm_d(key->input_vertices)));
 267       break;
 268    case nir_intrinsic_load_per_vertex_input: {
 269       src_reg indirect_offset = get_indirect_offset(instr);
 270       unsigned imm_offset = instr->const_index[0];
 271
 272       nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
 273       src_reg vertex_index =
 274          vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
 275                       : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
 276
 277       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 278       dst.writemask = brw_writemask_for_size(instr->num_components);
 279
 280       emit_input_urb_read(dst, vertex_index, imm_offset,
 281                           nir_intrinsic_component(instr), indirect_offset);
 282       break;
 283    }
 284    case nir_intrinsic_load_input:
 285       unreachable("nir_lower_io should use load_per_vertex_input intrinsics");
 286       break;
 287    case nir_intrinsic_load_output:
 288    case nir_intrinsic_load_per_vertex_output: {
 289       src_reg indirect_offset = get_indirect_offset(instr);
 290       unsigned imm_offset = instr->const_index[0];
 291
 292       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 293       dst.writemask = brw_writemask_for_size(instr->num_components);
 294
 295       if (imm_offset == 0 && indirect_offset.file == BAD_FILE) {
 296          dst.type = BRW_REGISTER_TYPE_F;
 297
 298          /* This is a read of gl_TessLevelInner[], which lives in the
 299           * Patch URB header.  The layout depends on the domain.
 300           */
 301          switch (key->tes_primitive_mode) {
 302          case GL_QUADS: {
 303             /* DWords 3-2 (reversed); use offset 0 and WZYX swizzle. */
 304             dst_reg tmp(this, glsl_type::vec4_type);
 305             emit_output_urb_read(tmp, 0, 0, src_reg());
 306             emit(MOV(writemask(dst, WRITEMASK_XY),
 307                      swizzle(src_reg(tmp), BRW_SWIZZLE_WZYX)));
 308             break;
 309          }
 310          case GL_TRIANGLES:
 311             /* DWord 4; use offset 1 but normal swizzle/writemask. */
 312             emit_output_urb_read(writemask(dst, WRITEMASK_X), 1, 0,
 313                                  src_reg());
 314             break;
 315          case GL_ISOLINES:
 316             /* All channels are undefined. */
 317             return;
 318          default:
 319             unreachable("Bogus tessellation domain");
 320          }
 321       } else if (imm_offset == 1 && indirect_offset.file == BAD_FILE) {
 322          dst.type = BRW_REGISTER_TYPE_F;
 323          unsigned swiz = BRW_SWIZZLE_WZYX;
 324
 325          /* This is a read of gl_TessLevelOuter[], which lives in the
 326           * high 4 DWords of the Patch URB header, in reverse order.
 327           */
 328          switch (key->tes_primitive_mode) {
 329          case GL_QUADS:
 330             dst.writemask = WRITEMASK_XYZW;
 331             break;
 332          case GL_TRIANGLES:
 333             dst.writemask = WRITEMASK_XYZ;
 334             break;
 335          case GL_ISOLINES:
 336             /* Isolines are not reversed; swizzle .zw -> .xy */
 337             swiz = BRW_SWIZZLE_ZWZW;
 338             dst.writemask = WRITEMASK_XY;
 339             return;
 340          default:
 341             unreachable("Bogus tessellation domain");
 342          }
 343
 344          dst_reg tmp(this, glsl_type::vec4_type);
 345          emit_output_urb_read(tmp, 1, 0, src_reg());
 346          emit(MOV(dst, swizzle(src_reg(tmp), swiz)));
 347       } else {
 348          emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr),
 349                               indirect_offset);
 350       }
 351       break;
 352    }
 353    case nir_intrinsic_store_output:
 354    case nir_intrinsic_store_per_vertex_output: {
 355       src_reg value = get_nir_src(instr->src[0]);
 356       unsigned mask = instr->const_index[1];
 357       unsigned swiz = BRW_SWIZZLE_XYZW;
 358
 359       src_reg indirect_offset = get_indirect_offset(instr);
 360       unsigned imm_offset = instr->const_index[0];
 361
 362       /* The passthrough shader writes the whole patch header as two vec4s;
 363        * skip all the gl_TessLevelInner/Outer swizzling.
 364        */
 365       if (indirect_offset.file == BAD_FILE && !is_passthrough_shader) {
 366          if (imm_offset == 0) {
 367             value.type = BRW_REGISTER_TYPE_F;
 368
 369             mask &=
 370                (1 << tesslevel_inner_components(key->tes_primitive_mode)) - 1;
 371
 372             /* This is a write to gl_TessLevelInner[], which lives in the
 373              * Patch URB header.  The layout depends on the domain.
 374              */
 375             switch (key->tes_primitive_mode) {
 376             case GL_QUADS:
 377                /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
 378                 * We use an XXYX swizzle to reverse put .xy in the .wz
 379                 * channels, and use a .zw writemask.
 380                 */
 381                swiz = BRW_SWIZZLE4(0, 0, 1, 0);
 382                mask = writemask_for_backwards_vector(mask);
 383                break;
 384             case GL_TRIANGLES:
 385                /* gl_TessLevelInner[].x lives at DWord 4, so we set the
 386                 * writemask to X and bump the URB offset by 1.
 387                 */
 388                imm_offset = 1;
 389                break;
 390             case GL_ISOLINES:
 391                /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
 392                return;
 393             default:
 394                unreachable("Bogus tessellation domain");
 395             }
 396          } else if (imm_offset == 1) {
 397             value.type = BRW_REGISTER_TYPE_F;
 398
 399             mask &=
 400                (1 << tesslevel_outer_components(key->tes_primitive_mode)) - 1;
 401
 402             /* This is a write to gl_TessLevelOuter[] which lives in the
 403              * Patch URB Header at DWords 4-7.  However, it's reversed, so
 404              * instead of .xyzw we have .wzyx.
 405              */
 406             if (key->tes_primitive_mode == GL_ISOLINES) {
 407                /* Isolines .xy should be stored in .zw, in order. */
 408                swiz = BRW_SWIZZLE4(0, 0, 0, 1);
 409                mask <<= 2;
 410             } else {
 411                /* Other domains are reversed; store .wzyx instead of .xyzw. */
 412                swiz = BRW_SWIZZLE_WZYX;
 413                mask = writemask_for_backwards_vector(mask);
 414             }
 415          }
 416       }
 417
 418       unsigned first_component = nir_intrinsic_component(instr);
 419       if (first_component) {
 420          assert(swiz == BRW_SWIZZLE_XYZW);
 421          swiz = BRW_SWZ_COMP_OUTPUT(first_component);
 422          mask = mask << first_component;
 423       }
 424
 425       emit_urb_write(swizzle(value, swiz), mask,
 426                      imm_offset, indirect_offset);
 427       break;
 428    }
 429
 430    case nir_intrinsic_barrier: {
 431       dst_reg header = dst_reg(this, glsl_type::uvec4_type);
 432       emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header);
 433       emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header));
 434       break;
 435    }
 436
 437    default:
 438       vec4_visitor::nir_emit_intrinsic(instr);
 439    }
 440 }
 441
 442
 443 extern "C" const unsigned *
 444 brw_compile_tcs(const struct brw_compiler *compiler,
 445                 void *log_data,
 446                 void *mem_ctx,
 447                 const struct brw_tcs_prog_key *key,
 448                 struct brw_tcs_prog_data *prog_data,
 449                 const nir_shader *src_shader,
 450                 int shader_time_index,
 451                 unsigned *final_assembly_size,
 452                 char **error_str)
 453 {
 454    const struct gen_device_info *devinfo = compiler->devinfo;
 455    struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
 456    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
 457
 458    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
 459    nir->info->outputs_written = key->outputs_written;
 460    nir->info->patch_outputs_written = key->patch_outputs_written;
 461
 462    struct brw_vue_map input_vue_map;
 463    brw_compute_vue_map(devinfo, &input_vue_map,
 464                        nir->info->inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
 465                        true);
 466
 467    brw_compute_tess_vue_map(&vue_prog_data->vue_map,
 468                             nir->info->outputs_written,
 469                             nir->info->patch_outputs_written);
 470
 471    nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
 472    brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map);
 473    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map);
 474    if (key->quads_workaround)
 475       brw_nir_apply_tcs_quads_workaround(nir);
 476
 477    nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
 478
 479    if (is_scalar)
 480       prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 8);
 481    else
 482       prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 2);
 483
 484    /* Compute URB entry size.  The maximum allowed URB entry size is 32k.
 485     * That divides up as follows:
 486     *
 487     *     32 bytes for the patch header (tessellation factors)
 488     *    480 bytes for per-patch varyings (a varying component is 4 bytes and
 489     *              gl_MaxTessPatchComponents = 120)
 490     *  16384 bytes for per-vertex varyings (a varying component is 4 bytes,
 491     *              gl_MaxPatchVertices = 32 and
 492     *              gl_MaxTessControlOutputComponents = 128)
 493     *
 494     *  15808 bytes left for varying packing overhead
 495     */
 496    const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots;
 497    const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots;
 498    unsigned output_size_bytes = 0;
 499    /* Note that the patch header is counted in num_per_patch_slots. */
 500    output_size_bytes += num_per_patch_slots * 16;
 501    output_size_bytes += nir->info->tcs.vertices_out * num_per_vertex_slots * 16;
 502
 503    assert(output_size_bytes >= 1);
 504    if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES)
 505       return NULL;
 506
 507    /* URB entry sizes are stored as a multiple of 64 bytes. */
 508    vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
 509
 510    /* HS does not use the usual payload pushing from URB to GRFs,
 511     * because we don't have enough registers for a full-size payload, and
 512     * the hardware is broken on Haswell anyway.
 513     */
 514    vue_prog_data->urb_read_length = 0;
 515
 516    if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 517       fprintf(stderr, "TCS Input ");
 518       brw_print_vue_map(stderr, &input_vue_map);
 519       fprintf(stderr, "TCS Output ");
 520       brw_print_vue_map(stderr, &vue_prog_data->vue_map);
 521    }
 522
 523    if (is_scalar) {
 524       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
 525                    &prog_data->base.base, NULL, nir, 8,
 526                    shader_time_index, &input_vue_map);
 527       if (!v.run_tcs_single_patch()) {
 528          if (error_str)
 529             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 530          return NULL;
 531       }
 532
 533       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
 534       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
 535
 536       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
 537                      &prog_data->base.base, v.promoted_constants, false,
 538                      MESA_SHADER_TESS_CTRL);
 539       if (unlikely(INTEL_DEBUG & DEBUG_TCS)) {
 540          g.enable_debug(ralloc_asprintf(mem_ctx,
 541                                         "%s tessellation control shader %s",
 542                                         nir->info->label ? nir->info->label
 543                                                         : "unnamed",
 544                                         nir->info->name));
 545       }
 546
 547       g.generate_code(v.cfg, 8);
 548
 549       return g.get_assembly(final_assembly_size);
 550    } else {
 551       vec4_tcs_visitor v(compiler, log_data, key, prog_data,
 552                          nir, mem_ctx, shader_time_index, &input_vue_map);
 553       if (!v.run()) {
 554          if (error_str)
 555             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
 556          return NULL;
 557       }
 558
 559       if (unlikely(INTEL_DEBUG & DEBUG_TCS))
 560          v.dump_instructions();
 561
 562
 563       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
 564                                         &prog_data->base, v.cfg,
 565                                         final_assembly_size);
 566    }
 567 }
 568
 569
 570 } /* namespace brw */