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25 * \file brw_vec4_tes.cpp
27 * Tessellaton evaluation shader specific code derived from the vec4_visitor class.
30 #include "brw_vec4_tes.h"
35 vec4_tes_visitor::vec4_tes_visitor(const struct brw_compiler
*compiler
,
37 const struct brw_tes_prog_key
*key
,
38 struct brw_tes_prog_data
*prog_data
,
39 const nir_shader
*shader
,
41 int shader_time_index
)
42 : vec4_visitor(compiler
, log_data
, &key
->tex
, &prog_data
->base
,
43 shader
, mem_ctx
, false, shader_time_index
)
49 vec4_tes_visitor::make_reg_for_system_value(int location
)
55 vec4_tes_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
57 switch (instr
->intrinsic
) {
58 case nir_intrinsic_load_tess_level_outer
:
59 case nir_intrinsic_load_tess_level_inner
:
62 vec4_visitor::nir_setup_system_value_intrinsic(instr
);
68 vec4_tes_visitor::setup_payload()
72 /* The payload always contains important data in r0 and r1, which contains
73 * the URB handles that are passed on to the URB write at the end
78 reg
= setup_uniforms(reg
);
80 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
81 for (int i
= 0; i
< 3; i
++) {
82 if (inst
->src
[i
].file
!= ATTR
)
86 brw_vec4_grf(reg
+ inst
->src
[i
].nr
/ 2, 4 * (inst
->src
[i
].nr
% 2));
87 grf
= stride(grf
, 0, 4, 1);
88 grf
.swizzle
= inst
->src
[i
].swizzle
;
89 grf
.type
= inst
->src
[i
].type
;
90 grf
.abs
= inst
->src
[i
].abs
;
91 grf
.negate
= inst
->src
[i
].negate
;
97 reg
+= 8 * prog_data
->urb_read_length
;
99 this->first_non_payload_grf
= reg
;
104 vec4_tes_visitor::emit_prolog()
106 input_read_header
= src_reg(this, glsl_type::uvec4_type
);
107 emit(TES_OPCODE_CREATE_INPUT_READ_HEADER
, dst_reg(input_read_header
));
109 this->current_annotation
= NULL
;
114 vec4_tes_visitor::emit_urb_write_header(int mrf
)
116 /* No need to do anything for DS; an implied write to this MRF will be
117 * performed by VS_OPCODE_URB_WRITE.
124 vec4_tes_visitor::emit_urb_write_opcode(bool complete
)
126 /* For DS, the URB writes end the thread. */
128 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
129 emit_shader_time_end();
132 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
133 inst
->urb_write_flags
= complete
?
134 BRW_URB_WRITE_EOT_COMPLETE
: BRW_URB_WRITE_NO_FLAGS
;
140 vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
142 const struct brw_tes_prog_data
*tes_prog_data
=
143 (const struct brw_tes_prog_data
*) prog_data
;
145 switch (instr
->intrinsic
) {
146 case nir_intrinsic_load_tess_coord
:
147 /* gl_TessCoord is part of the payload in g1 channels 0-2 and 4-6. */
148 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_F
),
149 src_reg(brw_vec8_grf(1, 0))));
151 case nir_intrinsic_load_tess_level_outer
:
152 if (tes_prog_data
->domain
== BRW_TESS_DOMAIN_ISOLINE
) {
153 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_F
),
154 swizzle(src_reg(ATTR
, 1, glsl_type::vec4_type
),
157 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_F
),
158 swizzle(src_reg(ATTR
, 1, glsl_type::vec4_type
),
162 case nir_intrinsic_load_tess_level_inner
:
163 if (tes_prog_data
->domain
== BRW_TESS_DOMAIN_QUAD
) {
164 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_F
),
165 swizzle(src_reg(ATTR
, 0, glsl_type::vec4_type
),
168 emit(MOV(get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_F
),
169 src_reg(ATTR
, 1, glsl_type::float_type
)));
172 case nir_intrinsic_load_primitive_id
:
173 emit(TES_OPCODE_GET_PRIMITIVE_ID
,
174 get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_UD
));
177 case nir_intrinsic_load_input
:
178 case nir_intrinsic_load_per_vertex_input
: {
179 src_reg indirect_offset
= get_indirect_offset(instr
);
180 dst_reg dst
= get_nir_dest(instr
->dest
, BRW_REGISTER_TYPE_D
);
181 unsigned imm_offset
= instr
->const_index
[0];
182 unsigned first_component
= nir_intrinsic_component(instr
);
183 src_reg header
= input_read_header
;
185 if (indirect_offset
.file
!= BAD_FILE
) {
186 header
= src_reg(this, glsl_type::uvec4_type
);
187 emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET
, dst_reg(header
),
188 input_read_header
, indirect_offset
);
190 /* Arbitrarily only push up to 24 vec4 slots worth of data,
191 * which is 12 registers (since each holds 2 vec4 slots).
193 const unsigned max_push_slots
= 24;
194 if (imm_offset
< max_push_slots
) {
195 src_reg src
= src_reg(ATTR
, imm_offset
, glsl_type::ivec4_type
);
196 src
.swizzle
= BRW_SWZ_COMP_INPUT(first_component
);
199 prog_data
->urb_read_length
=
200 MAX2(prog_data
->urb_read_length
,
201 DIV_ROUND_UP(imm_offset
+ 1, 2));
206 dst_reg
temp(this, glsl_type::ivec4_type
);
207 vec4_instruction
*read
=
208 emit(VEC4_OPCODE_URB_READ
, temp
, src_reg(header
));
209 read
->offset
= imm_offset
;
210 read
->urb_write_flags
= BRW_URB_WRITE_PER_SLOT_OFFSET
;
212 src_reg src
= src_reg(temp
);
213 src
.swizzle
= BRW_SWZ_COMP_INPUT(first_component
);
215 /* Copy to target. We might end up with some funky writemasks landing
216 * in here, but we really don't want them in the above pseudo-ops.
218 dst
.writemask
= brw_writemask_for_size(instr
->num_components
);
223 vec4_visitor::nir_emit_intrinsic(instr
);
229 vec4_tes_visitor::emit_thread_end()
231 /* For DS, we always end the thread by emitting a single vertex.
232 * emit_urb_write_opcode() will take care of setting the eot flag on the
238 } /* namespace brw */