src/mesa/drivers/dri/i965/brw_vec4_tes.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_vec4_tes.cpp
  26  *
  27  * Tessellaton evaluation shader specific code derived from the vec4_visitor class.
  28  */
  29
  30 #include "brw_vec4_tes.h"
  31
  32 namespace brw {
  33
  34 vec4_tes_visitor::vec4_tes_visitor(const struct brw_compiler *compiler,
  35                                   void *log_data,
  36                                   const struct brw_tes_prog_key *key,
  37                                   struct brw_tes_prog_data *prog_data,
  38                                   const nir_shader *shader,
  39                                   void *mem_ctx,
  40                                   int shader_time_index)
  41    : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base,
  42                   shader, mem_ctx, false, shader_time_index)
  43 {
  44 }
  45
  46
  47 dst_reg *
  48 vec4_tes_visitor::make_reg_for_system_value(int location, const glsl_type *type)
  49 {
  50    return NULL;
  51 }
  52
  53 void
  54 vec4_tes_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
  55 {
  56    const struct brw_tes_prog_data *tes_prog_data =
  57       (const struct brw_tes_prog_data *) prog_data;
  58
  59    switch (instr->intrinsic) {
  60    case nir_intrinsic_load_tess_level_outer: {
  61       dst_reg dst(this, glsl_type::vec4_type);
  62       nir_system_values[SYSTEM_VALUE_TESS_LEVEL_OUTER] = dst;
  63
  64       dst_reg temp(this, glsl_type::vec4_type);
  65       vec4_instruction *read =
  66          emit(VEC4_OPCODE_URB_READ, temp, input_read_header);
  67       read->offset = 1;
  68       read->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
  69       emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WZYX)));
  70       break;
  71    }
  72    case nir_intrinsic_load_tess_level_inner: {
  73       dst_reg dst(this, glsl_type::vec2_type);
  74       nir_system_values[SYSTEM_VALUE_TESS_LEVEL_INNER] = dst;
  75
  76       /* Set up the message header to reference the proper parts of the URB */
  77       dst_reg temp(this, glsl_type::vec4_type);
  78       vec4_instruction *read =
  79          emit(VEC4_OPCODE_URB_READ, temp, input_read_header);
  80       read->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
  81       if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) {
  82          emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WZYX)));
  83       } else {
  84          read->offset = 1;
  85          emit(MOV(dst, src_reg(temp)));
  86       }
  87       break;
  88    }
  89    default:
  90       vec4_visitor::nir_setup_system_value_intrinsic(instr);
  91    }
  92 }
  93
  94
  95 void
  96 vec4_tes_visitor::setup_payload()
  97 {
  98    int reg = 0;
  99
 100    /* The payload always contains important data in r0 and r1, which contains
 101     * the URB handles that are passed on to the URB write at the end
 102     * of the thread.
 103     */
 104    reg += 2;
 105
 106    reg = setup_uniforms(reg);
 107
 108    this->first_non_payload_grf = reg;
 109 }
 110
 111
 112 void
 113 vec4_tes_visitor::emit_prolog()
 114 {
 115    input_read_header = src_reg(this, glsl_type::uvec4_type);
 116    emit(TES_OPCODE_CREATE_INPUT_READ_HEADER, dst_reg(input_read_header));
 117
 118    this->current_annotation = NULL;
 119 }
 120
 121
 122 void
 123 vec4_tes_visitor::emit_urb_write_header(int mrf)
 124 {
 125    /* No need to do anything for DS; an implied write to this MRF will be
 126     * performed by VS_OPCODE_URB_WRITE.
 127     */
 128    (void) mrf;
 129 }
 130
 131
 132 vec4_instruction *
 133 vec4_tes_visitor::emit_urb_write_opcode(bool complete)
 134 {
 135    /* For DS, the URB writes end the thread. */
 136    if (complete) {
 137       if (INTEL_DEBUG & DEBUG_SHADER_TIME)
 138          emit_shader_time_end();
 139    }
 140
 141    vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
 142    inst->urb_write_flags = complete ?
 143       BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;
 144
 145    return inst;
 146 }
 147
 148 void
 149 vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
 150 {
 151    switch (instr->intrinsic) {
 152    case nir_intrinsic_load_tess_coord:
 153       /* gl_TessCoord is part of the payload in g1 channels 0-2 and 4-6. */
 154       emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_F),
 155                src_reg(brw_vec8_grf(1, 0))));
 156       break;
 157    case nir_intrinsic_load_primitive_id:
 158       emit(TES_OPCODE_GET_PRIMITIVE_ID,
 159            get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD));
 160       break;
 161
 162    case nir_intrinsic_load_input:
 163    case nir_intrinsic_load_per_vertex_input: {
 164       src_reg indirect_offset = get_indirect_offset(instr);
 165       unsigned imm_offset = instr->const_index[0];
 166       src_reg header = input_read_header;
 167
 168       if (indirect_offset.file != BAD_FILE) {
 169          header = src_reg(this, glsl_type::uvec4_type);
 170          emit(TES_OPCODE_ADD_INDIRECT_URB_OFFSET, dst_reg(header),
 171               input_read_header, indirect_offset);
 172       }
 173
 174       dst_reg temp(this, glsl_type::ivec4_type);
 175       vec4_instruction *read =
 176          emit(VEC4_OPCODE_URB_READ, temp, src_reg(header));
 177       read->offset = imm_offset;
 178       read->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
 179
 180       /* Copy to target.  We might end up with some funky writemasks landing
 181        * in here, but we really don't want them in the above pseudo-ops.
 182        */
 183       dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 184       dst.writemask = brw_writemask_for_size(instr->num_components);
 185       emit(MOV(dst, src_reg(temp)));
 186       break;
 187    }
 188    default:
 189       vec4_visitor::nir_emit_intrinsic(instr);
 190    }
 191 }
 192
 193
 194 void
 195 vec4_tes_visitor::emit_thread_end()
 196 {
 197    /* For DS, we always end the thread by emitting a single vertex.
 198     * emit_urb_write_opcode() will take care of setting the eot flag on the
 199     * SEND instruction.
 200     */
 201    emit_vertex();
 202 }
 203
 204 } /* namespace brw */