2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
31 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
32 const src_reg
&src0
, const src_reg
&src1
,
35 this->opcode
= opcode
;
40 this->saturate
= false;
41 this->force_writemask_all
= false;
42 this->no_dd_clear
= false;
43 this->no_dd_check
= false;
44 this->writes_accumulator
= false;
45 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
46 this->predicate
= BRW_PREDICATE_NONE
;
47 this->predicate_inverse
= false;
49 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
50 this->shadow_compare
= false;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_size
= 0;
54 this->flag_subreg
= 0;
58 this->annotation
= NULL
;
62 vec4_visitor::emit(vec4_instruction
*inst
)
64 inst
->ir
= this->base_ir
;
65 inst
->annotation
= this->current_annotation
;
67 this->instructions
.push_tail(inst
);
73 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
74 vec4_instruction
*new_inst
)
76 new_inst
->ir
= inst
->ir
;
77 new_inst
->annotation
= inst
->annotation
;
79 inst
->insert_before(block
, new_inst
);
85 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
86 const src_reg
&src1
, const src_reg
&src2
)
88 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
93 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
96 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
100 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
102 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
106 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
108 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
112 vec4_visitor::emit(enum opcode opcode
)
114 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
119 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
121 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
126 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
127 const src_reg &src1) \
129 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
133 #define ALU2_ACC(op) \
135 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
136 const src_reg &src1) \
138 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
139 BRW_OPCODE_##op, dst, src0, src1); \
140 inst->writes_accumulator = true; \
146 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
147 const src_reg &src1, const src_reg &src2) \
149 assert(devinfo->gen >= 6); \
150 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
187 /** Gen4 predicated IF. */
189 vec4_visitor::IF(enum brw_predicate predicate
)
191 vec4_instruction
*inst
;
193 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
199 /** Gen6 IF with embedded comparison. */
201 vec4_visitor::IF(src_reg src0
, src_reg src1
,
202 enum brw_conditional_mod condition
)
204 assert(devinfo
->gen
== 6);
206 vec4_instruction
*inst
;
208 resolve_ud_negate(&src0
);
209 resolve_ud_negate(&src1
);
211 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
213 inst
->conditional_mod
= condition
;
219 * CMP: Sets the low bit of the destination channels with the result
220 * of the comparison, while the upper bits are undefined, and updates
221 * the flag register with the packed 16 bits of the result.
224 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
225 enum brw_conditional_mod condition
)
227 vec4_instruction
*inst
;
229 /* Take the instruction:
231 * CMP null<d> src0<f> src1<f>
233 * Original gen4 does type conversion to the destination type before
234 * comparison, producing garbage results for floating point comparisons.
236 * The destination type doesn't matter on newer generations, so we set the
237 * type to match src0 so we can compact the instruction.
239 dst
.type
= src0
.type
;
240 if (dst
.file
== HW_REG
)
241 dst
.fixed_hw_reg
.type
= dst
.type
;
243 resolve_ud_negate(&src0
);
244 resolve_ud_negate(&src1
);
246 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
247 inst
->conditional_mod
= condition
;
253 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
255 vec4_instruction
*inst
;
257 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
266 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
267 const src_reg
&index
)
269 vec4_instruction
*inst
;
271 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
280 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
282 static enum opcode dot_opcodes
[] = {
283 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
286 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
290 vec4_visitor::fix_3src_operand(src_reg src
)
292 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
293 * able to use vertical stride of zero to replicate the vec4 uniform, like
295 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
297 * But you can't, since vertical stride is always four in three-source
298 * instructions. Instead, insert a MOV instruction to do the replication so
299 * that the three-source instruction can consume it.
302 /* The MOV is only needed if the source is a uniform or immediate. */
303 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
306 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
309 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
310 expanded
.type
= src
.type
;
311 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
312 return src_reg(expanded
);
316 vec4_visitor::fix_math_operand(src_reg src
)
318 if (devinfo
->gen
< 6 || devinfo
->gen
>= 8 || src
.file
== BAD_FILE
)
321 /* The gen6 math instruction ignores the source modifiers --
322 * swizzle, abs, negate, and at least some parts of the register
323 * region description.
325 * Rather than trying to enumerate all these cases, *always* expand the
326 * operand to a temp GRF for gen6.
328 * For gen7, keep the operand as-is, except if immediate, which gen7 still
332 if (devinfo
->gen
== 7 && src
.file
!= IMM
)
335 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
336 expanded
.type
= src
.type
;
337 emit(MOV(expanded
, src
));
338 return src_reg(expanded
);
342 vec4_visitor::emit_math(enum opcode opcode
,
344 const src_reg
&src0
, const src_reg
&src1
)
346 vec4_instruction
*math
=
347 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
349 if (devinfo
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
350 /* MATH on Gen6 must be align1, so we can't do writemasks. */
351 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
352 math
->dst
.type
= dst
.type
;
353 emit(MOV(dst
, src_reg(math
->dst
)));
354 } else if (devinfo
->gen
< 6) {
356 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
361 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
363 if (devinfo
->gen
< 7) {
364 unreachable("ir_unop_pack_half_2x16 should be lowered");
367 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
368 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
370 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
372 * Because this instruction does not have a 16-bit floating-point type,
373 * the destination data type must be Word (W).
375 * The destination must be DWord-aligned and specify a horizontal stride
376 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
377 * each destination channel and the upper word is not modified.
379 * The above restriction implies that the f32to16 instruction must use
380 * align1 mode, because only in align1 mode is it possible to specify
381 * horizontal stride. We choose here to defy the hardware docs and emit
382 * align16 instructions.
384 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
385 * instructions. I was partially successful in that the code passed all
386 * tests. However, the code was dubiously correct and fragile, and the
387 * tests were not harsh enough to probe that frailty. Not trusting the
388 * code, I chose instead to remain in align16 mode in defiance of the hw
391 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
392 * simulator, emitting a f32to16 in align16 mode with UD as destination
393 * data type is safe. The behavior differs from that specified in the PRM
394 * in that the upper word of each destination channel is cleared to 0.
397 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
398 src_reg
tmp_src(tmp_dst
);
401 /* Verify the undocumented behavior on which the following instructions
402 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
403 * then the result of the bit-or instruction below will be incorrect.
405 * You should inspect the disasm output in order to verify that the MOV is
406 * not optimized away.
408 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
411 /* Give tmp the form below, where "." means untouched.
414 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
416 * That the upper word of each write-channel be 0 is required for the
417 * following bit-shift and bit-or instructions to work. Note that this
418 * relies on the undocumented hardware behavior mentioned above.
420 tmp_dst
.writemask
= WRITEMASK_XY
;
421 emit(F32TO16(tmp_dst
, src0
));
423 /* Give the write-channels of dst the form:
426 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
427 emit(SHL(dst
, tmp_src
, src_reg(16u)));
429 /* Finally, give the write-channels of dst the form of packHalf2x16's
433 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
434 emit(OR(dst
, src_reg(dst
), tmp_src
));
438 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
440 if (devinfo
->gen
< 7) {
441 unreachable("ir_unop_unpack_half_2x16 should be lowered");
444 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
445 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
447 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
449 * Because this instruction does not have a 16-bit floating-point type,
450 * the source data type must be Word (W). The destination type must be
453 * To use W as the source data type, we must adjust horizontal strides,
454 * which is only possible in align1 mode. All my [chadv] attempts at
455 * emitting align1 instructions for unpackHalf2x16 failed to pass the
456 * Piglit tests, so I gave up.
458 * I've verified that, on gen7 hardware and the simulator, it is safe to
459 * emit f16to32 in align16 mode with UD as source data type.
462 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
463 src_reg
tmp_src(tmp_dst
);
465 tmp_dst
.writemask
= WRITEMASK_X
;
466 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
468 tmp_dst
.writemask
= WRITEMASK_Y
;
469 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
471 dst
.writemask
= WRITEMASK_XY
;
472 emit(F16TO32(dst
, tmp_src
));
476 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
478 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
479 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
480 * is not suitable to generate the shift values, but we can use the packed
481 * vector float and a type-converting MOV.
483 dst_reg
shift(this, glsl_type::uvec4_type
);
484 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
486 dst_reg
shifted(this, glsl_type::uvec4_type
);
487 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
488 emit(SHR(shifted
, src0
, src_reg(shift
)));
490 shifted
.type
= BRW_REGISTER_TYPE_UB
;
491 dst_reg
f(this, glsl_type::vec4_type
);
492 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
494 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
498 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
500 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
501 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
502 * is not suitable to generate the shift values, but we can use the packed
503 * vector float and a type-converting MOV.
505 dst_reg
shift(this, glsl_type::uvec4_type
);
506 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
508 dst_reg
shifted(this, glsl_type::uvec4_type
);
509 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
510 emit(SHR(shifted
, src0
, src_reg(shift
)));
512 shifted
.type
= BRW_REGISTER_TYPE_B
;
513 dst_reg
f(this, glsl_type::vec4_type
);
514 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
516 dst_reg
scaled(this, glsl_type::vec4_type
);
517 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
519 dst_reg
max(this, glsl_type::vec4_type
);
520 emit_minmax(BRW_CONDITIONAL_GE
, max
, src_reg(scaled
), src_reg(-1.0f
));
521 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
525 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
527 dst_reg
saturated(this, glsl_type::vec4_type
);
528 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
529 inst
->saturate
= true;
531 dst_reg
scaled(this, glsl_type::vec4_type
);
532 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
534 dst_reg
rounded(this, glsl_type::vec4_type
);
535 emit(RNDE(rounded
, src_reg(scaled
)));
537 dst_reg
u(this, glsl_type::uvec4_type
);
538 emit(MOV(u
, src_reg(rounded
)));
541 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
545 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
547 dst_reg
max(this, glsl_type::vec4_type
);
548 emit_minmax(BRW_CONDITIONAL_GE
, max
, src0
, src_reg(-1.0f
));
550 dst_reg
min(this, glsl_type::vec4_type
);
551 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
553 dst_reg
scaled(this, glsl_type::vec4_type
);
554 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
556 dst_reg
rounded(this, glsl_type::vec4_type
);
557 emit(RNDE(rounded
, src_reg(scaled
)));
559 dst_reg
i(this, glsl_type::ivec4_type
);
560 emit(MOV(i
, src_reg(rounded
)));
563 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
567 vec4_visitor::visit_instructions(const exec_list
*list
)
569 foreach_in_list(ir_instruction
, ir
, list
) {
576 * Returns the minimum number of vec4 elements needed to pack a type.
578 * For simple types, it will return 1 (a single vec4); for matrices, the
579 * number of columns; for array and struct, the sum of the vec4_size of
580 * each of its elements; and for sampler and atomic, zero.
582 * This method is useful to calculate how much register space is needed to
583 * store a particular type.
586 vec4_visitor::type_size(const struct glsl_type
*type
)
591 switch (type
->base_type
) {
594 case GLSL_TYPE_FLOAT
:
596 if (type
->is_matrix()) {
597 return type
->matrix_columns
;
599 /* Regardless of size of vector, it gets a vec4. This is bad
600 * packing for things like floats, but otherwise arrays become a
601 * mess. Hopefully a later pass over the code can pack scalars
602 * down if appropriate.
606 case GLSL_TYPE_ARRAY
:
607 assert(type
->length
> 0);
608 return type_size(type
->fields
.array
) * type
->length
;
609 case GLSL_TYPE_STRUCT
:
611 for (i
= 0; i
< type
->length
; i
++) {
612 size
+= type_size(type
->fields
.structure
[i
].type
);
615 case GLSL_TYPE_SUBROUTINE
:
618 case GLSL_TYPE_SAMPLER
:
619 /* Samplers take up no register space, since they're baked in at
623 case GLSL_TYPE_ATOMIC_UINT
:
625 case GLSL_TYPE_IMAGE
:
627 case GLSL_TYPE_DOUBLE
:
628 case GLSL_TYPE_ERROR
:
629 case GLSL_TYPE_INTERFACE
:
630 unreachable("not reached");
636 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
641 this->reg
= v
->alloc
.allocate(v
->type_size(type
));
643 if (type
->is_array() || type
->is_record()) {
644 this->swizzle
= BRW_SWIZZLE_NOOP
;
646 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
649 this->type
= brw_type_for_base_type(type
);
652 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
659 this->reg
= v
->alloc
.allocate(v
->type_size(type
) * size
);
661 this->swizzle
= BRW_SWIZZLE_NOOP
;
663 this->type
= brw_type_for_base_type(type
);
666 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
671 this->reg
= v
->alloc
.allocate(v
->type_size(type
));
673 if (type
->is_array() || type
->is_record()) {
674 this->writemask
= WRITEMASK_XYZW
;
676 this->writemask
= (1 << type
->vector_elements
) - 1;
679 this->type
= brw_type_for_base_type(type
);
683 vec4_visitor::setup_vector_uniform_values(const gl_constant_value
*values
,
686 static const gl_constant_value zero
= { 0 };
688 for (unsigned i
= 0; i
< n
; ++i
)
689 stage_prog_data
->param
[4 * uniforms
+ i
] = &values
[i
];
691 for (unsigned i
= n
; i
< 4; ++i
)
692 stage_prog_data
->param
[4 * uniforms
+ i
] = &zero
;
694 uniform_vector_size
[uniforms
++] = n
;
697 /* Our support for uniforms is piggy-backed on the struct
698 * gl_fragment_program, because that's where the values actually
699 * get stored, rather than in some global gl_shader_program uniform
703 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
705 int namelen
= strlen(ir
->name
);
707 /* The data for our (non-builtin) uniforms is stored in a series of
708 * gl_uniform_driver_storage structs for each subcomponent that
709 * glGetUniformLocation() could name. We know it's been set up in the same
710 * order we'd walk the type, so walk the list of storage and find anything
711 * with our name, or the prefix of a component that starts with our name.
713 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
714 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
716 if (storage
->builtin
)
719 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
720 (storage
->name
[namelen
] != 0 &&
721 storage
->name
[namelen
] != '.' &&
722 storage
->name
[namelen
] != '[')) {
726 const unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
727 storage
->type
->matrix_columns
);
728 const unsigned vector_size
= storage
->type
->vector_elements
;
730 for (unsigned s
= 0; s
< vector_count
; s
++)
731 setup_vector_uniform_values(&storage
->storage
[s
* vector_size
],
737 vec4_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
739 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
740 assert(this->uniforms
< uniform_array_size
);
741 this->uniform_vector_size
[this->uniforms
] = 4;
742 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
743 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
744 for (int j
= 0; j
< 4; ++j
) {
745 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
746 (gl_constant_value
*) &clip_planes
[i
][j
];
752 /* Our support for builtin uniforms is even scarier than non-builtin.
753 * It sits on top of the PROG_STATE_VAR parameters that are
754 * automatically updated from GL context state.
757 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
759 const ir_state_slot
*const slots
= ir
->get_state_slots();
760 assert(slots
!= NULL
);
762 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
763 /* This state reference has already been setup by ir_to_mesa,
764 * but we'll get the same index back here. We can reference
765 * ParameterValues directly, since unlike brw_fs.cpp, we never
766 * add new state references during compile.
768 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
769 (gl_state_index
*)slots
[i
].tokens
);
770 gl_constant_value
*values
=
771 &this->prog
->Parameters
->ParameterValues
[index
][0];
773 assert(this->uniforms
< uniform_array_size
);
775 for (unsigned j
= 0; j
< 4; j
++)
776 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
777 &values
[GET_SWZ(slots
[i
].swizzle
, j
)];
779 this->uniform_vector_size
[this->uniforms
] =
780 (ir
->type
->is_scalar() || ir
->type
->is_vector() ||
781 ir
->type
->is_matrix() ? ir
->type
->vector_elements
: 4);
788 vec4_visitor::variable_storage(ir_variable
*var
)
790 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
794 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
795 enum brw_predicate
*predicate
)
797 ir_expression
*expr
= ir
->as_expression();
799 *predicate
= BRW_PREDICATE_NORMAL
;
801 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
803 vec4_instruction
*inst
;
805 assert(expr
->get_num_operands() <= 3);
806 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
807 expr
->operands
[i
]->accept(this);
808 op
[i
] = this->result
;
810 resolve_ud_negate(&op
[i
]);
813 switch (expr
->operation
) {
814 case ir_unop_logic_not
:
815 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
816 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
819 case ir_binop_logic_xor
:
820 if (devinfo
->gen
<= 5) {
821 src_reg temp
= src_reg(this, ir
->type
);
822 emit(XOR(dst_reg(temp
), op
[0], op
[1]));
823 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
825 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
827 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
830 case ir_binop_logic_or
:
831 if (devinfo
->gen
<= 5) {
832 src_reg temp
= src_reg(this, ir
->type
);
833 emit(OR(dst_reg(temp
), op
[0], op
[1]));
834 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
836 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
838 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
841 case ir_binop_logic_and
:
842 if (devinfo
->gen
<= 5) {
843 src_reg temp
= src_reg(this, ir
->type
);
844 emit(AND(dst_reg(temp
), op
[0], op
[1]));
845 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
847 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
849 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
853 if (devinfo
->gen
>= 6) {
854 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
856 inst
= emit(MOV(dst_null_f(), op
[0]));
857 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
862 if (devinfo
->gen
>= 6) {
863 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
865 inst
= emit(MOV(dst_null_d(), op
[0]));
866 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
870 case ir_binop_all_equal
:
871 if (devinfo
->gen
<= 5) {
872 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
873 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
875 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
876 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
879 case ir_binop_any_nequal
:
880 if (devinfo
->gen
<= 5) {
881 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
882 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
884 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
885 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
889 if (devinfo
->gen
<= 5) {
890 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
892 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
893 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
896 case ir_binop_greater
:
897 case ir_binop_gequal
:
899 case ir_binop_lequal
:
901 case ir_binop_nequal
:
902 if (devinfo
->gen
<= 5) {
903 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
904 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
906 emit(CMP(dst_null_d(), op
[0], op
[1],
907 brw_conditional_for_comparison(expr
->operation
)));
910 case ir_triop_csel
: {
911 /* Expand the boolean condition into the flag register. */
912 inst
= emit(MOV(dst_null_d(), op
[0]));
913 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
915 /* Select which boolean to return. */
916 dst_reg
temp(this, expr
->operands
[1]->type
);
917 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
918 inst
->predicate
= BRW_PREDICATE_NORMAL
;
920 /* Expand the result to a condition code. */
921 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
922 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
927 unreachable("not reached");
934 resolve_ud_negate(&this->result
);
936 vec4_instruction
*inst
= emit(AND(dst_null_d(), this->result
, src_reg(1)));
937 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
941 * Emit a gen6 IF statement with the comparison folded into the IF
945 vec4_visitor::emit_if_gen6(ir_if
*ir
)
947 ir_expression
*expr
= ir
->condition
->as_expression();
949 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
953 assert(expr
->get_num_operands() <= 3);
954 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
955 expr
->operands
[i
]->accept(this);
956 op
[i
] = this->result
;
959 switch (expr
->operation
) {
960 case ir_unop_logic_not
:
961 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
964 case ir_binop_logic_xor
:
965 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
968 case ir_binop_logic_or
:
969 temp
= dst_reg(this, glsl_type::bool_type
);
970 emit(OR(temp
, op
[0], op
[1]));
971 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
974 case ir_binop_logic_and
:
975 temp
= dst_reg(this, glsl_type::bool_type
);
976 emit(AND(temp
, op
[0], op
[1]));
977 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
981 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
985 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
988 case ir_binop_greater
:
989 case ir_binop_gequal
:
991 case ir_binop_lequal
:
993 case ir_binop_nequal
:
994 emit(IF(op
[0], op
[1],
995 brw_conditional_for_comparison(expr
->operation
)));
998 case ir_binop_all_equal
:
999 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1000 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
1003 case ir_binop_any_nequal
:
1004 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1005 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1009 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1010 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1013 case ir_triop_csel
: {
1014 /* Expand the boolean condition into the flag register. */
1015 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
1016 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1018 /* Select which boolean to return. */
1019 dst_reg
temp(this, expr
->operands
[1]->type
);
1020 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
1021 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1023 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
1028 unreachable("not reached");
1033 ir
->condition
->accept(this);
1035 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
1039 vec4_visitor::visit(ir_variable
*ir
)
1041 dst_reg
*reg
= NULL
;
1043 if (variable_storage(ir
))
1046 switch (ir
->data
.mode
) {
1047 case ir_var_shader_in
:
1048 assert(ir
->data
.location
!= -1);
1049 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
1052 case ir_var_shader_out
:
1053 assert(ir
->data
.location
!= -1);
1054 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1056 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1057 output_reg
[ir
->data
.location
+ i
] = *reg
;
1058 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
1059 output_reg
[ir
->data
.location
+ i
].type
=
1060 brw_type_for_base_type(ir
->type
->get_scalar_type());
1061 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
1066 case ir_var_temporary
:
1067 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1070 case ir_var_uniform
:
1071 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1073 /* Thanks to the lower_ubo_reference pass, we will see only
1074 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1075 * variables, so no need for them to be in variable_ht.
1077 * Some uniforms, such as samplers and atomic counters, have no actual
1078 * storage, so we should ignore them.
1080 if (ir
->is_in_buffer_block() || type_size(ir
->type
) == 0)
1083 /* Track how big the whole uniform variable is, in case we need to put a
1084 * copy of its data into pull constants for array access.
1086 assert(this->uniforms
< uniform_array_size
);
1087 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1089 if (!strncmp(ir
->name
, "gl_", 3)) {
1090 setup_builtin_uniform_values(ir
);
1092 setup_uniform_values(ir
);
1096 case ir_var_system_value
:
1097 reg
= make_reg_for_system_value(ir
->data
.location
, ir
->type
);
1101 unreachable("not reached");
1104 reg
->type
= brw_type_for_base_type(ir
->type
);
1105 hash_table_insert(this->variable_ht
, reg
, ir
);
1109 vec4_visitor::visit(ir_loop
*ir
)
1111 /* We don't want debugging output to print the whole body of the
1112 * loop as the annotation.
1114 this->base_ir
= NULL
;
1116 emit(BRW_OPCODE_DO
);
1118 visit_instructions(&ir
->body_instructions
);
1120 emit(BRW_OPCODE_WHILE
);
1124 vec4_visitor::visit(ir_loop_jump
*ir
)
1127 case ir_loop_jump::jump_break
:
1128 emit(BRW_OPCODE_BREAK
);
1130 case ir_loop_jump::jump_continue
:
1131 emit(BRW_OPCODE_CONTINUE
);
1138 vec4_visitor::visit(ir_function_signature
*)
1140 unreachable("not reached");
1144 vec4_visitor::visit(ir_function
*ir
)
1146 /* Ignore function bodies other than main() -- we shouldn't see calls to
1147 * them since they should all be inlined.
1149 if (strcmp(ir
->name
, "main") == 0) {
1150 const ir_function_signature
*sig
;
1153 sig
= ir
->matching_signature(NULL
, &empty
, false);
1157 visit_instructions(&sig
->body
);
1162 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1164 /* 3-src instructions were introduced in gen6. */
1165 if (devinfo
->gen
< 6)
1168 /* MAD can only handle floating-point data. */
1169 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1174 bool mul_negate
, mul_abs
;
1176 for (int i
= 0; i
< 2; i
++) {
1180 mul
= ir
->operands
[i
]->as_expression();
1181 nonmul
= ir
->operands
[1 - i
];
1183 if (mul
&& mul
->operation
== ir_unop_abs
) {
1184 mul
= mul
->operands
[0]->as_expression();
1186 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
1187 mul
= mul
->operands
[0]->as_expression();
1191 if (mul
&& mul
->operation
== ir_binop_mul
)
1195 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1198 nonmul
->accept(this);
1199 src_reg src0
= fix_3src_operand(this->result
);
1201 mul
->operands
[0]->accept(this);
1202 src_reg src1
= fix_3src_operand(this->result
);
1203 src1
.negate
^= mul_negate
;
1206 src1
.negate
= false;
1208 mul
->operands
[1]->accept(this);
1209 src_reg src2
= fix_3src_operand(this->result
);
1212 src2
.negate
= false;
1214 this->result
= src_reg(this, ir
->type
);
1215 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1221 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1223 /* This optimization relies on CMP setting the destination to 0 when
1224 * false. Early hardware only sets the least significant bit, and
1225 * leaves the other bits undefined. So we can't use it.
1227 if (devinfo
->gen
< 6)
1230 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1235 switch (cmp
->operation
) {
1237 case ir_binop_greater
:
1238 case ir_binop_lequal
:
1239 case ir_binop_gequal
:
1240 case ir_binop_equal
:
1241 case ir_binop_nequal
:
1248 cmp
->operands
[0]->accept(this);
1249 const src_reg cmp_src0
= this->result
;
1251 cmp
->operands
[1]->accept(this);
1252 const src_reg cmp_src1
= this->result
;
1254 this->result
= src_reg(this, ir
->type
);
1256 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1257 brw_conditional_for_comparison(cmp
->operation
)));
1259 /* If the comparison is false, this->result will just happen to be zero.
1261 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1262 this->result
, src_reg(1.0f
));
1263 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1264 inst
->predicate_inverse
= true;
1270 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1271 src_reg src0
, src_reg src1
)
1273 vec4_instruction
*inst
;
1275 if (devinfo
->gen
>= 6) {
1276 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1277 inst
->conditional_mod
= conditionalmod
;
1279 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1281 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1282 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1287 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1288 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1290 if (devinfo
->gen
>= 6) {
1291 /* Note that the instruction's argument order is reversed from GLSL
1295 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1297 /* Earlier generations don't support three source operations, so we
1298 * need to emit x*(1-a) + y*a.
1300 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1301 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1302 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1303 y_times_a
.writemask
= dst
.writemask
;
1304 one_minus_a
.writemask
= dst
.writemask
;
1305 x_times_one_minus_a
.writemask
= dst
.writemask
;
1307 emit(MUL(y_times_a
, y
, a
));
1308 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1309 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1310 emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1315 * Emits the instructions needed to perform a pull constant load. before_block
1316 * and before_inst can be NULL in which case the instruction will be appended
1317 * to the end of the instruction list.
1320 vec4_visitor::emit_pull_constant_load_reg(dst_reg dst
,
1323 bblock_t
*before_block
,
1324 vec4_instruction
*before_inst
)
1326 assert((before_inst
== NULL
&& before_block
== NULL
) ||
1327 (before_inst
&& before_block
));
1329 vec4_instruction
*pull
;
1331 if (devinfo
->gen
>= 9) {
1332 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
1333 src_reg
header(this, glsl_type::uvec4_type
, 2);
1336 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
1340 emit_before(before_block
, before_inst
, pull
);
1344 dst_reg index_reg
= retype(offset(dst_reg(header
), 1),
1346 pull
= MOV(writemask(index_reg
, WRITEMASK_X
), offset_reg
);
1349 emit_before(before_block
, before_inst
, pull
);
1353 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1358 pull
->header_size
= 1;
1359 } else if (devinfo
->gen
>= 7) {
1360 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1362 grf_offset
.type
= offset_reg
.type
;
1364 pull
= MOV(grf_offset
, offset_reg
);
1367 emit_before(before_block
, before_inst
, pull
);
1371 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1374 src_reg(grf_offset
));
1377 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
1381 pull
->base_mrf
= 14;
1386 emit_before(before_block
, before_inst
, pull
);
1392 vec4_visitor::emit_uniformize(const src_reg
&src
)
1394 const src_reg
chan_index(this, glsl_type::uint_type
);
1395 const dst_reg dst
= retype(dst_reg(this, glsl_type::uint_type
),
1398 emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, dst_reg(chan_index
))
1399 ->force_writemask_all
= true;
1400 emit(SHADER_OPCODE_BROADCAST
, dst
, src
, chan_index
)
1401 ->force_writemask_all
= true;
1403 return src_reg(dst
);
1407 vec4_visitor::visit(ir_expression
*ir
)
1409 unsigned int operand
;
1410 src_reg op
[ARRAY_SIZE(ir
->operands
)];
1411 vec4_instruction
*inst
;
1413 if (ir
->operation
== ir_binop_add
) {
1414 if (try_emit_mad(ir
))
1418 if (ir
->operation
== ir_unop_b2f
) {
1419 if (try_emit_b2f_of_compare(ir
))
1423 /* Storage for our result. Ideally for an assignment we'd be using
1424 * the actual storage for the result here, instead.
1426 dst_reg
result_dst(this, ir
->type
);
1427 src_reg
result_src(result_dst
);
1429 if (ir
->operation
== ir_triop_csel
) {
1430 ir
->operands
[1]->accept(this);
1431 op
[1] = this->result
;
1432 ir
->operands
[2]->accept(this);
1433 op
[2] = this->result
;
1435 enum brw_predicate predicate
;
1436 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1437 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1438 inst
->predicate
= predicate
;
1439 this->result
= result_src
;
1443 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1444 this->result
.file
= BAD_FILE
;
1445 ir
->operands
[operand
]->accept(this);
1446 if (this->result
.file
== BAD_FILE
) {
1447 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1448 ir
->operands
[operand
]->fprint(stderr
);
1451 op
[operand
] = this->result
;
1453 /* Matrix expression operands should have been broken down to vector
1454 * operations already.
1456 assert(!ir
->operands
[operand
]->type
->is_matrix());
1459 /* If nothing special happens, this is the result. */
1460 this->result
= result_src
;
1462 switch (ir
->operation
) {
1463 case ir_unop_logic_not
:
1464 emit(NOT(result_dst
, op
[0]));
1467 op
[0].negate
= !op
[0].negate
;
1468 emit(MOV(result_dst
, op
[0]));
1472 op
[0].negate
= false;
1473 emit(MOV(result_dst
, op
[0]));
1477 if (ir
->type
->is_float()) {
1478 /* AND(val, 0x80000000) gives the sign bit.
1480 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1483 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1485 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1486 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1487 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1489 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1490 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1492 this->result
.type
= BRW_REGISTER_TYPE_F
;
1494 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1495 * -> non-negative val generates 0x00000000.
1496 * Predicated OR sets 1 if val is positive.
1498 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1500 emit(ASR(result_dst
, op
[0], src_reg(31)));
1502 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1503 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1508 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1512 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1515 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1519 unreachable("not reached: should be handled by ir_explog_to_explog2");
1521 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1524 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1528 case ir_unop_dFdx_coarse
:
1529 case ir_unop_dFdx_fine
:
1531 case ir_unop_dFdy_coarse
:
1532 case ir_unop_dFdy_fine
:
1533 unreachable("derivatives not valid in vertex shader");
1535 case ir_unop_bitfield_reverse
:
1536 emit(BFREV(result_dst
, op
[0]));
1538 case ir_unop_bit_count
:
1539 emit(CBIT(result_dst
, op
[0]));
1541 case ir_unop_find_msb
: {
1542 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1544 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1545 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1547 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1548 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1549 * subtract the result from 31 to convert the MSB count into an LSB count.
1552 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1553 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1554 emit(MOV(result_dst
, temp
));
1556 src_reg src_tmp
= src_reg(result_dst
);
1557 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1559 src_tmp
.negate
= true;
1560 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1561 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1564 case ir_unop_find_lsb
:
1565 emit(FBL(result_dst
, op
[0]));
1567 case ir_unop_saturate
:
1568 inst
= emit(MOV(result_dst
, op
[0]));
1569 inst
->saturate
= true;
1573 unreachable("not reached: should be handled by lower_noise");
1575 case ir_unop_subroutine_to_int
:
1576 emit(MOV(result_dst
, op
[0]));
1580 emit(ADD(result_dst
, op
[0], op
[1]));
1583 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1586 if (devinfo
->gen
< 8 && ir
->type
->is_integer()) {
1587 /* For integer multiplication, the MUL uses the low 16 bits of one of
1588 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1589 * accumulates in the contribution of the upper 16 bits of that
1590 * operand. If we can determine that one of the args is in the low
1591 * 16 bits, though, we can just emit a single MUL.
1593 if (ir
->operands
[0]->is_uint16_constant()) {
1594 if (devinfo
->gen
< 7)
1595 emit(MUL(result_dst
, op
[0], op
[1]));
1597 emit(MUL(result_dst
, op
[1], op
[0]));
1598 } else if (ir
->operands
[1]->is_uint16_constant()) {
1599 if (devinfo
->gen
< 7)
1600 emit(MUL(result_dst
, op
[1], op
[0]));
1602 emit(MUL(result_dst
, op
[0], op
[1]));
1604 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1606 emit(MUL(acc
, op
[0], op
[1]));
1607 emit(MACH(dst_null_d(), op
[0], op
[1]));
1608 emit(MOV(result_dst
, src_reg(acc
)));
1611 emit(MUL(result_dst
, op
[0], op
[1]));
1614 case ir_binop_imul_high
: {
1615 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1617 emit(MUL(acc
, op
[0], op
[1]));
1618 emit(MACH(result_dst
, op
[0], op
[1]));
1622 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1623 assert(ir
->type
->is_integer());
1624 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1627 case ir_binop_carry
:
1628 unreachable("Should have been lowered by carry_to_arith().");
1630 case ir_binop_borrow
:
1631 unreachable("Should have been lowered by borrow_to_arith().");
1634 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1635 assert(ir
->type
->is_integer());
1636 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1640 case ir_binop_greater
:
1641 case ir_binop_lequal
:
1642 case ir_binop_gequal
:
1643 case ir_binop_equal
:
1644 case ir_binop_nequal
: {
1645 if (devinfo
->gen
<= 5) {
1646 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1647 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1649 emit(CMP(result_dst
, op
[0], op
[1],
1650 brw_conditional_for_comparison(ir
->operation
)));
1654 case ir_binop_all_equal
:
1655 if (devinfo
->gen
<= 5) {
1656 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1657 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1660 /* "==" operator producing a scalar boolean. */
1661 if (ir
->operands
[0]->type
->is_vector() ||
1662 ir
->operands
[1]->type
->is_vector()) {
1663 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1664 emit(MOV(result_dst
, src_reg(0)));
1665 inst
= emit(MOV(result_dst
, src_reg(~0)));
1666 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1668 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1671 case ir_binop_any_nequal
:
1672 if (devinfo
->gen
<= 5) {
1673 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1674 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1677 /* "!=" operator producing a scalar boolean. */
1678 if (ir
->operands
[0]->type
->is_vector() ||
1679 ir
->operands
[1]->type
->is_vector()) {
1680 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1682 emit(MOV(result_dst
, src_reg(0)));
1683 inst
= emit(MOV(result_dst
, src_reg(~0)));
1684 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1686 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1691 if (devinfo
->gen
<= 5) {
1692 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1694 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1695 emit(MOV(result_dst
, src_reg(0)));
1697 inst
= emit(MOV(result_dst
, src_reg(~0)));
1698 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1701 case ir_binop_logic_xor
:
1702 emit(XOR(result_dst
, op
[0], op
[1]));
1705 case ir_binop_logic_or
:
1706 emit(OR(result_dst
, op
[0], op
[1]));
1709 case ir_binop_logic_and
:
1710 emit(AND(result_dst
, op
[0], op
[1]));
1714 assert(ir
->operands
[0]->type
->is_vector());
1715 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1716 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1720 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1723 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1726 case ir_unop_bitcast_i2f
:
1727 case ir_unop_bitcast_u2f
:
1728 this->result
= op
[0];
1729 this->result
.type
= BRW_REGISTER_TYPE_F
;
1732 case ir_unop_bitcast_f2i
:
1733 this->result
= op
[0];
1734 this->result
.type
= BRW_REGISTER_TYPE_D
;
1737 case ir_unop_bitcast_f2u
:
1738 this->result
= op
[0];
1739 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1748 emit(MOV(result_dst
, op
[0]));
1752 if (devinfo
->gen
<= 5) {
1753 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1755 emit(MOV(result_dst
, negate(op
[0])));
1758 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1761 emit(CMP(result_dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1765 emit(RNDZ(result_dst
, op
[0]));
1767 case ir_unop_ceil
: {
1768 src_reg tmp
= src_reg(this, ir
->type
);
1769 op
[0].negate
= !op
[0].negate
;
1770 emit(RNDD(dst_reg(tmp
), op
[0]));
1772 emit(MOV(result_dst
, tmp
));
1776 inst
= emit(RNDD(result_dst
, op
[0]));
1779 inst
= emit(FRC(result_dst
, op
[0]));
1781 case ir_unop_round_even
:
1782 emit(RNDE(result_dst
, op
[0]));
1786 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1789 emit_minmax(BRW_CONDITIONAL_GE
, result_dst
, op
[0], op
[1]);
1793 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1796 case ir_unop_bit_not
:
1797 inst
= emit(NOT(result_dst
, op
[0]));
1799 case ir_binop_bit_and
:
1800 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1802 case ir_binop_bit_xor
:
1803 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1805 case ir_binop_bit_or
:
1806 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1809 case ir_binop_lshift
:
1810 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1813 case ir_binop_rshift
:
1814 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1815 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1817 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1821 emit(BFI1(result_dst
, op
[0], op
[1]));
1824 case ir_binop_ubo_load
: {
1825 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1826 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1827 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1830 /* Now, load the vector from that offset. */
1831 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1833 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1834 packed_consts
.type
= result
.type
;
1837 if (const_uniform_block
) {
1838 /* The block index is a constant, so just emit the binding table entry
1841 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1842 const_uniform_block
->value
.u
[0]);
1844 /* The block index is not a constant. Evaluate the index expression
1845 * per-channel and add the base UBO index; we have to select a value
1846 * from any live channel.
1848 surf_index
= src_reg(this, glsl_type::uint_type
);
1849 emit(ADD(dst_reg(surf_index
), op
[0],
1850 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1851 surf_index
= emit_uniformize(surf_index
);
1853 /* Assume this may touch any UBO. It would be nice to provide
1854 * a tighter bound, but the array information is already lowered away.
1856 brw_mark_surface_used(&prog_data
->base
,
1857 prog_data
->base
.binding_table
.ubo_start
+
1858 shader_prog
->NumUniformBlocks
- 1);
1861 if (const_offset_ir
) {
1862 if (devinfo
->gen
>= 8) {
1863 /* Store the offset in a GRF so we can send-from-GRF. */
1864 offset
= src_reg(this, glsl_type::int_type
);
1865 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1867 /* Immediates are fine on older generations since they'll be moved
1868 * to a (potentially fake) MRF at the generator level.
1870 offset
= src_reg(const_offset
/ 16);
1873 offset
= src_reg(this, glsl_type::uint_type
);
1874 emit(SHR(dst_reg(offset
), op
[1], src_reg(4u)));
1877 emit_pull_constant_load_reg(dst_reg(packed_consts
),
1880 NULL
, NULL
/* before_block/inst */);
1882 packed_consts
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
1883 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1884 const_offset
% 16 / 4,
1885 const_offset
% 16 / 4,
1886 const_offset
% 16 / 4);
1888 /* UBO bools are any nonzero int. We need to convert them to 0/~0. */
1889 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1890 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1891 BRW_CONDITIONAL_NZ
));
1893 emit(MOV(result_dst
, packed_consts
));
1898 case ir_binop_vector_extract
:
1899 unreachable("should have been lowered by vec_index_to_cond_assign");
1902 op
[0] = fix_3src_operand(op
[0]);
1903 op
[1] = fix_3src_operand(op
[1]);
1904 op
[2] = fix_3src_operand(op
[2]);
1905 /* Note that the instruction's argument order is reversed from GLSL
1908 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1912 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1916 unreachable("already handled above");
1920 op
[0] = fix_3src_operand(op
[0]);
1921 op
[1] = fix_3src_operand(op
[1]);
1922 op
[2] = fix_3src_operand(op
[2]);
1923 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1926 case ir_triop_bitfield_extract
:
1927 op
[0] = fix_3src_operand(op
[0]);
1928 op
[1] = fix_3src_operand(op
[1]);
1929 op
[2] = fix_3src_operand(op
[2]);
1930 /* Note that the instruction's argument order is reversed from GLSL
1933 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1936 case ir_triop_vector_insert
:
1937 unreachable("should have been lowered by lower_vector_insert");
1939 case ir_quadop_bitfield_insert
:
1940 unreachable("not reached: should be handled by "
1941 "bitfield_insert_to_bfm_bfi\n");
1943 case ir_quadop_vector
:
1944 unreachable("not reached: should be handled by lower_quadop_vector");
1946 case ir_unop_pack_half_2x16
:
1947 emit_pack_half_2x16(result_dst
, op
[0]);
1949 case ir_unop_unpack_half_2x16
:
1950 emit_unpack_half_2x16(result_dst
, op
[0]);
1952 case ir_unop_unpack_unorm_4x8
:
1953 emit_unpack_unorm_4x8(result_dst
, op
[0]);
1955 case ir_unop_unpack_snorm_4x8
:
1956 emit_unpack_snorm_4x8(result_dst
, op
[0]);
1958 case ir_unop_pack_unorm_4x8
:
1959 emit_pack_unorm_4x8(result_dst
, op
[0]);
1961 case ir_unop_pack_snorm_4x8
:
1962 emit_pack_snorm_4x8(result_dst
, op
[0]);
1964 case ir_unop_pack_snorm_2x16
:
1965 case ir_unop_pack_unorm_2x16
:
1966 case ir_unop_unpack_snorm_2x16
:
1967 case ir_unop_unpack_unorm_2x16
:
1968 unreachable("not reached: should be handled by lower_packing_builtins");
1969 case ir_unop_unpack_half_2x16_split_x
:
1970 case ir_unop_unpack_half_2x16_split_y
:
1971 case ir_binop_pack_half_2x16_split
:
1972 case ir_unop_interpolate_at_centroid
:
1973 case ir_binop_interpolate_at_sample
:
1974 case ir_binop_interpolate_at_offset
:
1975 unreachable("not reached: should not occur in vertex shader");
1976 case ir_binop_ldexp
:
1977 unreachable("not reached: should be handled by ldexp_to_arith()");
1985 case ir_unop_pack_double_2x32
:
1986 case ir_unop_unpack_double_2x32
:
1987 case ir_unop_frexp_sig
:
1988 case ir_unop_frexp_exp
:
1989 unreachable("fp64 todo");
1995 vec4_visitor::visit(ir_swizzle
*ir
)
1997 /* Note that this is only swizzles in expressions, not those on the left
1998 * hand side of an assignment, which do write masking. See ir_assignment
2001 const unsigned swz
= brw_compose_swizzle(
2002 brw_swizzle_for_size(ir
->type
->vector_elements
),
2003 BRW_SWIZZLE4(ir
->mask
.x
, ir
->mask
.y
, ir
->mask
.z
, ir
->mask
.w
));
2005 ir
->val
->accept(this);
2006 this->result
= swizzle(this->result
, swz
);
2010 vec4_visitor::visit(ir_dereference_variable
*ir
)
2012 const struct glsl_type
*type
= ir
->type
;
2013 dst_reg
*reg
= variable_storage(ir
->var
);
2016 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
2017 this->result
= src_reg(brw_null_reg());
2021 this->result
= src_reg(*reg
);
2023 /* System values get their swizzle from the dst_reg writemask */
2024 if (ir
->var
->data
.mode
== ir_var_system_value
)
2027 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
2028 this->result
.swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2033 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
2035 /* Under normal circumstances array elements are stored consecutively, so
2036 * the stride is equal to the size of the array element.
2038 return type_size(ir
->type
);
2043 vec4_visitor::visit(ir_dereference_array
*ir
)
2045 ir_constant
*constant_index
;
2047 int array_stride
= compute_array_stride(ir
);
2049 constant_index
= ir
->array_index
->constant_expression_value();
2051 ir
->array
->accept(this);
2054 if (constant_index
) {
2055 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
2057 /* Variable index array dereference. It eats the "vec4" of the
2058 * base of the array and an index that offsets the Mesa register
2061 ir
->array_index
->accept(this);
2065 if (array_stride
== 1) {
2066 index_reg
= this->result
;
2068 index_reg
= src_reg(this, glsl_type::int_type
);
2070 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
2074 src_reg temp
= src_reg(this, glsl_type::int_type
);
2076 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
2081 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
2082 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2085 /* If the type is smaller than a vec4, replicate the last channel out. */
2086 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2087 src
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2089 src
.swizzle
= BRW_SWIZZLE_NOOP
;
2090 src
.type
= brw_type_for_base_type(ir
->type
);
2096 vec4_visitor::visit(ir_dereference_record
*ir
)
2099 const glsl_type
*struct_type
= ir
->record
->type
;
2102 ir
->record
->accept(this);
2104 for (i
= 0; i
< struct_type
->length
; i
++) {
2105 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2107 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2110 /* If the type is smaller than a vec4, replicate the last channel out. */
2111 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2112 this->result
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2114 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
2115 this->result
.type
= brw_type_for_base_type(ir
->type
);
2117 this->result
.reg_offset
+= offset
;
2121 * We want to be careful in assignment setup to hit the actual storage
2122 * instead of potentially using a temporary like we might with the
2123 * ir_dereference handler.
2126 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
2128 /* The LHS must be a dereference. If the LHS is a variable indexed array
2129 * access of a vector, it must be separated into a series conditional moves
2130 * before reaching this point (see ir_vec_index_to_cond_assign).
2132 assert(ir
->as_dereference());
2133 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2135 assert(!deref_array
->array
->type
->is_vector());
2138 /* Use the rvalue deref handler for the most part. We'll ignore
2139 * swizzles in it and write swizzles using writemask, though.
2142 return dst_reg(v
->result
);
2146 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
2147 const struct glsl_type
*type
,
2148 enum brw_predicate predicate
)
2150 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2151 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2152 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
2157 if (type
->is_array()) {
2158 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2159 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
2164 if (type
->is_matrix()) {
2165 const struct glsl_type
*vec_type
;
2167 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2168 type
->vector_elements
, 1);
2170 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2171 emit_block_move(dst
, src
, vec_type
, predicate
);
2176 assert(type
->is_scalar() || type
->is_vector());
2178 dst
->type
= brw_type_for_base_type(type
);
2179 src
->type
= dst
->type
;
2181 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2183 src
->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2185 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2186 inst
->predicate
= predicate
;
2193 /* If the RHS processing resulted in an instruction generating a
2194 * temporary value, and it would be easy to rewrite the instruction to
2195 * generate its result right into the LHS instead, do so. This ends
2196 * up reliably removing instructions where it can be tricky to do so
2197 * later without real UD chain information.
2200 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2203 vec4_instruction
*pre_rhs_inst
,
2204 vec4_instruction
*last_rhs_inst
)
2206 /* This could be supported, but it would take more smarts. */
2210 if (pre_rhs_inst
== last_rhs_inst
)
2211 return false; /* No instructions generated to work with. */
2213 /* Make sure the last instruction generated our source reg. */
2214 if (src
.file
!= GRF
||
2215 src
.file
!= last_rhs_inst
->dst
.file
||
2216 src
.reg
!= last_rhs_inst
->dst
.reg
||
2217 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2221 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2224 /* Check that that last instruction fully initialized the channels
2225 * we want to use, in the order we want to use them. We could
2226 * potentially reswizzle the operands of many instructions so that
2227 * we could handle out of order channels, but don't yet.
2230 for (unsigned i
= 0; i
< 4; i
++) {
2231 if (dst
.writemask
& (1 << i
)) {
2232 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2235 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2240 /* Success! Rewrite the instruction. */
2241 last_rhs_inst
->dst
.file
= dst
.file
;
2242 last_rhs_inst
->dst
.reg
= dst
.reg
;
2243 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2244 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2245 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2251 vec4_visitor::visit(ir_assignment
*ir
)
2253 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2254 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2256 if (!ir
->lhs
->type
->is_scalar() &&
2257 !ir
->lhs
->type
->is_vector()) {
2258 ir
->rhs
->accept(this);
2259 src_reg src
= this->result
;
2261 if (ir
->condition
) {
2262 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2265 /* emit_block_move doesn't account for swizzles in the source register.
2266 * This should be ok, since the source register is a structure or an
2267 * array, and those can't be swizzled. But double-check to be sure.
2269 assert(src
.swizzle
==
2270 (ir
->rhs
->type
->is_matrix()
2271 ? brw_swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2272 : BRW_SWIZZLE_NOOP
));
2274 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2278 /* Now we're down to just a scalar/vector with writemasks. */
2281 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2282 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2284 ir
->rhs
->accept(this);
2286 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2291 assert(ir
->lhs
->type
->is_vector() ||
2292 ir
->lhs
->type
->is_scalar());
2293 dst
.writemask
= ir
->write_mask
;
2295 /* Swizzle a small RHS vector into the channels being written.
2297 * glsl ir treats write_mask as dictating how many channels are
2298 * present on the RHS while in our instructions we need to make
2299 * those channels appear in the slots of the vec4 they're written to.
2301 for (int i
= 0; i
< 4; i
++)
2302 swizzles
[i
] = (ir
->write_mask
& (1 << i
) ? src_chan
++ : 0);
2304 src_reg src
= swizzle(this->result
,
2305 BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2306 swizzles
[2], swizzles
[3]));
2308 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2312 if (ir
->condition
) {
2313 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2316 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2317 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2318 inst
->predicate
= predicate
;
2326 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2328 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2329 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2330 emit_constant_values(dst
, field_value
);
2335 if (ir
->type
->is_array()) {
2336 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2337 emit_constant_values(dst
, ir
->array_elements
[i
]);
2342 if (ir
->type
->is_matrix()) {
2343 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2344 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2346 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2347 dst
->writemask
= 1 << j
;
2348 dst
->type
= BRW_REGISTER_TYPE_F
;
2350 emit(MOV(*dst
, src_reg(vec
[j
])));
2357 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2359 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2360 if (!(remaining_writemask
& (1 << i
)))
2363 dst
->writemask
= 1 << i
;
2364 dst
->type
= brw_type_for_base_type(ir
->type
);
2366 /* Find other components that match the one we're about to
2367 * write. Emits fewer instructions for things like vec4(0.5,
2370 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2371 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2372 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2373 dst
->writemask
|= (1 << j
);
2375 /* u, i, and f storage all line up, so no need for a
2376 * switch case for comparing each type.
2378 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2379 dst
->writemask
|= (1 << j
);
2383 switch (ir
->type
->base_type
) {
2384 case GLSL_TYPE_FLOAT
:
2385 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2388 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2390 case GLSL_TYPE_UINT
:
2391 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2393 case GLSL_TYPE_BOOL
:
2394 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
] != 0 ? ~0 : 0)));
2397 unreachable("Non-float/uint/int/bool constant");
2400 remaining_writemask
&= ~dst
->writemask
;
2406 vec4_visitor::visit(ir_constant
*ir
)
2408 dst_reg dst
= dst_reg(this, ir
->type
);
2409 this->result
= src_reg(dst
);
2411 emit_constant_values(&dst
, ir
);
2415 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2417 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2418 ir
->actual_parameters
.get_head());
2419 ir_variable
*location
= deref
->variable_referenced();
2420 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2421 location
->data
.binding
);
2423 /* Calculate the surface offset */
2424 src_reg
offset(this, glsl_type::uint_type
);
2425 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2427 deref_array
->array_index
->accept(this);
2429 src_reg
tmp(this, glsl_type::uint_type
);
2430 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2431 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2433 offset
= location
->data
.atomic
.offset
;
2436 /* Emit the appropriate machine instruction */
2437 const char *callee
= ir
->callee
->function_name();
2438 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2440 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2441 emit_untyped_surface_read(surf_index
, dst
, offset
);
2443 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2444 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2445 src_reg(), src_reg());
2447 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2448 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2449 src_reg(), src_reg());
2452 brw_mark_surface_used(stage_prog_data
, surf_index
);
2456 vec4_visitor::visit(ir_call
*ir
)
2458 const char *callee
= ir
->callee
->function_name();
2460 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2461 !strcmp("__intrinsic_atomic_increment", callee
) ||
2462 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2463 visit_atomic_counter_intrinsic(ir
);
2465 unreachable("Unsupported intrinsic.");
2470 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
)
2472 vec4_instruction
*inst
=
2473 new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
,
2474 dst_reg(this, glsl_type::uvec4_type
));
2476 inst
->src
[1] = sampler
;
2480 if (devinfo
->gen
>= 9) {
2481 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
2482 vec4_instruction
*header_inst
= new(mem_ctx
)
2483 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
2484 dst_reg(MRF
, inst
->base_mrf
));
2489 inst
->header_size
= 1;
2490 param_base
= inst
->base_mrf
+ 1;
2493 param_base
= inst
->base_mrf
;
2496 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2497 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2498 int zero_mask
= 0xf & ~coord_mask
;
2500 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2503 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2507 return src_reg(inst
->dst
);
2511 is_high_sampler(const struct brw_device_info
*devinfo
, src_reg sampler
)
2513 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
2516 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2520 vec4_visitor::visit(ir_texture
*ir
)
2523 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2525 ir_rvalue
*nonconst_sampler_index
=
2526 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2528 /* Handle non-constant sampler array indexing */
2529 src_reg sampler_reg
;
2530 if (nonconst_sampler_index
) {
2531 /* The highest sampler which may be used by this operation is
2532 * the last element of the array. Mark it here, because the generator
2533 * doesn't have enough information to determine the bound.
2535 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2536 ->array
->type
->array_size();
2538 uint32_t max_used
= sampler
+ array_size
- 1;
2539 if (ir
->op
== ir_tg4
&& devinfo
->gen
< 8) {
2540 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2542 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2545 brw_mark_surface_used(&prog_data
->base
, max_used
);
2547 /* Emit code to evaluate the actual indexing expression */
2548 nonconst_sampler_index
->accept(this);
2549 src_reg
temp(this, glsl_type::uint_type
);
2550 emit(ADD(dst_reg(temp
), this->result
, src_reg(sampler
)));
2551 sampler_reg
= emit_uniformize(temp
);
2553 /* Single sampler, or constant array index; the indexing expression
2554 * is just an immediate.
2556 sampler_reg
= src_reg(sampler
);
2559 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2560 * emitting anything other than setting up the constant result.
2562 if (ir
->op
== ir_tg4
) {
2563 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2564 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2565 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2566 dst_reg
result(this, ir
->type
);
2567 this->result
= src_reg(result
);
2568 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2573 /* Should be lowered by do_lower_texture_projection */
2574 assert(!ir
->projector
);
2576 /* Should be lowered */
2577 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2579 /* Generate code to compute all the subexpression trees. This has to be
2580 * done before loading any values into MRFs for the sampler message since
2581 * generating these values may involve SEND messages that need the MRFs.
2584 if (ir
->coordinate
) {
2585 ir
->coordinate
->accept(this);
2586 coordinate
= this->result
;
2589 src_reg shadow_comparitor
;
2590 if (ir
->shadow_comparitor
) {
2591 ir
->shadow_comparitor
->accept(this);
2592 shadow_comparitor
= this->result
;
2595 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2596 src_reg offset_value
;
2597 if (has_nonconstant_offset
) {
2598 ir
->offset
->accept(this);
2599 offset_value
= src_reg(this->result
);
2602 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2603 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2606 lod
= src_reg(0.0f
);
2607 lod_type
= glsl_type::float_type
;
2612 ir
->lod_info
.lod
->accept(this);
2614 lod_type
= ir
->lod_info
.lod
->type
;
2616 case ir_query_levels
:
2618 lod_type
= glsl_type::int_type
;
2621 ir
->lod_info
.sample_index
->accept(this);
2622 sample_index
= this->result
;
2623 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2625 if (devinfo
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2626 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
2631 ir
->lod_info
.grad
.dPdx
->accept(this);
2632 dPdx
= this->result
;
2634 ir
->lod_info
.grad
.dPdy
->accept(this);
2635 dPdy
= this->result
;
2637 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2647 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2648 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2649 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2650 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2651 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2652 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2653 case ir_tg4
: opcode
= has_nonconstant_offset
2654 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2655 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2657 unreachable("TXB is not valid for vertex shaders.");
2659 unreachable("LOD is not valid for vertex shaders.");
2661 unreachable("Unrecognized tex op");
2664 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(
2665 opcode
, dst_reg(this, ir
->type
));
2667 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2669 brw_texture_offset(ir
->offset
->as_constant()->value
.i
,
2670 ir
->offset
->type
->vector_elements
);
2673 /* Stuff the channel select bits in the top of the texture offset */
2674 if (ir
->op
== ir_tg4
)
2675 inst
->offset
|= gather_channel(ir
, sampler
) << 16;
2677 /* The message header is necessary for:
2679 * - Gen9+ for selecting SIMD4x2
2681 * - Gather channel selection
2682 * - Sampler indices too large to fit in a 4-bit value.
2685 (devinfo
->gen
< 5 || devinfo
->gen
>= 9 ||
2686 inst
->offset
!= 0 || ir
->op
== ir_tg4
||
2687 is_high_sampler(devinfo
, sampler_reg
)) ? 1 : 0;
2689 inst
->mlen
= inst
->header_size
+ 1; /* always at least one */
2690 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2691 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2693 inst
->src
[1] = sampler_reg
;
2695 /* MRF for the first parameter */
2696 int param_base
= inst
->base_mrf
+ inst
->header_size
;
2698 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2699 int writemask
= devinfo
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2700 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2702 /* Load the coordinate */
2703 /* FINISHME: gl_clamp_mask and saturate */
2704 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2705 int zero_mask
= 0xf & ~coord_mask
;
2707 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2710 if (zero_mask
!= 0) {
2711 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2714 /* Load the shadow comparitor */
2715 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2716 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2718 shadow_comparitor
));
2722 /* Load the LOD info */
2723 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2725 if (devinfo
->gen
>= 5) {
2726 mrf
= param_base
+ 1;
2727 if (ir
->shadow_comparitor
) {
2728 writemask
= WRITEMASK_Y
;
2729 /* mlen already incremented */
2731 writemask
= WRITEMASK_X
;
2734 } else /* devinfo->gen == 4 */ {
2736 writemask
= WRITEMASK_W
;
2738 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2739 } else if (ir
->op
== ir_txf
) {
2740 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2741 } else if (ir
->op
== ir_txf_ms
) {
2742 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2744 if (devinfo
->gen
>= 7) {
2745 /* MCS data is in the first channel of `mcs`, but we need to get it into
2746 * the .y channel of the second vec4 of params, so replicate .x across
2747 * the whole vec4 and then mask off everything except .y
2749 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2750 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2754 } else if (ir
->op
== ir_txd
) {
2755 const glsl_type
*type
= lod_type
;
2757 if (devinfo
->gen
>= 5) {
2758 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2759 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2760 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2761 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2764 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2765 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2766 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2767 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2768 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2771 if (ir
->shadow_comparitor
) {
2772 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2773 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2774 shadow_comparitor
));
2777 } else /* devinfo->gen == 4 */ {
2778 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2779 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2782 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2783 if (ir
->shadow_comparitor
) {
2784 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2785 shadow_comparitor
));
2788 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2796 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2797 * spec requires layers.
2799 if (ir
->op
== ir_txs
) {
2800 glsl_type
const *type
= ir
->sampler
->type
;
2801 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2802 type
->sampler_array
) {
2803 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2804 writemask(inst
->dst
, WRITEMASK_Z
),
2805 src_reg(inst
->dst
), src_reg(6));
2809 if (devinfo
->gen
== 6 && ir
->op
== ir_tg4
) {
2810 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2813 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2817 * Apply workarounds for Gen6 gather with UINT/SINT
2820 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2825 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2826 dst_reg dst_f
= dst
;
2827 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2829 /* Convert from UNORM to UINT */
2830 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2831 emit(MOV(dst
, src_reg(dst_f
)));
2834 /* Reinterpret the UINT value as a signed INT value by
2835 * shifting the sign bit into place, then shifting back
2838 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2839 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2844 * Set up the gather channel based on the swizzle, for gather4.
2847 vec4_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2849 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2850 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2852 case SWIZZLE_X
: return 0;
2854 /* gather4 sampler is broken for green channel on RG32F --
2855 * we must ask for blue instead.
2857 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2860 case SWIZZLE_Z
: return 2;
2861 case SWIZZLE_W
: return 3;
2863 unreachable("Not reached"); /* zero, one swizzles handled already */
2868 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
)
2870 int s
= key
->tex
.swizzles
[sampler
];
2872 this->result
= src_reg(this, ir
->type
);
2873 dst_reg
swizzled_result(this->result
);
2875 if (ir
->op
== ir_query_levels
) {
2876 /* # levels is in .w */
2877 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2878 emit(MOV(swizzled_result
, orig_val
));
2882 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2883 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2884 emit(MOV(swizzled_result
, orig_val
));
2889 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2890 int swizzle
[4] = {0};
2892 for (int i
= 0; i
< 4; i
++) {
2893 switch (GET_SWZ(s
, i
)) {
2895 zero_mask
|= (1 << i
);
2898 one_mask
|= (1 << i
);
2901 copy_mask
|= (1 << i
);
2902 swizzle
[i
] = GET_SWZ(s
, i
);
2908 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2909 swizzled_result
.writemask
= copy_mask
;
2910 emit(MOV(swizzled_result
, orig_val
));
2914 swizzled_result
.writemask
= zero_mask
;
2915 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2919 swizzled_result
.writemask
= one_mask
;
2920 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2925 vec4_visitor::visit(ir_return
*)
2927 unreachable("not reached");
2931 vec4_visitor::visit(ir_discard
*)
2933 unreachable("not reached");
2937 vec4_visitor::visit(ir_if
*ir
)
2939 /* Don't point the annotation at the if statement, because then it plus
2940 * the then and else blocks get printed.
2942 this->base_ir
= ir
->condition
;
2944 if (devinfo
->gen
== 6) {
2947 enum brw_predicate predicate
;
2948 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2949 emit(IF(predicate
));
2952 visit_instructions(&ir
->then_instructions
);
2954 if (!ir
->else_instructions
.is_empty()) {
2955 this->base_ir
= ir
->condition
;
2956 emit(BRW_OPCODE_ELSE
);
2958 visit_instructions(&ir
->else_instructions
);
2961 this->base_ir
= ir
->condition
;
2962 emit(BRW_OPCODE_ENDIF
);
2966 vec4_visitor::visit(ir_emit_vertex
*)
2968 unreachable("not reached");
2972 vec4_visitor::visit(ir_end_primitive
*)
2974 unreachable("not reached");
2978 vec4_visitor::visit(ir_barrier
*)
2980 unreachable("not reached");
2984 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2985 dst_reg dst
, src_reg offset
,
2986 src_reg src0
, src_reg src1
)
2990 /* Set the atomic operation offset. */
2991 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2994 /* Set the atomic operation arguments. */
2995 if (src0
.file
!= BAD_FILE
) {
2996 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
3000 if (src1
.file
!= BAD_FILE
) {
3001 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
3005 /* Emit the instruction. Note that this maps to the normal SIMD8
3006 * untyped atomic message on Ivy Bridge, but that's OK because
3007 * unused channels will be masked out.
3009 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
3011 src_reg(surf_index
), src_reg(atomic_op
));
3016 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
3019 /* Set the surface read offset. */
3020 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
3022 /* Emit the instruction. Note that this maps to the normal SIMD8
3023 * untyped surface read message, but that's OK because unused
3024 * channels will be masked out.
3026 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
,
3028 src_reg(surf_index
), src_reg(1));
3033 vec4_visitor::emit_ndc_computation()
3035 /* Get the position */
3036 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
3038 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
3039 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
3040 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
3042 current_annotation
= "NDC";
3043 dst_reg ndc_w
= ndc
;
3044 ndc_w
.writemask
= WRITEMASK_W
;
3045 src_reg pos_w
= pos
;
3046 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
3047 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
3049 dst_reg ndc_xyz
= ndc
;
3050 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
3052 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
3056 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
3058 if (devinfo
->gen
< 6 &&
3059 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
3060 key
->userclip_active
|| devinfo
->has_negative_rhw_bug
)) {
3061 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
3062 dst_reg header1_w
= header1
;
3063 header1_w
.writemask
= WRITEMASK_W
;
3065 emit(MOV(header1
, 0u));
3067 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3068 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
3070 current_annotation
= "Point size";
3071 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
3072 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
3075 if (key
->userclip_active
) {
3076 current_annotation
= "Clipping flags";
3077 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
3078 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
3080 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3081 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
3082 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
3084 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3085 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
3086 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
3087 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
3090 /* i965 clipping workaround:
3091 * 1) Test for -ve rhw
3093 * set ndc = (0,0,0,0)
3096 * Later, clipping will detect ucp[6] and ensure the primitive is
3097 * clipped against all fixed planes.
3099 if (devinfo
->has_negative_rhw_bug
) {
3100 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
3101 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
3102 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
3103 vec4_instruction
*inst
;
3104 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
3105 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3106 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
3107 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3110 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
3111 } else if (devinfo
->gen
< 6) {
3112 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
3114 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
3115 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3116 dst_reg reg_w
= reg
;
3117 reg_w
.writemask
= WRITEMASK_W
;
3118 emit(MOV(reg_w
, src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
3120 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
3121 dst_reg reg_y
= reg
;
3122 reg_y
.writemask
= WRITEMASK_Y
;
3123 reg_y
.type
= BRW_REGISTER_TYPE_D
;
3124 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
3126 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
3127 dst_reg reg_z
= reg
;
3128 reg_z
.writemask
= WRITEMASK_Z
;
3129 reg_z
.type
= BRW_REGISTER_TYPE_D
;
3130 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
3136 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
3138 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3140 * "If a linked set of shaders forming the vertex stage contains no
3141 * static write to gl_ClipVertex or gl_ClipDistance, but the
3142 * application has requested clipping against user clip planes through
3143 * the API, then the coordinate written to gl_Position is used for
3144 * comparison against the user clip planes."
3146 * This function is only called if the shader didn't write to
3147 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3148 * if the user wrote to it; otherwise we use gl_Position.
3150 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3151 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
3152 clip_vertex
= VARYING_SLOT_POS
;
3155 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
3157 reg
.writemask
= 1 << i
;
3159 src_reg(output_reg
[clip_vertex
]),
3160 src_reg(this->userplane
[i
+ offset
])));
3165 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
3167 assert (varying
< VARYING_SLOT_MAX
);
3168 reg
.type
= output_reg
[varying
].type
;
3169 current_annotation
= output_reg_annotation
[varying
];
3170 /* Copy the register, saturating if necessary */
3171 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
3175 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
3177 reg
.type
= BRW_REGISTER_TYPE_F
;
3180 case VARYING_SLOT_PSIZ
:
3182 /* PSIZ is always in slot 0, and is coupled with other flags. */
3183 current_annotation
= "indices, point width, clip flags";
3184 emit_psiz_and_flags(reg
);
3187 case BRW_VARYING_SLOT_NDC
:
3188 current_annotation
= "NDC";
3189 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
3191 case VARYING_SLOT_POS
:
3192 current_annotation
= "gl_Position";
3193 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
3195 case VARYING_SLOT_EDGE
:
3196 /* This is present when doing unfilled polygons. We're supposed to copy
3197 * the edge flag from the user-provided vertex array
3198 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3199 * of that attribute (starts as 1.0f). This is then used in clipping to
3200 * determine which edges should be drawn as wireframe.
3202 current_annotation
= "edge flag";
3203 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3204 glsl_type::float_type
, WRITEMASK_XYZW
))));
3206 case BRW_VARYING_SLOT_PAD
:
3207 /* No need to write to this slot */
3209 case VARYING_SLOT_COL0
:
3210 case VARYING_SLOT_COL1
:
3211 case VARYING_SLOT_BFC0
:
3212 case VARYING_SLOT_BFC1
: {
3213 /* These built-in varyings are only supported in compatibility mode,
3214 * and we only support GS in core profile. So, this must be a vertex
3217 assert(stage
== MESA_SHADER_VERTEX
);
3218 vec4_instruction
*inst
= emit_generic_urb_slot(reg
, varying
);
3219 if (((struct brw_vs_prog_key
*) key
)->clamp_vertex_color
)
3220 inst
->saturate
= true;
3225 emit_generic_urb_slot(reg
, varying
);
3231 align_interleaved_urb_mlen(const struct brw_device_info
*devinfo
, int mlen
)
3233 if (devinfo
->gen
>= 6) {
3234 /* URB data written (does not include the message header reg) must
3235 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3236 * section 5.4.3.2.2: URB_INTERLEAVED.
3238 * URB entries are allocated on a multiple of 1024 bits, so an
3239 * extra 128 bits written here to make the end align to 256 is
3242 if ((mlen
% 2) != 1)
3251 * Generates the VUE payload plus the necessary URB write instructions to
3254 * The VUE layout is documented in Volume 2a.
3257 vec4_visitor::emit_vertex()
3259 /* MRF 0 is reserved for the debugger, so start with message header
3264 /* In the process of generating our URB write message contents, we
3265 * may need to unspill a register or load from an array. Those
3266 * reads would use MRFs 14-15.
3268 int max_usable_mrf
= 13;
3270 /* The following assertion verifies that max_usable_mrf causes an
3271 * even-numbered amount of URB write data, which will meet gen6's
3272 * requirements for length alignment.
3274 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3276 /* First mrf is the g0-based message header containing URB handles and
3279 emit_urb_write_header(mrf
++);
3281 if (devinfo
->gen
< 6) {
3282 emit_ndc_computation();
3285 /* Lower legacy ff and ClipVertex clipping to clip distances */
3286 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3287 current_annotation
= "user clip distances";
3289 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3290 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3292 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3293 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3296 /* We may need to split this up into several URB writes, so do them in a
3300 bool complete
= false;
3302 /* URB offset is in URB row increments, and each of our MRFs is half of
3303 * one of those, since we're doing interleaved writes.
3305 int offset
= slot
/ 2;
3308 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3309 emit_urb_slot(dst_reg(MRF
, mrf
++),
3310 prog_data
->vue_map
.slot_to_varying
[slot
]);
3312 /* If this was max_usable_mrf, we can't fit anything more into this
3315 if (mrf
> max_usable_mrf
) {
3321 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3322 current_annotation
= "URB write";
3323 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3324 inst
->base_mrf
= base_mrf
;
3325 inst
->mlen
= align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
);
3326 inst
->offset
+= offset
;
3332 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3333 src_reg
*reladdr
, int reg_offset
)
3335 /* Because we store the values to scratch interleaved like our
3336 * vertex data, we need to scale the vec4 index by 2.
3338 int message_header_scale
= 2;
3340 /* Pre-gen6, the message header uses byte offsets instead of vec4
3341 * (16-byte) offset units.
3343 if (devinfo
->gen
< 6)
3344 message_header_scale
*= 16;
3347 src_reg index
= src_reg(this, glsl_type::int_type
);
3349 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3350 src_reg(reg_offset
)));
3351 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3352 src_reg(message_header_scale
)));
3356 return src_reg(reg_offset
* message_header_scale
);
3361 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3362 src_reg
*reladdr
, int reg_offset
)
3365 src_reg index
= src_reg(this, glsl_type::int_type
);
3367 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3368 src_reg(reg_offset
)));
3370 /* Pre-gen6, the message header uses byte offsets instead of vec4
3371 * (16-byte) offset units.
3373 if (devinfo
->gen
< 6) {
3374 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3378 } else if (devinfo
->gen
>= 8) {
3379 /* Store the offset in a GRF so we can send-from-GRF. */
3380 src_reg offset
= src_reg(this, glsl_type::int_type
);
3381 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3384 int message_header_scale
= devinfo
->gen
< 6 ? 16 : 1;
3385 return src_reg(reg_offset
* message_header_scale
);
3390 * Emits an instruction before @inst to load the value named by @orig_src
3391 * from scratch space at @base_offset to @temp.
3393 * @base_offset is measured in 32-byte units (the size of a register).
3396 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3397 dst_reg temp
, src_reg orig_src
,
3400 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3401 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3404 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3408 * Emits an instruction after @inst to store the value to be written
3409 * to @orig_dst to scratch space at @base_offset, from @temp.
3411 * @base_offset is measured in 32-byte units (the size of a register).
3414 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3417 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3418 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3421 /* Create a temporary register to store *inst's result in.
3423 * We have to be careful in MOVing from our temporary result register in
3424 * the scratch write. If we swizzle from channels of the temporary that
3425 * weren't initialized, it will confuse live interval analysis, which will
3426 * make spilling fail to make progress.
3428 const src_reg temp
= swizzle(retype(src_reg(this, glsl_type::vec4_type
),
3430 brw_swizzle_for_mask(inst
->dst
.writemask
));
3431 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3432 inst
->dst
.writemask
));
3433 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3434 write
->predicate
= inst
->predicate
;
3435 write
->ir
= inst
->ir
;
3436 write
->annotation
= inst
->annotation
;
3437 inst
->insert_after(block
, write
);
3439 inst
->dst
.file
= temp
.file
;
3440 inst
->dst
.reg
= temp
.reg
;
3441 inst
->dst
.reg_offset
= temp
.reg_offset
;
3442 inst
->dst
.reladdr
= NULL
;
3446 * Checks if \p src and/or \p src.reladdr require a scratch read, and if so,
3447 * adds the scratch read(s) before \p inst. The function also checks for
3448 * recursive reladdr scratch accesses, issuing the corresponding scratch
3449 * loads and rewriting reladdr references accordingly.
3451 * \return \p src if it did not require a scratch load, otherwise, the
3452 * register holding the result of the scratch load that the caller should
3453 * use to rewrite src.
3456 vec4_visitor::emit_resolve_reladdr(int scratch_loc
[], bblock_t
*block
,
3457 vec4_instruction
*inst
, src_reg src
)
3459 /* Resolve recursive reladdr scratch access by calling ourselves
3463 *src
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3466 /* Now handle scratch access on src */
3467 if (src
.file
== GRF
&& scratch_loc
[src
.reg
] != -1) {
3468 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3469 emit_scratch_read(block
, inst
, temp
, src
, scratch_loc
[src
.reg
]);
3471 src
.reg_offset
= temp
.reg_offset
;
3479 * We can't generally support array access in GRF space, because a
3480 * single instruction's destination can only span 2 contiguous
3481 * registers. So, we send all GRF arrays that get variable index
3482 * access to scratch space.
3485 vec4_visitor::move_grf_array_access_to_scratch()
3487 int scratch_loc
[this->alloc
.count
];
3488 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3490 /* First, calculate the set of virtual GRFs that need to be punted
3491 * to scratch due to having any array access on them, and where in
3494 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3495 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
) {
3496 if (scratch_loc
[inst
->dst
.reg
] == -1) {
3497 scratch_loc
[inst
->dst
.reg
] = last_scratch
;
3498 last_scratch
+= this->alloc
.sizes
[inst
->dst
.reg
];
3501 for (src_reg
*iter
= inst
->dst
.reladdr
;
3503 iter
= iter
->reladdr
) {
3504 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3505 scratch_loc
[iter
->reg
] = last_scratch
;
3506 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3511 for (int i
= 0 ; i
< 3; i
++) {
3512 for (src_reg
*iter
= &inst
->src
[i
];
3514 iter
= iter
->reladdr
) {
3515 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3516 scratch_loc
[iter
->reg
] = last_scratch
;
3517 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3523 /* Now, for anything that will be accessed through scratch, rewrite
3524 * it to load/store. Note that this is a _safe list walk, because
3525 * we may generate a new scratch_write instruction after the one
3528 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3529 /* Set up the annotation tracking for new generated instructions. */
3531 current_annotation
= inst
->annotation
;
3533 /* First handle scratch access on the dst. Notice we have to handle
3534 * the case where the dst's reladdr also points to scratch space.
3536 if (inst
->dst
.reladdr
)
3537 *inst
->dst
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3538 *inst
->dst
.reladdr
);
3540 /* Now that we have handled any (possibly recursive) reladdr scratch
3541 * accesses for dst we can safely do the scratch write for dst itself
3543 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1)
3544 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3546 /* Now handle scratch access on any src. In this case, since inst->src[i]
3547 * already is a src_reg, we can just call emit_resolve_reladdr with
3548 * inst->src[i] and it will take care of handling scratch loads for
3549 * both src and src.reladdr (recursively).
3551 for (int i
= 0 ; i
< 3; i
++) {
3552 inst
->src
[i
] = emit_resolve_reladdr(scratch_loc
, block
, inst
,
3559 * Emits an instruction before @inst to load the value named by @orig_src
3560 * from the pull constant buffer (surface) at @base_offset to @temp.
3563 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3564 dst_reg temp
, src_reg orig_src
,
3567 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3568 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3569 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3572 emit_pull_constant_load_reg(temp
,
3579 * Implements array access of uniforms by inserting a
3580 * PULL_CONSTANT_LOAD instruction.
3582 * Unlike temporary GRF array access (where we don't support it due to
3583 * the difficulty of doing relative addressing on instruction
3584 * destinations), we could potentially do array access of uniforms
3585 * that were loaded in GRF space as push constants. In real-world
3586 * usage we've seen, though, the arrays being used are always larger
3587 * than we could load as push constants, so just always move all
3588 * uniform array access out to a pull constant buffer.
3591 vec4_visitor::move_uniform_array_access_to_pull_constants()
3593 int pull_constant_loc
[this->uniforms
];
3594 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3595 bool nested_reladdr
;
3597 /* Walk through and find array access of uniforms. Put a copy of that
3598 * uniform in the pull constant buffer.
3600 * Note that we don't move constant-indexed accesses to arrays. No
3601 * testing has been done of the performance impact of this choice.
3604 nested_reladdr
= false;
3606 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3607 for (int i
= 0 ; i
< 3; i
++) {
3608 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3611 int uniform
= inst
->src
[i
].reg
;
3613 if (inst
->src
[i
].reladdr
->reladdr
)
3614 nested_reladdr
= true; /* will need another pass */
3616 /* If this array isn't already present in the pull constant buffer,
3619 if (pull_constant_loc
[uniform
] == -1) {
3620 const gl_constant_value
**values
=
3621 &stage_prog_data
->param
[uniform
* 4];
3623 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3625 assert(uniform
< uniform_array_size
);
3626 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3627 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3632 /* Set up the annotation tracking for new generated instructions. */
3634 current_annotation
= inst
->annotation
;
3636 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3638 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3639 pull_constant_loc
[uniform
]);
3641 inst
->src
[i
].file
= temp
.file
;
3642 inst
->src
[i
].reg
= temp
.reg
;
3643 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3644 inst
->src
[i
].reladdr
= NULL
;
3647 } while (nested_reladdr
);
3649 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3650 * no need to track them as larger-than-vec4 objects. This will be
3651 * relied on in cutting out unused uniform vectors from push
3654 split_uniform_registers();
3658 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3660 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3664 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3665 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3670 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3672 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3673 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3676 vec4_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, src_reg
*reg
)
3678 assert(devinfo
->gen
<= 5);
3680 if (!rvalue
->type
->is_boolean())
3683 src_reg and_result
= src_reg(this, rvalue
->type
);
3684 src_reg neg_result
= src_reg(this, rvalue
->type
);
3685 emit(AND(dst_reg(and_result
), *reg
, src_reg(1)));
3686 emit(MOV(dst_reg(neg_result
), negate(and_result
)));
3690 vec4_visitor::vec4_visitor(const struct brw_compiler
*compiler
,
3692 struct gl_program
*prog
,
3693 const struct brw_vue_prog_key
*key
,
3694 struct brw_vue_prog_data
*prog_data
,
3695 struct gl_shader_program
*shader_prog
,
3696 gl_shader_stage stage
,
3699 int shader_time_index
)
3700 : backend_shader(compiler
, log_data
, mem_ctx
,
3701 shader_prog
, prog
, &prog_data
->base
, stage
),
3703 prog_data(prog_data
),
3704 sanity_param_count(0),
3706 first_non_payload_grf(0),
3707 need_all_constants_in_pull_buffer(false),
3708 no_spills(no_spills
),
3709 shader_time_index(shader_time_index
),
3712 this->failed
= false;
3714 this->base_ir
= NULL
;
3715 this->current_annotation
= NULL
;
3716 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3718 this->variable_ht
= hash_table_ctor(0,
3719 hash_table_pointer_hash
,
3720 hash_table_pointer_compare
);
3722 this->virtual_grf_start
= NULL
;
3723 this->virtual_grf_end
= NULL
;
3724 this->live_intervals
= NULL
;
3726 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3730 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3731 * at least one. See setup_uniforms() in brw_vec4.cpp.
3733 this->uniform_array_size
= 1;
3735 this->uniform_array_size
=
3736 MAX2(DIV_ROUND_UP(stage_prog_data
->nr_params
, 4), 1);
3739 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3740 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3743 vec4_visitor::~vec4_visitor()
3745 hash_table_dtor(this->variable_ht
);
3750 vec4_visitor::fail(const char *format
, ...)
3760 va_start(va
, format
);
3761 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3763 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
3765 this->fail_msg
= msg
;
3767 if (debug_enabled
) {
3768 fprintf(stderr
, "%s", msg
);
3772 } /* namespace brw */