2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
32 src_reg::src_reg(dst_reg reg
)
36 this->file
= reg
.file
;
38 this->reg_offset
= reg
.reg_offset
;
39 this->type
= reg
.type
;
40 this->reladdr
= reg
.reladdr
;
41 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
47 for (int i
= 0; i
< 4; i
++) {
48 if (!(reg
.writemask
& (1 << i
)))
51 swizzles
[next_chan
++] = last
= i
;
54 for (; next_chan
< 4; next_chan
++) {
55 swizzles
[next_chan
] = last
;
58 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
59 swizzles
[2], swizzles
[3]);
62 dst_reg::dst_reg(src_reg reg
)
66 this->file
= reg
.file
;
68 this->reg_offset
= reg
.reg_offset
;
69 this->type
= reg
.type
;
70 this->writemask
= WRITEMASK_XYZW
;
71 this->reladdr
= reg
.reladdr
;
72 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
75 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
76 enum opcode opcode
, dst_reg dst
,
77 src_reg src0
, src_reg src1
, src_reg src2
)
79 this->opcode
= opcode
;
84 this->ir
= v
->base_ir
;
85 this->annotation
= v
->current_annotation
;
89 vec4_visitor::emit(vec4_instruction
*inst
)
91 this->instructions
.push_tail(inst
);
97 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
99 new_inst
->ir
= inst
->ir
;
100 new_inst
->annotation
= inst
->annotation
;
102 inst
->insert_before(new_inst
);
108 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
109 src_reg src0
, src_reg src1
, src_reg src2
)
111 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
117 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
119 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
123 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
125 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
129 vec4_visitor::emit(enum opcode opcode
)
131 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
136 vec4_visitor::op(dst_reg dst, src_reg src0) \
138 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
144 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
146 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
165 /** Gen4 predicated IF. */
167 vec4_visitor::IF(uint32_t predicate
)
169 vec4_instruction
*inst
;
171 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
172 inst
->predicate
= predicate
;
177 /** Gen6+ IF with embedded comparison. */
179 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
181 assert(intel
->gen
>= 6);
183 vec4_instruction
*inst
;
185 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
187 inst
->conditional_mod
= condition
;
193 * CMP: Sets the low bit of the destination channels with the result
194 * of the comparison, while the upper bits are undefined, and updates
195 * the flag register with the packed 16 bits of the result.
198 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
200 vec4_instruction
*inst
;
202 /* original gen4 does type conversion to the destination type
203 * before before comparison, producing garbage results for floating
207 dst
.type
= src0
.type
;
209 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
210 inst
->conditional_mod
= condition
;
216 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
218 vec4_instruction
*inst
;
220 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_READ
,
229 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
231 vec4_instruction
*inst
;
233 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_WRITE
,
242 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
244 static enum opcode dot_opcodes
[] = {
245 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
248 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
252 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
254 /* The gen6 math instruction ignores the source modifiers --
255 * swizzle, abs, negate, and at least some parts of the register
256 * region description.
258 * While it would seem that this MOV could be avoided at this point
259 * in the case that the swizzle is matched up with the destination
260 * writemask, note that uniform packing and register allocation
261 * could rearrange our swizzle, so let's leave this matter up to
262 * copy propagation later.
264 src_reg temp_src
= src_reg(this, glsl_type::vec4_type
);
265 emit(MOV(dst_reg(temp_src
), src
));
267 if (dst
.writemask
!= WRITEMASK_XYZW
) {
268 /* The gen6 math instruction must be align1, so we can't do
271 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
273 emit(opcode
, temp_dst
, temp_src
);
275 emit(MOV(dst
, src_reg(temp_dst
)));
277 emit(opcode
, dst
, temp_src
);
282 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
284 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
290 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
293 case SHADER_OPCODE_RCP
:
294 case SHADER_OPCODE_RSQ
:
295 case SHADER_OPCODE_SQRT
:
296 case SHADER_OPCODE_EXP2
:
297 case SHADER_OPCODE_LOG2
:
298 case SHADER_OPCODE_SIN
:
299 case SHADER_OPCODE_COS
:
302 assert(!"not reached: bad math opcode");
306 if (intel
->gen
>= 6) {
307 return emit_math1_gen6(opcode
, dst
, src
);
309 return emit_math1_gen4(opcode
, dst
, src
);
314 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
315 dst_reg dst
, src_reg src0
, src_reg src1
)
319 /* The gen6 math instruction ignores the source modifiers --
320 * swizzle, abs, negate, and at least some parts of the register
321 * region description. Move the sources to temporaries to make it
325 expanded
= src_reg(this, glsl_type::vec4_type
);
326 emit(MOV(dst_reg(expanded
), src0
));
329 expanded
= src_reg(this, glsl_type::vec4_type
);
330 emit(MOV(dst_reg(expanded
), src1
));
333 if (dst
.writemask
!= WRITEMASK_XYZW
) {
334 /* The gen6 math instruction must be align1, so we can't do
337 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
339 emit(opcode
, temp_dst
, src0
, src1
);
341 emit(MOV(dst
, src_reg(temp_dst
)));
343 emit(opcode
, dst
, src0
, src1
);
348 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
349 dst_reg dst
, src_reg src0
, src_reg src1
)
351 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
357 vec4_visitor::emit_math(enum opcode opcode
,
358 dst_reg dst
, src_reg src0
, src_reg src1
)
360 assert(opcode
== SHADER_OPCODE_POW
);
362 if (intel
->gen
>= 6) {
363 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
365 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
370 vec4_visitor::visit_instructions(const exec_list
*list
)
372 foreach_list(node
, list
) {
373 ir_instruction
*ir
= (ir_instruction
*)node
;
382 type_size(const struct glsl_type
*type
)
387 switch (type
->base_type
) {
390 case GLSL_TYPE_FLOAT
:
392 if (type
->is_matrix()) {
393 return type
->matrix_columns
;
395 /* Regardless of size of vector, it gets a vec4. This is bad
396 * packing for things like floats, but otherwise arrays become a
397 * mess. Hopefully a later pass over the code can pack scalars
398 * down if appropriate.
402 case GLSL_TYPE_ARRAY
:
403 assert(type
->length
> 0);
404 return type_size(type
->fields
.array
) * type
->length
;
405 case GLSL_TYPE_STRUCT
:
407 for (i
= 0; i
< type
->length
; i
++) {
408 size
+= type_size(type
->fields
.structure
[i
].type
);
411 case GLSL_TYPE_SAMPLER
:
412 /* Samplers take up one slot in UNIFORMS[], but they're baked in
423 vec4_visitor::virtual_grf_alloc(int size
)
425 if (virtual_grf_array_size
<= virtual_grf_count
) {
426 if (virtual_grf_array_size
== 0)
427 virtual_grf_array_size
= 16;
429 virtual_grf_array_size
*= 2;
430 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
431 virtual_grf_array_size
);
433 virtual_grf_sizes
[virtual_grf_count
] = size
;
434 return virtual_grf_count
++;
437 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
442 this->reg
= v
->virtual_grf_alloc(type_size(type
));
444 if (type
->is_array() || type
->is_record()) {
445 this->swizzle
= BRW_SWIZZLE_NOOP
;
447 this->swizzle
= swizzle_for_size(type
->vector_elements
);
450 this->type
= brw_type_for_base_type(type
);
453 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
458 this->reg
= v
->virtual_grf_alloc(type_size(type
));
460 if (type
->is_array() || type
->is_record()) {
461 this->writemask
= WRITEMASK_XYZW
;
463 this->writemask
= (1 << type
->vector_elements
) - 1;
466 this->type
= brw_type_for_base_type(type
);
469 /* Our support for uniforms is piggy-backed on the struct
470 * gl_fragment_program, because that's where the values actually
471 * get stored, rather than in some global gl_shader_program uniform
475 vec4_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
477 unsigned int offset
= 0;
478 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[loc
][0].f
;
480 if (type
->is_matrix()) {
481 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
482 type
->vector_elements
,
485 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
486 offset
+= setup_uniform_values(loc
+ offset
, column
);
492 switch (type
->base_type
) {
493 case GLSL_TYPE_FLOAT
:
497 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
498 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &values
[i
];
501 /* Set up pad elements to get things aligned to a vec4 boundary. */
502 for (unsigned int i
= type
->vector_elements
; i
< 4; i
++) {
503 static float zero
= 0;
505 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &zero
;
508 /* Track the size of this uniform vector, for future packing of
511 this->uniform_vector_size
[this->uniforms
] = type
->vector_elements
;
516 case GLSL_TYPE_STRUCT
:
517 for (unsigned int i
= 0; i
< type
->length
; i
++) {
518 offset
+= setup_uniform_values(loc
+ offset
,
519 type
->fields
.structure
[i
].type
);
523 case GLSL_TYPE_ARRAY
:
524 for (unsigned int i
= 0; i
< type
->length
; i
++) {
525 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
529 case GLSL_TYPE_SAMPLER
:
530 /* The sampler takes up a slot, but we don't use any values from it. */
534 assert(!"not reached");
539 /* Our support for builtin uniforms is even scarier than non-builtin.
540 * It sits on top of the PROG_STATE_VAR parameters that are
541 * automatically updated from GL context state.
544 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
546 const ir_state_slot
*const slots
= ir
->state_slots
;
547 assert(ir
->state_slots
!= NULL
);
549 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
550 /* This state reference has already been setup by ir_to_mesa,
551 * but we'll get the same index back here. We can reference
552 * ParameterValues directly, since unlike brw_fs.cpp, we never
553 * add new state references during compile.
555 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
556 (gl_state_index
*)slots
[i
].tokens
);
557 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
559 this->uniform_vector_size
[this->uniforms
] = 0;
560 /* Add each of the unique swizzled channels of the element.
561 * This will end up matching the size of the glsl_type of this field.
564 for (unsigned int j
= 0; j
< 4; j
++) {
565 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
568 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
569 if (swiz
<= last_swiz
)
570 this->uniform_vector_size
[this->uniforms
]++;
577 vec4_visitor::variable_storage(ir_variable
*var
)
579 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
583 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
585 ir_expression
*expr
= ir
->as_expression();
589 vec4_instruction
*inst
;
591 assert(expr
->get_num_operands() <= 2);
592 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
593 assert(expr
->operands
[i
]->type
->is_scalar());
595 expr
->operands
[i
]->accept(this);
596 op
[i
] = this->result
;
599 switch (expr
->operation
) {
600 case ir_unop_logic_not
:
601 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
602 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
605 case ir_binop_logic_xor
:
606 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
607 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
610 case ir_binop_logic_or
:
611 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
612 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
615 case ir_binop_logic_and
:
616 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
617 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
621 if (intel
->gen
>= 6) {
622 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
624 inst
= emit(MOV(dst_null_f(), op
[0]));
625 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
630 if (intel
->gen
>= 6) {
631 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
633 inst
= emit(MOV(dst_null_d(), op
[0]));
634 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
638 case ir_binop_greater
:
639 case ir_binop_gequal
:
641 case ir_binop_lequal
:
643 case ir_binop_all_equal
:
644 case ir_binop_nequal
:
645 case ir_binop_any_nequal
:
646 emit(CMP(dst_null_d(), op
[0], op
[1],
647 brw_conditional_for_comparison(expr
->operation
)));
651 assert(!"not reached");
659 if (intel
->gen
>= 6) {
660 vec4_instruction
*inst
= emit(AND(dst_null_d(),
661 this->result
, src_reg(1)));
662 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
664 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
665 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
670 * Emit a gen6 IF statement with the comparison folded into the IF
674 vec4_visitor::emit_if_gen6(ir_if
*ir
)
676 ir_expression
*expr
= ir
->condition
->as_expression();
682 assert(expr
->get_num_operands() <= 2);
683 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
684 expr
->operands
[i
]->accept(this);
685 op
[i
] = this->result
;
688 switch (expr
->operation
) {
689 case ir_unop_logic_not
:
690 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
693 case ir_binop_logic_xor
:
694 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
697 case ir_binop_logic_or
:
698 temp
= dst_reg(this, glsl_type::bool_type
);
699 emit(OR(temp
, op
[0], op
[1]));
700 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
703 case ir_binop_logic_and
:
704 temp
= dst_reg(this, glsl_type::bool_type
);
705 emit(AND(temp
, op
[0], op
[1]));
706 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
710 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
714 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
717 case ir_binop_greater
:
718 case ir_binop_gequal
:
720 case ir_binop_lequal
:
722 case ir_binop_nequal
:
723 emit(IF(op
[0], op
[1],
724 brw_conditional_for_comparison(expr
->operation
)));
727 case ir_binop_all_equal
:
728 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
729 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
732 case ir_binop_any_nequal
:
733 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
734 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
738 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
739 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
743 assert(!"not reached");
744 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
750 ir
->condition
->accept(this);
752 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
756 vec4_visitor::visit(ir_variable
*ir
)
760 if (variable_storage(ir
))
765 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
767 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
768 * come in as floating point conversions of the integer values.
770 for (int i
= ir
->location
; i
< ir
->location
+ type_size(ir
->type
); i
++) {
771 if (!c
->key
.gl_fixed_input_size
[i
])
775 dst
.writemask
= (1 << c
->key
.gl_fixed_input_size
[i
]) - 1;
776 emit(MUL(dst
, src_reg(dst
), src_reg(1.0f
/ 65536.0f
)));
781 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
783 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
784 output_reg
[ir
->location
+ i
] = *reg
;
785 output_reg
[ir
->location
+ i
].reg_offset
= i
;
786 output_reg
[ir
->location
+ i
].type
= BRW_REGISTER_TYPE_F
;
791 case ir_var_temporary
:
792 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
796 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
798 /* Track how big the whole uniform variable is, in case we need to put a
799 * copy of its data into pull constants for array access.
801 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
803 if (!strncmp(ir
->name
, "gl_", 3)) {
804 setup_builtin_uniform_values(ir
);
806 setup_uniform_values(ir
->location
, ir
->type
);
811 assert(!"not reached");
814 reg
->type
= brw_type_for_base_type(ir
->type
);
815 hash_table_insert(this->variable_ht
, reg
, ir
);
819 vec4_visitor::visit(ir_loop
*ir
)
823 /* We don't want debugging output to print the whole body of the
824 * loop as the annotation.
826 this->base_ir
= NULL
;
828 if (ir
->counter
!= NULL
) {
829 this->base_ir
= ir
->counter
;
830 ir
->counter
->accept(this);
831 counter
= *(variable_storage(ir
->counter
));
833 if (ir
->from
!= NULL
) {
834 this->base_ir
= ir
->from
;
835 ir
->from
->accept(this);
837 emit(MOV(counter
, this->result
));
844 this->base_ir
= ir
->to
;
845 ir
->to
->accept(this);
847 emit(CMP(dst_null_d(), src_reg(counter
), this->result
,
848 brw_conditional_for_comparison(ir
->cmp
)));
850 vec4_instruction
*inst
= emit(BRW_OPCODE_BREAK
);
851 inst
->predicate
= BRW_PREDICATE_NORMAL
;
854 visit_instructions(&ir
->body_instructions
);
858 this->base_ir
= ir
->increment
;
859 ir
->increment
->accept(this);
860 emit(ADD(counter
, src_reg(counter
), this->result
));
863 emit(BRW_OPCODE_WHILE
);
867 vec4_visitor::visit(ir_loop_jump
*ir
)
870 case ir_loop_jump::jump_break
:
871 emit(BRW_OPCODE_BREAK
);
873 case ir_loop_jump::jump_continue
:
874 emit(BRW_OPCODE_CONTINUE
);
881 vec4_visitor::visit(ir_function_signature
*ir
)
888 vec4_visitor::visit(ir_function
*ir
)
890 /* Ignore function bodies other than main() -- we shouldn't see calls to
891 * them since they should all be inlined.
893 if (strcmp(ir
->name
, "main") == 0) {
894 const ir_function_signature
*sig
;
897 sig
= ir
->matching_signature(&empty
);
901 visit_instructions(&sig
->body
);
906 vec4_visitor::try_emit_sat(ir_expression
*ir
)
908 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
912 sat_src
->accept(this);
913 src_reg src
= this->result
;
915 this->result
= src_reg(this, ir
->type
);
916 vec4_instruction
*inst
;
917 inst
= emit(MOV(dst_reg(this->result
), src
));
918 inst
->saturate
= true;
924 vec4_visitor::emit_bool_comparison(unsigned int op
,
925 dst_reg dst
, src_reg src0
, src_reg src1
)
927 /* original gen4 does destination conversion before comparison. */
929 dst
.type
= src0
.type
;
931 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
933 dst
.type
= BRW_REGISTER_TYPE_D
;
934 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
938 vec4_visitor::visit(ir_expression
*ir
)
940 unsigned int operand
;
941 src_reg op
[Elements(ir
->operands
)];
944 vec4_instruction
*inst
;
946 if (try_emit_sat(ir
))
949 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
950 this->result
.file
= BAD_FILE
;
951 ir
->operands
[operand
]->accept(this);
952 if (this->result
.file
== BAD_FILE
) {
953 printf("Failed to get tree for expression operand:\n");
954 ir
->operands
[operand
]->print();
957 op
[operand
] = this->result
;
959 /* Matrix expression operands should have been broken down to vector
960 * operations already.
962 assert(!ir
->operands
[operand
]->type
->is_matrix());
965 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
966 if (ir
->operands
[1]) {
967 vector_elements
= MAX2(vector_elements
,
968 ir
->operands
[1]->type
->vector_elements
);
971 this->result
.file
= BAD_FILE
;
973 /* Storage for our result. Ideally for an assignment we'd be using
974 * the actual storage for the result here, instead.
976 result_src
= src_reg(this, ir
->type
);
977 /* convenience for the emit functions below. */
978 result_dst
= dst_reg(result_src
);
979 /* If nothing special happens, this is the result. */
980 this->result
= result_src
;
981 /* Limit writes to the channels that will be used by result_src later.
982 * This does limit this temp's use as a temporary for multi-instruction
985 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
987 switch (ir
->operation
) {
988 case ir_unop_logic_not
:
989 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
990 * ones complement of the whole register, not just bit 0.
992 emit(XOR(result_dst
, op
[0], src_reg(1)));
995 op
[0].negate
= !op
[0].negate
;
996 this->result
= op
[0];
1000 op
[0].negate
= false;
1001 this->result
= op
[0];
1005 emit(MOV(result_dst
, src_reg(0.0f
)));
1007 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_G
));
1008 inst
= emit(MOV(result_dst
, src_reg(1.0f
)));
1009 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1011 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_L
));
1012 inst
= emit(MOV(result_dst
, src_reg(-1.0f
)));
1013 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1018 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1022 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1025 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1029 assert(!"not reached: should be handled by ir_explog_to_explog2");
1032 case ir_unop_sin_reduced
:
1033 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1036 case ir_unop_cos_reduced
:
1037 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1042 assert(!"derivatives not valid in vertex shader");
1046 assert(!"not reached: should be handled by lower_noise");
1050 emit(ADD(result_dst
, op
[0], op
[1]));
1053 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1057 if (ir
->type
->is_integer()) {
1058 /* For integer multiplication, the MUL uses the low 16 bits
1059 * of one of the operands (src0 on gen6, src1 on gen7). The
1060 * MACH accumulates in the contribution of the upper 16 bits
1063 * FINISHME: Emit just the MUL if we know an operand is small
1066 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
1068 emit(MUL(acc
, op
[0], op
[1]));
1069 emit(MACH(dst_null_d(), op
[0], op
[1]));
1070 emit(MOV(result_dst
, src_reg(acc
)));
1072 emit(MUL(result_dst
, op
[0], op
[1]));
1076 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1078 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1082 case ir_binop_greater
:
1083 case ir_binop_lequal
:
1084 case ir_binop_gequal
:
1085 case ir_binop_equal
:
1086 case ir_binop_nequal
: {
1087 emit(CMP(result_dst
, op
[0], op
[1],
1088 brw_conditional_for_comparison(ir
->operation
)));
1089 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1093 case ir_binop_all_equal
:
1094 /* "==" operator producing a scalar boolean. */
1095 if (ir
->operands
[0]->type
->is_vector() ||
1096 ir
->operands
[1]->type
->is_vector()) {
1097 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1098 emit(MOV(result_dst
, src_reg(0)));
1099 inst
= emit(MOV(result_dst
, src_reg(1)));
1100 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1102 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1103 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1106 case ir_binop_any_nequal
:
1107 /* "!=" operator producing a scalar boolean. */
1108 if (ir
->operands
[0]->type
->is_vector() ||
1109 ir
->operands
[1]->type
->is_vector()) {
1110 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1112 emit(MOV(result_dst
, src_reg(0)));
1113 inst
= emit(MOV(result_dst
, src_reg(1)));
1114 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1116 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1117 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1122 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1123 emit(MOV(result_dst
, src_reg(0)));
1125 inst
= emit(MOV(result_dst
, src_reg(1)));
1126 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1129 case ir_binop_logic_xor
:
1130 emit(XOR(result_dst
, op
[0], op
[1]));
1133 case ir_binop_logic_or
:
1134 emit(OR(result_dst
, op
[0], op
[1]));
1137 case ir_binop_logic_and
:
1138 emit(AND(result_dst
, op
[0], op
[1]));
1142 assert(ir
->operands
[0]->type
->is_vector());
1143 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1144 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1148 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1151 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1160 emit(MOV(result_dst
, op
[0]));
1164 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1165 emit(AND(result_dst
, result_src
, src_reg(1)));
1170 emit(RNDZ(result_dst
, op
[0]));
1173 op
[0].negate
= !op
[0].negate
;
1174 inst
= emit(RNDD(result_dst
, op
[0]));
1175 this->result
.negate
= true;
1178 inst
= emit(RNDD(result_dst
, op
[0]));
1181 inst
= emit(FRC(result_dst
, op
[0]));
1183 case ir_unop_round_even
:
1184 emit(RNDE(result_dst
, op
[0]));
1188 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1190 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1191 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1194 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_G
));
1196 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1197 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1201 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1204 case ir_unop_bit_not
:
1205 inst
= emit(NOT(result_dst
, op
[0]));
1207 case ir_binop_bit_and
:
1208 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1210 case ir_binop_bit_xor
:
1211 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1213 case ir_binop_bit_or
:
1214 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1217 case ir_binop_lshift
:
1218 case ir_binop_rshift
:
1219 assert(!"GLSL 1.30 features unsupported");
1222 case ir_quadop_vector
:
1223 assert(!"not reached: should be handled by lower_quadop_vector");
1230 vec4_visitor::visit(ir_swizzle
*ir
)
1236 /* Note that this is only swizzles in expressions, not those on the left
1237 * hand side of an assignment, which do write masking. See ir_assignment
1241 ir
->val
->accept(this);
1243 assert(src
.file
!= BAD_FILE
);
1245 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1248 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1251 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1254 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1257 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1261 for (; i
< 4; i
++) {
1262 /* Replicate the last channel out. */
1263 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1266 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1272 vec4_visitor::visit(ir_dereference_variable
*ir
)
1274 const struct glsl_type
*type
= ir
->type
;
1275 dst_reg
*reg
= variable_storage(ir
->var
);
1278 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1279 this->result
= src_reg(brw_null_reg());
1283 this->result
= src_reg(*reg
);
1285 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1286 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1290 vec4_visitor::visit(ir_dereference_array
*ir
)
1292 ir_constant
*constant_index
;
1294 int element_size
= type_size(ir
->type
);
1296 constant_index
= ir
->array_index
->constant_expression_value();
1298 ir
->array
->accept(this);
1301 if (constant_index
) {
1302 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1304 /* Variable index array dereference. It eats the "vec4" of the
1305 * base of the array and an index that offsets the Mesa register
1308 ir
->array_index
->accept(this);
1312 if (element_size
== 1) {
1313 index_reg
= this->result
;
1315 index_reg
= src_reg(this, glsl_type::int_type
);
1317 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(element_size
)));
1321 src_reg temp
= src_reg(this, glsl_type::int_type
);
1323 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1328 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1329 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1332 /* If the type is smaller than a vec4, replicate the last channel out. */
1333 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1334 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1336 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1337 src
.type
= brw_type_for_base_type(ir
->type
);
1343 vec4_visitor::visit(ir_dereference_record
*ir
)
1346 const glsl_type
*struct_type
= ir
->record
->type
;
1349 ir
->record
->accept(this);
1351 for (i
= 0; i
< struct_type
->length
; i
++) {
1352 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1354 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1357 /* If the type is smaller than a vec4, replicate the last channel out. */
1358 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1359 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1361 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1362 this->result
.type
= brw_type_for_base_type(ir
->type
);
1364 this->result
.reg_offset
+= offset
;
1368 * We want to be careful in assignment setup to hit the actual storage
1369 * instead of potentially using a temporary like we might with the
1370 * ir_dereference handler.
1373 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1375 /* The LHS must be a dereference. If the LHS is a variable indexed array
1376 * access of a vector, it must be separated into a series conditional moves
1377 * before reaching this point (see ir_vec_index_to_cond_assign).
1379 assert(ir
->as_dereference());
1380 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1382 assert(!deref_array
->array
->type
->is_vector());
1385 /* Use the rvalue deref handler for the most part. We'll ignore
1386 * swizzles in it and write swizzles using writemask, though.
1389 return dst_reg(v
->result
);
1393 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1394 const struct glsl_type
*type
, bool predicated
)
1396 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1397 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1398 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicated
);
1403 if (type
->is_array()) {
1404 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1405 emit_block_move(dst
, src
, type
->fields
.array
, predicated
);
1410 if (type
->is_matrix()) {
1411 const struct glsl_type
*vec_type
;
1413 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1414 type
->vector_elements
, 1);
1416 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1417 emit_block_move(dst
, src
, vec_type
, predicated
);
1422 assert(type
->is_scalar() || type
->is_vector());
1424 dst
->type
= brw_type_for_base_type(type
);
1425 src
->type
= dst
->type
;
1427 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1429 /* Do we need to worry about swizzling a swizzle? */
1430 assert(src
->swizzle
= BRW_SWIZZLE_NOOP
);
1431 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1433 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1435 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1442 /* If the RHS processing resulted in an instruction generating a
1443 * temporary value, and it would be easy to rewrite the instruction to
1444 * generate its result right into the LHS instead, do so. This ends
1445 * up reliably removing instructions where it can be tricky to do so
1446 * later without real UD chain information.
1449 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1452 vec4_instruction
*pre_rhs_inst
,
1453 vec4_instruction
*last_rhs_inst
)
1455 /* This could be supported, but it would take more smarts. */
1459 if (pre_rhs_inst
== last_rhs_inst
)
1460 return false; /* No instructions generated to work with. */
1462 /* Make sure the last instruction generated our source reg. */
1463 if (src
.file
!= GRF
||
1464 src
.file
!= last_rhs_inst
->dst
.file
||
1465 src
.reg
!= last_rhs_inst
->dst
.reg
||
1466 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1470 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1473 /* Check that that last instruction fully initialized the channels
1474 * we want to use, in the order we want to use them. We could
1475 * potentially reswizzle the operands of many instructions so that
1476 * we could handle out of order channels, but don't yet.
1478 for (int i
= 0; i
< 4; i
++) {
1479 if (dst
.writemask
& (1 << i
)) {
1480 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1483 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1488 /* Success! Rewrite the instruction. */
1489 last_rhs_inst
->dst
.file
= dst
.file
;
1490 last_rhs_inst
->dst
.reg
= dst
.reg
;
1491 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1492 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1493 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1499 vec4_visitor::visit(ir_assignment
*ir
)
1501 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1503 if (!ir
->lhs
->type
->is_scalar() &&
1504 !ir
->lhs
->type
->is_vector()) {
1505 ir
->rhs
->accept(this);
1506 src_reg src
= this->result
;
1508 if (ir
->condition
) {
1509 emit_bool_to_cond_code(ir
->condition
);
1512 emit_block_move(&dst
, &src
, ir
->rhs
->type
, ir
->condition
!= NULL
);
1516 /* Now we're down to just a scalar/vector with writemasks. */
1519 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1520 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1522 ir
->rhs
->accept(this);
1524 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1526 src_reg src
= this->result
;
1529 int first_enabled_chan
= 0;
1532 assert(ir
->lhs
->type
->is_vector() ||
1533 ir
->lhs
->type
->is_scalar());
1534 dst
.writemask
= ir
->write_mask
;
1536 for (int i
= 0; i
< 4; i
++) {
1537 if (dst
.writemask
& (1 << i
)) {
1538 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1543 /* Swizzle a small RHS vector into the channels being written.
1545 * glsl ir treats write_mask as dictating how many channels are
1546 * present on the RHS while in our instructions we need to make
1547 * those channels appear in the slots of the vec4 they're written to.
1549 for (int i
= 0; i
< 4; i
++) {
1550 if (dst
.writemask
& (1 << i
))
1551 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1553 swizzles
[i
] = first_enabled_chan
;
1555 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1556 swizzles
[2], swizzles
[3]);
1558 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
1562 if (ir
->condition
) {
1563 emit_bool_to_cond_code(ir
->condition
);
1566 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1567 vec4_instruction
*inst
= emit(MOV(dst
, src
));
1570 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1578 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
1580 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1581 foreach_list(node
, &ir
->components
) {
1582 ir_constant
*field_value
= (ir_constant
*)node
;
1584 emit_constant_values(dst
, field_value
);
1589 if (ir
->type
->is_array()) {
1590 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1591 emit_constant_values(dst
, ir
->array_elements
[i
]);
1596 if (ir
->type
->is_matrix()) {
1597 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1598 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
1599 dst
->writemask
= 1 << j
;
1600 dst
->type
= BRW_REGISTER_TYPE_F
;
1603 src_reg(ir
->value
.f
[i
* ir
->type
->vector_elements
+ j
])));
1610 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1611 dst
->writemask
= 1 << i
;
1612 dst
->type
= brw_type_for_base_type(ir
->type
);
1614 switch (ir
->type
->base_type
) {
1615 case GLSL_TYPE_FLOAT
:
1616 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
1619 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
1621 case GLSL_TYPE_UINT
:
1622 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
1624 case GLSL_TYPE_BOOL
:
1625 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
1628 assert(!"Non-float/uint/int/bool constant");
1636 vec4_visitor::visit(ir_constant
*ir
)
1638 dst_reg dst
= dst_reg(this, ir
->type
);
1639 this->result
= src_reg(dst
);
1641 emit_constant_values(&dst
, ir
);
1645 vec4_visitor::visit(ir_call
*ir
)
1647 assert(!"not reached");
1651 vec4_visitor::visit(ir_texture
*ir
)
1653 /* FINISHME: Implement vertex texturing.
1655 * With 0 vertex samplers available, the linker will reject
1656 * programs that do vertex texturing, but after our visitor has
1662 vec4_visitor::visit(ir_return
*ir
)
1664 assert(!"not reached");
1668 vec4_visitor::visit(ir_discard
*ir
)
1670 assert(!"not reached");
1674 vec4_visitor::visit(ir_if
*ir
)
1676 /* Don't point the annotation at the if statement, because then it plus
1677 * the then and else blocks get printed.
1679 this->base_ir
= ir
->condition
;
1681 if (intel
->gen
== 6) {
1684 emit_bool_to_cond_code(ir
->condition
);
1685 emit(IF(BRW_PREDICATE_NORMAL
));
1688 visit_instructions(&ir
->then_instructions
);
1690 if (!ir
->else_instructions
.is_empty()) {
1691 this->base_ir
= ir
->condition
;
1692 emit(BRW_OPCODE_ELSE
);
1694 visit_instructions(&ir
->else_instructions
);
1697 this->base_ir
= ir
->condition
;
1698 emit(BRW_OPCODE_ENDIF
);
1702 vec4_visitor::emit_ndc_computation()
1704 /* Get the position */
1705 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
1707 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1708 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1709 output_reg
[BRW_VERT_RESULT_NDC
] = ndc
;
1711 current_annotation
= "NDC";
1712 dst_reg ndc_w
= ndc
;
1713 ndc_w
.writemask
= WRITEMASK_W
;
1714 src_reg pos_w
= pos
;
1715 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1716 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1718 dst_reg ndc_xyz
= ndc
;
1719 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1721 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
1725 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
1727 if (intel
->gen
< 6 &&
1728 ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1729 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
)) {
1730 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1733 emit(MOV(header1
, 0u));
1735 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1736 assert(!"finishme: psiz");
1739 header1
.writemask
= WRITEMASK_W
;
1740 emit(MUL(header1
, psiz
, 1u << 11));
1741 emit(AND(header1
, src_reg(header1
), 0x7ff << 8));
1744 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1745 vec4_instruction
*inst
;
1747 inst
= emit(DP4(dst_null_f(), src_reg(output_reg
[VERT_RESULT_HPOS
]),
1748 src_reg(c
->userplane
[i
])));
1749 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1751 emit(OR(header1
, src_reg(header1
), 1u << i
));
1752 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1755 /* i965 clipping workaround:
1756 * 1) Test for -ve rhw
1758 * set ndc = (0,0,0,0)
1761 * Later, clipping will detect ucp[6] and ensure the primitive is
1762 * clipped against all fixed planes.
1764 if (brw
->has_negative_rhw_bug
) {
1768 vec8(brw_null_reg()),
1770 brw_swizzle1(output_reg
[BRW_VERT_RESULT_NDC
], 3),
1773 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1774 brw_MOV(p
, output_reg
[BRW_VERT_RESULT_NDC
], brw_imm_f(0));
1775 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1779 header1
.writemask
= WRITEMASK_XYZW
;
1780 emit(MOV(reg
, src_reg(header1
)));
1781 } else if (intel
->gen
< 6) {
1782 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
1784 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
1785 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1786 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
1787 src_reg(output_reg
[VERT_RESULT_PSIZ
])));
1793 vec4_visitor::emit_clip_distances(struct brw_reg reg
, int offset
)
1795 if (intel
->gen
< 6) {
1796 /* Clip distance slots are set aside in gen5, but they are not used. It
1797 * is not clear whether we actually need to set aside space for them,
1798 * but the performance cost is negligible.
1803 for (int i
= 0; i
+ offset
< c
->key
.nr_userclip
&& i
< 4; ++i
) {
1804 emit(DP4(dst_reg(brw_writemask(reg
, 1 << i
)),
1805 src_reg(output_reg
[VERT_RESULT_HPOS
]),
1806 src_reg(c
->userplane
[i
+ offset
])));
1811 vec4_visitor::emit_urb_slot(int mrf
, int vert_result
)
1813 struct brw_reg reg
= brw_message_reg(mrf
);
1815 switch (vert_result
) {
1816 case VERT_RESULT_PSIZ
:
1817 /* PSIZ is always in slot 0, and is coupled with other flags. */
1818 current_annotation
= "indices, point width, clip flags";
1819 emit_psiz_and_flags(reg
);
1821 case BRW_VERT_RESULT_NDC
:
1822 current_annotation
= "NDC";
1823 emit(MOV(reg
, src_reg(output_reg
[BRW_VERT_RESULT_NDC
])));
1825 case BRW_VERT_RESULT_HPOS_DUPLICATE
:
1826 case VERT_RESULT_HPOS
:
1827 current_annotation
= "gl_Position";
1828 emit(MOV(reg
, src_reg(output_reg
[VERT_RESULT_HPOS
])));
1830 case BRW_VERT_RESULT_CLIP0
:
1831 current_annotation
= "user clip distances";
1832 emit_clip_distances(reg
, 0);
1834 case BRW_VERT_RESULT_CLIP1
:
1835 current_annotation
= "user clip distances";
1836 emit_clip_distances(reg
, 4);
1838 case BRW_VERT_RESULT_PAD
:
1839 /* No need to write to this slot */
1842 assert (vert_result
< VERT_RESULT_MAX
);
1843 current_annotation
= NULL
;
1844 /* Copy the register, saturating if necessary */
1845 vec4_instruction
*inst
= emit(MOV(reg
,
1846 src_reg(output_reg
[vert_result
])));
1847 if ((vert_result
== VERT_RESULT_COL0
||
1848 vert_result
== VERT_RESULT_COL1
||
1849 vert_result
== VERT_RESULT_BFC0
||
1850 vert_result
== VERT_RESULT_BFC1
) &&
1851 c
->key
.clamp_vertex_color
) {
1852 inst
->saturate
= true;
1860 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
1862 struct intel_context
*intel
= &brw
->intel
;
1864 if (intel
->gen
>= 6) {
1865 /* URB data written (does not include the message header reg) must
1866 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1867 * section 5.4.3.2.2: URB_INTERLEAVED.
1869 * URB entries are allocated on a multiple of 1024 bits, so an
1870 * extra 128 bits written here to make the end align to 256 is
1873 if ((mlen
% 2) != 1)
1881 * Generates the VUE payload plus the 1 or 2 URB write instructions to
1882 * complete the VS thread.
1884 * The VUE layout is documented in Volume 2a.
1887 vec4_visitor::emit_urb_writes()
1889 /* MRF 0 is reserved for the debugger, so start with message header
1895 /* In the process of generating our URB write message contents, we
1896 * may need to unspill a register or load from an array. Those
1897 * reads would use MRFs 14-15.
1899 int max_usable_mrf
= 13;
1901 /* FINISHME: edgeflag */
1903 brw_compute_vue_map(&c
->vue_map
, intel
, c
->key
.nr_userclip
,
1904 c
->key
.two_side_color
, c
->prog_data
.outputs_written
);
1906 /* First mrf is the g0-based message header containing URB handles and such,
1907 * which is implied in VS_OPCODE_URB_WRITE.
1911 if (intel
->gen
< 6) {
1912 emit_ndc_computation();
1915 /* Set up the VUE data for the first URB write */
1917 for (slot
= 0; slot
< c
->vue_map
.num_slots
; ++slot
) {
1918 emit_urb_slot(mrf
++, c
->vue_map
.slot_to_vert_result
[slot
]);
1920 /* If this was MRF 15, we can't fit anything more into this URB
1921 * WRITE. Note that base_mrf of 1 means that MRF 15 is an
1922 * even-numbered amount of URB write data, which will meet
1923 * gen6's requirements for length alignment.
1925 if (mrf
> max_usable_mrf
) {
1931 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
1932 inst
->base_mrf
= base_mrf
;
1933 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1934 inst
->eot
= (slot
>= c
->vue_map
.num_slots
);
1936 urb_entry_size
= mrf
- base_mrf
;
1938 /* Optional second URB write */
1942 for (; slot
< c
->vue_map
.num_slots
; ++slot
) {
1943 assert(mrf
< max_usable_mrf
);
1945 emit_urb_slot(mrf
++, c
->vue_map
.slot_to_vert_result
[slot
]);
1948 inst
= emit(VS_OPCODE_URB_WRITE
);
1949 inst
->base_mrf
= base_mrf
;
1950 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1952 /* URB destination offset. In the previous write, we got MRFs
1953 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
1954 * URB row increments, and each of our MRFs is half of one of
1955 * those, since we're doing interleaved writes.
1957 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
1959 urb_entry_size
+= mrf
- base_mrf
;
1962 if (intel
->gen
== 6)
1963 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 8) / 8;
1965 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 4) / 4;
1969 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
1970 src_reg
*reladdr
, int reg_offset
)
1972 /* Because we store the values to scratch interleaved like our
1973 * vertex data, we need to scale the vec4 index by 2.
1975 int message_header_scale
= 2;
1977 /* Pre-gen6, the message header uses byte offsets instead of vec4
1978 * (16-byte) offset units.
1981 message_header_scale
*= 16;
1984 src_reg index
= src_reg(this, glsl_type::int_type
);
1986 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
1987 emit_before(inst
, MUL(dst_reg(index
),
1988 index
, src_reg(message_header_scale
)));
1992 return src_reg(reg_offset
* message_header_scale
);
1997 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
1998 src_reg
*reladdr
, int reg_offset
)
2001 src_reg index
= src_reg(this, glsl_type::int_type
);
2003 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2005 /* Pre-gen6, the message header uses byte offsets instead of vec4
2006 * (16-byte) offset units.
2008 if (intel
->gen
< 6) {
2009 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
2014 int message_header_scale
= intel
->gen
< 6 ? 16 : 1;
2015 return src_reg(reg_offset
* message_header_scale
);
2020 * Emits an instruction before @inst to load the value named by @orig_src
2021 * from scratch space at @base_offset to @temp.
2024 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2025 dst_reg temp
, src_reg orig_src
,
2028 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2029 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2031 emit_before(inst
, SCRATCH_READ(temp
, index
));
2035 * Emits an instruction after @inst to store the value to be written
2036 * to @orig_dst to scratch space at @base_offset, from @temp.
2039 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
,
2040 src_reg temp
, dst_reg orig_dst
,
2043 int reg_offset
= base_offset
+ orig_dst
.reg_offset
;
2044 src_reg index
= get_scratch_offset(inst
, orig_dst
.reladdr
, reg_offset
);
2046 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
2047 orig_dst
.writemask
));
2048 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
2049 write
->predicate
= inst
->predicate
;
2050 write
->ir
= inst
->ir
;
2051 write
->annotation
= inst
->annotation
;
2052 inst
->insert_after(write
);
2056 * We can't generally support array access in GRF space, because a
2057 * single instruction's destination can only span 2 contiguous
2058 * registers. So, we send all GRF arrays that get variable index
2059 * access to scratch space.
2062 vec4_visitor::move_grf_array_access_to_scratch()
2064 int scratch_loc
[this->virtual_grf_count
];
2066 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2067 scratch_loc
[i
] = -1;
2070 /* First, calculate the set of virtual GRFs that need to be punted
2071 * to scratch due to having any array access on them, and where in
2074 foreach_list(node
, &this->instructions
) {
2075 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2077 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2078 scratch_loc
[inst
->dst
.reg
] == -1) {
2079 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2080 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
] * 8 * 4;
2083 for (int i
= 0 ; i
< 3; i
++) {
2084 src_reg
*src
= &inst
->src
[i
];
2086 if (src
->file
== GRF
&& src
->reladdr
&&
2087 scratch_loc
[src
->reg
] == -1) {
2088 scratch_loc
[src
->reg
] = c
->last_scratch
;
2089 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
] * 8 * 4;
2094 /* Now, for anything that will be accessed through scratch, rewrite
2095 * it to load/store. Note that this is a _safe list walk, because
2096 * we may generate a new scratch_write instruction after the one
2099 foreach_list_safe(node
, &this->instructions
) {
2100 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2102 /* Set up the annotation tracking for new generated instructions. */
2104 current_annotation
= inst
->annotation
;
2106 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2107 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2109 emit_scratch_write(inst
, temp
, inst
->dst
, scratch_loc
[inst
->dst
.reg
]);
2111 inst
->dst
.file
= temp
.file
;
2112 inst
->dst
.reg
= temp
.reg
;
2113 inst
->dst
.reg_offset
= temp
.reg_offset
;
2114 inst
->dst
.reladdr
= NULL
;
2117 for (int i
= 0 ; i
< 3; i
++) {
2118 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2121 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2123 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2124 scratch_loc
[inst
->src
[i
].reg
]);
2126 inst
->src
[i
].file
= temp
.file
;
2127 inst
->src
[i
].reg
= temp
.reg
;
2128 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2129 inst
->src
[i
].reladdr
= NULL
;
2135 * Emits an instruction before @inst to load the value named by @orig_src
2136 * from the pull constant buffer (surface) at @base_offset to @temp.
2139 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
2140 dst_reg temp
, src_reg orig_src
,
2143 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2144 src_reg index
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
2145 vec4_instruction
*load
;
2147 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
2149 load
->base_mrf
= 14;
2151 emit_before(inst
, load
);
2155 * Implements array access of uniforms by inserting a
2156 * PULL_CONSTANT_LOAD instruction.
2158 * Unlike temporary GRF array access (where we don't support it due to
2159 * the difficulty of doing relative addressing on instruction
2160 * destinations), we could potentially do array access of uniforms
2161 * that were loaded in GRF space as push constants. In real-world
2162 * usage we've seen, though, the arrays being used are always larger
2163 * than we could load as push constants, so just always move all
2164 * uniform array access out to a pull constant buffer.
2167 vec4_visitor::move_uniform_array_access_to_pull_constants()
2169 int pull_constant_loc
[this->uniforms
];
2171 for (int i
= 0; i
< this->uniforms
; i
++) {
2172 pull_constant_loc
[i
] = -1;
2175 /* Walk through and find array access of uniforms. Put a copy of that
2176 * uniform in the pull constant buffer.
2178 * Note that we don't move constant-indexed accesses to arrays. No
2179 * testing has been done of the performance impact of this choice.
2181 foreach_list_safe(node
, &this->instructions
) {
2182 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2184 for (int i
= 0 ; i
< 3; i
++) {
2185 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2188 int uniform
= inst
->src
[i
].reg
;
2190 /* If this array isn't already present in the pull constant buffer,
2193 if (pull_constant_loc
[uniform
] == -1) {
2194 const float **values
= &prog_data
->param
[uniform
* 4];
2196 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
;
2198 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
2199 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
2203 /* Set up the annotation tracking for new generated instructions. */
2205 current_annotation
= inst
->annotation
;
2207 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2209 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
2210 pull_constant_loc
[uniform
]);
2212 inst
->src
[i
].file
= temp
.file
;
2213 inst
->src
[i
].reg
= temp
.reg
;
2214 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2215 inst
->src
[i
].reladdr
= NULL
;
2219 /* Now there are no accesses of the UNIFORM file with a reladdr, so
2220 * no need to track them as larger-than-vec4 objects. This will be
2221 * relied on in cutting out unused uniform vectors from push
2224 split_uniform_registers();
2227 vec4_visitor::vec4_visitor(struct brw_vs_compile
*c
,
2228 struct gl_shader_program
*prog
,
2229 struct brw_shader
*shader
)
2234 this->intel
= &brw
->intel
;
2235 this->ctx
= &intel
->ctx
;
2237 this->shader
= shader
;
2239 this->mem_ctx
= ralloc_context(NULL
);
2240 this->failed
= false;
2242 this->base_ir
= NULL
;
2243 this->current_annotation
= NULL
;
2246 this->vp
= prog
->VertexProgram
;
2247 this->prog_data
= &c
->prog_data
;
2249 this->variable_ht
= hash_table_ctor(0,
2250 hash_table_pointer_hash
,
2251 hash_table_pointer_compare
);
2253 this->virtual_grf_def
= NULL
;
2254 this->virtual_grf_use
= NULL
;
2255 this->virtual_grf_sizes
= NULL
;
2256 this->virtual_grf_count
= 0;
2257 this->virtual_grf_array_size
= 0;
2258 this->live_intervals_valid
= false;
2262 this->variable_ht
= hash_table_ctor(0,
2263 hash_table_pointer_hash
,
2264 hash_table_pointer_compare
);
2267 vec4_visitor::~vec4_visitor()
2269 ralloc_free(this->mem_ctx
);
2270 hash_table_dtor(this->variable_ht
);
2275 vec4_visitor::fail(const char *format
, ...)
2285 va_start(va
, format
);
2286 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
2288 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
2290 this->fail_msg
= msg
;
2292 if (INTEL_DEBUG
& DEBUG_VS
) {
2293 fprintf(stderr
, "%s", msg
);
2297 } /* namespace brw */