2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
32 src_reg::src_reg(dst_reg reg
)
36 this->file
= reg
.file
;
38 this->reg_offset
= reg
.reg_offset
;
39 this->type
= reg
.type
;
45 for (int i
= 0; i
< 4; i
++) {
46 if (!(reg
.writemask
& (1 << i
)))
49 swizzles
[next_chan
++] = last
= i
;
52 for (; next_chan
< 4; next_chan
++) {
53 swizzles
[next_chan
] = last
;
56 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
57 swizzles
[2], swizzles
[3]);
60 dst_reg::dst_reg(src_reg reg
)
64 this->file
= reg
.file
;
66 this->reg_offset
= reg
.reg_offset
;
67 this->type
= reg
.type
;
68 this->writemask
= WRITEMASK_XYZW
;
72 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
73 src_reg src0
, src_reg src1
, src_reg src2
)
75 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction();
77 inst
->opcode
= opcode
;
82 inst
->ir
= this->base_ir
;
83 inst
->annotation
= this->current_annotation
;
85 this->instructions
.push_tail(inst
);
92 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
94 return emit(opcode
, dst
, src0
, src1
, src_reg());
98 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
100 assert(dst
.writemask
!= 0);
101 return emit(opcode
, dst
, src0
, src_reg(), src_reg());
105 vec4_visitor::emit(enum opcode opcode
)
107 return emit(opcode
, dst_reg(), src_reg(), src_reg(), src_reg());
111 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
113 static enum opcode dot_opcodes
[] = {
114 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
117 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
121 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
123 /* The gen6 math instruction ignores the source modifiers --
124 * swizzle, abs, negate, and at least some parts of the register
125 * region description.
127 src_reg temp_src
= src_reg(this, glsl_type::vec4_type
);
128 emit(BRW_OPCODE_MOV
, dst_reg(temp_src
), src
);
130 emit(opcode
, dst
, temp_src
);
134 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
136 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
142 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
145 case SHADER_OPCODE_RCP
:
146 case SHADER_OPCODE_RSQ
:
147 case SHADER_OPCODE_SQRT
:
148 case SHADER_OPCODE_EXP2
:
149 case SHADER_OPCODE_LOG2
:
150 case SHADER_OPCODE_SIN
:
151 case SHADER_OPCODE_COS
:
154 assert(!"not reached: bad math opcode");
158 if (intel
->gen
>= 6) {
159 return emit_math1_gen6(opcode
, dst
, src
);
161 return emit_math1_gen4(opcode
, dst
, src
);
166 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
167 dst_reg dst
, src_reg src0
, src_reg src1
)
171 /* The gen6 math instruction ignores the source modifiers --
172 * swizzle, abs, negate, and at least some parts of the register
173 * region description. Move the sources to temporaries to make it
177 expanded
= src_reg(this, glsl_type::vec4_type
);
178 emit(BRW_OPCODE_MOV
, dst
, src0
);
181 expanded
= src_reg(this, glsl_type::vec4_type
);
182 emit(BRW_OPCODE_MOV
, dst
, src1
);
185 emit(opcode
, dst
, src0
, src1
);
189 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
190 dst_reg dst
, src_reg src0
, src_reg src1
)
192 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
198 vec4_visitor::emit_math(enum opcode opcode
,
199 dst_reg dst
, src_reg src0
, src_reg src1
)
201 assert(opcode
== SHADER_OPCODE_POW
);
203 if (intel
->gen
>= 6) {
204 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
206 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
211 vec4_visitor::visit_instructions(const exec_list
*list
)
213 foreach_iter(exec_list_iterator
, iter
, *list
) {
214 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
223 type_size(const struct glsl_type
*type
)
228 switch (type
->base_type
) {
231 case GLSL_TYPE_FLOAT
:
233 if (type
->is_matrix()) {
234 return type
->matrix_columns
;
236 /* Regardless of size of vector, it gets a vec4. This is bad
237 * packing for things like floats, but otherwise arrays become a
238 * mess. Hopefully a later pass over the code can pack scalars
239 * down if appropriate.
243 case GLSL_TYPE_ARRAY
:
244 assert(type
->length
> 0);
245 return type_size(type
->fields
.array
) * type
->length
;
246 case GLSL_TYPE_STRUCT
:
248 for (i
= 0; i
< type
->length
; i
++) {
249 size
+= type_size(type
->fields
.structure
[i
].type
);
252 case GLSL_TYPE_SAMPLER
:
253 /* Samplers take up one slot in UNIFORMS[], but they're baked in
264 vec4_visitor::virtual_grf_alloc(int size
)
266 if (virtual_grf_array_size
<= virtual_grf_count
) {
267 if (virtual_grf_array_size
== 0)
268 virtual_grf_array_size
= 16;
270 virtual_grf_array_size
*= 2;
271 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
272 virtual_grf_array_size
);
274 virtual_grf_sizes
[virtual_grf_count
] = size
;
275 return virtual_grf_count
++;
278 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
283 this->reg
= v
->virtual_grf_alloc(type_size(type
));
285 if (type
->is_array() || type
->is_record()) {
286 this->swizzle
= BRW_SWIZZLE_NOOP
;
288 this->swizzle
= swizzle_for_size(type
->vector_elements
);
291 this->type
= brw_type_for_base_type(type
);
294 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
299 this->reg
= v
->virtual_grf_alloc(type_size(type
));
301 if (type
->is_array() || type
->is_record()) {
302 this->writemask
= WRITEMASK_XYZW
;
304 this->writemask
= (1 << type
->vector_elements
) - 1;
307 this->type
= brw_type_for_base_type(type
);
310 /* Our support for uniforms is piggy-backed on the struct
311 * gl_fragment_program, because that's where the values actually
312 * get stored, rather than in some global gl_shader_program uniform
316 vec4_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
318 unsigned int offset
= 0;
319 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[loc
][0].f
;
321 if (type
->is_matrix()) {
322 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
323 type
->vector_elements
,
326 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
327 offset
+= setup_uniform_values(loc
+ offset
, column
);
333 switch (type
->base_type
) {
334 case GLSL_TYPE_FLOAT
:
338 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
339 int slot
= this->uniforms
* 4 + i
;
340 switch (type
->base_type
) {
341 case GLSL_TYPE_FLOAT
:
342 c
->prog_data
.param_convert
[slot
] = PARAM_NO_CONVERT
;
345 c
->prog_data
.param_convert
[slot
] = PARAM_CONVERT_F2U
;
348 c
->prog_data
.param_convert
[slot
] = PARAM_CONVERT_F2I
;
351 c
->prog_data
.param_convert
[slot
] = PARAM_CONVERT_F2B
;
354 assert(!"not reached");
355 c
->prog_data
.param_convert
[slot
] = PARAM_NO_CONVERT
;
358 c
->prog_data
.param
[slot
] = &values
[i
];
361 for (unsigned int i
= type
->vector_elements
; i
< 4; i
++) {
362 c
->prog_data
.param_convert
[this->uniforms
* 4 + i
] =
364 c
->prog_data
.param
[this->uniforms
* 4 + i
] = NULL
;
367 this->uniform_size
[this->uniforms
] = type
->vector_elements
;
372 case GLSL_TYPE_STRUCT
:
373 for (unsigned int i
= 0; i
< type
->length
; i
++) {
374 offset
+= setup_uniform_values(loc
+ offset
,
375 type
->fields
.structure
[i
].type
);
379 case GLSL_TYPE_ARRAY
:
380 for (unsigned int i
= 0; i
< type
->length
; i
++) {
381 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
385 case GLSL_TYPE_SAMPLER
:
386 /* The sampler takes up a slot, but we don't use any values from it. */
390 assert(!"not reached");
395 /* Our support for builtin uniforms is even scarier than non-builtin.
396 * It sits on top of the PROG_STATE_VAR parameters that are
397 * automatically updated from GL context state.
400 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
402 const ir_state_slot
*const slots
= ir
->state_slots
;
403 assert(ir
->state_slots
!= NULL
);
405 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
406 /* This state reference has already been setup by ir_to_mesa,
407 * but we'll get the same index back here. We can reference
408 * ParameterValues directly, since unlike brw_fs.cpp, we never
409 * add new state references during compile.
411 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
412 (gl_state_index
*)slots
[i
].tokens
);
413 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
415 this->uniform_size
[this->uniforms
] = 0;
416 /* Add each of the unique swizzled channels of the element.
417 * This will end up matching the size of the glsl_type of this field.
420 for (unsigned int j
= 0; j
< 4; j
++) {
421 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
422 if (swiz
== last_swiz
)
426 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
427 c
->prog_data
.param_convert
[this->uniforms
* 4 + j
] = PARAM_NO_CONVERT
;
428 this->uniform_size
[this->uniforms
]++;
435 vec4_visitor::variable_storage(ir_variable
*var
)
437 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
441 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
443 ir_expression
*expr
= ir
->as_expression();
447 vec4_instruction
*inst
;
449 assert(expr
->get_num_operands() <= 2);
450 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
451 assert(expr
->operands
[i
]->type
->is_scalar());
453 expr
->operands
[i
]->accept(this);
454 op
[i
] = this->result
;
457 switch (expr
->operation
) {
458 case ir_unop_logic_not
:
459 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], src_reg(1));
460 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
463 case ir_binop_logic_xor
:
464 inst
= emit(BRW_OPCODE_XOR
, dst_null_d(), op
[0], op
[1]);
465 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
468 case ir_binop_logic_or
:
469 inst
= emit(BRW_OPCODE_OR
, dst_null_d(), op
[0], op
[1]);
470 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
473 case ir_binop_logic_and
:
474 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], op
[1]);
475 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
479 if (intel
->gen
>= 6) {
480 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0.0f
));
482 inst
= emit(BRW_OPCODE_MOV
, dst_null_f(), op
[0]);
484 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
488 if (intel
->gen
>= 6) {
489 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
491 inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), op
[0]);
493 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
496 case ir_binop_greater
:
497 case ir_binop_gequal
:
499 case ir_binop_lequal
:
501 case ir_binop_all_equal
:
502 case ir_binop_nequal
:
503 case ir_binop_any_nequal
:
504 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
505 inst
->conditional_mod
=
506 brw_conditional_for_comparison(expr
->operation
);
510 assert(!"not reached");
518 if (intel
->gen
>= 6) {
519 vec4_instruction
*inst
= emit(BRW_OPCODE_AND
, dst_null_d(),
520 this->result
, src_reg(1));
521 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
523 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), this->result
);
524 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
529 * Emit a gen6 IF statement with the comparison folded into the IF
533 vec4_visitor::emit_if_gen6(ir_if
*ir
)
535 ir_expression
*expr
= ir
->condition
->as_expression();
539 vec4_instruction
*inst
;
542 assert(expr
->get_num_operands() <= 2);
543 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
544 assert(expr
->operands
[i
]->type
->is_scalar() ||
545 expr
->operation
== ir_binop_any_nequal
||
546 expr
->operation
== ir_binop_all_equal
);
548 expr
->operands
[i
]->accept(this);
549 op
[i
] = this->result
;
552 switch (expr
->operation
) {
553 case ir_unop_logic_not
:
554 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
555 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
558 case ir_binop_logic_xor
:
559 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
560 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
563 case ir_binop_logic_or
:
564 temp
= dst_reg(this, glsl_type::bool_type
);
565 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
566 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
567 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
570 case ir_binop_logic_and
:
571 temp
= dst_reg(this, glsl_type::bool_type
);
572 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
573 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
574 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
578 inst
= emit(BRW_OPCODE_IF
, dst_null_f(), op
[0], src_reg(0));
579 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
583 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
584 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
587 case ir_binop_greater
:
588 case ir_binop_gequal
:
590 case ir_binop_lequal
:
592 case ir_binop_nequal
:
593 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
594 inst
->conditional_mod
=
595 brw_conditional_for_comparison(expr
->operation
);
598 case ir_binop_all_equal
:
599 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
600 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
602 inst
= emit(BRW_OPCODE_IF
);
603 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
606 case ir_binop_any_nequal
:
607 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
608 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
610 inst
= emit(BRW_OPCODE_IF
);
611 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
615 assert(!"not reached");
616 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
617 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
623 ir
->condition
->accept(this);
625 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
, dst_null_d(),
626 this->result
, src_reg(0));
627 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
631 vec4_visitor::visit(ir_variable
*ir
)
635 if (variable_storage(ir
))
640 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
644 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
646 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
647 output_reg
[ir
->location
+ i
] = *reg
;
648 output_reg
[ir
->location
+ i
].reg_offset
= i
;
649 output_reg
[ir
->location
+ i
].type
= BRW_REGISTER_TYPE_F
;
654 case ir_var_temporary
:
655 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
659 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
661 if (!strncmp(ir
->name
, "gl_", 3)) {
662 setup_builtin_uniform_values(ir
);
664 setup_uniform_values(ir
->location
, ir
->type
);
669 assert(!"not reached");
672 reg
->type
= brw_type_for_base_type(ir
->type
);
673 hash_table_insert(this->variable_ht
, reg
, ir
);
677 vec4_visitor::visit(ir_loop
*ir
)
679 ir_dereference_variable
*counter
= NULL
;
683 /* We don't want debugging output to print the whole body of the
684 * loop as the annotation.
686 this->base_ir
= NULL
;
688 if (ir
->counter
!= NULL
)
689 counter
= new(ir
) ir_dereference_variable(ir
->counter
);
691 if (ir
->from
!= NULL
) {
692 assert(ir
->counter
!= NULL
);
694 ir_assignment
*a
= new(ir
) ir_assignment(counter
, ir
->from
, NULL
);
704 new(ir
) ir_expression(ir
->cmp
, glsl_type::bool_type
,
706 ir_if
*if_stmt
= new(ir
) ir_if(e
);
708 ir_loop_jump
*brk
= new(ir
) ir_loop_jump(ir_loop_jump::jump_break
);
710 if_stmt
->then_instructions
.push_tail(brk
);
712 if_stmt
->accept(this);
719 visit_instructions(&ir
->body_instructions
);
723 new(ir
) ir_expression(ir_binop_add
, counter
->type
,
724 counter
, ir
->increment
);
726 ir_assignment
*a
= new(ir
) ir_assignment(counter
, e
, NULL
);
733 emit(BRW_OPCODE_WHILE
);
737 vec4_visitor::visit(ir_loop_jump
*ir
)
740 case ir_loop_jump::jump_break
:
741 emit(BRW_OPCODE_BREAK
);
743 case ir_loop_jump::jump_continue
:
744 emit(BRW_OPCODE_CONTINUE
);
751 vec4_visitor::visit(ir_function_signature
*ir
)
758 vec4_visitor::visit(ir_function
*ir
)
760 /* Ignore function bodies other than main() -- we shouldn't see calls to
761 * them since they should all be inlined.
763 if (strcmp(ir
->name
, "main") == 0) {
764 const ir_function_signature
*sig
;
767 sig
= ir
->matching_signature(&empty
);
771 visit_instructions(&sig
->body
);
776 vec4_visitor::try_emit_sat(ir_expression
*ir
)
778 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
782 sat_src
->accept(this);
783 src_reg src
= this->result
;
785 this->result
= src_reg(this, ir
->type
);
786 vec4_instruction
*inst
;
787 inst
= emit(BRW_OPCODE_MOV
, dst_reg(this->result
), src
);
788 inst
->saturate
= true;
794 vec4_visitor::emit_bool_comparison(unsigned int op
,
795 dst_reg dst
, src_reg src0
, src_reg src1
)
797 /* original gen4 does destination conversion before comparison. */
799 dst
.type
= src0
.type
;
801 vec4_instruction
*inst
= emit(BRW_OPCODE_CMP
, dst
, src0
, src1
);
802 inst
->conditional_mod
= brw_conditional_for_comparison(op
);
804 dst
.type
= BRW_REGISTER_TYPE_D
;
805 emit(BRW_OPCODE_AND
, dst
, src_reg(dst
), src_reg(0x1));
809 vec4_visitor::visit(ir_expression
*ir
)
811 unsigned int operand
;
812 src_reg op
[Elements(ir
->operands
)];
815 vec4_instruction
*inst
;
817 if (try_emit_sat(ir
))
820 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
821 this->result
.file
= BAD_FILE
;
822 ir
->operands
[operand
]->accept(this);
823 if (this->result
.file
== BAD_FILE
) {
824 printf("Failed to get tree for expression operand:\n");
825 ir
->operands
[operand
]->print();
828 op
[operand
] = this->result
;
830 /* Matrix expression operands should have been broken down to vector
831 * operations already.
833 assert(!ir
->operands
[operand
]->type
->is_matrix());
836 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
837 if (ir
->operands
[1]) {
838 vector_elements
= MAX2(vector_elements
,
839 ir
->operands
[1]->type
->vector_elements
);
842 this->result
.file
= BAD_FILE
;
844 /* Storage for our result. Ideally for an assignment we'd be using
845 * the actual storage for the result here, instead.
847 result_src
= src_reg(this, ir
->type
);
848 /* convenience for the emit functions below. */
849 result_dst
= dst_reg(result_src
);
850 /* If nothing special happens, this is the result. */
851 this->result
= result_src
;
852 /* Limit writes to the channels that will be used by result_src later.
853 * This does limit this temp's use as a temporary for multi-instruction
856 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
858 switch (ir
->operation
) {
859 case ir_unop_logic_not
:
860 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
861 * ones complement of the whole register, not just bit 0.
863 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], src_reg(1));
866 op
[0].negate
= !op
[0].negate
;
867 this->result
= op
[0];
871 op
[0].negate
= false;
872 this->result
= op
[0];
876 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0.0f
));
878 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
879 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
880 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1.0f
));
881 inst
->predicate
= BRW_PREDICATE_NORMAL
;
883 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
884 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
885 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(-1.0f
));
886 inst
->predicate
= BRW_PREDICATE_NORMAL
;
891 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
895 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
898 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
902 assert(!"not reached: should be handled by ir_explog_to_explog2");
905 case ir_unop_sin_reduced
:
906 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
909 case ir_unop_cos_reduced
:
910 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
915 assert(!"derivatives not valid in vertex shader");
919 assert(!"not reached: should be handled by lower_noise");
923 emit(BRW_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
926 assert(!"not reached: should be handled by ir_sub_to_add_neg");
930 emit(BRW_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
933 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
935 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
939 case ir_binop_greater
:
940 case ir_binop_lequal
:
941 case ir_binop_gequal
:
943 case ir_binop_nequal
: {
944 dst_reg temp
= result_dst
;
945 /* original gen4 does implicit conversion before comparison. */
947 temp
.type
= op
[0].type
;
949 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
950 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
951 emit(BRW_OPCODE_AND
, result_dst
, this->result
, src_reg(0x1));
955 case ir_binop_all_equal
:
956 /* "==" operator producing a scalar boolean. */
957 if (ir
->operands
[0]->type
->is_vector() ||
958 ir
->operands
[1]->type
->is_vector()) {
959 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
960 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
962 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
963 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
964 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
966 dst_reg temp
= result_dst
;
967 /* original gen4 does implicit conversion before comparison. */
969 temp
.type
= op
[0].type
;
971 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
972 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
973 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
976 case ir_binop_any_nequal
:
977 /* "!=" operator producing a scalar boolean. */
978 if (ir
->operands
[0]->type
->is_vector() ||
979 ir
->operands
[1]->type
->is_vector()) {
980 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
981 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
983 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
984 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
985 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
987 dst_reg temp
= result_dst
;
988 /* original gen4 does implicit conversion before comparison. */
990 temp
.type
= op
[0].type
;
992 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
993 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
994 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
999 emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
1000 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1002 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1003 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1006 case ir_binop_logic_xor
:
1007 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1010 case ir_binop_logic_or
:
1011 emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1014 case ir_binop_logic_and
:
1015 emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1019 assert(ir
->operands
[0]->type
->is_vector());
1020 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1021 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1025 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1028 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1037 emit(BRW_OPCODE_MOV
, result_dst
, op
[0]);
1041 dst_reg temp
= result_dst
;
1042 /* original gen4 does implicit conversion before comparison. */
1044 temp
.type
= op
[0].type
;
1046 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], src_reg(0.0f
));
1047 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1048 inst
= emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(1));
1053 emit(BRW_OPCODE_RNDZ
, result_dst
, op
[0]);
1056 op
[0].negate
= !op
[0].negate
;
1057 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1058 this->result
.negate
= true;
1061 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1064 inst
= emit(BRW_OPCODE_FRC
, result_dst
, op
[0]);
1066 case ir_unop_round_even
:
1067 emit(BRW_OPCODE_RNDE
, result_dst
, op
[0]);
1071 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1072 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1074 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1075 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1078 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1079 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1081 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1082 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1086 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1089 case ir_unop_bit_not
:
1090 inst
= emit(BRW_OPCODE_NOT
, result_dst
, op
[0]);
1092 case ir_binop_bit_and
:
1093 inst
= emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1095 case ir_binop_bit_xor
:
1096 inst
= emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1098 case ir_binop_bit_or
:
1099 inst
= emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1102 case ir_binop_lshift
:
1103 case ir_binop_rshift
:
1104 assert(!"GLSL 1.30 features unsupported");
1107 case ir_quadop_vector
:
1108 assert(!"not reached: should be handled by lower_quadop_vector");
1115 vec4_visitor::visit(ir_swizzle
*ir
)
1121 /* Note that this is only swizzles in expressions, not those on the left
1122 * hand side of an assignment, which do write masking. See ir_assignment
1126 ir
->val
->accept(this);
1128 assert(src
.file
!= BAD_FILE
);
1130 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1133 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1136 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1139 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1142 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1146 for (; i
< 4; i
++) {
1147 /* Replicate the last channel out. */
1148 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1151 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1157 vec4_visitor::visit(ir_dereference_variable
*ir
)
1159 const struct glsl_type
*type
= ir
->type
;
1160 dst_reg
*reg
= variable_storage(ir
->var
);
1163 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1164 this->result
= src_reg(brw_null_reg());
1168 this->result
= src_reg(*reg
);
1170 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1171 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1175 vec4_visitor::visit(ir_dereference_array
*ir
)
1177 ir_constant
*constant_index
;
1179 int element_size
= type_size(ir
->type
);
1181 constant_index
= ir
->array_index
->constant_expression_value();
1183 ir
->array
->accept(this);
1186 if (constant_index
) {
1187 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1189 #if 0 /* Variable array index */
1190 /* Variable index array dereference. It eats the "vec4" of the
1191 * base of the array and an index that offsets the Mesa register
1194 ir
->array_index
->accept(this);
1198 if (element_size
== 1) {
1199 index_reg
= this->result
;
1201 index_reg
= src_reg(this, glsl_type::float_type
);
1203 emit(BRW_OPCODE_MUL
, dst_reg(index_reg
),
1204 this->result
, src_reg_for_float(element_size
));
1207 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1208 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1212 /* If the type is smaller than a vec4, replicate the last channel out. */
1213 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1214 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1216 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1217 src
.type
= brw_type_for_base_type(ir
->type
);
1223 vec4_visitor::visit(ir_dereference_record
*ir
)
1226 const glsl_type
*struct_type
= ir
->record
->type
;
1229 ir
->record
->accept(this);
1231 for (i
= 0; i
< struct_type
->length
; i
++) {
1232 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1234 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1237 /* If the type is smaller than a vec4, replicate the last channel out. */
1238 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1239 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1241 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1242 this->result
.type
= brw_type_for_base_type(ir
->type
);
1244 this->result
.reg_offset
+= offset
;
1248 * We want to be careful in assignment setup to hit the actual storage
1249 * instead of potentially using a temporary like we might with the
1250 * ir_dereference handler.
1253 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1255 /* The LHS must be a dereference. If the LHS is a variable indexed array
1256 * access of a vector, it must be separated into a series conditional moves
1257 * before reaching this point (see ir_vec_index_to_cond_assign).
1259 assert(ir
->as_dereference());
1260 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1262 assert(!deref_array
->array
->type
->is_vector());
1265 /* Use the rvalue deref handler for the most part. We'll ignore
1266 * swizzles in it and write swizzles using writemask, though.
1269 return dst_reg(v
->result
);
1273 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1274 const struct glsl_type
*type
, bool predicated
)
1276 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1277 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1278 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicated
);
1283 if (type
->is_array()) {
1284 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1285 emit_block_move(dst
, src
, type
->fields
.array
, predicated
);
1290 if (type
->is_matrix()) {
1291 const struct glsl_type
*vec_type
;
1293 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1294 type
->vector_elements
, 1);
1296 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1297 emit_block_move(dst
, src
, vec_type
, predicated
);
1302 assert(type
->is_scalar() || type
->is_vector());
1304 dst
->type
= brw_type_for_base_type(type
);
1305 src
->type
= dst
->type
;
1307 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1309 /* Do we need to worry about swizzling a swizzle? */
1310 assert(src
->swizzle
= BRW_SWIZZLE_NOOP
);
1311 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1313 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, *dst
, *src
);
1315 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1322 vec4_visitor::visit(ir_assignment
*ir
)
1324 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1326 if (!ir
->lhs
->type
->is_scalar() &&
1327 !ir
->lhs
->type
->is_vector()) {
1328 ir
->rhs
->accept(this);
1329 src_reg src
= this->result
;
1331 if (ir
->condition
) {
1332 emit_bool_to_cond_code(ir
->condition
);
1335 emit_block_move(&dst
, &src
, ir
->rhs
->type
, ir
->condition
!= NULL
);
1339 /* Now we're down to just a scalar/vector with writemasks. */
1342 ir
->rhs
->accept(this);
1343 src_reg src
= this->result
;
1346 int first_enabled_chan
= 0;
1349 assert(ir
->lhs
->type
->is_vector() ||
1350 ir
->lhs
->type
->is_scalar());
1351 dst
.writemask
= ir
->write_mask
;
1353 for (int i
= 0; i
< 4; i
++) {
1354 if (dst
.writemask
& (1 << i
)) {
1355 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1360 /* Swizzle a small RHS vector into the channels being written.
1362 * glsl ir treats write_mask as dictating how many channels are
1363 * present on the RHS while in our instructions we need to make
1364 * those channels appear in the slots of the vec4 they're written to.
1366 for (int i
= 0; i
< 4; i
++) {
1367 if (dst
.writemask
& (1 << i
))
1368 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1370 swizzles
[i
] = first_enabled_chan
;
1372 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1373 swizzles
[2], swizzles
[3]);
1375 if (ir
->condition
) {
1376 emit_bool_to_cond_code(ir
->condition
);
1379 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1380 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst
, src
);
1383 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1392 vec4_visitor::visit(ir_constant
*ir
)
1394 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1395 src_reg temp_base
= src_reg(this, ir
->type
);
1396 dst_reg temp
= dst_reg(temp_base
);
1398 foreach_iter(exec_list_iterator
, iter
, ir
->components
) {
1399 ir_constant
*field_value
= (ir_constant
*)iter
.get();
1400 int size
= type_size(field_value
->type
);
1404 field_value
->accept(this);
1405 src_reg src
= this->result
;
1407 for (int i
= 0; i
< (unsigned int)size
; i
++) {
1408 emit(BRW_OPCODE_MOV
, temp
, src
);
1414 this->result
= temp_base
;
1418 if (ir
->type
->is_array()) {
1419 src_reg temp_base
= src_reg(this, ir
->type
);
1420 dst_reg temp
= dst_reg(temp_base
);
1421 int size
= type_size(ir
->type
->fields
.array
);
1425 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1426 ir
->array_elements
[i
]->accept(this);
1427 src_reg src
= this->result
;
1428 for (int j
= 0; j
< size
; j
++) {
1429 emit(BRW_OPCODE_MOV
, temp
, src
);
1435 this->result
= temp_base
;
1439 if (ir
->type
->is_matrix()) {
1440 this->result
= src_reg(this, ir
->type
);
1441 dst_reg dst
= dst_reg(this->result
);
1443 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
1445 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1446 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
1447 dst
.writemask
= 1 << j
;
1448 emit(BRW_OPCODE_MOV
, dst
,
1449 src_reg(ir
->value
.f
[i
* ir
->type
->vector_elements
+ j
]));
1456 this->result
= src_reg(this, ir
->type
);
1457 dst_reg dst
= dst_reg(this->result
);
1459 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1460 dst
.writemask
= 1 << i
;
1462 switch (ir
->type
->base_type
) {
1463 case GLSL_TYPE_FLOAT
:
1464 emit(BRW_OPCODE_MOV
, dst
, src_reg(ir
->value
.f
[i
]));
1467 emit(BRW_OPCODE_MOV
, dst
, src_reg(ir
->value
.i
[i
]));
1469 case GLSL_TYPE_UINT
:
1470 emit(BRW_OPCODE_MOV
, dst
, src_reg(ir
->value
.u
[i
]));
1472 case GLSL_TYPE_BOOL
:
1473 emit(BRW_OPCODE_MOV
, dst
, src_reg(ir
->value
.b
[i
]));
1476 assert(!"Non-float/uint/int/bool constant");
1483 vec4_visitor::visit(ir_call
*ir
)
1485 assert(!"not reached");
1489 vec4_visitor::visit(ir_texture
*ir
)
1491 assert(!"not reached");
1495 vec4_visitor::visit(ir_return
*ir
)
1497 assert(!"not reached");
1501 vec4_visitor::visit(ir_discard
*ir
)
1503 assert(!"not reached");
1507 vec4_visitor::visit(ir_if
*ir
)
1509 /* Don't point the annotation at the if statement, because then it plus
1510 * the then and else blocks get printed.
1512 this->base_ir
= ir
->condition
;
1514 if (intel
->gen
== 6) {
1517 emit_bool_to_cond_code(ir
->condition
);
1518 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
);
1519 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1522 visit_instructions(&ir
->then_instructions
);
1524 if (!ir
->else_instructions
.is_empty()) {
1525 this->base_ir
= ir
->condition
;
1526 emit(BRW_OPCODE_ELSE
);
1528 visit_instructions(&ir
->else_instructions
);
1531 this->base_ir
= ir
->condition
;
1532 emit(BRW_OPCODE_ENDIF
);
1536 vec4_visitor::emit_vue_header_gen4(int header_mrf
)
1538 /* Get the position */
1539 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
1541 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1542 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1544 current_annotation
= "NDC";
1545 dst_reg ndc_w
= ndc
;
1546 ndc_w
.writemask
= WRITEMASK_W
;
1547 src_reg pos_w
= pos
;
1548 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1549 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1551 dst_reg ndc_xyz
= ndc
;
1552 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1554 emit(BRW_OPCODE_MUL
, ndc_xyz
, pos
, src_reg(ndc_w
));
1556 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1557 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
) {
1558 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1561 emit(BRW_OPCODE_MOV
, header1
, 0u);
1563 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1564 assert(!"finishme: psiz");
1567 header1
.writemask
= WRITEMASK_W
;
1568 emit(BRW_OPCODE_MUL
, header1
, psiz
, 1u << 11);
1569 emit(BRW_OPCODE_AND
, header1
, src_reg(header1
), 0x7ff << 8);
1572 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1573 vec4_instruction
*inst
;
1575 inst
= emit(BRW_OPCODE_DP4
, dst_reg(brw_null_reg()),
1576 pos
, src_reg(c
->userplane
[i
]));
1577 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1579 emit(BRW_OPCODE_OR
, header1
, src_reg(header1
), 1u << i
);
1580 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1583 /* i965 clipping workaround:
1584 * 1) Test for -ve rhw
1586 * set ndc = (0,0,0,0)
1589 * Later, clipping will detect ucp[6] and ensure the primitive is
1590 * clipped against all fixed planes.
1592 if (brw
->has_negative_rhw_bug
) {
1596 vec8(brw_null_reg()),
1598 brw_swizzle1(ndc
, 3),
1601 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1602 brw_MOV(p
, ndc
, brw_imm_f(0));
1603 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1607 header1
.writemask
= WRITEMASK_XYZW
;
1608 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(header1
));
1610 emit(BRW_OPCODE_MOV
, retype(brw_message_reg(header_mrf
++),
1611 BRW_REGISTER_TYPE_UD
), 0u);
1614 if (intel
->gen
== 5) {
1615 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
1616 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1617 * dword 4-7 (m2) is the ndc position (set above)
1618 * dword 8-11 (m3) of the vertex header is the 4D space position
1619 * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
1620 * m6 is a pad so that the vertex element data is aligned
1621 * m7 is the first vertex data we fill.
1623 current_annotation
= "NDC";
1624 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1626 current_annotation
= "gl_Position";
1627 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1629 /* user clip distance. */
1632 /* Pad so that vertex element data is aligned. */
1635 /* There are 8 dwords in VUE header pre-Ironlake:
1636 * dword 0-3 (m1) is indices, point width, clip flags.
1637 * dword 4-7 (m2) is ndc position (set above)
1639 * dword 8-11 (m3) is the first vertex data.
1641 current_annotation
= "NDC";
1642 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1644 current_annotation
= "gl_Position";
1645 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1652 vec4_visitor::emit_vue_header_gen6(int header_mrf
)
1656 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
1657 * dword 0-3 (m2) of the header is indices, point width, clip flags.
1658 * dword 4-7 (m3) is the 4D space position
1659 * dword 8-15 (m4,m5) of the vertex header is the user clip distance if
1662 * m4 or 6 is the first vertex element data we fill.
1665 current_annotation
= "indices, point width, clip flags";
1666 reg
= brw_message_reg(header_mrf
++);
1667 emit(BRW_OPCODE_MOV
, retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0));
1668 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1669 emit(BRW_OPCODE_MOV
, brw_writemask(reg
, WRITEMASK_W
),
1670 src_reg(output_reg
[VERT_RESULT_PSIZ
]));
1673 current_annotation
= "gl_Position";
1674 emit(BRW_OPCODE_MOV
,
1675 brw_message_reg(header_mrf
++), src_reg(output_reg
[VERT_RESULT_HPOS
]));
1677 current_annotation
= "user clip distances";
1678 if (c
->key
.nr_userclip
) {
1679 for (int i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1682 m
= brw_message_reg(header_mrf
);
1684 m
= brw_message_reg(header_mrf
+ 1);
1686 emit(BRW_OPCODE_DP4
,
1687 dst_reg(brw_writemask(m
, 1 << (i
& 3))),
1688 src_reg(c
->userplane
[i
]));
1693 current_annotation
= NULL
;
1699 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
1701 struct intel_context
*intel
= &brw
->intel
;
1703 if (intel
->gen
>= 6) {
1704 /* URB data written (does not include the message header reg) must
1705 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1706 * section 5.4.3.2.2: URB_INTERLEAVED.
1708 * URB entries are allocated on a multiple of 1024 bits, so an
1709 * extra 128 bits written here to make the end align to 256 is
1712 if ((mlen
% 2) != 1)
1720 * Generates the VUE payload plus the 1 or 2 URB write instructions to
1721 * complete the VS thread.
1723 * The VUE layout is documented in Volume 2a.
1726 vec4_visitor::emit_urb_writes()
1732 /* FINISHME: edgeflag */
1734 /* First mrf is the g0-based message header containing URB handles and such,
1735 * which is implied in VS_OPCODE_URB_WRITE.
1739 if (intel
->gen
>= 6) {
1740 mrf
= emit_vue_header_gen6(mrf
);
1742 mrf
= emit_vue_header_gen4(mrf
);
1746 for (attr
= 0; attr
< VERT_RESULT_MAX
; attr
++) {
1747 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1750 /* This is set up in the VUE header. */
1751 if (attr
== VERT_RESULT_HPOS
)
1754 /* This is loaded into the VUE header, and thus doesn't occupy
1755 * an attribute slot.
1757 if (attr
== VERT_RESULT_PSIZ
)
1760 emit(BRW_OPCODE_MOV
, brw_message_reg(mrf
++), src_reg(output_reg
[attr
]));
1762 /* If this is MRF 15, we can't fit anything more into this URB
1763 * WRITE. Note that base_mrf of 1 means that MRF 15 is an
1764 * even-numbered amount of URB write data, which will meet
1765 * gen6's requirements for length alignment.
1771 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
1772 inst
->base_mrf
= base_mrf
;
1773 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1776 urb_entry_size
= mrf
- base_mrf
;
1778 for (; attr
< VERT_RESULT_MAX
; attr
++) {
1779 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1781 fail("Second URB write not supported.\n");
1785 if (intel
->gen
== 6)
1786 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 8) / 8;
1788 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 4) / 4;
1791 vec4_visitor::vec4_visitor(struct brw_vs_compile
*c
,
1792 struct gl_shader_program
*prog
,
1793 struct brw_shader
*shader
)
1798 this->intel
= &brw
->intel
;
1799 this->ctx
= &intel
->ctx
;
1801 this->shader
= shader
;
1803 this->mem_ctx
= ralloc_context(NULL
);
1804 this->failed
= false;
1806 this->base_ir
= NULL
;
1807 this->current_annotation
= NULL
;
1810 this->vp
= brw
->vertex_program
; /* FINISHME: change for precompile */
1811 this->prog_data
= &c
->prog_data
;
1813 this->variable_ht
= hash_table_ctor(0,
1814 hash_table_pointer_hash
,
1815 hash_table_pointer_compare
);
1817 this->virtual_grf_sizes
= NULL
;
1818 this->virtual_grf_count
= 0;
1819 this->virtual_grf_array_size
= 0;
1823 this->variable_ht
= hash_table_ctor(0,
1824 hash_table_pointer_hash
,
1825 hash_table_pointer_compare
);
1828 vec4_visitor::~vec4_visitor()
1830 hash_table_dtor(this->variable_ht
);
1835 vec4_visitor::fail(const char *format
, ...)
1845 va_start(va
, format
);
1846 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
1848 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
1850 this->fail_msg
= msg
;
1852 if (INTEL_DEBUG
& DEBUG_VS
) {
1853 fprintf(stderr
, "%s", msg
);
1857 } /* namespace brw */