2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
32 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
33 enum opcode opcode
, dst_reg dst
,
34 src_reg src0
, src_reg src1
, src_reg src2
)
36 this->opcode
= opcode
;
41 this->saturate
= false;
42 this->force_writemask_all
= false;
43 this->no_dd_clear
= false;
44 this->no_dd_check
= false;
45 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
47 this->texture_offset
= 0;
49 this->shadow_compare
= false;
50 this->ir
= v
->base_ir
;
51 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
52 this->header_present
= false;
56 this->annotation
= v
->current_annotation
;
60 vec4_visitor::emit(vec4_instruction
*inst
)
62 this->instructions
.push_tail(inst
);
68 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
70 new_inst
->ir
= inst
->ir
;
71 new_inst
->annotation
= inst
->annotation
;
73 inst
->insert_before(new_inst
);
79 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
80 src_reg src0
, src_reg src1
, src_reg src2
)
82 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
88 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
90 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
94 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
96 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
100 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
)
102 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
));
106 vec4_visitor::emit(enum opcode opcode
)
108 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
113 vec4_visitor::op(dst_reg dst, src_reg src0) \
115 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
121 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
123 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
129 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1, src_reg src2)\
131 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
167 /** Gen4 predicated IF. */
169 vec4_visitor::IF(uint32_t predicate
)
171 vec4_instruction
*inst
;
173 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
174 inst
->predicate
= predicate
;
179 /** Gen6 IF with embedded comparison. */
181 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
183 assert(brw
->gen
== 6);
185 vec4_instruction
*inst
;
187 resolve_ud_negate(&src0
);
188 resolve_ud_negate(&src1
);
190 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
192 inst
->conditional_mod
= condition
;
198 * CMP: Sets the low bit of the destination channels with the result
199 * of the comparison, while the upper bits are undefined, and updates
200 * the flag register with the packed 16 bits of the result.
203 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
205 vec4_instruction
*inst
;
207 /* original gen4 does type conversion to the destination type
208 * before before comparison, producing garbage results for floating
212 dst
.type
= src0
.type
;
213 if (dst
.file
== HW_REG
)
214 dst
.fixed_hw_reg
.type
= dst
.type
;
217 resolve_ud_negate(&src0
);
218 resolve_ud_negate(&src1
);
220 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
221 inst
->conditional_mod
= condition
;
227 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
229 vec4_instruction
*inst
;
231 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_READ
,
240 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
242 vec4_instruction
*inst
;
244 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
253 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
255 static enum opcode dot_opcodes
[] = {
256 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
259 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
263 vec4_visitor::fix_3src_operand(src_reg src
)
265 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
266 * able to use vertical stride of zero to replicate the vec4 uniform, like
268 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
270 * But you can't, since vertical stride is always four in three-source
271 * instructions. Instead, insert a MOV instruction to do the replication so
272 * that the three-source instruction can consume it.
275 /* The MOV is only needed if the source is a uniform or immediate. */
276 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
279 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
280 expanded
.type
= src
.type
;
281 emit(MOV(expanded
, src
));
282 return src_reg(expanded
);
286 vec4_visitor::fix_math_operand(src_reg src
)
288 /* The gen6 math instruction ignores the source modifiers --
289 * swizzle, abs, negate, and at least some parts of the register
290 * region description.
292 * Rather than trying to enumerate all these cases, *always* expand the
293 * operand to a temp GRF for gen6.
295 * For gen7, keep the operand as-is, except if immediate, which gen7 still
299 if (brw
->gen
== 7 && src
.file
!= IMM
)
302 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
303 expanded
.type
= src
.type
;
304 emit(MOV(expanded
, src
));
305 return src_reg(expanded
);
309 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
311 src
= fix_math_operand(src
);
313 if (dst
.writemask
!= WRITEMASK_XYZW
) {
314 /* The gen6 math instruction must be align1, so we can't do
317 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
319 emit(opcode
, temp_dst
, src
);
321 emit(MOV(dst
, src_reg(temp_dst
)));
323 emit(opcode
, dst
, src
);
328 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
330 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
336 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
339 case SHADER_OPCODE_RCP
:
340 case SHADER_OPCODE_RSQ
:
341 case SHADER_OPCODE_SQRT
:
342 case SHADER_OPCODE_EXP2
:
343 case SHADER_OPCODE_LOG2
:
344 case SHADER_OPCODE_SIN
:
345 case SHADER_OPCODE_COS
:
348 assert(!"not reached: bad math opcode");
353 return emit_math1_gen6(opcode
, dst
, src
);
355 return emit_math1_gen4(opcode
, dst
, src
);
360 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
361 dst_reg dst
, src_reg src0
, src_reg src1
)
363 src0
= fix_math_operand(src0
);
364 src1
= fix_math_operand(src1
);
366 if (dst
.writemask
!= WRITEMASK_XYZW
) {
367 /* The gen6 math instruction must be align1, so we can't do
370 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
371 temp_dst
.type
= dst
.type
;
373 emit(opcode
, temp_dst
, src0
, src1
);
375 emit(MOV(dst
, src_reg(temp_dst
)));
377 emit(opcode
, dst
, src0
, src1
);
382 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
383 dst_reg dst
, src_reg src0
, src_reg src1
)
385 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
391 vec4_visitor::emit_math(enum opcode opcode
,
392 dst_reg dst
, src_reg src0
, src_reg src1
)
395 case SHADER_OPCODE_POW
:
396 case SHADER_OPCODE_INT_QUOTIENT
:
397 case SHADER_OPCODE_INT_REMAINDER
:
400 assert(!"not reached: unsupported binary math opcode");
405 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
407 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
412 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
415 assert(!"ir_unop_pack_half_2x16 should be lowered");
417 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
418 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
420 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
422 * Because this instruction does not have a 16-bit floating-point type,
423 * the destination data type must be Word (W).
425 * The destination must be DWord-aligned and specify a horizontal stride
426 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
427 * each destination channel and the upper word is not modified.
429 * The above restriction implies that the f32to16 instruction must use
430 * align1 mode, because only in align1 mode is it possible to specify
431 * horizontal stride. We choose here to defy the hardware docs and emit
432 * align16 instructions.
434 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
435 * instructions. I was partially successful in that the code passed all
436 * tests. However, the code was dubiously correct and fragile, and the
437 * tests were not harsh enough to probe that frailty. Not trusting the
438 * code, I chose instead to remain in align16 mode in defiance of the hw
441 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
442 * simulator, emitting a f32to16 in align16 mode with UD as destination
443 * data type is safe. The behavior differs from that specified in the PRM
444 * in that the upper word of each destination channel is cleared to 0.
447 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
448 src_reg
tmp_src(tmp_dst
);
451 /* Verify the undocumented behavior on which the following instructions
452 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
453 * then the result of the bit-or instruction below will be incorrect.
455 * You should inspect the disasm output in order to verify that the MOV is
456 * not optimized away.
458 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
461 /* Give tmp the form below, where "." means untouched.
464 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
466 * That the upper word of each write-channel be 0 is required for the
467 * following bit-shift and bit-or instructions to work. Note that this
468 * relies on the undocumented hardware behavior mentioned above.
470 tmp_dst
.writemask
= WRITEMASK_XY
;
471 emit(F32TO16(tmp_dst
, src0
));
473 /* Give the write-channels of dst the form:
476 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
477 emit(SHL(dst
, tmp_src
, src_reg(16u)));
479 /* Finally, give the write-channels of dst the form of packHalf2x16's
483 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
484 emit(OR(dst
, src_reg(dst
), tmp_src
));
488 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
491 assert(!"ir_unop_unpack_half_2x16 should be lowered");
493 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
494 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
496 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
498 * Because this instruction does not have a 16-bit floating-point type,
499 * the source data type must be Word (W). The destination type must be
502 * To use W as the source data type, we must adjust horizontal strides,
503 * which is only possible in align1 mode. All my [chadv] attempts at
504 * emitting align1 instructions for unpackHalf2x16 failed to pass the
505 * Piglit tests, so I gave up.
507 * I've verified that, on gen7 hardware and the simulator, it is safe to
508 * emit f16to32 in align16 mode with UD as source data type.
511 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
512 src_reg
tmp_src(tmp_dst
);
514 tmp_dst
.writemask
= WRITEMASK_X
;
515 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
517 tmp_dst
.writemask
= WRITEMASK_Y
;
518 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
520 dst
.writemask
= WRITEMASK_XY
;
521 emit(F16TO32(dst
, tmp_src
));
525 vec4_visitor::visit_instructions(const exec_list
*list
)
527 foreach_list(node
, list
) {
528 ir_instruction
*ir
= (ir_instruction
*)node
;
537 type_size(const struct glsl_type
*type
)
542 switch (type
->base_type
) {
545 case GLSL_TYPE_FLOAT
:
547 if (type
->is_matrix()) {
548 return type
->matrix_columns
;
550 /* Regardless of size of vector, it gets a vec4. This is bad
551 * packing for things like floats, but otherwise arrays become a
552 * mess. Hopefully a later pass over the code can pack scalars
553 * down if appropriate.
557 case GLSL_TYPE_ARRAY
:
558 assert(type
->length
> 0);
559 return type_size(type
->fields
.array
) * type
->length
;
560 case GLSL_TYPE_STRUCT
:
562 for (i
= 0; i
< type
->length
; i
++) {
563 size
+= type_size(type
->fields
.structure
[i
].type
);
566 case GLSL_TYPE_SAMPLER
:
567 /* Samplers take up one slot in UNIFORMS[], but they're baked in
571 case GLSL_TYPE_ATOMIC_UINT
:
573 case GLSL_TYPE_IMAGE
:
575 case GLSL_TYPE_ERROR
:
576 case GLSL_TYPE_INTERFACE
:
585 vec4_visitor::virtual_grf_alloc(int size
)
587 if (virtual_grf_array_size
<= virtual_grf_count
) {
588 if (virtual_grf_array_size
== 0)
589 virtual_grf_array_size
= 16;
591 virtual_grf_array_size
*= 2;
592 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
593 virtual_grf_array_size
);
594 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
595 virtual_grf_array_size
);
597 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
598 virtual_grf_reg_count
+= size
;
599 virtual_grf_sizes
[virtual_grf_count
] = size
;
600 return virtual_grf_count
++;
603 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
608 this->reg
= v
->virtual_grf_alloc(type_size(type
));
610 if (type
->is_array() || type
->is_record()) {
611 this->swizzle
= BRW_SWIZZLE_NOOP
;
613 this->swizzle
= swizzle_for_size(type
->vector_elements
);
616 this->type
= brw_type_for_base_type(type
);
619 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
624 this->reg
= v
->virtual_grf_alloc(type_size(type
));
626 if (type
->is_array() || type
->is_record()) {
627 this->writemask
= WRITEMASK_XYZW
;
629 this->writemask
= (1 << type
->vector_elements
) - 1;
632 this->type
= brw_type_for_base_type(type
);
635 /* Our support for uniforms is piggy-backed on the struct
636 * gl_fragment_program, because that's where the values actually
637 * get stored, rather than in some global gl_shader_program uniform
641 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
643 int namelen
= strlen(ir
->name
);
645 /* The data for our (non-builtin) uniforms is stored in a series of
646 * gl_uniform_driver_storage structs for each subcomponent that
647 * glGetUniformLocation() could name. We know it's been set up in the same
648 * order we'd walk the type, so walk the list of storage and find anything
649 * with our name, or the prefix of a component that starts with our name.
651 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
652 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
654 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
655 (storage
->name
[namelen
] != 0 &&
656 storage
->name
[namelen
] != '.' &&
657 storage
->name
[namelen
] != '[')) {
661 gl_constant_value
*components
= storage
->storage
;
662 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
663 storage
->type
->matrix_columns
);
665 for (unsigned s
= 0; s
< vector_count
; s
++) {
666 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
669 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
670 stage_prog_data
->param
[uniforms
* 4 + i
] = &components
->f
;
674 static float zero
= 0;
675 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
684 vec4_visitor::setup_uniform_clipplane_values()
686 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
688 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
689 this->uniform_vector_size
[this->uniforms
] = 4;
690 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
691 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
692 for (int j
= 0; j
< 4; ++j
) {
693 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
699 /* Our support for builtin uniforms is even scarier than non-builtin.
700 * It sits on top of the PROG_STATE_VAR parameters that are
701 * automatically updated from GL context state.
704 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
706 const ir_state_slot
*const slots
= ir
->state_slots
;
707 assert(ir
->state_slots
!= NULL
);
709 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
710 /* This state reference has already been setup by ir_to_mesa,
711 * but we'll get the same index back here. We can reference
712 * ParameterValues directly, since unlike brw_fs.cpp, we never
713 * add new state references during compile.
715 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
716 (gl_state_index
*)slots
[i
].tokens
);
717 float *values
= &this->prog
->Parameters
->ParameterValues
[index
][0].f
;
719 this->uniform_vector_size
[this->uniforms
] = 0;
720 /* Add each of the unique swizzled channels of the element.
721 * This will end up matching the size of the glsl_type of this field.
724 for (unsigned int j
= 0; j
< 4; j
++) {
725 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
728 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
729 if (swiz
<= last_swiz
)
730 this->uniform_vector_size
[this->uniforms
]++;
737 vec4_visitor::variable_storage(ir_variable
*var
)
739 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
743 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
)
745 ir_expression
*expr
= ir
->as_expression();
747 *predicate
= BRW_PREDICATE_NORMAL
;
751 vec4_instruction
*inst
;
753 assert(expr
->get_num_operands() <= 2);
754 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
755 expr
->operands
[i
]->accept(this);
756 op
[i
] = this->result
;
758 resolve_ud_negate(&op
[i
]);
761 switch (expr
->operation
) {
762 case ir_unop_logic_not
:
763 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
764 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
767 case ir_binop_logic_xor
:
768 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
769 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
772 case ir_binop_logic_or
:
773 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
774 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
777 case ir_binop_logic_and
:
778 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
779 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
784 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
786 inst
= emit(MOV(dst_null_f(), op
[0]));
787 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
793 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
795 inst
= emit(MOV(dst_null_d(), op
[0]));
796 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
800 case ir_binop_all_equal
:
801 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
802 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
805 case ir_binop_any_nequal
:
806 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
807 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
811 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
812 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
815 case ir_binop_greater
:
816 case ir_binop_gequal
:
818 case ir_binop_lequal
:
820 case ir_binop_nequal
:
821 emit(CMP(dst_null_d(), op
[0], op
[1],
822 brw_conditional_for_comparison(expr
->operation
)));
826 assert(!"not reached");
834 resolve_ud_negate(&this->result
);
837 vec4_instruction
*inst
= emit(AND(dst_null_d(),
838 this->result
, src_reg(1)));
839 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
841 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
842 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
847 * Emit a gen6 IF statement with the comparison folded into the IF
851 vec4_visitor::emit_if_gen6(ir_if
*ir
)
853 ir_expression
*expr
= ir
->condition
->as_expression();
859 assert(expr
->get_num_operands() <= 2);
860 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
861 expr
->operands
[i
]->accept(this);
862 op
[i
] = this->result
;
865 switch (expr
->operation
) {
866 case ir_unop_logic_not
:
867 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
870 case ir_binop_logic_xor
:
871 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
874 case ir_binop_logic_or
:
875 temp
= dst_reg(this, glsl_type::bool_type
);
876 emit(OR(temp
, op
[0], op
[1]));
877 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
880 case ir_binop_logic_and
:
881 temp
= dst_reg(this, glsl_type::bool_type
);
882 emit(AND(temp
, op
[0], op
[1]));
883 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
887 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
891 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
894 case ir_binop_greater
:
895 case ir_binop_gequal
:
897 case ir_binop_lequal
:
899 case ir_binop_nequal
:
900 emit(IF(op
[0], op
[1],
901 brw_conditional_for_comparison(expr
->operation
)));
904 case ir_binop_all_equal
:
905 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
906 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
909 case ir_binop_any_nequal
:
910 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
911 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
915 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
916 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
920 assert(!"not reached");
921 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
927 ir
->condition
->accept(this);
929 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
933 vec4_visitor::visit(ir_variable
*ir
)
937 if (variable_storage(ir
))
940 switch (ir
->data
.mode
) {
941 case ir_var_shader_in
:
942 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
945 case ir_var_shader_out
:
946 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
948 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
949 output_reg
[ir
->data
.location
+ i
] = *reg
;
950 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
951 output_reg
[ir
->data
.location
+ i
].type
=
952 brw_type_for_base_type(ir
->type
->get_scalar_type());
953 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
958 case ir_var_temporary
:
959 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
963 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
965 /* Thanks to the lower_ubo_reference pass, we will see only
966 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
967 * variables, so no need for them to be in variable_ht.
969 * Atomic counters take no uniform storage, no need to do
972 if (ir
->is_in_uniform_block() || ir
->type
->contains_atomic())
975 /* Track how big the whole uniform variable is, in case we need to put a
976 * copy of its data into pull constants for array access.
978 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
980 if (!strncmp(ir
->name
, "gl_", 3)) {
981 setup_builtin_uniform_values(ir
);
983 setup_uniform_values(ir
);
987 case ir_var_system_value
:
988 reg
= make_reg_for_system_value(ir
);
992 assert(!"not reached");
995 reg
->type
= brw_type_for_base_type(ir
->type
);
996 hash_table_insert(this->variable_ht
, reg
, ir
);
1000 vec4_visitor::visit(ir_loop
*ir
)
1002 /* We don't want debugging output to print the whole body of the
1003 * loop as the annotation.
1005 this->base_ir
= NULL
;
1007 emit(BRW_OPCODE_DO
);
1009 visit_instructions(&ir
->body_instructions
);
1011 emit(BRW_OPCODE_WHILE
);
1015 vec4_visitor::visit(ir_loop_jump
*ir
)
1018 case ir_loop_jump::jump_break
:
1019 emit(BRW_OPCODE_BREAK
);
1021 case ir_loop_jump::jump_continue
:
1022 emit(BRW_OPCODE_CONTINUE
);
1029 vec4_visitor::visit(ir_function_signature
*ir
)
1036 vec4_visitor::visit(ir_function
*ir
)
1038 /* Ignore function bodies other than main() -- we shouldn't see calls to
1039 * them since they should all be inlined.
1041 if (strcmp(ir
->name
, "main") == 0) {
1042 const ir_function_signature
*sig
;
1045 sig
= ir
->matching_signature(NULL
, &empty
);
1049 visit_instructions(&sig
->body
);
1054 vec4_visitor::try_emit_sat(ir_expression
*ir
)
1056 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
1060 sat_src
->accept(this);
1061 src_reg src
= this->result
;
1063 this->result
= src_reg(this, ir
->type
);
1064 vec4_instruction
*inst
;
1065 inst
= emit(MOV(dst_reg(this->result
), src
));
1066 inst
->saturate
= true;
1072 vec4_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
1074 /* 3-src instructions were introduced in gen6. */
1078 /* MAD can only handle floating-point data. */
1079 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1082 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
1083 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
1085 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1088 nonmul
->accept(this);
1089 src_reg src0
= fix_3src_operand(this->result
);
1091 mul
->operands
[0]->accept(this);
1092 src_reg src1
= fix_3src_operand(this->result
);
1094 mul
->operands
[1]->accept(this);
1095 src_reg src2
= fix_3src_operand(this->result
);
1097 this->result
= src_reg(this, ir
->type
);
1098 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1104 vec4_visitor::emit_bool_comparison(unsigned int op
,
1105 dst_reg dst
, src_reg src0
, src_reg src1
)
1107 /* original gen4 does destination conversion before comparison. */
1109 dst
.type
= src0
.type
;
1111 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
1113 dst
.type
= BRW_REGISTER_TYPE_D
;
1114 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
1118 vec4_visitor::emit_minmax(uint32_t conditionalmod
, dst_reg dst
,
1119 src_reg src0
, src_reg src1
)
1121 vec4_instruction
*inst
;
1123 if (brw
->gen
>= 6) {
1124 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1125 inst
->conditional_mod
= conditionalmod
;
1127 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1129 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1130 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1135 is_16bit_constant(ir_rvalue
*rvalue
)
1137 ir_constant
*constant
= rvalue
->as_constant();
1141 if (constant
->type
!= glsl_type::int_type
&&
1142 constant
->type
!= glsl_type::uint_type
)
1145 return constant
->value
.u
[0] < (1 << 16);
1149 vec4_visitor::visit(ir_expression
*ir
)
1151 unsigned int operand
;
1152 src_reg op
[Elements(ir
->operands
)];
1155 vec4_instruction
*inst
;
1157 if (try_emit_sat(ir
))
1160 if (ir
->operation
== ir_binop_add
) {
1161 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
1165 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1166 this->result
.file
= BAD_FILE
;
1167 ir
->operands
[operand
]->accept(this);
1168 if (this->result
.file
== BAD_FILE
) {
1169 printf("Failed to get tree for expression operand:\n");
1170 ir
->operands
[operand
]->print();
1173 op
[operand
] = this->result
;
1175 /* Matrix expression operands should have been broken down to vector
1176 * operations already.
1178 assert(!ir
->operands
[operand
]->type
->is_matrix());
1181 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1182 if (ir
->operands
[1]) {
1183 vector_elements
= MAX2(vector_elements
,
1184 ir
->operands
[1]->type
->vector_elements
);
1187 this->result
.file
= BAD_FILE
;
1189 /* Storage for our result. Ideally for an assignment we'd be using
1190 * the actual storage for the result here, instead.
1192 result_src
= src_reg(this, ir
->type
);
1193 /* convenience for the emit functions below. */
1194 result_dst
= dst_reg(result_src
);
1195 /* If nothing special happens, this is the result. */
1196 this->result
= result_src
;
1197 /* Limit writes to the channels that will be used by result_src later.
1198 * This does limit this temp's use as a temporary for multi-instruction
1201 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1203 switch (ir
->operation
) {
1204 case ir_unop_logic_not
:
1205 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1206 * ones complement of the whole register, not just bit 0.
1208 emit(XOR(result_dst
, op
[0], src_reg(1)));
1211 op
[0].negate
= !op
[0].negate
;
1212 emit(MOV(result_dst
, op
[0]));
1216 op
[0].negate
= false;
1217 emit(MOV(result_dst
, op
[0]));
1221 if (ir
->type
->is_float()) {
1222 /* AND(val, 0x80000000) gives the sign bit.
1224 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1227 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1229 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1230 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1231 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1233 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1234 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1236 this->result
.type
= BRW_REGISTER_TYPE_F
;
1238 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1239 * -> non-negative val generates 0x00000000.
1240 * Predicated OR sets 1 if val is positive.
1242 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1244 emit(ASR(result_dst
, op
[0], src_reg(31)));
1246 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1247 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1252 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1256 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1259 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1263 assert(!"not reached: should be handled by ir_explog_to_explog2");
1266 case ir_unop_sin_reduced
:
1267 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1270 case ir_unop_cos_reduced
:
1271 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1276 assert(!"derivatives not valid in vertex shader");
1279 case ir_unop_bitfield_reverse
:
1280 emit(BFREV(result_dst
, op
[0]));
1282 case ir_unop_bit_count
:
1283 emit(CBIT(result_dst
, op
[0]));
1285 case ir_unop_find_msb
: {
1286 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1288 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1289 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1291 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1292 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1293 * subtract the result from 31 to convert the MSB count into an LSB count.
1296 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1297 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1298 emit(MOV(result_dst
, temp
));
1300 src_reg src_tmp
= src_reg(result_dst
);
1301 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1303 src_tmp
.negate
= true;
1304 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1305 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1308 case ir_unop_find_lsb
:
1309 emit(FBL(result_dst
, op
[0]));
1313 assert(!"not reached: should be handled by lower_noise");
1317 emit(ADD(result_dst
, op
[0], op
[1]));
1320 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1324 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
1325 /* For integer multiplication, the MUL uses the low 16 bits of one of
1326 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1327 * accumulates in the contribution of the upper 16 bits of that
1328 * operand. If we can determine that one of the args is in the low
1329 * 16 bits, though, we can just emit a single MUL.
1331 if (is_16bit_constant(ir
->operands
[0])) {
1333 emit(MUL(result_dst
, op
[0], op
[1]));
1335 emit(MUL(result_dst
, op
[1], op
[0]));
1336 } else if (is_16bit_constant(ir
->operands
[1])) {
1338 emit(MUL(result_dst
, op
[1], op
[0]));
1340 emit(MUL(result_dst
, op
[0], op
[1]));
1342 struct brw_reg acc
= retype(brw_acc_reg(), result_dst
.type
);
1344 emit(MUL(acc
, op
[0], op
[1]));
1345 emit(MACH(dst_null_d(), op
[0], op
[1]));
1346 emit(MOV(result_dst
, src_reg(acc
)));
1349 emit(MUL(result_dst
, op
[0], op
[1]));
1352 case ir_binop_imul_high
: {
1353 struct brw_reg acc
= retype(brw_acc_reg(), result_dst
.type
);
1355 emit(MUL(acc
, op
[0], op
[1]));
1356 emit(MACH(result_dst
, op
[0], op
[1]));
1360 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1361 assert(ir
->type
->is_integer());
1362 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1364 case ir_binop_carry
: {
1365 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
1367 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1368 emit(MOV(result_dst
, src_reg(acc
)));
1371 case ir_binop_borrow
: {
1372 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
1374 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1375 emit(MOV(result_dst
, src_reg(acc
)));
1379 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1380 assert(ir
->type
->is_integer());
1381 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1385 case ir_binop_greater
:
1386 case ir_binop_lequal
:
1387 case ir_binop_gequal
:
1388 case ir_binop_equal
:
1389 case ir_binop_nequal
: {
1390 emit(CMP(result_dst
, op
[0], op
[1],
1391 brw_conditional_for_comparison(ir
->operation
)));
1392 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1396 case ir_binop_all_equal
:
1397 /* "==" operator producing a scalar boolean. */
1398 if (ir
->operands
[0]->type
->is_vector() ||
1399 ir
->operands
[1]->type
->is_vector()) {
1400 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1401 emit(MOV(result_dst
, src_reg(0)));
1402 inst
= emit(MOV(result_dst
, src_reg(1)));
1403 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1405 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1406 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1409 case ir_binop_any_nequal
:
1410 /* "!=" operator producing a scalar boolean. */
1411 if (ir
->operands
[0]->type
->is_vector() ||
1412 ir
->operands
[1]->type
->is_vector()) {
1413 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1415 emit(MOV(result_dst
, src_reg(0)));
1416 inst
= emit(MOV(result_dst
, src_reg(1)));
1417 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1419 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1420 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1425 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1426 emit(MOV(result_dst
, src_reg(0)));
1428 inst
= emit(MOV(result_dst
, src_reg(1)));
1429 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1432 case ir_binop_logic_xor
:
1433 emit(XOR(result_dst
, op
[0], op
[1]));
1436 case ir_binop_logic_or
:
1437 emit(OR(result_dst
, op
[0], op
[1]));
1440 case ir_binop_logic_and
:
1441 emit(AND(result_dst
, op
[0], op
[1]));
1445 assert(ir
->operands
[0]->type
->is_vector());
1446 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1447 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1451 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1454 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1457 case ir_unop_bitcast_i2f
:
1458 case ir_unop_bitcast_u2f
:
1459 this->result
= op
[0];
1460 this->result
.type
= BRW_REGISTER_TYPE_F
;
1463 case ir_unop_bitcast_f2i
:
1464 this->result
= op
[0];
1465 this->result
.type
= BRW_REGISTER_TYPE_D
;
1468 case ir_unop_bitcast_f2u
:
1469 this->result
= op
[0];
1470 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1481 emit(MOV(result_dst
, op
[0]));
1485 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1486 emit(AND(result_dst
, result_src
, src_reg(1)));
1491 emit(RNDZ(result_dst
, op
[0]));
1494 op
[0].negate
= !op
[0].negate
;
1495 inst
= emit(RNDD(result_dst
, op
[0]));
1496 this->result
.negate
= true;
1499 inst
= emit(RNDD(result_dst
, op
[0]));
1502 inst
= emit(FRC(result_dst
, op
[0]));
1504 case ir_unop_round_even
:
1505 emit(RNDE(result_dst
, op
[0]));
1509 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1512 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1516 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1519 case ir_unop_bit_not
:
1520 inst
= emit(NOT(result_dst
, op
[0]));
1522 case ir_binop_bit_and
:
1523 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1525 case ir_binop_bit_xor
:
1526 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1528 case ir_binop_bit_or
:
1529 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1532 case ir_binop_lshift
:
1533 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1536 case ir_binop_rshift
:
1537 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1538 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1540 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1544 emit(BFI1(result_dst
, op
[0], op
[1]));
1547 case ir_binop_ubo_load
: {
1548 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
1549 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1550 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1553 /* Now, load the vector from that offset. */
1554 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1556 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1557 packed_consts
.type
= result
.type
;
1558 src_reg surf_index
=
1559 src_reg(prog_data
->base
.binding_table
.ubo_start
+ uniform_block
->value
.u
[0]);
1560 if (const_offset_ir
) {
1561 if (brw
->gen
>= 8) {
1562 /* Store the offset in a GRF so we can send-from-GRF. */
1563 offset
= src_reg(this, glsl_type::int_type
);
1564 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1566 /* Immediates are fine on older generations since they'll be moved
1567 * to a (potentially fake) MRF at the generator level.
1569 offset
= src_reg(const_offset
/ 16);
1572 offset
= src_reg(this, glsl_type::uint_type
);
1573 emit(SHR(dst_reg(offset
), op
[1], src_reg(4)));
1576 if (brw
->gen
>= 7) {
1577 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1578 grf_offset
.type
= offset
.type
;
1580 emit(MOV(grf_offset
, offset
));
1582 emit(new(mem_ctx
) vec4_instruction(this,
1583 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1584 dst_reg(packed_consts
),
1586 src_reg(grf_offset
)));
1588 vec4_instruction
*pull
=
1589 emit(new(mem_ctx
) vec4_instruction(this,
1590 VS_OPCODE_PULL_CONSTANT_LOAD
,
1591 dst_reg(packed_consts
),
1594 pull
->base_mrf
= 14;
1598 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1599 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1600 const_offset
% 16 / 4,
1601 const_offset
% 16 / 4,
1602 const_offset
% 16 / 4);
1604 /* UBO bools are any nonzero int. We store bools as either 0 or 1. */
1605 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1606 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1607 BRW_CONDITIONAL_NZ
));
1608 emit(AND(result_dst
, result
, src_reg(0x1)));
1610 emit(MOV(result_dst
, packed_consts
));
1615 case ir_binop_vector_extract
:
1616 assert(!"should have been lowered by vec_index_to_cond_assign");
1620 op
[0] = fix_3src_operand(op
[0]);
1621 op
[1] = fix_3src_operand(op
[1]);
1622 op
[2] = fix_3src_operand(op
[2]);
1623 /* Note that the instruction's argument order is reversed from GLSL
1626 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1630 op
[0] = fix_3src_operand(op
[0]);
1631 op
[1] = fix_3src_operand(op
[1]);
1632 op
[2] = fix_3src_operand(op
[2]);
1633 /* Note that the instruction's argument order is reversed from GLSL
1636 emit(LRP(result_dst
, op
[2], op
[1], op
[0]));
1640 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1641 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1642 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1646 op
[0] = fix_3src_operand(op
[0]);
1647 op
[1] = fix_3src_operand(op
[1]);
1648 op
[2] = fix_3src_operand(op
[2]);
1649 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1652 case ir_triop_bitfield_extract
:
1653 op
[0] = fix_3src_operand(op
[0]);
1654 op
[1] = fix_3src_operand(op
[1]);
1655 op
[2] = fix_3src_operand(op
[2]);
1656 /* Note that the instruction's argument order is reversed from GLSL
1659 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1662 case ir_triop_vector_insert
:
1663 assert(!"should have been lowered by lower_vector_insert");
1666 case ir_quadop_bitfield_insert
:
1667 assert(!"not reached: should be handled by "
1668 "bitfield_insert_to_bfm_bfi\n");
1671 case ir_quadop_vector
:
1672 assert(!"not reached: should be handled by lower_quadop_vector");
1675 case ir_unop_pack_half_2x16
:
1676 emit_pack_half_2x16(result_dst
, op
[0]);
1678 case ir_unop_unpack_half_2x16
:
1679 emit_unpack_half_2x16(result_dst
, op
[0]);
1681 case ir_unop_pack_snorm_2x16
:
1682 case ir_unop_pack_snorm_4x8
:
1683 case ir_unop_pack_unorm_2x16
:
1684 case ir_unop_pack_unorm_4x8
:
1685 case ir_unop_unpack_snorm_2x16
:
1686 case ir_unop_unpack_snorm_4x8
:
1687 case ir_unop_unpack_unorm_2x16
:
1688 case ir_unop_unpack_unorm_4x8
:
1689 assert(!"not reached: should be handled by lower_packing_builtins");
1691 case ir_unop_unpack_half_2x16_split_x
:
1692 case ir_unop_unpack_half_2x16_split_y
:
1693 case ir_binop_pack_half_2x16_split
:
1694 assert(!"not reached: should not occur in vertex shader");
1696 case ir_binop_ldexp
:
1697 assert(!"not reached: should be handled by ldexp_to_arith()");
1704 vec4_visitor::visit(ir_swizzle
*ir
)
1710 /* Note that this is only swizzles in expressions, not those on the left
1711 * hand side of an assignment, which do write masking. See ir_assignment
1715 ir
->val
->accept(this);
1717 assert(src
.file
!= BAD_FILE
);
1719 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1722 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1725 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1728 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1731 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1735 for (; i
< 4; i
++) {
1736 /* Replicate the last channel out. */
1737 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1740 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1746 vec4_visitor::visit(ir_dereference_variable
*ir
)
1748 const struct glsl_type
*type
= ir
->type
;
1749 dst_reg
*reg
= variable_storage(ir
->var
);
1752 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1753 this->result
= src_reg(brw_null_reg());
1757 this->result
= src_reg(*reg
);
1759 /* System values get their swizzle from the dst_reg writemask */
1760 if (ir
->var
->data
.mode
== ir_var_system_value
)
1763 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1764 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1769 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1771 /* Under normal circumstances array elements are stored consecutively, so
1772 * the stride is equal to the size of the array element.
1774 return type_size(ir
->type
);
1779 vec4_visitor::visit(ir_dereference_array
*ir
)
1781 ir_constant
*constant_index
;
1783 int array_stride
= compute_array_stride(ir
);
1785 constant_index
= ir
->array_index
->constant_expression_value();
1787 ir
->array
->accept(this);
1790 if (constant_index
) {
1791 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1793 /* Variable index array dereference. It eats the "vec4" of the
1794 * base of the array and an index that offsets the Mesa register
1797 ir
->array_index
->accept(this);
1801 if (array_stride
== 1) {
1802 index_reg
= this->result
;
1804 index_reg
= src_reg(this, glsl_type::int_type
);
1806 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1810 src_reg temp
= src_reg(this, glsl_type::int_type
);
1812 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1817 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1818 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1821 /* If the type is smaller than a vec4, replicate the last channel out. */
1822 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1823 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1825 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1826 src
.type
= brw_type_for_base_type(ir
->type
);
1832 vec4_visitor::visit(ir_dereference_record
*ir
)
1835 const glsl_type
*struct_type
= ir
->record
->type
;
1838 ir
->record
->accept(this);
1840 for (i
= 0; i
< struct_type
->length
; i
++) {
1841 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1843 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1846 /* If the type is smaller than a vec4, replicate the last channel out. */
1847 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1848 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1850 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1851 this->result
.type
= brw_type_for_base_type(ir
->type
);
1853 this->result
.reg_offset
+= offset
;
1857 * We want to be careful in assignment setup to hit the actual storage
1858 * instead of potentially using a temporary like we might with the
1859 * ir_dereference handler.
1862 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1864 /* The LHS must be a dereference. If the LHS is a variable indexed array
1865 * access of a vector, it must be separated into a series conditional moves
1866 * before reaching this point (see ir_vec_index_to_cond_assign).
1868 assert(ir
->as_dereference());
1869 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1871 assert(!deref_array
->array
->type
->is_vector());
1874 /* Use the rvalue deref handler for the most part. We'll ignore
1875 * swizzles in it and write swizzles using writemask, though.
1878 return dst_reg(v
->result
);
1882 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1883 const struct glsl_type
*type
, uint32_t predicate
)
1885 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1886 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1887 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1892 if (type
->is_array()) {
1893 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1894 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1899 if (type
->is_matrix()) {
1900 const struct glsl_type
*vec_type
;
1902 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1903 type
->vector_elements
, 1);
1905 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1906 emit_block_move(dst
, src
, vec_type
, predicate
);
1911 assert(type
->is_scalar() || type
->is_vector());
1913 dst
->type
= brw_type_for_base_type(type
);
1914 src
->type
= dst
->type
;
1916 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1918 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1920 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1921 inst
->predicate
= predicate
;
1928 /* If the RHS processing resulted in an instruction generating a
1929 * temporary value, and it would be easy to rewrite the instruction to
1930 * generate its result right into the LHS instead, do so. This ends
1931 * up reliably removing instructions where it can be tricky to do so
1932 * later without real UD chain information.
1935 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1938 vec4_instruction
*pre_rhs_inst
,
1939 vec4_instruction
*last_rhs_inst
)
1941 /* This could be supported, but it would take more smarts. */
1945 if (pre_rhs_inst
== last_rhs_inst
)
1946 return false; /* No instructions generated to work with. */
1948 /* Make sure the last instruction generated our source reg. */
1949 if (src
.file
!= GRF
||
1950 src
.file
!= last_rhs_inst
->dst
.file
||
1951 src
.reg
!= last_rhs_inst
->dst
.reg
||
1952 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1956 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1959 /* Check that that last instruction fully initialized the channels
1960 * we want to use, in the order we want to use them. We could
1961 * potentially reswizzle the operands of many instructions so that
1962 * we could handle out of order channels, but don't yet.
1965 for (unsigned i
= 0; i
< 4; i
++) {
1966 if (dst
.writemask
& (1 << i
)) {
1967 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1970 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1975 /* Success! Rewrite the instruction. */
1976 last_rhs_inst
->dst
.file
= dst
.file
;
1977 last_rhs_inst
->dst
.reg
= dst
.reg
;
1978 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1979 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1980 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1986 vec4_visitor::visit(ir_assignment
*ir
)
1988 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1989 uint32_t predicate
= BRW_PREDICATE_NONE
;
1991 if (!ir
->lhs
->type
->is_scalar() &&
1992 !ir
->lhs
->type
->is_vector()) {
1993 ir
->rhs
->accept(this);
1994 src_reg src
= this->result
;
1996 if (ir
->condition
) {
1997 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2000 /* emit_block_move doesn't account for swizzles in the source register.
2001 * This should be ok, since the source register is a structure or an
2002 * array, and those can't be swizzled. But double-check to be sure.
2004 assert(src
.swizzle
==
2005 (ir
->rhs
->type
->is_matrix()
2006 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2007 : BRW_SWIZZLE_NOOP
));
2009 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2013 /* Now we're down to just a scalar/vector with writemasks. */
2016 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2017 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2019 ir
->rhs
->accept(this);
2021 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2023 src_reg src
= this->result
;
2026 int first_enabled_chan
= 0;
2029 assert(ir
->lhs
->type
->is_vector() ||
2030 ir
->lhs
->type
->is_scalar());
2031 dst
.writemask
= ir
->write_mask
;
2033 for (int i
= 0; i
< 4; i
++) {
2034 if (dst
.writemask
& (1 << i
)) {
2035 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2040 /* Swizzle a small RHS vector into the channels being written.
2042 * glsl ir treats write_mask as dictating how many channels are
2043 * present on the RHS while in our instructions we need to make
2044 * those channels appear in the slots of the vec4 they're written to.
2046 for (int i
= 0; i
< 4; i
++) {
2047 if (dst
.writemask
& (1 << i
))
2048 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2050 swizzles
[i
] = first_enabled_chan
;
2052 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2053 swizzles
[2], swizzles
[3]);
2055 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2059 if (ir
->condition
) {
2060 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2063 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2064 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2065 inst
->predicate
= predicate
;
2073 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2075 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2076 foreach_list(node
, &ir
->components
) {
2077 ir_constant
*field_value
= (ir_constant
*)node
;
2079 emit_constant_values(dst
, field_value
);
2084 if (ir
->type
->is_array()) {
2085 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2086 emit_constant_values(dst
, ir
->array_elements
[i
]);
2091 if (ir
->type
->is_matrix()) {
2092 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2093 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2095 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2096 dst
->writemask
= 1 << j
;
2097 dst
->type
= BRW_REGISTER_TYPE_F
;
2099 emit(MOV(*dst
, src_reg(vec
[j
])));
2106 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2108 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2109 if (!(remaining_writemask
& (1 << i
)))
2112 dst
->writemask
= 1 << i
;
2113 dst
->type
= brw_type_for_base_type(ir
->type
);
2115 /* Find other components that match the one we're about to
2116 * write. Emits fewer instructions for things like vec4(0.5,
2119 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2120 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2121 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2122 dst
->writemask
|= (1 << j
);
2124 /* u, i, and f storage all line up, so no need for a
2125 * switch case for comparing each type.
2127 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2128 dst
->writemask
|= (1 << j
);
2132 switch (ir
->type
->base_type
) {
2133 case GLSL_TYPE_FLOAT
:
2134 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2137 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2139 case GLSL_TYPE_UINT
:
2140 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2142 case GLSL_TYPE_BOOL
:
2143 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
2146 assert(!"Non-float/uint/int/bool constant");
2150 remaining_writemask
&= ~dst
->writemask
;
2156 vec4_visitor::visit(ir_constant
*ir
)
2158 dst_reg dst
= dst_reg(this, ir
->type
);
2159 this->result
= src_reg(dst
);
2161 emit_constant_values(&dst
, ir
);
2165 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2167 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2168 ir
->actual_parameters
.get_head());
2169 ir_variable
*location
= deref
->variable_referenced();
2170 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2171 location
->data
.atomic
.buffer_index
);
2173 /* Calculate the surface offset */
2174 src_reg
offset(this, glsl_type::uint_type
);
2175 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2177 deref_array
->array_index
->accept(this);
2179 src_reg
tmp(this, glsl_type::uint_type
);
2180 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2181 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2183 offset
= location
->data
.atomic
.offset
;
2186 /* Emit the appropriate machine instruction */
2187 const char *callee
= ir
->callee
->function_name();
2188 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2190 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2191 emit_untyped_surface_read(surf_index
, dst
, offset
);
2193 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2194 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2195 src_reg(), src_reg());
2197 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2198 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2199 src_reg(), src_reg());
2204 vec4_visitor::visit(ir_call
*ir
)
2206 const char *callee
= ir
->callee
->function_name();
2208 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2209 !strcmp("__intrinsic_atomic_increment", callee
) ||
2210 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2211 visit_atomic_counter_intrinsic(ir
);
2213 assert(!"Unsupported intrinsic.");
2218 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, int sampler
)
2220 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_MCS
);
2223 inst
->sampler
= sampler
;
2224 inst
->dst
= dst_reg(this, glsl_type::uvec4_type
);
2225 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2227 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2228 int param_base
= inst
->base_mrf
;
2229 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2230 int zero_mask
= 0xf & ~coord_mask
;
2232 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2235 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2239 return src_reg(inst
->dst
);
2243 vec4_visitor::visit(ir_texture
*ir
)
2246 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2248 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2249 * emitting anything other than setting up the constant result.
2251 if (ir
->op
== ir_tg4
) {
2252 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2253 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2254 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2255 dst_reg
result(this, ir
->type
);
2256 this->result
= src_reg(result
);
2257 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2262 /* Should be lowered by do_lower_texture_projection */
2263 assert(!ir
->projector
);
2265 /* Should be lowered */
2266 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2268 /* Generate code to compute all the subexpression trees. This has to be
2269 * done before loading any values into MRFs for the sampler message since
2270 * generating these values may involve SEND messages that need the MRFs.
2273 if (ir
->coordinate
) {
2274 ir
->coordinate
->accept(this);
2275 coordinate
= this->result
;
2278 src_reg shadow_comparitor
;
2279 if (ir
->shadow_comparitor
) {
2280 ir
->shadow_comparitor
->accept(this);
2281 shadow_comparitor
= this->result
;
2284 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2285 src_reg offset_value
;
2286 if (has_nonconstant_offset
) {
2287 ir
->offset
->accept(this);
2288 offset_value
= src_reg(this->result
);
2291 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2292 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2295 lod
= src_reg(0.0f
);
2296 lod_type
= glsl_type::float_type
;
2301 ir
->lod_info
.lod
->accept(this);
2303 lod_type
= ir
->lod_info
.lod
->type
;
2305 case ir_query_levels
:
2307 lod_type
= glsl_type::int_type
;
2310 ir
->lod_info
.sample_index
->accept(this);
2311 sample_index
= this->result
;
2312 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2314 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2315 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler
);
2320 ir
->lod_info
.grad
.dPdx
->accept(this);
2321 dPdx
= this->result
;
2323 ir
->lod_info
.grad
.dPdy
->accept(this);
2324 dPdy
= this->result
;
2326 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2334 vec4_instruction
*inst
= NULL
;
2338 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXL
);
2341 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXD
);
2344 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF
);
2347 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_CMS
);
2350 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
2353 if (has_nonconstant_offset
)
2354 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TG4_OFFSET
);
2356 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TG4
);
2358 case ir_query_levels
:
2359 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
2362 assert(!"TXB is not valid for vertex shaders.");
2365 assert(!"LOD is not valid for vertex shaders.");
2368 assert(!"Unrecognized tex op");
2371 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
2372 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
2374 /* Stuff the channel select bits in the top of the texture offset */
2375 if (ir
->op
== ir_tg4
)
2376 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16;
2378 /* The message header is necessary for:
2381 * - Gather channel selection
2382 * - Sampler indices too large to fit in a 4-bit value.
2384 inst
->header_present
=
2385 brw
->gen
< 5 || inst
->texture_offset
!= 0 || ir
->op
== ir_tg4
||
2388 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2389 inst
->sampler
= sampler
;
2390 inst
->dst
= dst_reg(this, ir
->type
);
2391 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2392 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2394 /* MRF for the first parameter */
2395 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2397 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2398 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2399 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2401 /* Load the coordinate */
2402 /* FINISHME: gl_clamp_mask and saturate */
2403 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2404 int zero_mask
= 0xf & ~coord_mask
;
2406 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2409 if (zero_mask
!= 0) {
2410 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2413 /* Load the shadow comparitor */
2414 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2415 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2417 shadow_comparitor
));
2421 /* Load the LOD info */
2422 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2424 if (brw
->gen
>= 5) {
2425 mrf
= param_base
+ 1;
2426 if (ir
->shadow_comparitor
) {
2427 writemask
= WRITEMASK_Y
;
2428 /* mlen already incremented */
2430 writemask
= WRITEMASK_X
;
2433 } else /* brw->gen == 4 */ {
2435 writemask
= WRITEMASK_W
;
2437 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2438 } else if (ir
->op
== ir_txf
) {
2439 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2440 } else if (ir
->op
== ir_txf_ms
) {
2441 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2444 /* MCS data is in the first channel of `mcs`, but we need to get it into
2445 * the .y channel of the second vec4 of params, so replicate .x across
2446 * the whole vec4 and then mask off everything except .y
2448 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2449 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2452 } else if (ir
->op
== ir_txd
) {
2453 const glsl_type
*type
= lod_type
;
2455 if (brw
->gen
>= 5) {
2456 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2457 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2458 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2459 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2462 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2463 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2464 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2465 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2466 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2469 if (ir
->shadow_comparitor
) {
2470 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2471 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2472 shadow_comparitor
));
2475 } else /* brw->gen == 4 */ {
2476 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2477 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2480 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2481 if (ir
->shadow_comparitor
) {
2482 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2483 shadow_comparitor
));
2486 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2494 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2495 * spec requires layers.
2497 if (ir
->op
== ir_txs
) {
2498 glsl_type
const *type
= ir
->sampler
->type
;
2499 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2500 type
->sampler_array
) {
2501 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2502 writemask(inst
->dst
, WRITEMASK_Z
),
2503 src_reg(inst
->dst
), src_reg(6));
2507 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2508 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2511 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2515 * Apply workarounds for Gen6 gather with UINT/SINT
2518 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2523 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2524 dst_reg dst_f
= dst
;
2525 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2527 /* Convert from UNORM to UINT */
2528 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2529 emit(MOV(dst
, src_reg(dst_f
)));
2532 /* Reinterpret the UINT value as a signed INT value by
2533 * shifting the sign bit into place, then shifting back
2536 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2537 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2542 * Set up the gather channel based on the swizzle, for gather4.
2545 vec4_visitor::gather_channel(ir_texture
*ir
, int sampler
)
2547 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2548 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2550 case SWIZZLE_X
: return 0;
2552 /* gather4 sampler is broken for green channel on RG32F --
2553 * we must ask for blue instead.
2555 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2558 case SWIZZLE_Z
: return 2;
2559 case SWIZZLE_W
: return 3;
2561 assert(!"Not reached"); /* zero, one swizzles handled already */
2567 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
)
2569 int s
= key
->tex
.swizzles
[sampler
];
2571 this->result
= src_reg(this, ir
->type
);
2572 dst_reg
swizzled_result(this->result
);
2574 if (ir
->op
== ir_query_levels
) {
2575 /* # levels is in .w */
2576 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2577 emit(MOV(swizzled_result
, orig_val
));
2581 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2582 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2583 emit(MOV(swizzled_result
, orig_val
));
2588 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2589 int swizzle
[4] = {0};
2591 for (int i
= 0; i
< 4; i
++) {
2592 switch (GET_SWZ(s
, i
)) {
2594 zero_mask
|= (1 << i
);
2597 one_mask
|= (1 << i
);
2600 copy_mask
|= (1 << i
);
2601 swizzle
[i
] = GET_SWZ(s
, i
);
2607 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2608 swizzled_result
.writemask
= copy_mask
;
2609 emit(MOV(swizzled_result
, orig_val
));
2613 swizzled_result
.writemask
= zero_mask
;
2614 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2618 swizzled_result
.writemask
= one_mask
;
2619 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2624 vec4_visitor::visit(ir_return
*ir
)
2626 assert(!"not reached");
2630 vec4_visitor::visit(ir_discard
*ir
)
2632 assert(!"not reached");
2636 vec4_visitor::visit(ir_if
*ir
)
2638 /* Don't point the annotation at the if statement, because then it plus
2639 * the then and else blocks get printed.
2641 this->base_ir
= ir
->condition
;
2643 if (brw
->gen
== 6) {
2647 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2648 emit(IF(predicate
));
2651 visit_instructions(&ir
->then_instructions
);
2653 if (!ir
->else_instructions
.is_empty()) {
2654 this->base_ir
= ir
->condition
;
2655 emit(BRW_OPCODE_ELSE
);
2657 visit_instructions(&ir
->else_instructions
);
2660 this->base_ir
= ir
->condition
;
2661 emit(BRW_OPCODE_ENDIF
);
2665 vec4_visitor::visit(ir_emit_vertex
*)
2667 assert(!"not reached");
2671 vec4_visitor::visit(ir_end_primitive
*)
2673 assert(!"not reached");
2677 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2678 dst_reg dst
, src_reg offset
,
2679 src_reg src0
, src_reg src1
)
2683 /* Set the atomic operation offset. */
2684 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2687 /* Set the atomic operation arguments. */
2688 if (src0
.file
!= BAD_FILE
) {
2689 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2693 if (src1
.file
!= BAD_FILE
) {
2694 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2698 /* Emit the instruction. Note that this maps to the normal SIMD8
2699 * untyped atomic message on Ivy Bridge, but that's OK because
2700 * unused channels will be masked out.
2702 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2703 src_reg(atomic_op
), src_reg(surf_index
));
2709 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
2712 /* Set the surface read offset. */
2713 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
2715 /* Emit the instruction. Note that this maps to the normal SIMD8
2716 * untyped surface read message, but that's OK because unused
2717 * channels will be masked out.
2719 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
,
2720 dst
, src_reg(surf_index
));
2726 vec4_visitor::emit_ndc_computation()
2728 /* Get the position */
2729 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2731 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2732 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2733 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2735 current_annotation
= "NDC";
2736 dst_reg ndc_w
= ndc
;
2737 ndc_w
.writemask
= WRITEMASK_W
;
2738 src_reg pos_w
= pos
;
2739 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2740 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2742 dst_reg ndc_xyz
= ndc
;
2743 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2745 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2749 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
2752 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2753 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2754 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2755 dst_reg header1_w
= header1
;
2756 header1_w
.writemask
= WRITEMASK_W
;
2758 emit(MOV(header1
, 0u));
2760 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2761 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2763 current_annotation
= "Point size";
2764 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2765 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2768 if (key
->userclip_active
) {
2769 current_annotation
= "Clipping flags";
2770 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
2771 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
2773 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2774 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
2775 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
2777 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2778 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
2779 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
2780 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
2783 /* i965 clipping workaround:
2784 * 1) Test for -ve rhw
2786 * set ndc = (0,0,0,0)
2789 * Later, clipping will detect ucp[6] and ensure the primitive is
2790 * clipped against all fixed planes.
2792 if (brw
->has_negative_rhw_bug
) {
2793 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2794 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2795 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2796 vec4_instruction
*inst
;
2797 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2798 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2799 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
2800 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2803 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2804 } else if (brw
->gen
< 6) {
2805 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2807 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2808 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2809 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
2810 src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
2812 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
2813 emit(MOV(retype(brw_writemask(reg
, WRITEMASK_Y
), BRW_REGISTER_TYPE_D
),
2814 src_reg(output_reg
[VARYING_SLOT_LAYER
])));
2816 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
2817 emit(MOV(retype(brw_writemask(reg
, WRITEMASK_Z
), BRW_REGISTER_TYPE_D
),
2818 src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
2824 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
2826 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2828 * "If a linked set of shaders forming the vertex stage contains no
2829 * static write to gl_ClipVertex or gl_ClipDistance, but the
2830 * application has requested clipping against user clip planes through
2831 * the API, then the coordinate written to gl_Position is used for
2832 * comparison against the user clip planes."
2834 * This function is only called if the shader didn't write to
2835 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2836 * if the user wrote to it; otherwise we use gl_Position.
2838 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
2839 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
2840 clip_vertex
= VARYING_SLOT_POS
;
2843 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
2845 reg
.writemask
= 1 << i
;
2847 src_reg(output_reg
[clip_vertex
]),
2848 src_reg(this->userplane
[i
+ offset
])));
2853 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
2855 assert (varying
< VARYING_SLOT_MAX
);
2856 reg
.type
= output_reg
[varying
].type
;
2857 current_annotation
= output_reg_annotation
[varying
];
2858 /* Copy the register, saturating if necessary */
2859 vec4_instruction
*inst
= emit(MOV(reg
,
2860 src_reg(output_reg
[varying
])));
2861 if ((varying
== VARYING_SLOT_COL0
||
2862 varying
== VARYING_SLOT_COL1
||
2863 varying
== VARYING_SLOT_BFC0
||
2864 varying
== VARYING_SLOT_BFC1
) &&
2865 key
->clamp_vertex_color
) {
2866 inst
->saturate
= true;
2871 vec4_visitor::emit_urb_slot(int mrf
, int varying
)
2873 struct brw_reg hw_reg
= brw_message_reg(mrf
);
2874 dst_reg reg
= dst_reg(MRF
, mrf
);
2875 reg
.type
= BRW_REGISTER_TYPE_F
;
2878 case VARYING_SLOT_PSIZ
:
2879 /* PSIZ is always in slot 0, and is coupled with other flags. */
2880 current_annotation
= "indices, point width, clip flags";
2881 emit_psiz_and_flags(hw_reg
);
2883 case BRW_VARYING_SLOT_NDC
:
2884 current_annotation
= "NDC";
2885 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
2887 case VARYING_SLOT_POS
:
2888 current_annotation
= "gl_Position";
2889 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
2891 case VARYING_SLOT_EDGE
:
2892 /* This is present when doing unfilled polygons. We're supposed to copy
2893 * the edge flag from the user-provided vertex array
2894 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
2895 * of that attribute (starts as 1.0f). This is then used in clipping to
2896 * determine which edges should be drawn as wireframe.
2898 current_annotation
= "edge flag";
2899 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
2900 glsl_type::float_type
, WRITEMASK_XYZW
))));
2902 case BRW_VARYING_SLOT_PAD
:
2903 /* No need to write to this slot */
2906 emit_generic_urb_slot(reg
, varying
);
2912 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
2914 if (brw
->gen
>= 6) {
2915 /* URB data written (does not include the message header reg) must
2916 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
2917 * section 5.4.3.2.2: URB_INTERLEAVED.
2919 * URB entries are allocated on a multiple of 1024 bits, so an
2920 * extra 128 bits written here to make the end align to 256 is
2923 if ((mlen
% 2) != 1)
2932 * Generates the VUE payload plus the necessary URB write instructions to
2935 * The VUE layout is documented in Volume 2a.
2938 vec4_visitor::emit_vertex()
2940 /* MRF 0 is reserved for the debugger, so start with message header
2945 /* In the process of generating our URB write message contents, we
2946 * may need to unspill a register or load from an array. Those
2947 * reads would use MRFs 14-15.
2949 int max_usable_mrf
= 13;
2951 /* The following assertion verifies that max_usable_mrf causes an
2952 * even-numbered amount of URB write data, which will meet gen6's
2953 * requirements for length alignment.
2955 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
2957 /* First mrf is the g0-based message header containing URB handles and
2960 emit_urb_write_header(mrf
++);
2963 emit_ndc_computation();
2966 /* Lower legacy ff and ClipVertex clipping to clip distances */
2967 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
2968 current_annotation
= "user clip distances";
2970 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
2971 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
2973 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
2974 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
2977 /* We may need to split this up into several URB writes, so do them in a
2981 bool complete
= false;
2983 /* URB offset is in URB row increments, and each of our MRFs is half of
2984 * one of those, since we're doing interleaved writes.
2986 int offset
= slot
/ 2;
2989 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
2990 emit_urb_slot(mrf
++, prog_data
->vue_map
.slot_to_varying
[slot
]);
2992 /* If this was max_usable_mrf, we can't fit anything more into this
2995 if (mrf
> max_usable_mrf
) {
3001 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3002 current_annotation
= "URB write";
3003 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3004 inst
->base_mrf
= base_mrf
;
3005 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
3006 inst
->offset
+= offset
;
3012 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
3013 src_reg
*reladdr
, int reg_offset
)
3015 /* Because we store the values to scratch interleaved like our
3016 * vertex data, we need to scale the vec4 index by 2.
3018 int message_header_scale
= 2;
3020 /* Pre-gen6, the message header uses byte offsets instead of vec4
3021 * (16-byte) offset units.
3024 message_header_scale
*= 16;
3027 src_reg index
= src_reg(this, glsl_type::int_type
);
3029 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
3030 emit_before(inst
, MUL(dst_reg(index
),
3031 index
, src_reg(message_header_scale
)));
3035 return src_reg(reg_offset
* message_header_scale
);
3040 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
3041 src_reg
*reladdr
, int reg_offset
)
3044 src_reg index
= src_reg(this, glsl_type::int_type
);
3046 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
3048 /* Pre-gen6, the message header uses byte offsets instead of vec4
3049 * (16-byte) offset units.
3052 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3056 } else if (brw
->gen
>= 8) {
3057 /* Store the offset in a GRF so we can send-from-GRF. */
3058 src_reg offset
= src_reg(this, glsl_type::int_type
);
3059 emit_before(inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3062 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
3063 return src_reg(reg_offset
* message_header_scale
);
3068 * Emits an instruction before @inst to load the value named by @orig_src
3069 * from scratch space at @base_offset to @temp.
3071 * @base_offset is measured in 32-byte units (the size of a register).
3074 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
3075 dst_reg temp
, src_reg orig_src
,
3078 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3079 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
3081 emit_before(inst
, SCRATCH_READ(temp
, index
));
3085 * Emits an instruction after @inst to store the value to be written
3086 * to @orig_dst to scratch space at @base_offset, from @temp.
3088 * @base_offset is measured in 32-byte units (the size of a register).
3091 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
, int base_offset
)
3093 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3094 src_reg index
= get_scratch_offset(inst
, inst
->dst
.reladdr
, reg_offset
);
3096 /* Create a temporary register to store *inst's result in.
3098 * We have to be careful in MOVing from our temporary result register in
3099 * the scratch write. If we swizzle from channels of the temporary that
3100 * weren't initialized, it will confuse live interval analysis, which will
3101 * make spilling fail to make progress.
3103 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
3104 temp
.type
= inst
->dst
.type
;
3105 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
3107 for (int i
= 0; i
< 4; i
++)
3108 if (inst
->dst
.writemask
& (1 << i
))
3111 swizzles
[i
] = first_writemask_chan
;
3112 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3113 swizzles
[2], swizzles
[3]);
3115 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3116 inst
->dst
.writemask
));
3117 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3118 write
->predicate
= inst
->predicate
;
3119 write
->ir
= inst
->ir
;
3120 write
->annotation
= inst
->annotation
;
3121 inst
->insert_after(write
);
3123 inst
->dst
.file
= temp
.file
;
3124 inst
->dst
.reg
= temp
.reg
;
3125 inst
->dst
.reg_offset
= temp
.reg_offset
;
3126 inst
->dst
.reladdr
= NULL
;
3130 * We can't generally support array access in GRF space, because a
3131 * single instruction's destination can only span 2 contiguous
3132 * registers. So, we send all GRF arrays that get variable index
3133 * access to scratch space.
3136 vec4_visitor::move_grf_array_access_to_scratch()
3138 int scratch_loc
[this->virtual_grf_count
];
3140 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
3141 scratch_loc
[i
] = -1;
3144 /* First, calculate the set of virtual GRFs that need to be punted
3145 * to scratch due to having any array access on them, and where in
3148 foreach_list(node
, &this->instructions
) {
3149 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3151 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3152 scratch_loc
[inst
->dst
.reg
] == -1) {
3153 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3154 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
3157 for (int i
= 0 ; i
< 3; i
++) {
3158 src_reg
*src
= &inst
->src
[i
];
3160 if (src
->file
== GRF
&& src
->reladdr
&&
3161 scratch_loc
[src
->reg
] == -1) {
3162 scratch_loc
[src
->reg
] = c
->last_scratch
;
3163 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
3168 /* Now, for anything that will be accessed through scratch, rewrite
3169 * it to load/store. Note that this is a _safe list walk, because
3170 * we may generate a new scratch_write instruction after the one
3173 foreach_list_safe(node
, &this->instructions
) {
3174 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3176 /* Set up the annotation tracking for new generated instructions. */
3178 current_annotation
= inst
->annotation
;
3180 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3181 emit_scratch_write(inst
, scratch_loc
[inst
->dst
.reg
]);
3184 for (int i
= 0 ; i
< 3; i
++) {
3185 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3188 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3190 emit_scratch_read(inst
, temp
, inst
->src
[i
],
3191 scratch_loc
[inst
->src
[i
].reg
]);
3193 inst
->src
[i
].file
= temp
.file
;
3194 inst
->src
[i
].reg
= temp
.reg
;
3195 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3196 inst
->src
[i
].reladdr
= NULL
;
3202 * Emits an instruction before @inst to load the value named by @orig_src
3203 * from the pull constant buffer (surface) at @base_offset to @temp.
3206 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
3207 dst_reg temp
, src_reg orig_src
,
3210 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3211 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3212 src_reg offset
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
3213 vec4_instruction
*load
;
3215 if (brw
->gen
>= 7) {
3216 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3217 grf_offset
.type
= offset
.type
;
3218 emit_before(inst
, MOV(grf_offset
, offset
));
3220 load
= new(mem_ctx
) vec4_instruction(this,
3221 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3222 temp
, index
, src_reg(grf_offset
));
3224 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
3225 temp
, index
, offset
);
3226 load
->base_mrf
= 14;
3229 emit_before(inst
, load
);
3233 * Implements array access of uniforms by inserting a
3234 * PULL_CONSTANT_LOAD instruction.
3236 * Unlike temporary GRF array access (where we don't support it due to
3237 * the difficulty of doing relative addressing on instruction
3238 * destinations), we could potentially do array access of uniforms
3239 * that were loaded in GRF space as push constants. In real-world
3240 * usage we've seen, though, the arrays being used are always larger
3241 * than we could load as push constants, so just always move all
3242 * uniform array access out to a pull constant buffer.
3245 vec4_visitor::move_uniform_array_access_to_pull_constants()
3247 int pull_constant_loc
[this->uniforms
];
3249 for (int i
= 0; i
< this->uniforms
; i
++) {
3250 pull_constant_loc
[i
] = -1;
3253 /* Walk through and find array access of uniforms. Put a copy of that
3254 * uniform in the pull constant buffer.
3256 * Note that we don't move constant-indexed accesses to arrays. No
3257 * testing has been done of the performance impact of this choice.
3259 foreach_list_safe(node
, &this->instructions
) {
3260 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3262 for (int i
= 0 ; i
< 3; i
++) {
3263 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3266 int uniform
= inst
->src
[i
].reg
;
3268 /* If this array isn't already present in the pull constant buffer,
3271 if (pull_constant_loc
[uniform
] == -1) {
3272 const float **values
= &stage_prog_data
->param
[uniform
* 4];
3274 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3276 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3277 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3282 /* Set up the annotation tracking for new generated instructions. */
3284 current_annotation
= inst
->annotation
;
3286 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3288 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
3289 pull_constant_loc
[uniform
]);
3291 inst
->src
[i
].file
= temp
.file
;
3292 inst
->src
[i
].reg
= temp
.reg
;
3293 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3294 inst
->src
[i
].reladdr
= NULL
;
3298 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3299 * no need to track them as larger-than-vec4 objects. This will be
3300 * relied on in cutting out unused uniform vectors from push
3303 split_uniform_registers();
3307 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3309 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3313 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3314 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3318 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3319 struct brw_vec4_compile
*c
,
3320 struct gl_program
*prog
,
3321 const struct brw_vec4_prog_key
*key
,
3322 struct brw_vec4_prog_data
*prog_data
,
3323 struct gl_shader_program
*shader_prog
,
3324 struct brw_shader
*shader
,
3328 shader_time_shader_type st_base
,
3329 shader_time_shader_type st_written
,
3330 shader_time_shader_type st_reset
)
3331 : sanity_param_count(0),
3333 first_non_payload_grf(0),
3334 need_all_constants_in_pull_buffer(false),
3335 debug_flag(debug_flag
),
3336 no_spills(no_spills
),
3338 st_written(st_written
),
3342 this->ctx
= &brw
->ctx
;
3343 this->shader_prog
= shader_prog
;
3344 this->shader
= shader
;
3346 this->mem_ctx
= mem_ctx
;
3347 this->failed
= false;
3349 this->base_ir
= NULL
;
3350 this->current_annotation
= NULL
;
3351 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3356 this->prog_data
= prog_data
;
3357 this->stage_prog_data
= &prog_data
->base
;
3359 this->variable_ht
= hash_table_ctor(0,
3360 hash_table_pointer_hash
,
3361 hash_table_pointer_compare
);
3363 this->virtual_grf_start
= NULL
;
3364 this->virtual_grf_end
= NULL
;
3365 this->virtual_grf_sizes
= NULL
;
3366 this->virtual_grf_count
= 0;
3367 this->virtual_grf_reg_map
= NULL
;
3368 this->virtual_grf_reg_count
= 0;
3369 this->virtual_grf_array_size
= 0;
3370 this->live_intervals_valid
= false;
3372 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3377 vec4_visitor::~vec4_visitor()
3379 hash_table_dtor(this->variable_ht
);
3384 vec4_visitor::fail(const char *format
, ...)
3394 va_start(va
, format
);
3395 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3397 msg
= ralloc_asprintf(mem_ctx
, "vec4 compile failed: %s\n", msg
);
3399 this->fail_msg
= msg
;
3402 fprintf(stderr
, "%s", msg
);
3406 } /* namespace brw */