2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
31 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
32 const src_reg
&src0
, const src_reg
&src1
,
35 this->opcode
= opcode
;
40 this->saturate
= false;
41 this->force_writemask_all
= false;
42 this->no_dd_clear
= false;
43 this->no_dd_check
= false;
44 this->writes_accumulator
= false;
45 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
46 this->predicate
= BRW_PREDICATE_NONE
;
47 this->predicate_inverse
= false;
49 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
50 this->shadow_compare
= false;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_present
= false;
54 this->flag_subreg
= 0;
58 this->annotation
= NULL
;
62 vec4_visitor::emit(vec4_instruction
*inst
)
64 inst
->ir
= this->base_ir
;
65 inst
->annotation
= this->current_annotation
;
67 this->instructions
.push_tail(inst
);
73 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
74 vec4_instruction
*new_inst
)
76 new_inst
->ir
= inst
->ir
;
77 new_inst
->annotation
= inst
->annotation
;
79 inst
->insert_before(block
, new_inst
);
85 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
86 const src_reg
&src1
, const src_reg
&src2
)
88 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
93 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
96 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
100 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
102 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
106 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
108 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
112 vec4_visitor::emit(enum opcode opcode
)
114 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
119 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
121 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
126 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
127 const src_reg &src1) \
129 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
133 #define ALU2_ACC(op) \
135 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
136 const src_reg &src1) \
138 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
139 BRW_OPCODE_##op, dst, src0, src1); \
140 inst->writes_accumulator = true; \
146 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
147 const src_reg &src1, const src_reg &src2) \
149 assert(brw->gen >= 6); \
150 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
187 /** Gen4 predicated IF. */
189 vec4_visitor::IF(enum brw_predicate predicate
)
191 vec4_instruction
*inst
;
193 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
199 /** Gen6 IF with embedded comparison. */
201 vec4_visitor::IF(src_reg src0
, src_reg src1
,
202 enum brw_conditional_mod condition
)
204 assert(brw
->gen
== 6);
206 vec4_instruction
*inst
;
208 resolve_ud_negate(&src0
);
209 resolve_ud_negate(&src1
);
211 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
213 inst
->conditional_mod
= condition
;
219 * CMP: Sets the low bit of the destination channels with the result
220 * of the comparison, while the upper bits are undefined, and updates
221 * the flag register with the packed 16 bits of the result.
224 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
225 enum brw_conditional_mod condition
)
227 vec4_instruction
*inst
;
229 /* Take the instruction:
231 * CMP null<d> src0<f> src1<f>
233 * Original gen4 does type conversion to the destination type before
234 * comparison, producing garbage results for floating point comparisons.
236 * The destination type doesn't matter on newer generations, so we set the
237 * type to match src0 so we can compact the instruction.
239 dst
.type
= src0
.type
;
240 if (dst
.file
== HW_REG
)
241 dst
.fixed_hw_reg
.type
= dst
.type
;
243 resolve_ud_negate(&src0
);
244 resolve_ud_negate(&src1
);
246 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
247 inst
->conditional_mod
= condition
;
253 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
255 vec4_instruction
*inst
;
257 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
266 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
267 const src_reg
&index
)
269 vec4_instruction
*inst
;
271 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
280 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
282 static enum opcode dot_opcodes
[] = {
283 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
286 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
290 vec4_visitor::fix_3src_operand(src_reg src
)
292 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
293 * able to use vertical stride of zero to replicate the vec4 uniform, like
295 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
297 * But you can't, since vertical stride is always four in three-source
298 * instructions. Instead, insert a MOV instruction to do the replication so
299 * that the three-source instruction can consume it.
302 /* The MOV is only needed if the source is a uniform or immediate. */
303 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
306 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
309 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
310 expanded
.type
= src
.type
;
311 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
312 return src_reg(expanded
);
316 vec4_visitor::fix_math_operand(src_reg src
)
318 if (brw
->gen
< 6 || brw
->gen
>= 8 || src
.file
== BAD_FILE
)
321 /* The gen6 math instruction ignores the source modifiers --
322 * swizzle, abs, negate, and at least some parts of the register
323 * region description.
325 * Rather than trying to enumerate all these cases, *always* expand the
326 * operand to a temp GRF for gen6.
328 * For gen7, keep the operand as-is, except if immediate, which gen7 still
332 if (brw
->gen
== 7 && src
.file
!= IMM
)
335 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
336 expanded
.type
= src
.type
;
337 emit(MOV(expanded
, src
));
338 return src_reg(expanded
);
342 vec4_visitor::emit_math(enum opcode opcode
,
344 const src_reg
&src0
, const src_reg
&src1
)
346 vec4_instruction
*math
=
347 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
349 if (brw
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
350 /* MATH on Gen6 must be align1, so we can't do writemasks. */
351 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
352 math
->dst
.type
= dst
.type
;
353 emit(MOV(dst
, src_reg(math
->dst
)));
354 } else if (brw
->gen
< 6) {
356 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
361 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
364 unreachable("ir_unop_pack_half_2x16 should be lowered");
367 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
368 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
370 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
372 * Because this instruction does not have a 16-bit floating-point type,
373 * the destination data type must be Word (W).
375 * The destination must be DWord-aligned and specify a horizontal stride
376 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
377 * each destination channel and the upper word is not modified.
379 * The above restriction implies that the f32to16 instruction must use
380 * align1 mode, because only in align1 mode is it possible to specify
381 * horizontal stride. We choose here to defy the hardware docs and emit
382 * align16 instructions.
384 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
385 * instructions. I was partially successful in that the code passed all
386 * tests. However, the code was dubiously correct and fragile, and the
387 * tests were not harsh enough to probe that frailty. Not trusting the
388 * code, I chose instead to remain in align16 mode in defiance of the hw
391 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
392 * simulator, emitting a f32to16 in align16 mode with UD as destination
393 * data type is safe. The behavior differs from that specified in the PRM
394 * in that the upper word of each destination channel is cleared to 0.
397 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
398 src_reg
tmp_src(tmp_dst
);
401 /* Verify the undocumented behavior on which the following instructions
402 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
403 * then the result of the bit-or instruction below will be incorrect.
405 * You should inspect the disasm output in order to verify that the MOV is
406 * not optimized away.
408 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
411 /* Give tmp the form below, where "." means untouched.
414 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
416 * That the upper word of each write-channel be 0 is required for the
417 * following bit-shift and bit-or instructions to work. Note that this
418 * relies on the undocumented hardware behavior mentioned above.
420 tmp_dst
.writemask
= WRITEMASK_XY
;
421 emit(F32TO16(tmp_dst
, src0
));
423 /* Give the write-channels of dst the form:
426 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
427 emit(SHL(dst
, tmp_src
, src_reg(16u)));
429 /* Finally, give the write-channels of dst the form of packHalf2x16's
433 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
434 emit(OR(dst
, src_reg(dst
), tmp_src
));
438 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
441 unreachable("ir_unop_unpack_half_2x16 should be lowered");
444 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
445 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
447 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
449 * Because this instruction does not have a 16-bit floating-point type,
450 * the source data type must be Word (W). The destination type must be
453 * To use W as the source data type, we must adjust horizontal strides,
454 * which is only possible in align1 mode. All my [chadv] attempts at
455 * emitting align1 instructions for unpackHalf2x16 failed to pass the
456 * Piglit tests, so I gave up.
458 * I've verified that, on gen7 hardware and the simulator, it is safe to
459 * emit f16to32 in align16 mode with UD as source data type.
462 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
463 src_reg
tmp_src(tmp_dst
);
465 tmp_dst
.writemask
= WRITEMASK_X
;
466 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
468 tmp_dst
.writemask
= WRITEMASK_Y
;
469 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
471 dst
.writemask
= WRITEMASK_XY
;
472 emit(F16TO32(dst
, tmp_src
));
476 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
478 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
479 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
480 * is not suitable to generate the shift values, but we can use the packed
481 * vector float and a type-converting MOV.
483 dst_reg
shift(this, glsl_type::uvec4_type
);
484 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
486 dst_reg
shifted(this, glsl_type::uvec4_type
);
487 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
488 emit(SHR(shifted
, src0
, src_reg(shift
)));
490 shifted
.type
= BRW_REGISTER_TYPE_UB
;
491 dst_reg
f(this, glsl_type::vec4_type
);
492 emit(MOV(f
, src_reg(shifted
)));
494 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
498 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
500 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
501 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
502 * is not suitable to generate the shift values, but we can use the packed
503 * vector float and a type-converting MOV.
505 dst_reg
shift(this, glsl_type::uvec4_type
);
506 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
508 dst_reg
shifted(this, glsl_type::uvec4_type
);
509 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
510 emit(SHR(shifted
, src0
, src_reg(shift
)));
512 shifted
.type
= BRW_REGISTER_TYPE_B
;
513 dst_reg
f(this, glsl_type::vec4_type
);
514 emit(MOV(f
, src_reg(shifted
)));
516 dst_reg
scaled(this, glsl_type::vec4_type
);
517 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
519 dst_reg
max(this, glsl_type::vec4_type
);
520 emit_minmax(BRW_CONDITIONAL_G
, max
, src_reg(scaled
), src_reg(-1.0f
));
521 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
525 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
527 dst_reg
saturated(this, glsl_type::vec4_type
);
528 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
529 inst
->saturate
= true;
531 dst_reg
scaled(this, glsl_type::vec4_type
);
532 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
534 dst_reg
rounded(this, glsl_type::vec4_type
);
535 emit(RNDE(rounded
, src_reg(scaled
)));
537 dst_reg
u(this, glsl_type::uvec4_type
);
538 emit(MOV(u
, src_reg(rounded
)));
541 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
545 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
547 dst_reg
max(this, glsl_type::vec4_type
);
548 emit_minmax(BRW_CONDITIONAL_G
, max
, src0
, src_reg(-1.0f
));
550 dst_reg
min(this, glsl_type::vec4_type
);
551 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
553 dst_reg
scaled(this, glsl_type::vec4_type
);
554 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
556 dst_reg
rounded(this, glsl_type::vec4_type
);
557 emit(RNDE(rounded
, src_reg(scaled
)));
559 dst_reg
i(this, glsl_type::ivec4_type
);
560 emit(MOV(i
, src_reg(rounded
)));
563 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
567 vec4_visitor::visit_instructions(const exec_list
*list
)
569 foreach_in_list(ir_instruction
, ir
, list
) {
577 type_size(const struct glsl_type
*type
)
582 switch (type
->base_type
) {
585 case GLSL_TYPE_FLOAT
:
587 if (type
->is_matrix()) {
588 return type
->matrix_columns
;
590 /* Regardless of size of vector, it gets a vec4. This is bad
591 * packing for things like floats, but otherwise arrays become a
592 * mess. Hopefully a later pass over the code can pack scalars
593 * down if appropriate.
597 case GLSL_TYPE_ARRAY
:
598 assert(type
->length
> 0);
599 return type_size(type
->fields
.array
) * type
->length
;
600 case GLSL_TYPE_STRUCT
:
602 for (i
= 0; i
< type
->length
; i
++) {
603 size
+= type_size(type
->fields
.structure
[i
].type
);
606 case GLSL_TYPE_SAMPLER
:
607 /* Samplers take up no register space, since they're baked in at
611 case GLSL_TYPE_ATOMIC_UINT
:
613 case GLSL_TYPE_IMAGE
:
615 case GLSL_TYPE_DOUBLE
:
616 case GLSL_TYPE_ERROR
:
617 case GLSL_TYPE_INTERFACE
:
618 unreachable("not reached");
624 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
629 this->reg
= v
->alloc
.allocate(type_size(type
));
631 if (type
->is_array() || type
->is_record()) {
632 this->swizzle
= BRW_SWIZZLE_NOOP
;
634 this->swizzle
= swizzle_for_size(type
->vector_elements
);
637 this->type
= brw_type_for_base_type(type
);
640 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
647 this->reg
= v
->alloc
.allocate(type_size(type
) * size
);
649 this->swizzle
= BRW_SWIZZLE_NOOP
;
651 this->type
= brw_type_for_base_type(type
);
654 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
659 this->reg
= v
->alloc
.allocate(type_size(type
));
661 if (type
->is_array() || type
->is_record()) {
662 this->writemask
= WRITEMASK_XYZW
;
664 this->writemask
= (1 << type
->vector_elements
) - 1;
667 this->type
= brw_type_for_base_type(type
);
670 /* Our support for uniforms is piggy-backed on the struct
671 * gl_fragment_program, because that's where the values actually
672 * get stored, rather than in some global gl_shader_program uniform
676 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
678 int namelen
= strlen(ir
->name
);
680 /* The data for our (non-builtin) uniforms is stored in a series of
681 * gl_uniform_driver_storage structs for each subcomponent that
682 * glGetUniformLocation() could name. We know it's been set up in the same
683 * order we'd walk the type, so walk the list of storage and find anything
684 * with our name, or the prefix of a component that starts with our name.
686 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
687 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
689 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
690 (storage
->name
[namelen
] != 0 &&
691 storage
->name
[namelen
] != '.' &&
692 storage
->name
[namelen
] != '[')) {
696 gl_constant_value
*components
= storage
->storage
;
697 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
698 storage
->type
->matrix_columns
);
700 for (unsigned s
= 0; s
< vector_count
; s
++) {
701 assert(uniforms
< uniform_array_size
);
702 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
705 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
706 stage_prog_data
->param
[uniforms
* 4 + i
] = components
;
710 static gl_constant_value zero
= { 0.0 };
711 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
720 vec4_visitor::setup_uniform_clipplane_values()
722 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
724 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
725 assert(this->uniforms
< uniform_array_size
);
726 this->uniform_vector_size
[this->uniforms
] = 4;
727 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
728 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
729 for (int j
= 0; j
< 4; ++j
) {
730 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
731 (gl_constant_value
*) &clip_planes
[i
][j
];
737 /* Our support for builtin uniforms is even scarier than non-builtin.
738 * It sits on top of the PROG_STATE_VAR parameters that are
739 * automatically updated from GL context state.
742 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
744 const ir_state_slot
*const slots
= ir
->get_state_slots();
745 assert(slots
!= NULL
);
747 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
748 /* This state reference has already been setup by ir_to_mesa,
749 * but we'll get the same index back here. We can reference
750 * ParameterValues directly, since unlike brw_fs.cpp, we never
751 * add new state references during compile.
753 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
754 (gl_state_index
*)slots
[i
].tokens
);
755 gl_constant_value
*values
=
756 &this->prog
->Parameters
->ParameterValues
[index
][0];
758 assert(this->uniforms
< uniform_array_size
);
759 this->uniform_vector_size
[this->uniforms
] = 0;
760 /* Add each of the unique swizzled channels of the element.
761 * This will end up matching the size of the glsl_type of this field.
764 for (unsigned int j
= 0; j
< 4; j
++) {
765 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
768 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
769 assert(this->uniforms
< uniform_array_size
);
770 if (swiz
<= last_swiz
)
771 this->uniform_vector_size
[this->uniforms
]++;
778 vec4_visitor::variable_storage(ir_variable
*var
)
780 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
784 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
785 enum brw_predicate
*predicate
)
787 ir_expression
*expr
= ir
->as_expression();
789 *predicate
= BRW_PREDICATE_NORMAL
;
791 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
793 vec4_instruction
*inst
;
795 assert(expr
->get_num_operands() <= 3);
796 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
797 expr
->operands
[i
]->accept(this);
798 op
[i
] = this->result
;
800 resolve_ud_negate(&op
[i
]);
803 switch (expr
->operation
) {
804 case ir_unop_logic_not
:
805 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
806 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
809 case ir_binop_logic_xor
:
811 src_reg temp
= src_reg(this, ir
->type
);
812 emit(XOR(dst_reg(temp
), op
[0], op
[1]));
813 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
815 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
817 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
820 case ir_binop_logic_or
:
822 src_reg temp
= src_reg(this, ir
->type
);
823 emit(OR(dst_reg(temp
), op
[0], op
[1]));
824 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
826 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
828 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
831 case ir_binop_logic_and
:
833 src_reg temp
= src_reg(this, ir
->type
);
834 emit(AND(dst_reg(temp
), op
[0], op
[1]));
835 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
837 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
839 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
844 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
846 inst
= emit(MOV(dst_null_f(), op
[0]));
847 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
853 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
855 inst
= emit(MOV(dst_null_d(), op
[0]));
856 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
860 case ir_binop_all_equal
:
862 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
863 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
865 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
866 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
869 case ir_binop_any_nequal
:
871 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
872 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
874 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
875 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
880 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
882 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
883 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
886 case ir_binop_greater
:
887 case ir_binop_gequal
:
889 case ir_binop_lequal
:
891 case ir_binop_nequal
:
893 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
894 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
896 emit(CMP(dst_null_d(), op
[0], op
[1],
897 brw_conditional_for_comparison(expr
->operation
)));
900 case ir_triop_csel
: {
901 /* Expand the boolean condition into the flag register. */
902 inst
= emit(MOV(dst_null_d(), op
[0]));
903 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
905 /* Select which boolean to return. */
906 dst_reg
temp(this, expr
->operands
[1]->type
);
907 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
908 inst
->predicate
= BRW_PREDICATE_NORMAL
;
910 /* Expand the result to a condition code. */
911 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
912 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
917 unreachable("not reached");
924 resolve_ud_negate(&this->result
);
926 vec4_instruction
*inst
= emit(AND(dst_null_d(), this->result
, src_reg(1)));
927 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
931 * Emit a gen6 IF statement with the comparison folded into the IF
935 vec4_visitor::emit_if_gen6(ir_if
*ir
)
937 ir_expression
*expr
= ir
->condition
->as_expression();
939 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
943 assert(expr
->get_num_operands() <= 3);
944 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
945 expr
->operands
[i
]->accept(this);
946 op
[i
] = this->result
;
949 switch (expr
->operation
) {
950 case ir_unop_logic_not
:
951 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
954 case ir_binop_logic_xor
:
955 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
958 case ir_binop_logic_or
:
959 temp
= dst_reg(this, glsl_type::bool_type
);
960 emit(OR(temp
, op
[0], op
[1]));
961 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
964 case ir_binop_logic_and
:
965 temp
= dst_reg(this, glsl_type::bool_type
);
966 emit(AND(temp
, op
[0], op
[1]));
967 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
971 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
975 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
978 case ir_binop_greater
:
979 case ir_binop_gequal
:
981 case ir_binop_lequal
:
983 case ir_binop_nequal
:
984 emit(IF(op
[0], op
[1],
985 brw_conditional_for_comparison(expr
->operation
)));
988 case ir_binop_all_equal
:
989 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
990 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
993 case ir_binop_any_nequal
:
994 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
995 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
999 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1000 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1003 case ir_triop_csel
: {
1004 /* Expand the boolean condition into the flag register. */
1005 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
1006 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1008 /* Select which boolean to return. */
1009 dst_reg
temp(this, expr
->operands
[1]->type
);
1010 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
1011 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1013 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
1018 unreachable("not reached");
1023 ir
->condition
->accept(this);
1025 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
1029 vec4_visitor::visit(ir_variable
*ir
)
1031 dst_reg
*reg
= NULL
;
1033 if (variable_storage(ir
))
1036 switch (ir
->data
.mode
) {
1037 case ir_var_shader_in
:
1038 assert(ir
->data
.location
!= -1);
1039 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
1042 case ir_var_shader_out
:
1043 assert(ir
->data
.location
!= -1);
1044 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1046 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1047 output_reg
[ir
->data
.location
+ i
] = *reg
;
1048 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
1049 output_reg
[ir
->data
.location
+ i
].type
=
1050 brw_type_for_base_type(ir
->type
->get_scalar_type());
1051 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
1056 case ir_var_temporary
:
1057 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1060 case ir_var_uniform
:
1061 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1063 /* Thanks to the lower_ubo_reference pass, we will see only
1064 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1065 * variables, so no need for them to be in variable_ht.
1067 * Some uniforms, such as samplers and atomic counters, have no actual
1068 * storage, so we should ignore them.
1070 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
1073 /* Track how big the whole uniform variable is, in case we need to put a
1074 * copy of its data into pull constants for array access.
1076 assert(this->uniforms
< uniform_array_size
);
1077 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1079 if (!strncmp(ir
->name
, "gl_", 3)) {
1080 setup_builtin_uniform_values(ir
);
1082 setup_uniform_values(ir
);
1086 case ir_var_system_value
:
1087 reg
= make_reg_for_system_value(ir
);
1091 unreachable("not reached");
1094 reg
->type
= brw_type_for_base_type(ir
->type
);
1095 hash_table_insert(this->variable_ht
, reg
, ir
);
1099 vec4_visitor::visit(ir_loop
*ir
)
1101 /* We don't want debugging output to print the whole body of the
1102 * loop as the annotation.
1104 this->base_ir
= NULL
;
1106 emit(BRW_OPCODE_DO
);
1108 visit_instructions(&ir
->body_instructions
);
1110 emit(BRW_OPCODE_WHILE
);
1114 vec4_visitor::visit(ir_loop_jump
*ir
)
1117 case ir_loop_jump::jump_break
:
1118 emit(BRW_OPCODE_BREAK
);
1120 case ir_loop_jump::jump_continue
:
1121 emit(BRW_OPCODE_CONTINUE
);
1128 vec4_visitor::visit(ir_function_signature
*)
1130 unreachable("not reached");
1134 vec4_visitor::visit(ir_function
*ir
)
1136 /* Ignore function bodies other than main() -- we shouldn't see calls to
1137 * them since they should all be inlined.
1139 if (strcmp(ir
->name
, "main") == 0) {
1140 const ir_function_signature
*sig
;
1143 sig
= ir
->matching_signature(NULL
, &empty
, false);
1147 visit_instructions(&sig
->body
);
1152 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1154 /* 3-src instructions were introduced in gen6. */
1158 /* MAD can only handle floating-point data. */
1159 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1162 ir_rvalue
*nonmul
= ir
->operands
[1];
1163 ir_expression
*mul
= ir
->operands
[0]->as_expression();
1165 bool mul_negate
= false, mul_abs
= false;
1166 if (mul
&& mul
->operation
== ir_unop_abs
) {
1167 mul
= mul
->operands
[0]->as_expression();
1169 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
1170 mul
= mul
->operands
[0]->as_expression();
1174 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
1175 nonmul
= ir
->operands
[0];
1176 mul
= ir
->operands
[1]->as_expression();
1178 if (mul
&& mul
->operation
== ir_unop_abs
) {
1179 mul
= mul
->operands
[0]->as_expression();
1181 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
1182 mul
= mul
->operands
[0]->as_expression();
1186 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1190 nonmul
->accept(this);
1191 src_reg src0
= fix_3src_operand(this->result
);
1193 mul
->operands
[0]->accept(this);
1194 src_reg src1
= fix_3src_operand(this->result
);
1195 src1
.negate
^= mul_negate
;
1198 src1
.negate
= false;
1200 mul
->operands
[1]->accept(this);
1201 src_reg src2
= fix_3src_operand(this->result
);
1204 src2
.negate
= false;
1206 this->result
= src_reg(this, ir
->type
);
1207 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1213 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1215 /* This optimization relies on CMP setting the destination to 0 when
1216 * false. Early hardware only sets the least significant bit, and
1217 * leaves the other bits undefined. So we can't use it.
1222 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1227 switch (cmp
->operation
) {
1229 case ir_binop_greater
:
1230 case ir_binop_lequal
:
1231 case ir_binop_gequal
:
1232 case ir_binop_equal
:
1233 case ir_binop_nequal
:
1240 cmp
->operands
[0]->accept(this);
1241 const src_reg cmp_src0
= this->result
;
1243 cmp
->operands
[1]->accept(this);
1244 const src_reg cmp_src1
= this->result
;
1246 this->result
= src_reg(this, ir
->type
);
1248 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1249 brw_conditional_for_comparison(cmp
->operation
)));
1251 /* If the comparison is false, this->result will just happen to be zero.
1253 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1254 this->result
, src_reg(1.0f
));
1255 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1256 inst
->predicate_inverse
= true;
1262 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1263 src_reg src0
, src_reg src1
)
1265 vec4_instruction
*inst
;
1267 if (brw
->gen
>= 6) {
1268 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1269 inst
->conditional_mod
= conditionalmod
;
1271 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1273 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1274 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1279 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1280 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1282 if (brw
->gen
>= 6) {
1283 /* Note that the instruction's argument order is reversed from GLSL
1287 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1289 /* Earlier generations don't support three source operations, so we
1290 * need to emit x*(1-a) + y*a.
1292 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1293 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1294 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1295 y_times_a
.writemask
= dst
.writemask
;
1296 one_minus_a
.writemask
= dst
.writemask
;
1297 x_times_one_minus_a
.writemask
= dst
.writemask
;
1299 emit(MUL(y_times_a
, y
, a
));
1300 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1301 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1302 emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1307 vec4_visitor::visit(ir_expression
*ir
)
1309 unsigned int operand
;
1310 src_reg op
[Elements(ir
->operands
)];
1311 vec4_instruction
*inst
;
1313 if (ir
->operation
== ir_binop_add
) {
1314 if (try_emit_mad(ir
))
1318 if (ir
->operation
== ir_unop_b2f
) {
1319 if (try_emit_b2f_of_compare(ir
))
1323 /* Storage for our result. Ideally for an assignment we'd be using
1324 * the actual storage for the result here, instead.
1326 dst_reg
result_dst(this, ir
->type
);
1327 src_reg
result_src(result_dst
);
1329 if (ir
->operation
== ir_triop_csel
) {
1330 ir
->operands
[1]->accept(this);
1331 op
[1] = this->result
;
1332 ir
->operands
[2]->accept(this);
1333 op
[2] = this->result
;
1335 enum brw_predicate predicate
;
1336 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1337 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1338 inst
->predicate
= predicate
;
1339 this->result
= result_src
;
1343 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1344 this->result
.file
= BAD_FILE
;
1345 ir
->operands
[operand
]->accept(this);
1346 if (this->result
.file
== BAD_FILE
) {
1347 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1348 ir
->operands
[operand
]->fprint(stderr
);
1351 op
[operand
] = this->result
;
1353 /* Matrix expression operands should have been broken down to vector
1354 * operations already.
1356 assert(!ir
->operands
[operand
]->type
->is_matrix());
1359 /* If nothing special happens, this is the result. */
1360 this->result
= result_src
;
1362 switch (ir
->operation
) {
1363 case ir_unop_logic_not
:
1364 emit(NOT(result_dst
, op
[0]));
1367 op
[0].negate
= !op
[0].negate
;
1368 emit(MOV(result_dst
, op
[0]));
1372 op
[0].negate
= false;
1373 emit(MOV(result_dst
, op
[0]));
1377 if (ir
->type
->is_float()) {
1378 /* AND(val, 0x80000000) gives the sign bit.
1380 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1383 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1385 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1386 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1387 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1389 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1390 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1392 this->result
.type
= BRW_REGISTER_TYPE_F
;
1394 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1395 * -> non-negative val generates 0x00000000.
1396 * Predicated OR sets 1 if val is positive.
1398 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1400 emit(ASR(result_dst
, op
[0], src_reg(31)));
1402 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1403 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1408 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1412 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1415 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1419 unreachable("not reached: should be handled by ir_explog_to_explog2");
1421 case ir_unop_sin_reduced
:
1422 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1425 case ir_unop_cos_reduced
:
1426 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1430 case ir_unop_dFdx_coarse
:
1431 case ir_unop_dFdx_fine
:
1433 case ir_unop_dFdy_coarse
:
1434 case ir_unop_dFdy_fine
:
1435 unreachable("derivatives not valid in vertex shader");
1437 case ir_unop_bitfield_reverse
:
1438 emit(BFREV(result_dst
, op
[0]));
1440 case ir_unop_bit_count
:
1441 emit(CBIT(result_dst
, op
[0]));
1443 case ir_unop_find_msb
: {
1444 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1446 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1447 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1449 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1450 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1451 * subtract the result from 31 to convert the MSB count into an LSB count.
1454 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1455 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1456 emit(MOV(result_dst
, temp
));
1458 src_reg src_tmp
= src_reg(result_dst
);
1459 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1461 src_tmp
.negate
= true;
1462 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1463 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1466 case ir_unop_find_lsb
:
1467 emit(FBL(result_dst
, op
[0]));
1469 case ir_unop_saturate
:
1470 inst
= emit(MOV(result_dst
, op
[0]));
1471 inst
->saturate
= true;
1475 unreachable("not reached: should be handled by lower_noise");
1478 emit(ADD(result_dst
, op
[0], op
[1]));
1481 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1484 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
1485 /* For integer multiplication, the MUL uses the low 16 bits of one of
1486 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1487 * accumulates in the contribution of the upper 16 bits of that
1488 * operand. If we can determine that one of the args is in the low
1489 * 16 bits, though, we can just emit a single MUL.
1491 if (ir
->operands
[0]->is_uint16_constant()) {
1493 emit(MUL(result_dst
, op
[0], op
[1]));
1495 emit(MUL(result_dst
, op
[1], op
[0]));
1496 } else if (ir
->operands
[1]->is_uint16_constant()) {
1498 emit(MUL(result_dst
, op
[1], op
[0]));
1500 emit(MUL(result_dst
, op
[0], op
[1]));
1502 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1504 emit(MUL(acc
, op
[0], op
[1]));
1505 emit(MACH(dst_null_d(), op
[0], op
[1]));
1506 emit(MOV(result_dst
, src_reg(acc
)));
1509 emit(MUL(result_dst
, op
[0], op
[1]));
1512 case ir_binop_imul_high
: {
1513 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1515 emit(MUL(acc
, op
[0], op
[1]));
1516 emit(MACH(result_dst
, op
[0], op
[1]));
1520 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1521 assert(ir
->type
->is_integer());
1522 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1524 case ir_binop_carry
: {
1525 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1527 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1528 emit(MOV(result_dst
, src_reg(acc
)));
1531 case ir_binop_borrow
: {
1532 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1534 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1535 emit(MOV(result_dst
, src_reg(acc
)));
1539 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1540 assert(ir
->type
->is_integer());
1541 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1545 case ir_binop_greater
:
1546 case ir_binop_lequal
:
1547 case ir_binop_gequal
:
1548 case ir_binop_equal
:
1549 case ir_binop_nequal
: {
1550 if (brw
->gen
<= 5) {
1551 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1552 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1554 emit(CMP(result_dst
, op
[0], op
[1],
1555 brw_conditional_for_comparison(ir
->operation
)));
1559 case ir_binop_all_equal
:
1560 /* "==" operator producing a scalar boolean. */
1561 if (ir
->operands
[0]->type
->is_vector() ||
1562 ir
->operands
[1]->type
->is_vector()) {
1563 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1564 emit(MOV(result_dst
, src_reg(0)));
1565 inst
= emit(MOV(result_dst
, src_reg((int)ctx
->Const
.UniformBooleanTrue
)));
1566 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1568 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1571 case ir_binop_any_nequal
:
1572 /* "!=" operator producing a scalar boolean. */
1573 if (ir
->operands
[0]->type
->is_vector() ||
1574 ir
->operands
[1]->type
->is_vector()) {
1575 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1577 emit(MOV(result_dst
, src_reg(0)));
1578 inst
= emit(MOV(result_dst
, src_reg((int)ctx
->Const
.UniformBooleanTrue
)));
1579 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1581 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1586 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1587 emit(MOV(result_dst
, src_reg(0)));
1589 inst
= emit(MOV(result_dst
, src_reg((int)ctx
->Const
.UniformBooleanTrue
)));
1590 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1593 case ir_binop_logic_xor
:
1594 emit(XOR(result_dst
, op
[0], op
[1]));
1597 case ir_binop_logic_or
:
1598 emit(OR(result_dst
, op
[0], op
[1]));
1601 case ir_binop_logic_and
:
1602 emit(AND(result_dst
, op
[0], op
[1]));
1606 assert(ir
->operands
[0]->type
->is_vector());
1607 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1608 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1612 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1615 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1618 case ir_unop_bitcast_i2f
:
1619 case ir_unop_bitcast_u2f
:
1620 this->result
= op
[0];
1621 this->result
.type
= BRW_REGISTER_TYPE_F
;
1624 case ir_unop_bitcast_f2i
:
1625 this->result
= op
[0];
1626 this->result
.type
= BRW_REGISTER_TYPE_D
;
1629 case ir_unop_bitcast_f2u
:
1630 this->result
= op
[0];
1631 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1640 emit(MOV(result_dst
, op
[0]));
1643 emit(AND(result_dst
, op
[0], src_reg(1)));
1646 if (brw
->gen
<= 5) {
1647 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1649 op
[0].type
= BRW_REGISTER_TYPE_D
;
1650 result_dst
.type
= BRW_REGISTER_TYPE_D
;
1651 emit(AND(result_dst
, op
[0], src_reg(0x3f800000u
)));
1652 result_dst
.type
= BRW_REGISTER_TYPE_F
;
1655 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1658 emit(AND(result_dst
, op
[0], src_reg(1)));
1662 emit(RNDZ(result_dst
, op
[0]));
1664 case ir_unop_ceil
: {
1665 src_reg tmp
= src_reg(this, ir
->type
);
1666 op
[0].negate
= !op
[0].negate
;
1667 emit(RNDD(dst_reg(tmp
), op
[0]));
1669 emit(MOV(result_dst
, tmp
));
1673 inst
= emit(RNDD(result_dst
, op
[0]));
1676 inst
= emit(FRC(result_dst
, op
[0]));
1678 case ir_unop_round_even
:
1679 emit(RNDE(result_dst
, op
[0]));
1683 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1686 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1690 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1693 case ir_unop_bit_not
:
1694 inst
= emit(NOT(result_dst
, op
[0]));
1696 case ir_binop_bit_and
:
1697 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1699 case ir_binop_bit_xor
:
1700 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1702 case ir_binop_bit_or
:
1703 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1706 case ir_binop_lshift
:
1707 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1710 case ir_binop_rshift
:
1711 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1712 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1714 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1718 emit(BFI1(result_dst
, op
[0], op
[1]));
1721 case ir_binop_ubo_load
: {
1722 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1723 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1724 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1727 /* Now, load the vector from that offset. */
1728 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1730 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1731 packed_consts
.type
= result
.type
;
1734 if (const_uniform_block
) {
1735 /* The block index is a constant, so just emit the binding table entry
1738 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1739 const_uniform_block
->value
.u
[0]);
1741 /* The block index is not a constant. Evaluate the index expression
1742 * per-channel and add the base UBO index; the generator will select
1743 * a value from any live channel.
1745 surf_index
= src_reg(this, glsl_type::uint_type
);
1746 emit(ADD(dst_reg(surf_index
), op
[0],
1747 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1749 /* Assume this may touch any UBO. It would be nice to provide
1750 * a tighter bound, but the array information is already lowered away.
1752 brw_mark_surface_used(&prog_data
->base
,
1753 prog_data
->base
.binding_table
.ubo_start
+
1754 shader_prog
->NumUniformBlocks
- 1);
1757 if (const_offset_ir
) {
1758 if (brw
->gen
>= 8) {
1759 /* Store the offset in a GRF so we can send-from-GRF. */
1760 offset
= src_reg(this, glsl_type::int_type
);
1761 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1763 /* Immediates are fine on older generations since they'll be moved
1764 * to a (potentially fake) MRF at the generator level.
1766 offset
= src_reg(const_offset
/ 16);
1769 offset
= src_reg(this, glsl_type::uint_type
);
1770 emit(SHR(dst_reg(offset
), op
[1], src_reg(4)));
1773 if (brw
->gen
>= 7) {
1774 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1775 grf_offset
.type
= offset
.type
;
1777 emit(MOV(grf_offset
, offset
));
1779 vec4_instruction
*pull
=
1780 emit(new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1781 dst_reg(packed_consts
),
1783 src_reg(grf_offset
)));
1786 vec4_instruction
*pull
=
1787 emit(new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
1788 dst_reg(packed_consts
),
1791 pull
->base_mrf
= 14;
1795 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1796 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1797 const_offset
% 16 / 4,
1798 const_offset
% 16 / 4,
1799 const_offset
% 16 / 4);
1801 /* UBO bools are any nonzero int. We need to convert them to use the
1802 * value of true stored in ctx->Const.UniformBooleanTrue.
1804 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1805 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1806 BRW_CONDITIONAL_NZ
));
1808 emit(MOV(result_dst
, packed_consts
));
1813 case ir_binop_vector_extract
:
1814 unreachable("should have been lowered by vec_index_to_cond_assign");
1817 op
[0] = fix_3src_operand(op
[0]);
1818 op
[1] = fix_3src_operand(op
[1]);
1819 op
[2] = fix_3src_operand(op
[2]);
1820 /* Note that the instruction's argument order is reversed from GLSL
1823 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1827 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1831 unreachable("already handled above");
1835 op
[0] = fix_3src_operand(op
[0]);
1836 op
[1] = fix_3src_operand(op
[1]);
1837 op
[2] = fix_3src_operand(op
[2]);
1838 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1841 case ir_triop_bitfield_extract
:
1842 op
[0] = fix_3src_operand(op
[0]);
1843 op
[1] = fix_3src_operand(op
[1]);
1844 op
[2] = fix_3src_operand(op
[2]);
1845 /* Note that the instruction's argument order is reversed from GLSL
1848 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1851 case ir_triop_vector_insert
:
1852 unreachable("should have been lowered by lower_vector_insert");
1854 case ir_quadop_bitfield_insert
:
1855 unreachable("not reached: should be handled by "
1856 "bitfield_insert_to_bfm_bfi\n");
1858 case ir_quadop_vector
:
1859 unreachable("not reached: should be handled by lower_quadop_vector");
1861 case ir_unop_pack_half_2x16
:
1862 emit_pack_half_2x16(result_dst
, op
[0]);
1864 case ir_unop_unpack_half_2x16
:
1865 emit_unpack_half_2x16(result_dst
, op
[0]);
1867 case ir_unop_unpack_unorm_4x8
:
1868 emit_unpack_unorm_4x8(result_dst
, op
[0]);
1870 case ir_unop_unpack_snorm_4x8
:
1871 emit_unpack_snorm_4x8(result_dst
, op
[0]);
1873 case ir_unop_pack_unorm_4x8
:
1874 emit_pack_unorm_4x8(result_dst
, op
[0]);
1876 case ir_unop_pack_snorm_4x8
:
1877 emit_pack_snorm_4x8(result_dst
, op
[0]);
1879 case ir_unop_pack_snorm_2x16
:
1880 case ir_unop_pack_unorm_2x16
:
1881 case ir_unop_unpack_snorm_2x16
:
1882 case ir_unop_unpack_unorm_2x16
:
1883 unreachable("not reached: should be handled by lower_packing_builtins");
1884 case ir_unop_unpack_half_2x16_split_x
:
1885 case ir_unop_unpack_half_2x16_split_y
:
1886 case ir_binop_pack_half_2x16_split
:
1887 case ir_unop_interpolate_at_centroid
:
1888 case ir_binop_interpolate_at_sample
:
1889 case ir_binop_interpolate_at_offset
:
1890 unreachable("not reached: should not occur in vertex shader");
1891 case ir_binop_ldexp
:
1892 unreachable("not reached: should be handled by ldexp_to_arith()");
1900 case ir_unop_pack_double_2x32
:
1901 case ir_unop_unpack_double_2x32
:
1902 case ir_unop_frexp_sig
:
1903 case ir_unop_frexp_exp
:
1904 unreachable("fp64 todo");
1910 vec4_visitor::visit(ir_swizzle
*ir
)
1916 /* Note that this is only swizzles in expressions, not those on the left
1917 * hand side of an assignment, which do write masking. See ir_assignment
1921 ir
->val
->accept(this);
1923 assert(src
.file
!= BAD_FILE
);
1925 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1928 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1931 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1934 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1937 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1941 for (; i
< 4; i
++) {
1942 /* Replicate the last channel out. */
1943 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1946 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1952 vec4_visitor::visit(ir_dereference_variable
*ir
)
1954 const struct glsl_type
*type
= ir
->type
;
1955 dst_reg
*reg
= variable_storage(ir
->var
);
1958 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1959 this->result
= src_reg(brw_null_reg());
1963 this->result
= src_reg(*reg
);
1965 /* System values get their swizzle from the dst_reg writemask */
1966 if (ir
->var
->data
.mode
== ir_var_system_value
)
1969 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1970 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1975 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1977 /* Under normal circumstances array elements are stored consecutively, so
1978 * the stride is equal to the size of the array element.
1980 return type_size(ir
->type
);
1985 vec4_visitor::visit(ir_dereference_array
*ir
)
1987 ir_constant
*constant_index
;
1989 int array_stride
= compute_array_stride(ir
);
1991 constant_index
= ir
->array_index
->constant_expression_value();
1993 ir
->array
->accept(this);
1996 if (constant_index
) {
1997 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1999 /* Variable index array dereference. It eats the "vec4" of the
2000 * base of the array and an index that offsets the Mesa register
2003 ir
->array_index
->accept(this);
2007 if (array_stride
== 1) {
2008 index_reg
= this->result
;
2010 index_reg
= src_reg(this, glsl_type::int_type
);
2012 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
2016 src_reg temp
= src_reg(this, glsl_type::int_type
);
2018 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
2023 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
2024 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2027 /* If the type is smaller than a vec4, replicate the last channel out. */
2028 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2029 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2031 src
.swizzle
= BRW_SWIZZLE_NOOP
;
2032 src
.type
= brw_type_for_base_type(ir
->type
);
2038 vec4_visitor::visit(ir_dereference_record
*ir
)
2041 const glsl_type
*struct_type
= ir
->record
->type
;
2044 ir
->record
->accept(this);
2046 for (i
= 0; i
< struct_type
->length
; i
++) {
2047 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2049 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2052 /* If the type is smaller than a vec4, replicate the last channel out. */
2053 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2054 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2056 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
2057 this->result
.type
= brw_type_for_base_type(ir
->type
);
2059 this->result
.reg_offset
+= offset
;
2063 * We want to be careful in assignment setup to hit the actual storage
2064 * instead of potentially using a temporary like we might with the
2065 * ir_dereference handler.
2068 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
2070 /* The LHS must be a dereference. If the LHS is a variable indexed array
2071 * access of a vector, it must be separated into a series conditional moves
2072 * before reaching this point (see ir_vec_index_to_cond_assign).
2074 assert(ir
->as_dereference());
2075 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2077 assert(!deref_array
->array
->type
->is_vector());
2080 /* Use the rvalue deref handler for the most part. We'll ignore
2081 * swizzles in it and write swizzles using writemask, though.
2084 return dst_reg(v
->result
);
2088 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
2089 const struct glsl_type
*type
,
2090 enum brw_predicate predicate
)
2092 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2093 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2094 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
2099 if (type
->is_array()) {
2100 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2101 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
2106 if (type
->is_matrix()) {
2107 const struct glsl_type
*vec_type
;
2109 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2110 type
->vector_elements
, 1);
2112 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2113 emit_block_move(dst
, src
, vec_type
, predicate
);
2118 assert(type
->is_scalar() || type
->is_vector());
2120 dst
->type
= brw_type_for_base_type(type
);
2121 src
->type
= dst
->type
;
2123 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2125 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
2127 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2128 inst
->predicate
= predicate
;
2135 /* If the RHS processing resulted in an instruction generating a
2136 * temporary value, and it would be easy to rewrite the instruction to
2137 * generate its result right into the LHS instead, do so. This ends
2138 * up reliably removing instructions where it can be tricky to do so
2139 * later without real UD chain information.
2142 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2145 vec4_instruction
*pre_rhs_inst
,
2146 vec4_instruction
*last_rhs_inst
)
2148 /* This could be supported, but it would take more smarts. */
2152 if (pre_rhs_inst
== last_rhs_inst
)
2153 return false; /* No instructions generated to work with. */
2155 /* Make sure the last instruction generated our source reg. */
2156 if (src
.file
!= GRF
||
2157 src
.file
!= last_rhs_inst
->dst
.file
||
2158 src
.reg
!= last_rhs_inst
->dst
.reg
||
2159 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2163 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2166 /* Check that that last instruction fully initialized the channels
2167 * we want to use, in the order we want to use them. We could
2168 * potentially reswizzle the operands of many instructions so that
2169 * we could handle out of order channels, but don't yet.
2172 for (unsigned i
= 0; i
< 4; i
++) {
2173 if (dst
.writemask
& (1 << i
)) {
2174 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2177 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2182 /* Success! Rewrite the instruction. */
2183 last_rhs_inst
->dst
.file
= dst
.file
;
2184 last_rhs_inst
->dst
.reg
= dst
.reg
;
2185 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2186 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2187 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2193 vec4_visitor::visit(ir_assignment
*ir
)
2195 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2196 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2198 if (!ir
->lhs
->type
->is_scalar() &&
2199 !ir
->lhs
->type
->is_vector()) {
2200 ir
->rhs
->accept(this);
2201 src_reg src
= this->result
;
2203 if (ir
->condition
) {
2204 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2207 /* emit_block_move doesn't account for swizzles in the source register.
2208 * This should be ok, since the source register is a structure or an
2209 * array, and those can't be swizzled. But double-check to be sure.
2211 assert(src
.swizzle
==
2212 (ir
->rhs
->type
->is_matrix()
2213 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2214 : BRW_SWIZZLE_NOOP
));
2216 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2220 /* Now we're down to just a scalar/vector with writemasks. */
2223 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2224 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2226 ir
->rhs
->accept(this);
2228 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2230 src_reg src
= this->result
;
2233 int first_enabled_chan
= 0;
2236 assert(ir
->lhs
->type
->is_vector() ||
2237 ir
->lhs
->type
->is_scalar());
2238 dst
.writemask
= ir
->write_mask
;
2240 for (int i
= 0; i
< 4; i
++) {
2241 if (dst
.writemask
& (1 << i
)) {
2242 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2247 /* Swizzle a small RHS vector into the channels being written.
2249 * glsl ir treats write_mask as dictating how many channels are
2250 * present on the RHS while in our instructions we need to make
2251 * those channels appear in the slots of the vec4 they're written to.
2253 for (int i
= 0; i
< 4; i
++) {
2254 if (dst
.writemask
& (1 << i
))
2255 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2257 swizzles
[i
] = first_enabled_chan
;
2259 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2260 swizzles
[2], swizzles
[3]);
2262 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2266 if (ir
->condition
) {
2267 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2270 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2271 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2272 inst
->predicate
= predicate
;
2280 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2282 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2283 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2284 emit_constant_values(dst
, field_value
);
2289 if (ir
->type
->is_array()) {
2290 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2291 emit_constant_values(dst
, ir
->array_elements
[i
]);
2296 if (ir
->type
->is_matrix()) {
2297 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2298 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2300 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2301 dst
->writemask
= 1 << j
;
2302 dst
->type
= BRW_REGISTER_TYPE_F
;
2304 emit(MOV(*dst
, src_reg(vec
[j
])));
2311 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2313 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2314 if (!(remaining_writemask
& (1 << i
)))
2317 dst
->writemask
= 1 << i
;
2318 dst
->type
= brw_type_for_base_type(ir
->type
);
2320 /* Find other components that match the one we're about to
2321 * write. Emits fewer instructions for things like vec4(0.5,
2324 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2325 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2326 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2327 dst
->writemask
|= (1 << j
);
2329 /* u, i, and f storage all line up, so no need for a
2330 * switch case for comparing each type.
2332 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2333 dst
->writemask
|= (1 << j
);
2337 switch (ir
->type
->base_type
) {
2338 case GLSL_TYPE_FLOAT
:
2339 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2342 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2344 case GLSL_TYPE_UINT
:
2345 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2347 case GLSL_TYPE_BOOL
:
2349 src_reg(ir
->value
.b
[i
] != 0 ? (int)ctx
->Const
.UniformBooleanTrue
2353 unreachable("Non-float/uint/int/bool constant");
2356 remaining_writemask
&= ~dst
->writemask
;
2362 vec4_visitor::visit(ir_constant
*ir
)
2364 dst_reg dst
= dst_reg(this, ir
->type
);
2365 this->result
= src_reg(dst
);
2367 emit_constant_values(&dst
, ir
);
2371 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2373 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2374 ir
->actual_parameters
.get_head());
2375 ir_variable
*location
= deref
->variable_referenced();
2376 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2377 location
->data
.binding
);
2379 /* Calculate the surface offset */
2380 src_reg
offset(this, glsl_type::uint_type
);
2381 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2383 deref_array
->array_index
->accept(this);
2385 src_reg
tmp(this, glsl_type::uint_type
);
2386 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2387 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2389 offset
= location
->data
.atomic
.offset
;
2392 /* Emit the appropriate machine instruction */
2393 const char *callee
= ir
->callee
->function_name();
2394 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2396 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2397 emit_untyped_surface_read(surf_index
, dst
, offset
);
2399 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2400 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2401 src_reg(), src_reg());
2403 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2404 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2405 src_reg(), src_reg());
2410 vec4_visitor::visit(ir_call
*ir
)
2412 const char *callee
= ir
->callee
->function_name();
2414 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2415 !strcmp("__intrinsic_atomic_increment", callee
) ||
2416 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2417 visit_atomic_counter_intrinsic(ir
);
2419 unreachable("Unsupported intrinsic.");
2424 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
)
2426 vec4_instruction
*inst
=
2427 new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
,
2428 dst_reg(this, glsl_type::uvec4_type
));
2431 inst
->src
[1] = sampler
;
2433 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2434 int param_base
= inst
->base_mrf
;
2435 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2436 int zero_mask
= 0xf & ~coord_mask
;
2438 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2441 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2445 return src_reg(inst
->dst
);
2449 is_high_sampler(struct brw_context
*brw
, src_reg sampler
)
2451 if (brw
->gen
< 8 && !brw
->is_haswell
)
2454 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2458 vec4_visitor::visit(ir_texture
*ir
)
2461 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2463 ir_rvalue
*nonconst_sampler_index
=
2464 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2466 /* Handle non-constant sampler array indexing */
2467 src_reg sampler_reg
;
2468 if (nonconst_sampler_index
) {
2469 /* The highest sampler which may be used by this operation is
2470 * the last element of the array. Mark it here, because the generator
2471 * doesn't have enough information to determine the bound.
2473 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2474 ->array
->type
->array_size();
2476 uint32_t max_used
= sampler
+ array_size
- 1;
2477 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
2478 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2480 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2483 brw_mark_surface_used(&prog_data
->base
, max_used
);
2485 /* Emit code to evaluate the actual indexing expression */
2486 nonconst_sampler_index
->accept(this);
2487 dst_reg
temp(this, glsl_type::uint_type
);
2488 emit(ADD(temp
, this->result
, src_reg(sampler
)))
2489 ->force_writemask_all
= true;
2490 sampler_reg
= src_reg(temp
);
2492 /* Single sampler, or constant array index; the indexing expression
2493 * is just an immediate.
2495 sampler_reg
= src_reg(sampler
);
2498 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2499 * emitting anything other than setting up the constant result.
2501 if (ir
->op
== ir_tg4
) {
2502 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2503 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2504 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2505 dst_reg
result(this, ir
->type
);
2506 this->result
= src_reg(result
);
2507 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2512 /* Should be lowered by do_lower_texture_projection */
2513 assert(!ir
->projector
);
2515 /* Should be lowered */
2516 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2518 /* Generate code to compute all the subexpression trees. This has to be
2519 * done before loading any values into MRFs for the sampler message since
2520 * generating these values may involve SEND messages that need the MRFs.
2523 if (ir
->coordinate
) {
2524 ir
->coordinate
->accept(this);
2525 coordinate
= this->result
;
2528 src_reg shadow_comparitor
;
2529 if (ir
->shadow_comparitor
) {
2530 ir
->shadow_comparitor
->accept(this);
2531 shadow_comparitor
= this->result
;
2534 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2535 src_reg offset_value
;
2536 if (has_nonconstant_offset
) {
2537 ir
->offset
->accept(this);
2538 offset_value
= src_reg(this->result
);
2541 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2542 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2545 lod
= src_reg(0.0f
);
2546 lod_type
= glsl_type::float_type
;
2551 ir
->lod_info
.lod
->accept(this);
2553 lod_type
= ir
->lod_info
.lod
->type
;
2555 case ir_query_levels
:
2557 lod_type
= glsl_type::int_type
;
2560 ir
->lod_info
.sample_index
->accept(this);
2561 sample_index
= this->result
;
2562 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2564 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2565 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
2570 ir
->lod_info
.grad
.dPdx
->accept(this);
2571 dPdx
= this->result
;
2573 ir
->lod_info
.grad
.dPdy
->accept(this);
2574 dPdy
= this->result
;
2576 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2586 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2587 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2588 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2589 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2590 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2591 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2592 case ir_tg4
: opcode
= has_nonconstant_offset
2593 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2594 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2596 unreachable("TXB is not valid for vertex shaders.");
2598 unreachable("LOD is not valid for vertex shaders.");
2600 unreachable("Unrecognized tex op");
2603 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(
2604 opcode
, dst_reg(this, ir
->type
));
2606 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2608 brw_texture_offset(ctx
, ir
->offset
->as_constant()->value
.i
,
2609 ir
->offset
->type
->vector_elements
);
2612 /* Stuff the channel select bits in the top of the texture offset */
2613 if (ir
->op
== ir_tg4
)
2614 inst
->offset
|= gather_channel(ir
, sampler
) << 16;
2616 /* The message header is necessary for:
2618 * - Gen9+ for selecting SIMD4x2
2620 * - Gather channel selection
2621 * - Sampler indices too large to fit in a 4-bit value.
2623 inst
->header_present
=
2624 brw
->gen
< 5 || brw
->gen
>= 9 ||
2625 inst
->offset
!= 0 || ir
->op
== ir_tg4
||
2626 is_high_sampler(brw
, sampler_reg
);
2628 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2629 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2630 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2632 inst
->src
[1] = sampler_reg
;
2634 /* MRF for the first parameter */
2635 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2637 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2638 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2639 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2641 /* Load the coordinate */
2642 /* FINISHME: gl_clamp_mask and saturate */
2643 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2644 int zero_mask
= 0xf & ~coord_mask
;
2646 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2649 if (zero_mask
!= 0) {
2650 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2653 /* Load the shadow comparitor */
2654 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2655 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2657 shadow_comparitor
));
2661 /* Load the LOD info */
2662 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2664 if (brw
->gen
>= 5) {
2665 mrf
= param_base
+ 1;
2666 if (ir
->shadow_comparitor
) {
2667 writemask
= WRITEMASK_Y
;
2668 /* mlen already incremented */
2670 writemask
= WRITEMASK_X
;
2673 } else /* brw->gen == 4 */ {
2675 writemask
= WRITEMASK_W
;
2677 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2678 } else if (ir
->op
== ir_txf
) {
2679 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2680 } else if (ir
->op
== ir_txf_ms
) {
2681 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2683 if (brw
->gen
>= 7) {
2684 /* MCS data is in the first channel of `mcs`, but we need to get it into
2685 * the .y channel of the second vec4 of params, so replicate .x across
2686 * the whole vec4 and then mask off everything except .y
2688 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2689 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2693 } else if (ir
->op
== ir_txd
) {
2694 const glsl_type
*type
= lod_type
;
2696 if (brw
->gen
>= 5) {
2697 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2698 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2699 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2700 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2703 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2704 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2705 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2706 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2707 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2710 if (ir
->shadow_comparitor
) {
2711 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2712 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2713 shadow_comparitor
));
2716 } else /* brw->gen == 4 */ {
2717 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2718 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2721 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2722 if (ir
->shadow_comparitor
) {
2723 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2724 shadow_comparitor
));
2727 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2735 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2736 * spec requires layers.
2738 if (ir
->op
== ir_txs
) {
2739 glsl_type
const *type
= ir
->sampler
->type
;
2740 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2741 type
->sampler_array
) {
2742 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2743 writemask(inst
->dst
, WRITEMASK_Z
),
2744 src_reg(inst
->dst
), src_reg(6));
2748 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2749 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2752 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2756 * Apply workarounds for Gen6 gather with UINT/SINT
2759 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2764 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2765 dst_reg dst_f
= dst
;
2766 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2768 /* Convert from UNORM to UINT */
2769 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2770 emit(MOV(dst
, src_reg(dst_f
)));
2773 /* Reinterpret the UINT value as a signed INT value by
2774 * shifting the sign bit into place, then shifting back
2777 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2778 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2783 * Set up the gather channel based on the swizzle, for gather4.
2786 vec4_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2788 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2789 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2791 case SWIZZLE_X
: return 0;
2793 /* gather4 sampler is broken for green channel on RG32F --
2794 * we must ask for blue instead.
2796 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2799 case SWIZZLE_Z
: return 2;
2800 case SWIZZLE_W
: return 3;
2802 unreachable("Not reached"); /* zero, one swizzles handled already */
2807 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
)
2809 int s
= key
->tex
.swizzles
[sampler
];
2811 this->result
= src_reg(this, ir
->type
);
2812 dst_reg
swizzled_result(this->result
);
2814 if (ir
->op
== ir_query_levels
) {
2815 /* # levels is in .w */
2816 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2817 emit(MOV(swizzled_result
, orig_val
));
2821 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2822 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2823 emit(MOV(swizzled_result
, orig_val
));
2828 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2829 int swizzle
[4] = {0};
2831 for (int i
= 0; i
< 4; i
++) {
2832 switch (GET_SWZ(s
, i
)) {
2834 zero_mask
|= (1 << i
);
2837 one_mask
|= (1 << i
);
2840 copy_mask
|= (1 << i
);
2841 swizzle
[i
] = GET_SWZ(s
, i
);
2847 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2848 swizzled_result
.writemask
= copy_mask
;
2849 emit(MOV(swizzled_result
, orig_val
));
2853 swizzled_result
.writemask
= zero_mask
;
2854 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2858 swizzled_result
.writemask
= one_mask
;
2859 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2864 vec4_visitor::visit(ir_return
*)
2866 unreachable("not reached");
2870 vec4_visitor::visit(ir_discard
*)
2872 unreachable("not reached");
2876 vec4_visitor::visit(ir_if
*ir
)
2878 /* Don't point the annotation at the if statement, because then it plus
2879 * the then and else blocks get printed.
2881 this->base_ir
= ir
->condition
;
2883 if (brw
->gen
== 6) {
2886 enum brw_predicate predicate
;
2887 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2888 emit(IF(predicate
));
2891 visit_instructions(&ir
->then_instructions
);
2893 if (!ir
->else_instructions
.is_empty()) {
2894 this->base_ir
= ir
->condition
;
2895 emit(BRW_OPCODE_ELSE
);
2897 visit_instructions(&ir
->else_instructions
);
2900 this->base_ir
= ir
->condition
;
2901 emit(BRW_OPCODE_ENDIF
);
2905 vec4_visitor::visit(ir_emit_vertex
*)
2907 unreachable("not reached");
2911 vec4_visitor::visit(ir_end_primitive
*)
2913 unreachable("not reached");
2917 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2918 dst_reg dst
, src_reg offset
,
2919 src_reg src0
, src_reg src1
)
2923 /* Set the atomic operation offset. */
2924 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2927 /* Set the atomic operation arguments. */
2928 if (src0
.file
!= BAD_FILE
) {
2929 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2933 if (src1
.file
!= BAD_FILE
) {
2934 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2938 /* Emit the instruction. Note that this maps to the normal SIMD8
2939 * untyped atomic message on Ivy Bridge, but that's OK because
2940 * unused channels will be masked out.
2942 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2943 src_reg(atomic_op
), src_reg(surf_index
));
2949 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
2952 /* Set the surface read offset. */
2953 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
2955 /* Emit the instruction. Note that this maps to the normal SIMD8
2956 * untyped surface read message, but that's OK because unused
2957 * channels will be masked out.
2959 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
,
2960 dst
, src_reg(surf_index
));
2966 vec4_visitor::emit_ndc_computation()
2968 /* Get the position */
2969 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2971 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2972 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2973 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2975 current_annotation
= "NDC";
2976 dst_reg ndc_w
= ndc
;
2977 ndc_w
.writemask
= WRITEMASK_W
;
2978 src_reg pos_w
= pos
;
2979 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2980 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2982 dst_reg ndc_xyz
= ndc
;
2983 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2985 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2989 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
2992 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2993 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2994 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2995 dst_reg header1_w
= header1
;
2996 header1_w
.writemask
= WRITEMASK_W
;
2998 emit(MOV(header1
, 0u));
3000 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3001 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
3003 current_annotation
= "Point size";
3004 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
3005 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
3008 if (key
->userclip_active
) {
3009 current_annotation
= "Clipping flags";
3010 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
3011 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
3013 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3014 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
3015 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
3017 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3018 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
3019 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
3020 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
3023 /* i965 clipping workaround:
3024 * 1) Test for -ve rhw
3026 * set ndc = (0,0,0,0)
3029 * Later, clipping will detect ucp[6] and ensure the primitive is
3030 * clipped against all fixed planes.
3032 if (brw
->has_negative_rhw_bug
) {
3033 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
3034 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
3035 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
3036 vec4_instruction
*inst
;
3037 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
3038 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3039 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
3040 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3043 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
3044 } else if (brw
->gen
< 6) {
3045 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
3047 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
3048 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3049 dst_reg reg_w
= reg
;
3050 reg_w
.writemask
= WRITEMASK_W
;
3051 emit(MOV(reg_w
, src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
3053 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
3054 dst_reg reg_y
= reg
;
3055 reg_y
.writemask
= WRITEMASK_Y
;
3056 reg_y
.type
= BRW_REGISTER_TYPE_D
;
3057 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
3059 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
3060 dst_reg reg_z
= reg
;
3061 reg_z
.writemask
= WRITEMASK_Z
;
3062 reg_z
.type
= BRW_REGISTER_TYPE_D
;
3063 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
3069 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
3071 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3073 * "If a linked set of shaders forming the vertex stage contains no
3074 * static write to gl_ClipVertex or gl_ClipDistance, but the
3075 * application has requested clipping against user clip planes through
3076 * the API, then the coordinate written to gl_Position is used for
3077 * comparison against the user clip planes."
3079 * This function is only called if the shader didn't write to
3080 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3081 * if the user wrote to it; otherwise we use gl_Position.
3083 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3084 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
3085 clip_vertex
= VARYING_SLOT_POS
;
3088 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
3090 reg
.writemask
= 1 << i
;
3092 src_reg(output_reg
[clip_vertex
]),
3093 src_reg(this->userplane
[i
+ offset
])));
3098 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
3100 assert (varying
< VARYING_SLOT_MAX
);
3101 reg
.type
= output_reg
[varying
].type
;
3102 current_annotation
= output_reg_annotation
[varying
];
3103 /* Copy the register, saturating if necessary */
3104 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
3108 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
3110 reg
.type
= BRW_REGISTER_TYPE_F
;
3113 case VARYING_SLOT_PSIZ
:
3115 /* PSIZ is always in slot 0, and is coupled with other flags. */
3116 current_annotation
= "indices, point width, clip flags";
3117 emit_psiz_and_flags(reg
);
3120 case BRW_VARYING_SLOT_NDC
:
3121 current_annotation
= "NDC";
3122 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
3124 case VARYING_SLOT_POS
:
3125 current_annotation
= "gl_Position";
3126 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
3128 case VARYING_SLOT_EDGE
:
3129 /* This is present when doing unfilled polygons. We're supposed to copy
3130 * the edge flag from the user-provided vertex array
3131 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3132 * of that attribute (starts as 1.0f). This is then used in clipping to
3133 * determine which edges should be drawn as wireframe.
3135 current_annotation
= "edge flag";
3136 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3137 glsl_type::float_type
, WRITEMASK_XYZW
))));
3139 case BRW_VARYING_SLOT_PAD
:
3140 /* No need to write to this slot */
3142 case VARYING_SLOT_COL0
:
3143 case VARYING_SLOT_COL1
:
3144 case VARYING_SLOT_BFC0
:
3145 case VARYING_SLOT_BFC1
: {
3146 /* These built-in varyings are only supported in compatibility mode,
3147 * and we only support GS in core profile. So, this must be a vertex
3150 assert(stage
== MESA_SHADER_VERTEX
);
3151 vec4_instruction
*inst
= emit_generic_urb_slot(reg
, varying
);
3152 if (((struct brw_vs_prog_key
*) key
)->clamp_vertex_color
)
3153 inst
->saturate
= true;
3158 emit_generic_urb_slot(reg
, varying
);
3164 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
3166 if (brw
->gen
>= 6) {
3167 /* URB data written (does not include the message header reg) must
3168 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3169 * section 5.4.3.2.2: URB_INTERLEAVED.
3171 * URB entries are allocated on a multiple of 1024 bits, so an
3172 * extra 128 bits written here to make the end align to 256 is
3175 if ((mlen
% 2) != 1)
3184 * Generates the VUE payload plus the necessary URB write instructions to
3187 * The VUE layout is documented in Volume 2a.
3190 vec4_visitor::emit_vertex()
3192 /* MRF 0 is reserved for the debugger, so start with message header
3197 /* In the process of generating our URB write message contents, we
3198 * may need to unspill a register or load from an array. Those
3199 * reads would use MRFs 14-15.
3201 int max_usable_mrf
= 13;
3203 /* The following assertion verifies that max_usable_mrf causes an
3204 * even-numbered amount of URB write data, which will meet gen6's
3205 * requirements for length alignment.
3207 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3209 /* First mrf is the g0-based message header containing URB handles and
3212 emit_urb_write_header(mrf
++);
3215 emit_ndc_computation();
3218 /* Lower legacy ff and ClipVertex clipping to clip distances */
3219 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3220 current_annotation
= "user clip distances";
3222 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3223 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3225 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3226 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3229 /* We may need to split this up into several URB writes, so do them in a
3233 bool complete
= false;
3235 /* URB offset is in URB row increments, and each of our MRFs is half of
3236 * one of those, since we're doing interleaved writes.
3238 int offset
= slot
/ 2;
3241 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3242 emit_urb_slot(dst_reg(MRF
, mrf
++),
3243 prog_data
->vue_map
.slot_to_varying
[slot
]);
3245 /* If this was max_usable_mrf, we can't fit anything more into this
3248 if (mrf
> max_usable_mrf
) {
3254 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3255 current_annotation
= "URB write";
3256 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3257 inst
->base_mrf
= base_mrf
;
3258 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
3259 inst
->offset
+= offset
;
3265 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3266 src_reg
*reladdr
, int reg_offset
)
3268 /* Because we store the values to scratch interleaved like our
3269 * vertex data, we need to scale the vec4 index by 2.
3271 int message_header_scale
= 2;
3273 /* Pre-gen6, the message header uses byte offsets instead of vec4
3274 * (16-byte) offset units.
3277 message_header_scale
*= 16;
3280 src_reg index
= src_reg(this, glsl_type::int_type
);
3282 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3283 src_reg(reg_offset
)));
3284 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3285 src_reg(message_header_scale
)));
3289 return src_reg(reg_offset
* message_header_scale
);
3294 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3295 src_reg
*reladdr
, int reg_offset
)
3298 src_reg index
= src_reg(this, glsl_type::int_type
);
3300 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3301 src_reg(reg_offset
)));
3303 /* Pre-gen6, the message header uses byte offsets instead of vec4
3304 * (16-byte) offset units.
3307 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3311 } else if (brw
->gen
>= 8) {
3312 /* Store the offset in a GRF so we can send-from-GRF. */
3313 src_reg offset
= src_reg(this, glsl_type::int_type
);
3314 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3317 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
3318 return src_reg(reg_offset
* message_header_scale
);
3323 * Emits an instruction before @inst to load the value named by @orig_src
3324 * from scratch space at @base_offset to @temp.
3326 * @base_offset is measured in 32-byte units (the size of a register).
3329 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3330 dst_reg temp
, src_reg orig_src
,
3333 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3334 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3337 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3341 * Emits an instruction after @inst to store the value to be written
3342 * to @orig_dst to scratch space at @base_offset, from @temp.
3344 * @base_offset is measured in 32-byte units (the size of a register).
3347 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3350 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3351 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3354 /* Create a temporary register to store *inst's result in.
3356 * We have to be careful in MOVing from our temporary result register in
3357 * the scratch write. If we swizzle from channels of the temporary that
3358 * weren't initialized, it will confuse live interval analysis, which will
3359 * make spilling fail to make progress.
3361 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
3362 temp
.type
= inst
->dst
.type
;
3363 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
3365 for (int i
= 0; i
< 4; i
++)
3366 if (inst
->dst
.writemask
& (1 << i
))
3369 swizzles
[i
] = first_writemask_chan
;
3370 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3371 swizzles
[2], swizzles
[3]);
3373 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3374 inst
->dst
.writemask
));
3375 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3376 write
->predicate
= inst
->predicate
;
3377 write
->ir
= inst
->ir
;
3378 write
->annotation
= inst
->annotation
;
3379 inst
->insert_after(block
, write
);
3381 inst
->dst
.file
= temp
.file
;
3382 inst
->dst
.reg
= temp
.reg
;
3383 inst
->dst
.reg_offset
= temp
.reg_offset
;
3384 inst
->dst
.reladdr
= NULL
;
3388 * We can't generally support array access in GRF space, because a
3389 * single instruction's destination can only span 2 contiguous
3390 * registers. So, we send all GRF arrays that get variable index
3391 * access to scratch space.
3394 vec4_visitor::move_grf_array_access_to_scratch()
3396 int scratch_loc
[this->alloc
.count
];
3397 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3399 /* First, calculate the set of virtual GRFs that need to be punted
3400 * to scratch due to having any array access on them, and where in
3403 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3404 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3405 scratch_loc
[inst
->dst
.reg
] == -1) {
3406 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3407 c
->last_scratch
+= this->alloc
.sizes
[inst
->dst
.reg
];
3410 for (int i
= 0 ; i
< 3; i
++) {
3411 src_reg
*src
= &inst
->src
[i
];
3413 if (src
->file
== GRF
&& src
->reladdr
&&
3414 scratch_loc
[src
->reg
] == -1) {
3415 scratch_loc
[src
->reg
] = c
->last_scratch
;
3416 c
->last_scratch
+= this->alloc
.sizes
[src
->reg
];
3421 /* Now, for anything that will be accessed through scratch, rewrite
3422 * it to load/store. Note that this is a _safe list walk, because
3423 * we may generate a new scratch_write instruction after the one
3426 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3427 /* Set up the annotation tracking for new generated instructions. */
3429 current_annotation
= inst
->annotation
;
3431 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3432 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3435 for (int i
= 0 ; i
< 3; i
++) {
3436 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3439 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3441 emit_scratch_read(block
, inst
, temp
, inst
->src
[i
],
3442 scratch_loc
[inst
->src
[i
].reg
]);
3444 inst
->src
[i
].file
= temp
.file
;
3445 inst
->src
[i
].reg
= temp
.reg
;
3446 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3447 inst
->src
[i
].reladdr
= NULL
;
3453 * Emits an instruction before @inst to load the value named by @orig_src
3454 * from the pull constant buffer (surface) at @base_offset to @temp.
3457 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3458 dst_reg temp
, src_reg orig_src
,
3461 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3462 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3463 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3465 vec4_instruction
*load
;
3467 if (brw
->gen
>= 7) {
3468 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3469 grf_offset
.type
= offset
.type
;
3470 emit_before(block
, inst
, MOV(grf_offset
, offset
));
3472 load
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3473 temp
, index
, src_reg(grf_offset
));
3476 load
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
3477 temp
, index
, offset
);
3478 load
->base_mrf
= 14;
3481 emit_before(block
, inst
, load
);
3485 * Implements array access of uniforms by inserting a
3486 * PULL_CONSTANT_LOAD instruction.
3488 * Unlike temporary GRF array access (where we don't support it due to
3489 * the difficulty of doing relative addressing on instruction
3490 * destinations), we could potentially do array access of uniforms
3491 * that were loaded in GRF space as push constants. In real-world
3492 * usage we've seen, though, the arrays being used are always larger
3493 * than we could load as push constants, so just always move all
3494 * uniform array access out to a pull constant buffer.
3497 vec4_visitor::move_uniform_array_access_to_pull_constants()
3499 int pull_constant_loc
[this->uniforms
];
3500 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3501 bool nested_reladdr
;
3503 /* Walk through and find array access of uniforms. Put a copy of that
3504 * uniform in the pull constant buffer.
3506 * Note that we don't move constant-indexed accesses to arrays. No
3507 * testing has been done of the performance impact of this choice.
3510 nested_reladdr
= false;
3512 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3513 for (int i
= 0 ; i
< 3; i
++) {
3514 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3517 int uniform
= inst
->src
[i
].reg
;
3519 if (inst
->src
[i
].reladdr
->reladdr
)
3520 nested_reladdr
= true; /* will need another pass */
3522 /* If this array isn't already present in the pull constant buffer,
3525 if (pull_constant_loc
[uniform
] == -1) {
3526 const gl_constant_value
**values
=
3527 &stage_prog_data
->param
[uniform
* 4];
3529 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3531 assert(uniform
< uniform_array_size
);
3532 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3533 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3538 /* Set up the annotation tracking for new generated instructions. */
3540 current_annotation
= inst
->annotation
;
3542 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3544 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3545 pull_constant_loc
[uniform
]);
3547 inst
->src
[i
].file
= temp
.file
;
3548 inst
->src
[i
].reg
= temp
.reg
;
3549 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3550 inst
->src
[i
].reladdr
= NULL
;
3553 } while (nested_reladdr
);
3555 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3556 * no need to track them as larger-than-vec4 objects. This will be
3557 * relied on in cutting out unused uniform vectors from push
3560 split_uniform_registers();
3564 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3566 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3570 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3571 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3576 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3578 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3579 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3582 vec4_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, src_reg
*reg
)
3584 assert(brw
->gen
<= 5);
3586 if (!rvalue
->type
->is_boolean())
3589 src_reg and_result
= src_reg(this, rvalue
->type
);
3590 src_reg neg_result
= src_reg(this, rvalue
->type
);
3591 emit(AND(dst_reg(and_result
), *reg
, src_reg(1)));
3592 emit(MOV(dst_reg(neg_result
), negate(and_result
)));
3596 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3597 struct brw_vec4_compile
*c
,
3598 struct gl_program
*prog
,
3599 const struct brw_vue_prog_key
*key
,
3600 struct brw_vue_prog_data
*prog_data
,
3601 struct gl_shader_program
*shader_prog
,
3602 gl_shader_stage stage
,
3605 shader_time_shader_type st_base
,
3606 shader_time_shader_type st_written
,
3607 shader_time_shader_type st_reset
)
3608 : backend_visitor(brw
, shader_prog
, prog
, &prog_data
->base
, stage
),
3611 prog_data(prog_data
),
3612 sanity_param_count(0),
3614 first_non_payload_grf(0),
3615 need_all_constants_in_pull_buffer(false),
3616 no_spills(no_spills
),
3618 st_written(st_written
),
3621 this->mem_ctx
= mem_ctx
;
3622 this->failed
= false;
3624 this->base_ir
= NULL
;
3625 this->current_annotation
= NULL
;
3626 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3628 this->variable_ht
= hash_table_ctor(0,
3629 hash_table_pointer_hash
,
3630 hash_table_pointer_compare
);
3632 this->virtual_grf_start
= NULL
;
3633 this->virtual_grf_end
= NULL
;
3634 this->live_intervals
= NULL
;
3636 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3640 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3641 * at least one. See setup_uniforms() in brw_vec4.cpp.
3643 this->uniform_array_size
= 1;
3645 this->uniform_array_size
= MAX2(stage_prog_data
->nr_params
, 1);
3648 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3649 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3652 vec4_visitor::~vec4_visitor()
3654 hash_table_dtor(this->variable_ht
);
3659 vec4_visitor::fail(const char *format
, ...)
3669 va_start(va
, format
);
3670 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3672 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
3674 this->fail_msg
= msg
;
3676 if (debug_enabled
) {
3677 fprintf(stderr
, "%s", msg
);
3681 } /* namespace brw */