2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
28 #include "main/context.h"
29 #include "main/macros.h"
30 #include "program/prog_parameter.h"
31 #include "program/sampler.h"
36 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
37 enum opcode opcode
, dst_reg dst
,
38 src_reg src0
, src_reg src1
, src_reg src2
)
40 this->opcode
= opcode
;
45 this->ir
= v
->base_ir
;
46 this->annotation
= v
->current_annotation
;
50 vec4_visitor::emit(vec4_instruction
*inst
)
52 this->instructions
.push_tail(inst
);
58 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
60 new_inst
->ir
= inst
->ir
;
61 new_inst
->annotation
= inst
->annotation
;
63 inst
->insert_before(new_inst
);
69 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
70 src_reg src0
, src_reg src1
, src_reg src2
)
72 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
78 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
80 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
84 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
86 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
90 vec4_visitor::emit(enum opcode opcode
)
92 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
97 vec4_visitor::op(dst_reg dst, src_reg src0) \
99 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
105 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
107 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
113 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1, src_reg src2)\
115 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
149 /** Gen4 predicated IF. */
151 vec4_visitor::IF(uint32_t predicate
)
153 vec4_instruction
*inst
;
155 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
156 inst
->predicate
= predicate
;
161 /** Gen6+ IF with embedded comparison. */
163 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
165 assert(brw
->gen
>= 6);
167 vec4_instruction
*inst
;
169 resolve_ud_negate(&src0
);
170 resolve_ud_negate(&src1
);
172 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
174 inst
->conditional_mod
= condition
;
180 * CMP: Sets the low bit of the destination channels with the result
181 * of the comparison, while the upper bits are undefined, and updates
182 * the flag register with the packed 16 bits of the result.
185 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
187 vec4_instruction
*inst
;
189 /* original gen4 does type conversion to the destination type
190 * before before comparison, producing garbage results for floating
194 dst
.type
= src0
.type
;
195 if (dst
.file
== HW_REG
)
196 dst
.fixed_hw_reg
.type
= dst
.type
;
199 resolve_ud_negate(&src0
);
200 resolve_ud_negate(&src1
);
202 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
203 inst
->conditional_mod
= condition
;
209 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
211 vec4_instruction
*inst
;
213 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_READ
,
222 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
224 vec4_instruction
*inst
;
226 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_WRITE
,
235 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
237 static enum opcode dot_opcodes
[] = {
238 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
241 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
245 vec4_visitor::fix_3src_operand(src_reg src
)
247 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
248 * able to use vertical stride of zero to replicate the vec4 uniform, like
250 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
252 * But you can't, since vertical stride is always four in three-source
253 * instructions. Instead, insert a MOV instruction to do the replication so
254 * that the three-source instruction can consume it.
257 /* The MOV is only needed if the source is a uniform or immediate. */
258 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
261 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
262 expanded
.type
= src
.type
;
263 emit(MOV(expanded
, src
));
264 return src_reg(expanded
);
268 vec4_visitor::fix_math_operand(src_reg src
)
270 /* The gen6 math instruction ignores the source modifiers --
271 * swizzle, abs, negate, and at least some parts of the register
272 * region description.
274 * Rather than trying to enumerate all these cases, *always* expand the
275 * operand to a temp GRF for gen6.
277 * For gen7, keep the operand as-is, except if immediate, which gen7 still
281 if (brw
->gen
== 7 && src
.file
!= IMM
)
284 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
285 expanded
.type
= src
.type
;
286 emit(MOV(expanded
, src
));
287 return src_reg(expanded
);
291 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
293 src
= fix_math_operand(src
);
295 if (dst
.writemask
!= WRITEMASK_XYZW
) {
296 /* The gen6 math instruction must be align1, so we can't do
299 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
301 emit(opcode
, temp_dst
, src
);
303 emit(MOV(dst
, src_reg(temp_dst
)));
305 emit(opcode
, dst
, src
);
310 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
312 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
318 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
321 case SHADER_OPCODE_RCP
:
322 case SHADER_OPCODE_RSQ
:
323 case SHADER_OPCODE_SQRT
:
324 case SHADER_OPCODE_EXP2
:
325 case SHADER_OPCODE_LOG2
:
326 case SHADER_OPCODE_SIN
:
327 case SHADER_OPCODE_COS
:
330 assert(!"not reached: bad math opcode");
335 return emit_math1_gen6(opcode
, dst
, src
);
337 return emit_math1_gen4(opcode
, dst
, src
);
342 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
343 dst_reg dst
, src_reg src0
, src_reg src1
)
345 src0
= fix_math_operand(src0
);
346 src1
= fix_math_operand(src1
);
348 if (dst
.writemask
!= WRITEMASK_XYZW
) {
349 /* The gen6 math instruction must be align1, so we can't do
352 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
353 temp_dst
.type
= dst
.type
;
355 emit(opcode
, temp_dst
, src0
, src1
);
357 emit(MOV(dst
, src_reg(temp_dst
)));
359 emit(opcode
, dst
, src0
, src1
);
364 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
365 dst_reg dst
, src_reg src0
, src_reg src1
)
367 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
373 vec4_visitor::emit_math(enum opcode opcode
,
374 dst_reg dst
, src_reg src0
, src_reg src1
)
377 case SHADER_OPCODE_POW
:
378 case SHADER_OPCODE_INT_QUOTIENT
:
379 case SHADER_OPCODE_INT_REMAINDER
:
382 assert(!"not reached: unsupported binary math opcode");
387 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
389 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
394 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
397 assert(!"ir_unop_pack_half_2x16 should be lowered");
399 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
400 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
402 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
404 * Because this instruction does not have a 16-bit floating-point type,
405 * the destination data type must be Word (W).
407 * The destination must be DWord-aligned and specify a horizontal stride
408 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
409 * each destination channel and the upper word is not modified.
411 * The above restriction implies that the f32to16 instruction must use
412 * align1 mode, because only in align1 mode is it possible to specify
413 * horizontal stride. We choose here to defy the hardware docs and emit
414 * align16 instructions.
416 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
417 * instructions. I was partially successful in that the code passed all
418 * tests. However, the code was dubiously correct and fragile, and the
419 * tests were not harsh enough to probe that frailty. Not trusting the
420 * code, I chose instead to remain in align16 mode in defiance of the hw
423 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
424 * simulator, emitting a f32to16 in align16 mode with UD as destination
425 * data type is safe. The behavior differs from that specified in the PRM
426 * in that the upper word of each destination channel is cleared to 0.
429 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
430 src_reg
tmp_src(tmp_dst
);
433 /* Verify the undocumented behavior on which the following instructions
434 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
435 * then the result of the bit-or instruction below will be incorrect.
437 * You should inspect the disasm output in order to verify that the MOV is
438 * not optimized away.
440 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
443 /* Give tmp the form below, where "." means untouched.
446 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
448 * That the upper word of each write-channel be 0 is required for the
449 * following bit-shift and bit-or instructions to work. Note that this
450 * relies on the undocumented hardware behavior mentioned above.
452 tmp_dst
.writemask
= WRITEMASK_XY
;
453 emit(F32TO16(tmp_dst
, src0
));
455 /* Give the write-channels of dst the form:
458 tmp_src
.swizzle
= SWIZZLE_Y
;
459 emit(SHL(dst
, tmp_src
, src_reg(16u)));
461 /* Finally, give the write-channels of dst the form of packHalf2x16's
465 tmp_src
.swizzle
= SWIZZLE_X
;
466 emit(OR(dst
, src_reg(dst
), tmp_src
));
470 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
473 assert(!"ir_unop_unpack_half_2x16 should be lowered");
475 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
476 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
478 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
480 * Because this instruction does not have a 16-bit floating-point type,
481 * the source data type must be Word (W). The destination type must be
484 * To use W as the source data type, we must adjust horizontal strides,
485 * which is only possible in align1 mode. All my [chadv] attempts at
486 * emitting align1 instructions for unpackHalf2x16 failed to pass the
487 * Piglit tests, so I gave up.
489 * I've verified that, on gen7 hardware and the simulator, it is safe to
490 * emit f16to32 in align16 mode with UD as source data type.
493 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
494 src_reg
tmp_src(tmp_dst
);
496 tmp_dst
.writemask
= WRITEMASK_X
;
497 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
499 tmp_dst
.writemask
= WRITEMASK_Y
;
500 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
502 dst
.writemask
= WRITEMASK_XY
;
503 emit(F16TO32(dst
, tmp_src
));
507 vec4_visitor::visit_instructions(const exec_list
*list
)
509 foreach_list(node
, list
) {
510 ir_instruction
*ir
= (ir_instruction
*)node
;
519 type_size(const struct glsl_type
*type
)
524 switch (type
->base_type
) {
527 case GLSL_TYPE_FLOAT
:
529 if (type
->is_matrix()) {
530 return type
->matrix_columns
;
532 /* Regardless of size of vector, it gets a vec4. This is bad
533 * packing for things like floats, but otherwise arrays become a
534 * mess. Hopefully a later pass over the code can pack scalars
535 * down if appropriate.
539 case GLSL_TYPE_ARRAY
:
540 assert(type
->length
> 0);
541 return type_size(type
->fields
.array
) * type
->length
;
542 case GLSL_TYPE_STRUCT
:
544 for (i
= 0; i
< type
->length
; i
++) {
545 size
+= type_size(type
->fields
.structure
[i
].type
);
548 case GLSL_TYPE_SAMPLER
:
549 /* Samplers take up one slot in UNIFORMS[], but they're baked in
554 case GLSL_TYPE_ERROR
:
555 case GLSL_TYPE_INTERFACE
:
564 vec4_visitor::virtual_grf_alloc(int size
)
566 if (virtual_grf_array_size
<= virtual_grf_count
) {
567 if (virtual_grf_array_size
== 0)
568 virtual_grf_array_size
= 16;
570 virtual_grf_array_size
*= 2;
571 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
572 virtual_grf_array_size
);
573 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
574 virtual_grf_array_size
);
576 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
577 virtual_grf_reg_count
+= size
;
578 virtual_grf_sizes
[virtual_grf_count
] = size
;
579 return virtual_grf_count
++;
582 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
587 this->reg
= v
->virtual_grf_alloc(type_size(type
));
589 if (type
->is_array() || type
->is_record()) {
590 this->swizzle
= BRW_SWIZZLE_NOOP
;
592 this->swizzle
= swizzle_for_size(type
->vector_elements
);
595 this->type
= brw_type_for_base_type(type
);
598 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
603 this->reg
= v
->virtual_grf_alloc(type_size(type
));
605 if (type
->is_array() || type
->is_record()) {
606 this->writemask
= WRITEMASK_XYZW
;
608 this->writemask
= (1 << type
->vector_elements
) - 1;
611 this->type
= brw_type_for_base_type(type
);
614 /* Our support for uniforms is piggy-backed on the struct
615 * gl_fragment_program, because that's where the values actually
616 * get stored, rather than in some global gl_shader_program uniform
620 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
622 int namelen
= strlen(ir
->name
);
624 /* The data for our (non-builtin) uniforms is stored in a series of
625 * gl_uniform_driver_storage structs for each subcomponent that
626 * glGetUniformLocation() could name. We know it's been set up in the same
627 * order we'd walk the type, so walk the list of storage and find anything
628 * with our name, or the prefix of a component that starts with our name.
630 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
631 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
633 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
634 (storage
->name
[namelen
] != 0 &&
635 storage
->name
[namelen
] != '.' &&
636 storage
->name
[namelen
] != '[')) {
640 gl_constant_value
*components
= storage
->storage
;
641 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
642 storage
->type
->matrix_columns
);
644 for (unsigned s
= 0; s
< vector_count
; s
++) {
645 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
648 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
649 prog_data
->param
[uniforms
* 4 + i
] = &components
->f
;
653 static float zero
= 0;
654 prog_data
->param
[uniforms
* 4 + i
] = &zero
;
663 vec4_visitor::setup_uniform_clipplane_values()
665 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
667 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
668 this->uniform_vector_size
[this->uniforms
] = 4;
669 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
670 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
671 for (int j
= 0; j
< 4; ++j
) {
672 prog_data
->param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
678 /* Our support for builtin uniforms is even scarier than non-builtin.
679 * It sits on top of the PROG_STATE_VAR parameters that are
680 * automatically updated from GL context state.
683 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
685 const ir_state_slot
*const slots
= ir
->state_slots
;
686 assert(ir
->state_slots
!= NULL
);
688 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
689 /* This state reference has already been setup by ir_to_mesa,
690 * but we'll get the same index back here. We can reference
691 * ParameterValues directly, since unlike brw_fs.cpp, we never
692 * add new state references during compile.
694 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
695 (gl_state_index
*)slots
[i
].tokens
);
696 float *values
= &this->prog
->Parameters
->ParameterValues
[index
][0].f
;
698 this->uniform_vector_size
[this->uniforms
] = 0;
699 /* Add each of the unique swizzled channels of the element.
700 * This will end up matching the size of the glsl_type of this field.
703 for (unsigned int j
= 0; j
< 4; j
++) {
704 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
707 prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
708 if (swiz
<= last_swiz
)
709 this->uniform_vector_size
[this->uniforms
]++;
716 vec4_visitor::variable_storage(ir_variable
*var
)
718 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
722 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
)
724 ir_expression
*expr
= ir
->as_expression();
726 *predicate
= BRW_PREDICATE_NORMAL
;
730 vec4_instruction
*inst
;
732 assert(expr
->get_num_operands() <= 2);
733 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
734 expr
->operands
[i
]->accept(this);
735 op
[i
] = this->result
;
737 resolve_ud_negate(&op
[i
]);
740 switch (expr
->operation
) {
741 case ir_unop_logic_not
:
742 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
743 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
746 case ir_binop_logic_xor
:
747 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
748 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
751 case ir_binop_logic_or
:
752 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
753 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
756 case ir_binop_logic_and
:
757 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
758 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
763 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
765 inst
= emit(MOV(dst_null_f(), op
[0]));
766 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
772 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
774 inst
= emit(MOV(dst_null_d(), op
[0]));
775 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
779 case ir_binop_all_equal
:
780 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
781 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
784 case ir_binop_any_nequal
:
785 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
786 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
790 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
791 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
794 case ir_binop_greater
:
795 case ir_binop_gequal
:
797 case ir_binop_lequal
:
799 case ir_binop_nequal
:
800 emit(CMP(dst_null_d(), op
[0], op
[1],
801 brw_conditional_for_comparison(expr
->operation
)));
805 assert(!"not reached");
813 resolve_ud_negate(&this->result
);
816 vec4_instruction
*inst
= emit(AND(dst_null_d(),
817 this->result
, src_reg(1)));
818 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
820 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
821 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
826 * Emit a gen6 IF statement with the comparison folded into the IF
830 vec4_visitor::emit_if_gen6(ir_if
*ir
)
832 ir_expression
*expr
= ir
->condition
->as_expression();
838 assert(expr
->get_num_operands() <= 2);
839 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
840 expr
->operands
[i
]->accept(this);
841 op
[i
] = this->result
;
844 switch (expr
->operation
) {
845 case ir_unop_logic_not
:
846 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
849 case ir_binop_logic_xor
:
850 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
853 case ir_binop_logic_or
:
854 temp
= dst_reg(this, glsl_type::bool_type
);
855 emit(OR(temp
, op
[0], op
[1]));
856 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
859 case ir_binop_logic_and
:
860 temp
= dst_reg(this, glsl_type::bool_type
);
861 emit(AND(temp
, op
[0], op
[1]));
862 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
866 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
870 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
873 case ir_binop_greater
:
874 case ir_binop_gequal
:
876 case ir_binop_lequal
:
878 case ir_binop_nequal
:
879 emit(IF(op
[0], op
[1],
880 brw_conditional_for_comparison(expr
->operation
)));
883 case ir_binop_all_equal
:
884 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
885 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
888 case ir_binop_any_nequal
:
889 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
890 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
894 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
895 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
899 assert(!"not reached");
900 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
906 ir
->condition
->accept(this);
908 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
912 with_writemask(dst_reg
const & r
, int mask
)
915 result
.writemask
= mask
;
920 vec4_vs_visitor::emit_prolog()
922 dst_reg sign_recovery_shift
;
923 dst_reg normalize_factor
;
924 dst_reg es3_normalize_factor
;
926 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
927 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
928 uint8_t wa_flags
= vs_compile
->key
.gl_attrib_wa_flags
[i
];
929 dst_reg
reg(ATTR
, i
);
931 reg_d
.type
= BRW_REGISTER_TYPE_D
;
932 dst_reg reg_ud
= reg
;
933 reg_ud
.type
= BRW_REGISTER_TYPE_UD
;
935 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
936 * come in as floating point conversions of the integer values.
938 if (wa_flags
& BRW_ATTRIB_WA_COMPONENT_MASK
) {
940 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
941 dst
.writemask
= (1 << (wa_flags
& BRW_ATTRIB_WA_COMPONENT_MASK
)) - 1;
942 emit(MUL(dst
, src_reg(dst
), src_reg(1.0f
/ 65536.0f
)));
945 /* Do sign recovery for 2101010 formats if required. */
946 if (wa_flags
& BRW_ATTRIB_WA_SIGN
) {
947 if (sign_recovery_shift
.file
== BAD_FILE
) {
948 /* shift constant: <22,22,22,30> */
949 sign_recovery_shift
= dst_reg(this, glsl_type::uvec4_type
);
950 emit(MOV(with_writemask(sign_recovery_shift
, WRITEMASK_XYZ
), src_reg(22u)));
951 emit(MOV(with_writemask(sign_recovery_shift
, WRITEMASK_W
), src_reg(30u)));
954 emit(SHL(reg_ud
, src_reg(reg_ud
), src_reg(sign_recovery_shift
)));
955 emit(ASR(reg_d
, src_reg(reg_d
), src_reg(sign_recovery_shift
)));
958 /* Apply BGRA swizzle if required. */
959 if (wa_flags
& BRW_ATTRIB_WA_BGRA
) {
960 src_reg temp
= src_reg(reg
);
961 temp
.swizzle
= BRW_SWIZZLE4(2,1,0,3);
962 emit(MOV(reg
, temp
));
965 if (wa_flags
& BRW_ATTRIB_WA_NORMALIZE
) {
966 /* ES 3.0 has different rules for converting signed normalized
967 * fixed-point numbers than desktop GL.
969 if (_mesa_is_gles3(ctx
) && (wa_flags
& BRW_ATTRIB_WA_SIGN
)) {
970 /* According to equation 2.2 of the ES 3.0 specification,
971 * signed normalization conversion is done by:
973 * f = c / (2^(b-1)-1)
975 if (es3_normalize_factor
.file
== BAD_FILE
) {
976 /* mul constant: 1 / (2^(b-1) - 1) */
977 es3_normalize_factor
= dst_reg(this, glsl_type::vec4_type
);
978 emit(MOV(with_writemask(es3_normalize_factor
, WRITEMASK_XYZ
),
979 src_reg(1.0f
/ ((1<<9) - 1))));
980 emit(MOV(with_writemask(es3_normalize_factor
, WRITEMASK_W
),
981 src_reg(1.0f
/ ((1<<1) - 1))));
985 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
986 emit(MOV(dst
, src_reg(reg_d
)));
987 emit(MUL(dst
, src_reg(dst
), src_reg(es3_normalize_factor
)));
988 emit_minmax(BRW_CONDITIONAL_G
, dst
, src_reg(dst
), src_reg(-1.0f
));
990 /* The following equations are from the OpenGL 3.2 specification:
992 * 2.1 unsigned normalization
995 * 2.2 signed normalization
998 * Both of these share a common divisor, which is represented by
999 * "normalize_factor" in the code below.
1001 if (normalize_factor
.file
== BAD_FILE
) {
1002 /* 1 / (2^b - 1) for b=<10,10,10,2> */
1003 normalize_factor
= dst_reg(this, glsl_type::vec4_type
);
1004 emit(MOV(with_writemask(normalize_factor
, WRITEMASK_XYZ
),
1005 src_reg(1.0f
/ ((1<<10) - 1))));
1006 emit(MOV(with_writemask(normalize_factor
, WRITEMASK_W
),
1007 src_reg(1.0f
/ ((1<<2) - 1))));
1011 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
1012 emit(MOV(dst
, src_reg((wa_flags
& BRW_ATTRIB_WA_SIGN
) ? reg_d
: reg_ud
)));
1014 /* For signed normalization, we want the numerator to be 2c+1. */
1015 if (wa_flags
& BRW_ATTRIB_WA_SIGN
) {
1016 emit(MUL(dst
, src_reg(dst
), src_reg(2.0f
)));
1017 emit(ADD(dst
, src_reg(dst
), src_reg(1.0f
)));
1020 emit(MUL(dst
, src_reg(dst
), src_reg(normalize_factor
)));
1024 if (wa_flags
& BRW_ATTRIB_WA_SCALE
) {
1026 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
1027 emit(MOV(dst
, src_reg((wa_flags
& BRW_ATTRIB_WA_SIGN
) ? reg_d
: reg_ud
)));
1035 vec4_vs_visitor::make_reg_for_system_value(ir_variable
*ir
)
1037 /* VertexID is stored by the VF as the last vertex element, but
1038 * we don't represent it with a flag in inputs_read, so we call
1039 * it VERT_ATTRIB_MAX, which setup_attributes() picks up on.
1041 dst_reg
*reg
= new(mem_ctx
) dst_reg(ATTR
, VERT_ATTRIB_MAX
);
1042 vs_prog_data
->uses_vertexid
= true;
1044 switch (ir
->location
) {
1045 case SYSTEM_VALUE_VERTEX_ID
:
1046 reg
->writemask
= WRITEMASK_X
;
1048 case SYSTEM_VALUE_INSTANCE_ID
:
1049 reg
->writemask
= WRITEMASK_Y
;
1052 assert(!"not reached");
1061 vec4_visitor::visit(ir_variable
*ir
)
1063 dst_reg
*reg
= NULL
;
1065 if (variable_storage(ir
))
1069 case ir_var_shader_in
:
1070 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
1073 case ir_var_shader_out
:
1074 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1076 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1077 output_reg
[ir
->location
+ i
] = *reg
;
1078 output_reg
[ir
->location
+ i
].reg_offset
= i
;
1079 output_reg
[ir
->location
+ i
].type
=
1080 brw_type_for_base_type(ir
->type
->get_scalar_type());
1081 output_reg_annotation
[ir
->location
+ i
] = ir
->name
;
1086 case ir_var_temporary
:
1087 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1090 case ir_var_uniform
:
1091 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1093 /* Thanks to the lower_ubo_reference pass, we will see only
1094 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1095 * variables, so no need for them to be in variable_ht.
1097 if (ir
->is_in_uniform_block())
1100 /* Track how big the whole uniform variable is, in case we need to put a
1101 * copy of its data into pull constants for array access.
1103 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1105 if (!strncmp(ir
->name
, "gl_", 3)) {
1106 setup_builtin_uniform_values(ir
);
1108 setup_uniform_values(ir
);
1112 case ir_var_system_value
:
1113 reg
= make_reg_for_system_value(ir
);
1117 assert(!"not reached");
1120 reg
->type
= brw_type_for_base_type(ir
->type
);
1121 hash_table_insert(this->variable_ht
, reg
, ir
);
1125 vec4_visitor::visit(ir_loop
*ir
)
1129 /* We don't want debugging output to print the whole body of the
1130 * loop as the annotation.
1132 this->base_ir
= NULL
;
1134 if (ir
->counter
!= NULL
) {
1135 this->base_ir
= ir
->counter
;
1136 ir
->counter
->accept(this);
1137 counter
= *(variable_storage(ir
->counter
));
1139 if (ir
->from
!= NULL
) {
1140 this->base_ir
= ir
->from
;
1141 ir
->from
->accept(this);
1143 emit(MOV(counter
, this->result
));
1147 emit(BRW_OPCODE_DO
);
1150 this->base_ir
= ir
->to
;
1151 ir
->to
->accept(this);
1153 emit(CMP(dst_null_d(), src_reg(counter
), this->result
,
1154 brw_conditional_for_comparison(ir
->cmp
)));
1156 vec4_instruction
*inst
= emit(BRW_OPCODE_BREAK
);
1157 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1160 visit_instructions(&ir
->body_instructions
);
1163 if (ir
->increment
) {
1164 this->base_ir
= ir
->increment
;
1165 ir
->increment
->accept(this);
1166 emit(ADD(counter
, src_reg(counter
), this->result
));
1169 emit(BRW_OPCODE_WHILE
);
1173 vec4_visitor::visit(ir_loop_jump
*ir
)
1176 case ir_loop_jump::jump_break
:
1177 emit(BRW_OPCODE_BREAK
);
1179 case ir_loop_jump::jump_continue
:
1180 emit(BRW_OPCODE_CONTINUE
);
1187 vec4_visitor::visit(ir_function_signature
*ir
)
1194 vec4_visitor::visit(ir_function
*ir
)
1196 /* Ignore function bodies other than main() -- we shouldn't see calls to
1197 * them since they should all be inlined.
1199 if (strcmp(ir
->name
, "main") == 0) {
1200 const ir_function_signature
*sig
;
1203 sig
= ir
->matching_signature(&empty
);
1207 visit_instructions(&sig
->body
);
1212 vec4_visitor::try_emit_sat(ir_expression
*ir
)
1214 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
1218 sat_src
->accept(this);
1219 src_reg src
= this->result
;
1221 this->result
= src_reg(this, ir
->type
);
1222 vec4_instruction
*inst
;
1223 inst
= emit(MOV(dst_reg(this->result
), src
));
1224 inst
->saturate
= true;
1230 vec4_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
1232 /* 3-src instructions were introduced in gen6. */
1236 /* MAD can only handle floating-point data. */
1237 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1240 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
1241 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
1243 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1246 nonmul
->accept(this);
1247 src_reg src0
= fix_3src_operand(this->result
);
1249 mul
->operands
[0]->accept(this);
1250 src_reg src1
= fix_3src_operand(this->result
);
1252 mul
->operands
[1]->accept(this);
1253 src_reg src2
= fix_3src_operand(this->result
);
1255 this->result
= src_reg(this, ir
->type
);
1256 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1262 vec4_visitor::emit_bool_comparison(unsigned int op
,
1263 dst_reg dst
, src_reg src0
, src_reg src1
)
1265 /* original gen4 does destination conversion before comparison. */
1267 dst
.type
= src0
.type
;
1269 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
1271 dst
.type
= BRW_REGISTER_TYPE_D
;
1272 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
1276 vec4_visitor::emit_minmax(uint32_t conditionalmod
, dst_reg dst
,
1277 src_reg src0
, src_reg src1
)
1279 vec4_instruction
*inst
;
1281 if (brw
->gen
>= 6) {
1282 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1283 inst
->conditional_mod
= conditionalmod
;
1285 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1287 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1288 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1293 is_16bit_constant(ir_rvalue
*rvalue
)
1295 ir_constant
*constant
= rvalue
->as_constant();
1299 if (constant
->type
!= glsl_type::int_type
&&
1300 constant
->type
!= glsl_type::uint_type
)
1303 return constant
->value
.u
[0] < (1 << 16);
1307 vec4_visitor::visit(ir_expression
*ir
)
1309 unsigned int operand
;
1310 src_reg op
[Elements(ir
->operands
)];
1313 vec4_instruction
*inst
;
1315 if (try_emit_sat(ir
))
1318 if (ir
->operation
== ir_binop_add
) {
1319 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
1323 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1324 this->result
.file
= BAD_FILE
;
1325 ir
->operands
[operand
]->accept(this);
1326 if (this->result
.file
== BAD_FILE
) {
1327 printf("Failed to get tree for expression operand:\n");
1328 ir
->operands
[operand
]->print();
1331 op
[operand
] = this->result
;
1333 /* Matrix expression operands should have been broken down to vector
1334 * operations already.
1336 assert(!ir
->operands
[operand
]->type
->is_matrix());
1339 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1340 if (ir
->operands
[1]) {
1341 vector_elements
= MAX2(vector_elements
,
1342 ir
->operands
[1]->type
->vector_elements
);
1345 this->result
.file
= BAD_FILE
;
1347 /* Storage for our result. Ideally for an assignment we'd be using
1348 * the actual storage for the result here, instead.
1350 result_src
= src_reg(this, ir
->type
);
1351 /* convenience for the emit functions below. */
1352 result_dst
= dst_reg(result_src
);
1353 /* If nothing special happens, this is the result. */
1354 this->result
= result_src
;
1355 /* Limit writes to the channels that will be used by result_src later.
1356 * This does limit this temp's use as a temporary for multi-instruction
1359 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1361 switch (ir
->operation
) {
1362 case ir_unop_logic_not
:
1363 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1364 * ones complement of the whole register, not just bit 0.
1366 emit(XOR(result_dst
, op
[0], src_reg(1)));
1369 op
[0].negate
= !op
[0].negate
;
1370 emit(MOV(result_dst
, op
[0]));
1374 op
[0].negate
= false;
1375 emit(MOV(result_dst
, op
[0]));
1379 emit(MOV(result_dst
, src_reg(0.0f
)));
1381 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_G
));
1382 inst
= emit(MOV(result_dst
, src_reg(1.0f
)));
1383 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1385 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_L
));
1386 inst
= emit(MOV(result_dst
, src_reg(-1.0f
)));
1387 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1392 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1396 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1399 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1403 assert(!"not reached: should be handled by ir_explog_to_explog2");
1406 case ir_unop_sin_reduced
:
1407 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1410 case ir_unop_cos_reduced
:
1411 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1416 assert(!"derivatives not valid in vertex shader");
1419 case ir_unop_bitfield_reverse
:
1420 emit(BFREV(result_dst
, op
[0]));
1422 case ir_unop_bit_count
:
1423 emit(CBIT(result_dst
, op
[0]));
1425 case ir_unop_find_msb
: {
1426 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1428 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1429 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1431 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1432 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1433 * subtract the result from 31 to convert the MSB count into an LSB count.
1436 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1437 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1438 emit(MOV(result_dst
, temp
));
1440 src_reg src_tmp
= src_reg(result_dst
);
1441 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1443 src_tmp
.negate
= true;
1444 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1445 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1448 case ir_unop_find_lsb
:
1449 emit(FBL(result_dst
, op
[0]));
1453 assert(!"not reached: should be handled by lower_noise");
1457 emit(ADD(result_dst
, op
[0], op
[1]));
1460 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1464 if (ir
->type
->is_integer()) {
1465 /* For integer multiplication, the MUL uses the low 16 bits of one of
1466 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1467 * accumulates in the contribution of the upper 16 bits of that
1468 * operand. If we can determine that one of the args is in the low
1469 * 16 bits, though, we can just emit a single MUL.
1471 if (is_16bit_constant(ir
->operands
[0])) {
1473 emit(MUL(result_dst
, op
[0], op
[1]));
1475 emit(MUL(result_dst
, op
[1], op
[0]));
1476 } else if (is_16bit_constant(ir
->operands
[1])) {
1478 emit(MUL(result_dst
, op
[1], op
[0]));
1480 emit(MUL(result_dst
, op
[0], op
[1]));
1482 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
1484 emit(MUL(acc
, op
[0], op
[1]));
1485 emit(MACH(dst_null_d(), op
[0], op
[1]));
1486 emit(MOV(result_dst
, src_reg(acc
)));
1489 emit(MUL(result_dst
, op
[0], op
[1]));
1493 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1494 assert(ir
->type
->is_integer());
1495 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1498 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1499 assert(ir
->type
->is_integer());
1500 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1504 case ir_binop_greater
:
1505 case ir_binop_lequal
:
1506 case ir_binop_gequal
:
1507 case ir_binop_equal
:
1508 case ir_binop_nequal
: {
1509 emit(CMP(result_dst
, op
[0], op
[1],
1510 brw_conditional_for_comparison(ir
->operation
)));
1511 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1515 case ir_binop_all_equal
:
1516 /* "==" operator producing a scalar boolean. */
1517 if (ir
->operands
[0]->type
->is_vector() ||
1518 ir
->operands
[1]->type
->is_vector()) {
1519 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1520 emit(MOV(result_dst
, src_reg(0)));
1521 inst
= emit(MOV(result_dst
, src_reg(1)));
1522 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1524 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1525 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1528 case ir_binop_any_nequal
:
1529 /* "!=" operator producing a scalar boolean. */
1530 if (ir
->operands
[0]->type
->is_vector() ||
1531 ir
->operands
[1]->type
->is_vector()) {
1532 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1534 emit(MOV(result_dst
, src_reg(0)));
1535 inst
= emit(MOV(result_dst
, src_reg(1)));
1536 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1538 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1539 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1544 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1545 emit(MOV(result_dst
, src_reg(0)));
1547 inst
= emit(MOV(result_dst
, src_reg(1)));
1548 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1551 case ir_binop_logic_xor
:
1552 emit(XOR(result_dst
, op
[0], op
[1]));
1555 case ir_binop_logic_or
:
1556 emit(OR(result_dst
, op
[0], op
[1]));
1559 case ir_binop_logic_and
:
1560 emit(AND(result_dst
, op
[0], op
[1]));
1564 assert(ir
->operands
[0]->type
->is_vector());
1565 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1566 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1570 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1573 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1576 case ir_unop_bitcast_i2f
:
1577 case ir_unop_bitcast_u2f
:
1578 this->result
= op
[0];
1579 this->result
.type
= BRW_REGISTER_TYPE_F
;
1582 case ir_unop_bitcast_f2i
:
1583 this->result
= op
[0];
1584 this->result
.type
= BRW_REGISTER_TYPE_D
;
1587 case ir_unop_bitcast_f2u
:
1588 this->result
= op
[0];
1589 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1600 emit(MOV(result_dst
, op
[0]));
1604 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1605 emit(AND(result_dst
, result_src
, src_reg(1)));
1610 emit(RNDZ(result_dst
, op
[0]));
1613 op
[0].negate
= !op
[0].negate
;
1614 inst
= emit(RNDD(result_dst
, op
[0]));
1615 this->result
.negate
= true;
1618 inst
= emit(RNDD(result_dst
, op
[0]));
1621 inst
= emit(FRC(result_dst
, op
[0]));
1623 case ir_unop_round_even
:
1624 emit(RNDE(result_dst
, op
[0]));
1628 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1631 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1635 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1638 case ir_unop_bit_not
:
1639 inst
= emit(NOT(result_dst
, op
[0]));
1641 case ir_binop_bit_and
:
1642 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1644 case ir_binop_bit_xor
:
1645 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1647 case ir_binop_bit_or
:
1648 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1651 case ir_binop_lshift
:
1652 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1655 case ir_binop_rshift
:
1656 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1657 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1659 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1663 emit(BFI1(result_dst
, op
[0], op
[1]));
1666 case ir_binop_ubo_load
: {
1667 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
1668 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1669 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1670 src_reg offset
= op
[1];
1672 /* Now, load the vector from that offset. */
1673 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1675 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1676 packed_consts
.type
= result
.type
;
1677 src_reg surf_index
=
1678 src_reg(SURF_INDEX_VS_UBO(uniform_block
->value
.u
[0]));
1679 if (const_offset_ir
) {
1680 offset
= src_reg(const_offset
/ 16);
1682 emit(SHR(dst_reg(offset
), offset
, src_reg(4)));
1685 vec4_instruction
*pull
=
1686 emit(new(mem_ctx
) vec4_instruction(this,
1687 VS_OPCODE_PULL_CONSTANT_LOAD
,
1688 dst_reg(packed_consts
),
1691 pull
->base_mrf
= 14;
1694 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1695 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1696 const_offset
% 16 / 4,
1697 const_offset
% 16 / 4,
1698 const_offset
% 16 / 4);
1700 /* UBO bools are any nonzero int. We store bools as either 0 or 1. */
1701 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1702 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1703 BRW_CONDITIONAL_NZ
));
1704 emit(AND(result_dst
, result
, src_reg(0x1)));
1706 emit(MOV(result_dst
, packed_consts
));
1711 case ir_binop_vector_extract
:
1712 assert(!"should have been lowered by vec_index_to_cond_assign");
1716 op
[0] = fix_3src_operand(op
[0]);
1717 op
[1] = fix_3src_operand(op
[1]);
1718 op
[2] = fix_3src_operand(op
[2]);
1719 /* Note that the instruction's argument order is reversed from GLSL
1722 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1726 op
[0] = fix_3src_operand(op
[0]);
1727 op
[1] = fix_3src_operand(op
[1]);
1728 op
[2] = fix_3src_operand(op
[2]);
1729 /* Note that the instruction's argument order is reversed from GLSL
1732 emit(LRP(result_dst
, op
[2], op
[1], op
[0]));
1736 op
[0] = fix_3src_operand(op
[0]);
1737 op
[1] = fix_3src_operand(op
[1]);
1738 op
[2] = fix_3src_operand(op
[2]);
1739 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1742 case ir_triop_bitfield_extract
:
1743 op
[0] = fix_3src_operand(op
[0]);
1744 op
[1] = fix_3src_operand(op
[1]);
1745 op
[2] = fix_3src_operand(op
[2]);
1746 /* Note that the instruction's argument order is reversed from GLSL
1749 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1752 case ir_triop_vector_insert
:
1753 assert(!"should have been lowered by lower_vector_insert");
1756 case ir_quadop_bitfield_insert
:
1757 assert(!"not reached: should be handled by "
1758 "bitfield_insert_to_bfm_bfi\n");
1761 case ir_quadop_vector
:
1762 assert(!"not reached: should be handled by lower_quadop_vector");
1765 case ir_unop_pack_half_2x16
:
1766 emit_pack_half_2x16(result_dst
, op
[0]);
1768 case ir_unop_unpack_half_2x16
:
1769 emit_unpack_half_2x16(result_dst
, op
[0]);
1771 case ir_unop_pack_snorm_2x16
:
1772 case ir_unop_pack_snorm_4x8
:
1773 case ir_unop_pack_unorm_2x16
:
1774 case ir_unop_pack_unorm_4x8
:
1775 case ir_unop_unpack_snorm_2x16
:
1776 case ir_unop_unpack_snorm_4x8
:
1777 case ir_unop_unpack_unorm_2x16
:
1778 case ir_unop_unpack_unorm_4x8
:
1779 assert(!"not reached: should be handled by lower_packing_builtins");
1781 case ir_unop_unpack_half_2x16_split_x
:
1782 case ir_unop_unpack_half_2x16_split_y
:
1783 case ir_binop_pack_half_2x16_split
:
1784 assert(!"not reached: should not occur in vertex shader");
1791 vec4_visitor::visit(ir_swizzle
*ir
)
1797 /* Note that this is only swizzles in expressions, not those on the left
1798 * hand side of an assignment, which do write masking. See ir_assignment
1802 ir
->val
->accept(this);
1804 assert(src
.file
!= BAD_FILE
);
1806 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1809 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1812 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1815 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1818 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1822 for (; i
< 4; i
++) {
1823 /* Replicate the last channel out. */
1824 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1827 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1833 vec4_visitor::visit(ir_dereference_variable
*ir
)
1835 const struct glsl_type
*type
= ir
->type
;
1836 dst_reg
*reg
= variable_storage(ir
->var
);
1839 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1840 this->result
= src_reg(brw_null_reg());
1844 this->result
= src_reg(*reg
);
1846 /* System values get their swizzle from the dst_reg writemask */
1847 if (ir
->var
->mode
== ir_var_system_value
)
1850 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1851 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1856 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1858 /* Under normal circumstances array elements are stored consecutively, so
1859 * the stride is equal to the size of the array element.
1861 return type_size(ir
->type
);
1866 vec4_visitor::visit(ir_dereference_array
*ir
)
1868 ir_constant
*constant_index
;
1870 int array_stride
= compute_array_stride(ir
);
1872 constant_index
= ir
->array_index
->constant_expression_value();
1874 ir
->array
->accept(this);
1877 if (constant_index
) {
1878 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1880 /* Variable index array dereference. It eats the "vec4" of the
1881 * base of the array and an index that offsets the Mesa register
1884 ir
->array_index
->accept(this);
1888 if (array_stride
== 1) {
1889 index_reg
= this->result
;
1891 index_reg
= src_reg(this, glsl_type::int_type
);
1893 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1897 src_reg temp
= src_reg(this, glsl_type::int_type
);
1899 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1904 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1905 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1908 /* If the type is smaller than a vec4, replicate the last channel out. */
1909 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1910 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1912 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1913 src
.type
= brw_type_for_base_type(ir
->type
);
1919 vec4_visitor::visit(ir_dereference_record
*ir
)
1922 const glsl_type
*struct_type
= ir
->record
->type
;
1925 ir
->record
->accept(this);
1927 for (i
= 0; i
< struct_type
->length
; i
++) {
1928 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1930 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1933 /* If the type is smaller than a vec4, replicate the last channel out. */
1934 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1935 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1937 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1938 this->result
.type
= brw_type_for_base_type(ir
->type
);
1940 this->result
.reg_offset
+= offset
;
1944 * We want to be careful in assignment setup to hit the actual storage
1945 * instead of potentially using a temporary like we might with the
1946 * ir_dereference handler.
1949 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1951 /* The LHS must be a dereference. If the LHS is a variable indexed array
1952 * access of a vector, it must be separated into a series conditional moves
1953 * before reaching this point (see ir_vec_index_to_cond_assign).
1955 assert(ir
->as_dereference());
1956 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1958 assert(!deref_array
->array
->type
->is_vector());
1961 /* Use the rvalue deref handler for the most part. We'll ignore
1962 * swizzles in it and write swizzles using writemask, though.
1965 return dst_reg(v
->result
);
1969 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1970 const struct glsl_type
*type
, uint32_t predicate
)
1972 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1973 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1974 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1979 if (type
->is_array()) {
1980 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1981 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1986 if (type
->is_matrix()) {
1987 const struct glsl_type
*vec_type
;
1989 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1990 type
->vector_elements
, 1);
1992 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1993 emit_block_move(dst
, src
, vec_type
, predicate
);
1998 assert(type
->is_scalar() || type
->is_vector());
2000 dst
->type
= brw_type_for_base_type(type
);
2001 src
->type
= dst
->type
;
2003 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2005 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
2007 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2008 inst
->predicate
= predicate
;
2015 /* If the RHS processing resulted in an instruction generating a
2016 * temporary value, and it would be easy to rewrite the instruction to
2017 * generate its result right into the LHS instead, do so. This ends
2018 * up reliably removing instructions where it can be tricky to do so
2019 * later without real UD chain information.
2022 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2025 vec4_instruction
*pre_rhs_inst
,
2026 vec4_instruction
*last_rhs_inst
)
2028 /* This could be supported, but it would take more smarts. */
2032 if (pre_rhs_inst
== last_rhs_inst
)
2033 return false; /* No instructions generated to work with. */
2035 /* Make sure the last instruction generated our source reg. */
2036 if (src
.file
!= GRF
||
2037 src
.file
!= last_rhs_inst
->dst
.file
||
2038 src
.reg
!= last_rhs_inst
->dst
.reg
||
2039 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2043 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2046 /* Check that that last instruction fully initialized the channels
2047 * we want to use, in the order we want to use them. We could
2048 * potentially reswizzle the operands of many instructions so that
2049 * we could handle out of order channels, but don't yet.
2052 for (unsigned i
= 0; i
< 4; i
++) {
2053 if (dst
.writemask
& (1 << i
)) {
2054 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2057 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2062 /* Success! Rewrite the instruction. */
2063 last_rhs_inst
->dst
.file
= dst
.file
;
2064 last_rhs_inst
->dst
.reg
= dst
.reg
;
2065 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2066 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2067 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2073 vec4_visitor::visit(ir_assignment
*ir
)
2075 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2076 uint32_t predicate
= BRW_PREDICATE_NONE
;
2078 if (!ir
->lhs
->type
->is_scalar() &&
2079 !ir
->lhs
->type
->is_vector()) {
2080 ir
->rhs
->accept(this);
2081 src_reg src
= this->result
;
2083 if (ir
->condition
) {
2084 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2087 /* emit_block_move doesn't account for swizzles in the source register.
2088 * This should be ok, since the source register is a structure or an
2089 * array, and those can't be swizzled. But double-check to be sure.
2091 assert(src
.swizzle
==
2092 (ir
->rhs
->type
->is_matrix()
2093 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2094 : BRW_SWIZZLE_NOOP
));
2096 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2100 /* Now we're down to just a scalar/vector with writemasks. */
2103 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2104 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2106 ir
->rhs
->accept(this);
2108 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2110 src_reg src
= this->result
;
2113 int first_enabled_chan
= 0;
2116 assert(ir
->lhs
->type
->is_vector() ||
2117 ir
->lhs
->type
->is_scalar());
2118 dst
.writemask
= ir
->write_mask
;
2120 for (int i
= 0; i
< 4; i
++) {
2121 if (dst
.writemask
& (1 << i
)) {
2122 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2127 /* Swizzle a small RHS vector into the channels being written.
2129 * glsl ir treats write_mask as dictating how many channels are
2130 * present on the RHS while in our instructions we need to make
2131 * those channels appear in the slots of the vec4 they're written to.
2133 for (int i
= 0; i
< 4; i
++) {
2134 if (dst
.writemask
& (1 << i
))
2135 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2137 swizzles
[i
] = first_enabled_chan
;
2139 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2140 swizzles
[2], swizzles
[3]);
2142 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2146 if (ir
->condition
) {
2147 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2150 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2151 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2152 inst
->predicate
= predicate
;
2160 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2162 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2163 foreach_list(node
, &ir
->components
) {
2164 ir_constant
*field_value
= (ir_constant
*)node
;
2166 emit_constant_values(dst
, field_value
);
2171 if (ir
->type
->is_array()) {
2172 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2173 emit_constant_values(dst
, ir
->array_elements
[i
]);
2178 if (ir
->type
->is_matrix()) {
2179 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2180 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2182 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2183 dst
->writemask
= 1 << j
;
2184 dst
->type
= BRW_REGISTER_TYPE_F
;
2186 emit(MOV(*dst
, src_reg(vec
[j
])));
2193 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2195 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2196 if (!(remaining_writemask
& (1 << i
)))
2199 dst
->writemask
= 1 << i
;
2200 dst
->type
= brw_type_for_base_type(ir
->type
);
2202 /* Find other components that match the one we're about to
2203 * write. Emits fewer instructions for things like vec4(0.5,
2206 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2207 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2208 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2209 dst
->writemask
|= (1 << j
);
2211 /* u, i, and f storage all line up, so no need for a
2212 * switch case for comparing each type.
2214 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2215 dst
->writemask
|= (1 << j
);
2219 switch (ir
->type
->base_type
) {
2220 case GLSL_TYPE_FLOAT
:
2221 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2224 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2226 case GLSL_TYPE_UINT
:
2227 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2229 case GLSL_TYPE_BOOL
:
2230 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
2233 assert(!"Non-float/uint/int/bool constant");
2237 remaining_writemask
&= ~dst
->writemask
;
2243 vec4_visitor::visit(ir_constant
*ir
)
2245 dst_reg dst
= dst_reg(this, ir
->type
);
2246 this->result
= src_reg(dst
);
2248 emit_constant_values(&dst
, ir
);
2252 vec4_visitor::visit(ir_call
*ir
)
2254 assert(!"not reached");
2258 vec4_visitor::visit(ir_texture
*ir
)
2261 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2263 /* Should be lowered by do_lower_texture_projection */
2264 assert(!ir
->projector
);
2266 /* Generate code to compute all the subexpression trees. This has to be
2267 * done before loading any values into MRFs for the sampler message since
2268 * generating these values may involve SEND messages that need the MRFs.
2271 if (ir
->coordinate
) {
2272 ir
->coordinate
->accept(this);
2273 coordinate
= this->result
;
2276 src_reg shadow_comparitor
;
2277 if (ir
->shadow_comparitor
) {
2278 ir
->shadow_comparitor
->accept(this);
2279 shadow_comparitor
= this->result
;
2282 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2283 src_reg lod
, dPdx
, dPdy
, sample_index
;
2286 lod
= src_reg(0.0f
);
2287 lod_type
= glsl_type::float_type
;
2292 ir
->lod_info
.lod
->accept(this);
2294 lod_type
= ir
->lod_info
.lod
->type
;
2297 ir
->lod_info
.sample_index
->accept(this);
2298 sample_index
= this->result
;
2299 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2302 ir
->lod_info
.grad
.dPdx
->accept(this);
2303 dPdx
= this->result
;
2305 ir
->lod_info
.grad
.dPdy
->accept(this);
2306 dPdy
= this->result
;
2308 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2315 vec4_instruction
*inst
= NULL
;
2319 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXL
);
2322 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXD
);
2325 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF
);
2328 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_MS
);
2331 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
2334 assert(!"TXB is not valid for vertex shaders.");
2337 assert(!"LOD is not valid for vertex shaders.");
2341 bool use_texture_offset
= ir
->offset
!= NULL
&& ir
->op
!= ir_txf
;
2343 /* Texel offsets go in the message header; Gen4 also requires headers. */
2344 inst
->header_present
= use_texture_offset
|| brw
->gen
< 5;
2346 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2347 inst
->sampler
= sampler
;
2348 inst
->dst
= dst_reg(this, ir
->type
);
2349 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2350 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2352 if (use_texture_offset
)
2353 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
2355 /* MRF for the first parameter */
2356 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2358 if (ir
->op
== ir_txs
) {
2359 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2360 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2362 int i
, coord_mask
= 0, zero_mask
= 0;
2363 /* Load the coordinate */
2364 /* FINISHME: gl_clamp_mask and saturate */
2365 for (i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++)
2366 coord_mask
|= (1 << i
);
2368 zero_mask
|= (1 << i
);
2370 if (ir
->offset
&& ir
->op
== ir_txf
) {
2371 /* It appears that the ld instruction used for txf does its
2372 * address bounds check before adding in the offset. To work
2373 * around this, just add the integer offset to the integer
2374 * texel coordinate, and don't put the offset in the header.
2376 ir_constant
*offset
= ir
->offset
->as_constant();
2379 for (int j
= 0; j
< ir
->coordinate
->type
->vector_elements
; j
++) {
2380 src_reg src
= coordinate
;
2381 src
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(src
.swizzle
, j
),
2382 BRW_GET_SWZ(src
.swizzle
, j
),
2383 BRW_GET_SWZ(src
.swizzle
, j
),
2384 BRW_GET_SWZ(src
.swizzle
, j
));
2385 emit(ADD(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, 1 << j
),
2386 src
, offset
->value
.i
[j
]));
2389 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2392 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2394 /* Load the shadow comparitor */
2395 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
2396 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2398 shadow_comparitor
));
2402 /* Load the LOD info */
2403 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2405 if (brw
->gen
>= 5) {
2406 mrf
= param_base
+ 1;
2407 if (ir
->shadow_comparitor
) {
2408 writemask
= WRITEMASK_Y
;
2409 /* mlen already incremented */
2411 writemask
= WRITEMASK_X
;
2414 } else /* brw->gen == 4 */ {
2416 writemask
= WRITEMASK_W
;
2418 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2419 } else if (ir
->op
== ir_txf
) {
2420 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2421 } else if (ir
->op
== ir_txf_ms
) {
2422 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2426 /* on Gen7, there is an additional MCS parameter here after SI,
2427 * but we don't bother to emit it since it's always zero. If
2428 * we start supporting texturing from CMS surfaces, this will have
2431 } else if (ir
->op
== ir_txd
) {
2432 const glsl_type
*type
= lod_type
;
2434 if (brw
->gen
>= 5) {
2435 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2436 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2437 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2438 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2441 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2442 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2443 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2444 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2445 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2448 if (ir
->shadow_comparitor
) {
2449 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2450 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2451 shadow_comparitor
));
2454 } else /* brw->gen == 4 */ {
2455 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2456 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2464 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2465 * spec requires layers.
2467 if (ir
->op
== ir_txs
) {
2468 glsl_type
const *type
= ir
->sampler
->type
;
2469 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2470 type
->sampler_array
) {
2471 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2472 with_writemask(inst
->dst
, WRITEMASK_Z
),
2473 src_reg(inst
->dst
), src_reg(6));
2477 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2481 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
)
2483 int s
= key
->tex
.swizzles
[sampler
];
2485 this->result
= src_reg(this, ir
->type
);
2486 dst_reg
swizzled_result(this->result
);
2488 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2489 || s
== SWIZZLE_NOOP
) {
2490 emit(MOV(swizzled_result
, orig_val
));
2494 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2495 int swizzle
[4] = {0};
2497 for (int i
= 0; i
< 4; i
++) {
2498 switch (GET_SWZ(s
, i
)) {
2500 zero_mask
|= (1 << i
);
2503 one_mask
|= (1 << i
);
2506 copy_mask
|= (1 << i
);
2507 swizzle
[i
] = GET_SWZ(s
, i
);
2513 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2514 swizzled_result
.writemask
= copy_mask
;
2515 emit(MOV(swizzled_result
, orig_val
));
2519 swizzled_result
.writemask
= zero_mask
;
2520 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2524 swizzled_result
.writemask
= one_mask
;
2525 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2530 vec4_visitor::visit(ir_return
*ir
)
2532 assert(!"not reached");
2536 vec4_visitor::visit(ir_discard
*ir
)
2538 assert(!"not reached");
2542 vec4_visitor::visit(ir_if
*ir
)
2544 /* Don't point the annotation at the if statement, because then it plus
2545 * the then and else blocks get printed.
2547 this->base_ir
= ir
->condition
;
2549 if (brw
->gen
== 6) {
2553 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2554 emit(IF(predicate
));
2557 visit_instructions(&ir
->then_instructions
);
2559 if (!ir
->else_instructions
.is_empty()) {
2560 this->base_ir
= ir
->condition
;
2561 emit(BRW_OPCODE_ELSE
);
2563 visit_instructions(&ir
->else_instructions
);
2566 this->base_ir
= ir
->condition
;
2567 emit(BRW_OPCODE_ENDIF
);
2571 vec4_visitor::visit(ir_emit_vertex
*)
2573 assert(!"not reached");
2577 vec4_visitor::visit(ir_end_primitive
*)
2579 assert(!"not reached");
2583 vec4_visitor::emit_ndc_computation()
2585 /* Get the position */
2586 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2588 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2589 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2590 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2592 current_annotation
= "NDC";
2593 dst_reg ndc_w
= ndc
;
2594 ndc_w
.writemask
= WRITEMASK_W
;
2595 src_reg pos_w
= pos
;
2596 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2597 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2599 dst_reg ndc_xyz
= ndc
;
2600 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2602 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2606 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
2609 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2610 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2611 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2612 dst_reg header1_w
= header1
;
2613 header1_w
.writemask
= WRITEMASK_W
;
2615 emit(MOV(header1
, 0u));
2617 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2618 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2620 current_annotation
= "Point size";
2621 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2622 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2625 if (key
->userclip_active
) {
2626 current_annotation
= "Clipping flags";
2627 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
2628 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
2630 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2631 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
2632 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
2634 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2635 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
2636 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
2637 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
2640 /* i965 clipping workaround:
2641 * 1) Test for -ve rhw
2643 * set ndc = (0,0,0,0)
2646 * Later, clipping will detect ucp[6] and ensure the primitive is
2647 * clipped against all fixed planes.
2649 if (brw
->has_negative_rhw_bug
) {
2650 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2651 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2652 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2653 vec4_instruction
*inst
;
2654 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2655 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2656 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
2657 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2660 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2661 } else if (brw
->gen
< 6) {
2662 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2664 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2665 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2666 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
2667 src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
2669 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
2670 emit(MOV(retype(brw_writemask(reg
, WRITEMASK_Y
), BRW_REGISTER_TYPE_D
),
2671 src_reg(output_reg
[VARYING_SLOT_LAYER
])));
2677 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
2679 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2681 * "If a linked set of shaders forming the vertex stage contains no
2682 * static write to gl_ClipVertex or gl_ClipDistance, but the
2683 * application has requested clipping against user clip planes through
2684 * the API, then the coordinate written to gl_Position is used for
2685 * comparison against the user clip planes."
2687 * This function is only called if the shader didn't write to
2688 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2689 * if the user wrote to it; otherwise we use gl_Position.
2691 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
2692 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
2693 clip_vertex
= VARYING_SLOT_POS
;
2696 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
2698 reg
.writemask
= 1 << i
;
2700 src_reg(output_reg
[clip_vertex
]),
2701 src_reg(this->userplane
[i
+ offset
])));
2706 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
2708 assert (varying
< VARYING_SLOT_MAX
);
2709 reg
.type
= output_reg
[varying
].type
;
2710 current_annotation
= output_reg_annotation
[varying
];
2711 /* Copy the register, saturating if necessary */
2712 vec4_instruction
*inst
= emit(MOV(reg
,
2713 src_reg(output_reg
[varying
])));
2714 if ((varying
== VARYING_SLOT_COL0
||
2715 varying
== VARYING_SLOT_COL1
||
2716 varying
== VARYING_SLOT_BFC0
||
2717 varying
== VARYING_SLOT_BFC1
) &&
2718 key
->clamp_vertex_color
) {
2719 inst
->saturate
= true;
2724 vec4_visitor::emit_urb_slot(int mrf
, int varying
)
2726 struct brw_reg hw_reg
= brw_message_reg(mrf
);
2727 dst_reg reg
= dst_reg(MRF
, mrf
);
2728 reg
.type
= BRW_REGISTER_TYPE_F
;
2731 case VARYING_SLOT_PSIZ
:
2732 /* PSIZ is always in slot 0, and is coupled with other flags. */
2733 current_annotation
= "indices, point width, clip flags";
2734 emit_psiz_and_flags(hw_reg
);
2736 case BRW_VARYING_SLOT_NDC
:
2737 current_annotation
= "NDC";
2738 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
2740 case VARYING_SLOT_POS
:
2741 current_annotation
= "gl_Position";
2742 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
2744 case VARYING_SLOT_EDGE
:
2745 /* This is present when doing unfilled polygons. We're supposed to copy
2746 * the edge flag from the user-provided vertex array
2747 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
2748 * of that attribute (starts as 1.0f). This is then used in clipping to
2749 * determine which edges should be drawn as wireframe.
2751 current_annotation
= "edge flag";
2752 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
2753 glsl_type::float_type
, WRITEMASK_XYZW
))));
2755 case BRW_VARYING_SLOT_PAD
:
2756 /* No need to write to this slot */
2759 emit_generic_urb_slot(reg
, varying
);
2765 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
2767 if (brw
->gen
>= 6) {
2768 /* URB data written (does not include the message header reg) must
2769 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
2770 * section 5.4.3.2.2: URB_INTERLEAVED.
2772 * URB entries are allocated on a multiple of 1024 bits, so an
2773 * extra 128 bits written here to make the end align to 256 is
2776 if ((mlen
% 2) != 1)
2784 vec4_vs_visitor::emit_urb_write_header(int mrf
)
2786 /* No need to do anything for VS; an implied write to this MRF will be
2787 * performed by VS_OPCODE_URB_WRITE.
2793 vec4_vs_visitor::emit_urb_write_opcode(bool complete
)
2795 /* For VS, the URB writes end the thread. */
2797 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
2798 emit_shader_time_end();
2801 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
2802 inst
->urb_write_flags
= complete
?
2803 BRW_URB_WRITE_EOT_COMPLETE
: BRW_URB_WRITE_NO_FLAGS
;
2809 * Generates the VUE payload plus the necessary URB write instructions to
2812 * The VUE layout is documented in Volume 2a.
2815 vec4_visitor::emit_vertex()
2817 /* MRF 0 is reserved for the debugger, so start with message header
2822 /* In the process of generating our URB write message contents, we
2823 * may need to unspill a register or load from an array. Those
2824 * reads would use MRFs 14-15.
2826 int max_usable_mrf
= 13;
2828 /* The following assertion verifies that max_usable_mrf causes an
2829 * even-numbered amount of URB write data, which will meet gen6's
2830 * requirements for length alignment.
2832 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
2834 /* First mrf is the g0-based message header containing URB handles and
2837 emit_urb_write_header(mrf
++);
2840 emit_ndc_computation();
2843 /* Lower legacy ff and ClipVertex clipping to clip distances */
2844 if (key
->userclip_active
&& !key
->uses_clip_distance
) {
2845 current_annotation
= "user clip distances";
2847 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
2848 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
2850 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
2851 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
2854 /* Set up the VUE data for the first URB write */
2856 for (slot
= 0; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
2857 emit_urb_slot(mrf
++, prog_data
->vue_map
.slot_to_varying
[slot
]);
2859 /* If this was max_usable_mrf, we can't fit anything more into this URB
2862 if (mrf
> max_usable_mrf
) {
2868 bool complete
= slot
>= prog_data
->vue_map
.num_slots
;
2869 current_annotation
= "URB write";
2870 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
2871 inst
->base_mrf
= base_mrf
;
2872 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2874 /* Optional second URB write */
2878 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
2879 assert(mrf
< max_usable_mrf
);
2881 emit_urb_slot(mrf
++, prog_data
->vue_map
.slot_to_varying
[slot
]);
2884 current_annotation
= "URB write";
2885 inst
= emit_urb_write_opcode(true /* complete */);
2886 inst
->base_mrf
= base_mrf
;
2887 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2888 /* URB destination offset. In the previous write, we got MRFs
2889 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
2890 * URB row increments, and each of our MRFs is half of one of
2891 * those, since we're doing interleaved writes.
2893 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
2898 vec4_vs_visitor::emit_thread_end()
2900 /* For VS, we always end the thread by emitting a single vertex.
2901 * emit_urb_write_opcode() will take care of setting the eot flag on the
2908 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
2909 src_reg
*reladdr
, int reg_offset
)
2911 /* Because we store the values to scratch interleaved like our
2912 * vertex data, we need to scale the vec4 index by 2.
2914 int message_header_scale
= 2;
2916 /* Pre-gen6, the message header uses byte offsets instead of vec4
2917 * (16-byte) offset units.
2920 message_header_scale
*= 16;
2923 src_reg index
= src_reg(this, glsl_type::int_type
);
2925 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2926 emit_before(inst
, MUL(dst_reg(index
),
2927 index
, src_reg(message_header_scale
)));
2931 return src_reg(reg_offset
* message_header_scale
);
2936 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
2937 src_reg
*reladdr
, int reg_offset
)
2940 src_reg index
= src_reg(this, glsl_type::int_type
);
2942 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2944 /* Pre-gen6, the message header uses byte offsets instead of vec4
2945 * (16-byte) offset units.
2948 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
2953 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
2954 return src_reg(reg_offset
* message_header_scale
);
2959 * Emits an instruction before @inst to load the value named by @orig_src
2960 * from scratch space at @base_offset to @temp.
2962 * @base_offset is measured in 32-byte units (the size of a register).
2965 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2966 dst_reg temp
, src_reg orig_src
,
2969 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2970 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2972 emit_before(inst
, SCRATCH_READ(temp
, index
));
2976 * Emits an instruction after @inst to store the value to be written
2977 * to @orig_dst to scratch space at @base_offset, from @temp.
2979 * @base_offset is measured in 32-byte units (the size of a register).
2982 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
, int base_offset
)
2984 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
2985 src_reg index
= get_scratch_offset(inst
, inst
->dst
.reladdr
, reg_offset
);
2987 /* Create a temporary register to store *inst's result in.
2989 * We have to be careful in MOVing from our temporary result register in
2990 * the scratch write. If we swizzle from channels of the temporary that
2991 * weren't initialized, it will confuse live interval analysis, which will
2992 * make spilling fail to make progress.
2994 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2995 temp
.type
= inst
->dst
.type
;
2996 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
2998 for (int i
= 0; i
< 4; i
++)
2999 if (inst
->dst
.writemask
& (1 << i
))
3002 swizzles
[i
] = first_writemask_chan
;
3003 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3004 swizzles
[2], swizzles
[3]);
3006 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3007 inst
->dst
.writemask
));
3008 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3009 write
->predicate
= inst
->predicate
;
3010 write
->ir
= inst
->ir
;
3011 write
->annotation
= inst
->annotation
;
3012 inst
->insert_after(write
);
3014 inst
->dst
.file
= temp
.file
;
3015 inst
->dst
.reg
= temp
.reg
;
3016 inst
->dst
.reg_offset
= temp
.reg_offset
;
3017 inst
->dst
.reladdr
= NULL
;
3021 * We can't generally support array access in GRF space, because a
3022 * single instruction's destination can only span 2 contiguous
3023 * registers. So, we send all GRF arrays that get variable index
3024 * access to scratch space.
3027 vec4_visitor::move_grf_array_access_to_scratch()
3029 int scratch_loc
[this->virtual_grf_count
];
3031 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
3032 scratch_loc
[i
] = -1;
3035 /* First, calculate the set of virtual GRFs that need to be punted
3036 * to scratch due to having any array access on them, and where in
3039 foreach_list(node
, &this->instructions
) {
3040 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3042 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3043 scratch_loc
[inst
->dst
.reg
] == -1) {
3044 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3045 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
3048 for (int i
= 0 ; i
< 3; i
++) {
3049 src_reg
*src
= &inst
->src
[i
];
3051 if (src
->file
== GRF
&& src
->reladdr
&&
3052 scratch_loc
[src
->reg
] == -1) {
3053 scratch_loc
[src
->reg
] = c
->last_scratch
;
3054 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
3059 /* Now, for anything that will be accessed through scratch, rewrite
3060 * it to load/store. Note that this is a _safe list walk, because
3061 * we may generate a new scratch_write instruction after the one
3064 foreach_list_safe(node
, &this->instructions
) {
3065 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3067 /* Set up the annotation tracking for new generated instructions. */
3069 current_annotation
= inst
->annotation
;
3071 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3072 emit_scratch_write(inst
, scratch_loc
[inst
->dst
.reg
]);
3075 for (int i
= 0 ; i
< 3; i
++) {
3076 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3079 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3081 emit_scratch_read(inst
, temp
, inst
->src
[i
],
3082 scratch_loc
[inst
->src
[i
].reg
]);
3084 inst
->src
[i
].file
= temp
.file
;
3085 inst
->src
[i
].reg
= temp
.reg
;
3086 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3087 inst
->src
[i
].reladdr
= NULL
;
3093 * Emits an instruction before @inst to load the value named by @orig_src
3094 * from the pull constant buffer (surface) at @base_offset to @temp.
3097 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
3098 dst_reg temp
, src_reg orig_src
,
3101 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3102 src_reg index
= src_reg((unsigned)SURF_INDEX_VERT_CONST_BUFFER
);
3103 src_reg offset
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
3104 vec4_instruction
*load
;
3106 if (brw
->gen
>= 7) {
3107 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3108 grf_offset
.type
= offset
.type
;
3109 emit_before(inst
, MOV(grf_offset
, offset
));
3111 load
= new(mem_ctx
) vec4_instruction(this,
3112 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3113 temp
, index
, src_reg(grf_offset
));
3115 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
3116 temp
, index
, offset
);
3117 load
->base_mrf
= 14;
3120 emit_before(inst
, load
);
3124 * Implements array access of uniforms by inserting a
3125 * PULL_CONSTANT_LOAD instruction.
3127 * Unlike temporary GRF array access (where we don't support it due to
3128 * the difficulty of doing relative addressing on instruction
3129 * destinations), we could potentially do array access of uniforms
3130 * that were loaded in GRF space as push constants. In real-world
3131 * usage we've seen, though, the arrays being used are always larger
3132 * than we could load as push constants, so just always move all
3133 * uniform array access out to a pull constant buffer.
3136 vec4_visitor::move_uniform_array_access_to_pull_constants()
3138 int pull_constant_loc
[this->uniforms
];
3140 for (int i
= 0; i
< this->uniforms
; i
++) {
3141 pull_constant_loc
[i
] = -1;
3144 /* Walk through and find array access of uniforms. Put a copy of that
3145 * uniform in the pull constant buffer.
3147 * Note that we don't move constant-indexed accesses to arrays. No
3148 * testing has been done of the performance impact of this choice.
3150 foreach_list_safe(node
, &this->instructions
) {
3151 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3153 for (int i
= 0 ; i
< 3; i
++) {
3154 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3157 int uniform
= inst
->src
[i
].reg
;
3159 /* If this array isn't already present in the pull constant buffer,
3162 if (pull_constant_loc
[uniform
] == -1) {
3163 const float **values
= &prog_data
->param
[uniform
* 4];
3165 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
/ 4;
3167 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3168 prog_data
->pull_param
[prog_data
->nr_pull_params
++]
3173 /* Set up the annotation tracking for new generated instructions. */
3175 current_annotation
= inst
->annotation
;
3177 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3179 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
3180 pull_constant_loc
[uniform
]);
3182 inst
->src
[i
].file
= temp
.file
;
3183 inst
->src
[i
].reg
= temp
.reg
;
3184 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3185 inst
->src
[i
].reladdr
= NULL
;
3189 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3190 * no need to track them as larger-than-vec4 objects. This will be
3191 * relied on in cutting out unused uniform vectors from push
3194 split_uniform_registers();
3198 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3200 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3204 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3205 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3209 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3210 struct brw_vec4_compile
*c
,
3211 struct gl_program
*prog
,
3212 const struct brw_vec4_prog_key
*key
,
3213 struct brw_vec4_prog_data
*prog_data
,
3214 struct gl_shader_program
*shader_prog
,
3215 struct brw_shader
*shader
,
3218 : debug_flag(debug_flag
)
3221 this->ctx
= &brw
->ctx
;
3222 this->shader_prog
= shader_prog
;
3223 this->shader
= shader
;
3225 this->mem_ctx
= mem_ctx
;
3226 this->failed
= false;
3228 this->base_ir
= NULL
;
3229 this->current_annotation
= NULL
;
3230 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3235 this->prog_data
= prog_data
;
3237 this->variable_ht
= hash_table_ctor(0,
3238 hash_table_pointer_hash
,
3239 hash_table_pointer_compare
);
3241 this->virtual_grf_start
= NULL
;
3242 this->virtual_grf_end
= NULL
;
3243 this->virtual_grf_sizes
= NULL
;
3244 this->virtual_grf_count
= 0;
3245 this->virtual_grf_reg_map
= NULL
;
3246 this->virtual_grf_reg_count
= 0;
3247 this->virtual_grf_array_size
= 0;
3248 this->live_intervals_valid
= false;
3250 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3255 vec4_visitor::~vec4_visitor()
3257 hash_table_dtor(this->variable_ht
);
3261 vec4_vs_visitor::vec4_vs_visitor(struct brw_context
*brw
,
3262 struct brw_vs_compile
*vs_compile
,
3263 struct brw_vs_prog_data
*vs_prog_data
,
3264 struct gl_shader_program
*prog
,
3265 struct brw_shader
*shader
,
3267 : vec4_visitor(brw
, &vs_compile
->base
, &vs_compile
->vp
->program
.Base
,
3268 &vs_compile
->key
.base
, &vs_prog_data
->base
, prog
, shader
,
3269 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
),
3270 vs_compile(vs_compile
),
3271 vs_prog_data(vs_prog_data
)
3277 vec4_visitor::fail(const char *format
, ...)
3287 va_start(va
, format
);
3288 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3290 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
3292 this->fail_msg
= msg
;
3295 fprintf(stderr
, "%s", msg
);
3299 } /* namespace brw */