2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
31 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
32 const src_reg
&src0
, const src_reg
&src1
,
35 this->opcode
= opcode
;
40 this->saturate
= false;
41 this->force_writemask_all
= false;
42 this->no_dd_clear
= false;
43 this->no_dd_check
= false;
44 this->writes_accumulator
= false;
45 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
46 this->predicate
= BRW_PREDICATE_NONE
;
47 this->predicate_inverse
= false;
49 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
50 this->shadow_compare
= false;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_size
= 0;
54 this->flag_subreg
= 0;
58 this->annotation
= NULL
;
62 vec4_visitor::emit(vec4_instruction
*inst
)
64 inst
->ir
= this->base_ir
;
65 inst
->annotation
= this->current_annotation
;
67 this->instructions
.push_tail(inst
);
73 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
74 vec4_instruction
*new_inst
)
76 new_inst
->ir
= inst
->ir
;
77 new_inst
->annotation
= inst
->annotation
;
79 inst
->insert_before(block
, new_inst
);
85 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
86 const src_reg
&src1
, const src_reg
&src2
)
88 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
93 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
96 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
100 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
102 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
106 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
108 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
112 vec4_visitor::emit(enum opcode opcode
)
114 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
119 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
121 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
126 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
127 const src_reg &src1) \
129 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
133 #define ALU2_ACC(op) \
135 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
136 const src_reg &src1) \
138 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
139 BRW_OPCODE_##op, dst, src0, src1); \
140 inst->writes_accumulator = true; \
146 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
147 const src_reg &src1, const src_reg &src2) \
149 assert(devinfo->gen >= 6); \
150 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
187 /** Gen4 predicated IF. */
189 vec4_visitor::IF(enum brw_predicate predicate
)
191 vec4_instruction
*inst
;
193 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
199 /** Gen6 IF with embedded comparison. */
201 vec4_visitor::IF(src_reg src0
, src_reg src1
,
202 enum brw_conditional_mod condition
)
204 assert(devinfo
->gen
== 6);
206 vec4_instruction
*inst
;
208 resolve_ud_negate(&src0
);
209 resolve_ud_negate(&src1
);
211 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
213 inst
->conditional_mod
= condition
;
219 * CMP: Sets the low bit of the destination channels with the result
220 * of the comparison, while the upper bits are undefined, and updates
221 * the flag register with the packed 16 bits of the result.
224 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
225 enum brw_conditional_mod condition
)
227 vec4_instruction
*inst
;
229 /* Take the instruction:
231 * CMP null<d> src0<f> src1<f>
233 * Original gen4 does type conversion to the destination type before
234 * comparison, producing garbage results for floating point comparisons.
236 * The destination type doesn't matter on newer generations, so we set the
237 * type to match src0 so we can compact the instruction.
239 dst
.type
= src0
.type
;
240 if (dst
.file
== HW_REG
)
241 dst
.fixed_hw_reg
.type
= dst
.type
;
243 resolve_ud_negate(&src0
);
244 resolve_ud_negate(&src1
);
246 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
247 inst
->conditional_mod
= condition
;
253 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
255 vec4_instruction
*inst
;
257 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
266 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
267 const src_reg
&index
)
269 vec4_instruction
*inst
;
271 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
280 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
282 static enum opcode dot_opcodes
[] = {
283 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
286 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
290 vec4_visitor::fix_3src_operand(const src_reg
&src
)
292 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
293 * able to use vertical stride of zero to replicate the vec4 uniform, like
295 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
297 * But you can't, since vertical stride is always four in three-source
298 * instructions. Instead, insert a MOV instruction to do the replication so
299 * that the three-source instruction can consume it.
302 /* The MOV is only needed if the source is a uniform or immediate. */
303 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
306 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
309 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
310 expanded
.type
= src
.type
;
311 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
312 return src_reg(expanded
);
316 vec4_visitor::resolve_source_modifiers(const src_reg
&src
)
318 if (!src
.abs
&& !src
.negate
)
321 dst_reg resolved
= dst_reg(this, glsl_type::ivec4_type
);
322 resolved
.type
= src
.type
;
323 emit(MOV(resolved
, src
));
325 return src_reg(resolved
);
329 vec4_visitor::fix_math_operand(const src_reg
&src
)
331 if (devinfo
->gen
< 6 || devinfo
->gen
>= 8 || src
.file
== BAD_FILE
)
334 /* The gen6 math instruction ignores the source modifiers --
335 * swizzle, abs, negate, and at least some parts of the register
336 * region description.
338 * Rather than trying to enumerate all these cases, *always* expand the
339 * operand to a temp GRF for gen6.
341 * For gen7, keep the operand as-is, except if immediate, which gen7 still
345 if (devinfo
->gen
== 7 && src
.file
!= IMM
)
348 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
349 expanded
.type
= src
.type
;
350 emit(MOV(expanded
, src
));
351 return src_reg(expanded
);
355 vec4_visitor::emit_math(enum opcode opcode
,
357 const src_reg
&src0
, const src_reg
&src1
)
359 vec4_instruction
*math
=
360 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
362 if (devinfo
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
363 /* MATH on Gen6 must be align1, so we can't do writemasks. */
364 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
365 math
->dst
.type
= dst
.type
;
366 math
= emit(MOV(dst
, src_reg(math
->dst
)));
367 } else if (devinfo
->gen
< 6) {
369 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
376 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
378 if (devinfo
->gen
< 7) {
379 unreachable("ir_unop_pack_half_2x16 should be lowered");
382 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
383 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
385 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
387 * Because this instruction does not have a 16-bit floating-point type,
388 * the destination data type must be Word (W).
390 * The destination must be DWord-aligned and specify a horizontal stride
391 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
392 * each destination channel and the upper word is not modified.
394 * The above restriction implies that the f32to16 instruction must use
395 * align1 mode, because only in align1 mode is it possible to specify
396 * horizontal stride. We choose here to defy the hardware docs and emit
397 * align16 instructions.
399 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
400 * instructions. I was partially successful in that the code passed all
401 * tests. However, the code was dubiously correct and fragile, and the
402 * tests were not harsh enough to probe that frailty. Not trusting the
403 * code, I chose instead to remain in align16 mode in defiance of the hw
406 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
407 * simulator, emitting a f32to16 in align16 mode with UD as destination
408 * data type is safe. The behavior differs from that specified in the PRM
409 * in that the upper word of each destination channel is cleared to 0.
412 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
413 src_reg
tmp_src(tmp_dst
);
416 /* Verify the undocumented behavior on which the following instructions
417 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
418 * then the result of the bit-or instruction below will be incorrect.
420 * You should inspect the disasm output in order to verify that the MOV is
421 * not optimized away.
423 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
426 /* Give tmp the form below, where "." means untouched.
429 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
431 * That the upper word of each write-channel be 0 is required for the
432 * following bit-shift and bit-or instructions to work. Note that this
433 * relies on the undocumented hardware behavior mentioned above.
435 tmp_dst
.writemask
= WRITEMASK_XY
;
436 emit(F32TO16(tmp_dst
, src0
));
438 /* Give the write-channels of dst the form:
441 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
442 emit(SHL(dst
, tmp_src
, src_reg(16u)));
444 /* Finally, give the write-channels of dst the form of packHalf2x16's
448 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
449 emit(OR(dst
, src_reg(dst
), tmp_src
));
453 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
455 if (devinfo
->gen
< 7) {
456 unreachable("ir_unop_unpack_half_2x16 should be lowered");
459 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
460 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
462 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
464 * Because this instruction does not have a 16-bit floating-point type,
465 * the source data type must be Word (W). The destination type must be
468 * To use W as the source data type, we must adjust horizontal strides,
469 * which is only possible in align1 mode. All my [chadv] attempts at
470 * emitting align1 instructions for unpackHalf2x16 failed to pass the
471 * Piglit tests, so I gave up.
473 * I've verified that, on gen7 hardware and the simulator, it is safe to
474 * emit f16to32 in align16 mode with UD as source data type.
477 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
478 src_reg
tmp_src(tmp_dst
);
480 tmp_dst
.writemask
= WRITEMASK_X
;
481 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
483 tmp_dst
.writemask
= WRITEMASK_Y
;
484 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
486 dst
.writemask
= WRITEMASK_XY
;
487 emit(F16TO32(dst
, tmp_src
));
491 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
493 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
494 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
495 * is not suitable to generate the shift values, but we can use the packed
496 * vector float and a type-converting MOV.
498 dst_reg
shift(this, glsl_type::uvec4_type
);
499 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
501 dst_reg
shifted(this, glsl_type::uvec4_type
);
502 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
503 emit(SHR(shifted
, src0
, src_reg(shift
)));
505 shifted
.type
= BRW_REGISTER_TYPE_UB
;
506 dst_reg
f(this, glsl_type::vec4_type
);
507 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
509 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
513 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
515 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
516 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
517 * is not suitable to generate the shift values, but we can use the packed
518 * vector float and a type-converting MOV.
520 dst_reg
shift(this, glsl_type::uvec4_type
);
521 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
523 dst_reg
shifted(this, glsl_type::uvec4_type
);
524 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
525 emit(SHR(shifted
, src0
, src_reg(shift
)));
527 shifted
.type
= BRW_REGISTER_TYPE_B
;
528 dst_reg
f(this, glsl_type::vec4_type
);
529 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
531 dst_reg
scaled(this, glsl_type::vec4_type
);
532 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
534 dst_reg
max(this, glsl_type::vec4_type
);
535 emit_minmax(BRW_CONDITIONAL_GE
, max
, src_reg(scaled
), src_reg(-1.0f
));
536 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
540 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
542 dst_reg
saturated(this, glsl_type::vec4_type
);
543 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
544 inst
->saturate
= true;
546 dst_reg
scaled(this, glsl_type::vec4_type
);
547 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
549 dst_reg
rounded(this, glsl_type::vec4_type
);
550 emit(RNDE(rounded
, src_reg(scaled
)));
552 dst_reg
u(this, glsl_type::uvec4_type
);
553 emit(MOV(u
, src_reg(rounded
)));
556 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
560 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
562 dst_reg
max(this, glsl_type::vec4_type
);
563 emit_minmax(BRW_CONDITIONAL_GE
, max
, src0
, src_reg(-1.0f
));
565 dst_reg
min(this, glsl_type::vec4_type
);
566 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
568 dst_reg
scaled(this, glsl_type::vec4_type
);
569 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
571 dst_reg
rounded(this, glsl_type::vec4_type
);
572 emit(RNDE(rounded
, src_reg(scaled
)));
574 dst_reg
i(this, glsl_type::ivec4_type
);
575 emit(MOV(i
, src_reg(rounded
)));
578 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
582 vec4_visitor::visit_instructions(const exec_list
*list
)
584 foreach_in_list(ir_instruction
, ir
, list
) {
591 * Returns the minimum number of vec4 elements needed to pack a type.
593 * For simple types, it will return 1 (a single vec4); for matrices, the
594 * number of columns; for array and struct, the sum of the vec4_size of
595 * each of its elements; and for sampler and atomic, zero.
597 * This method is useful to calculate how much register space is needed to
598 * store a particular type.
601 vec4_visitor::type_size(const struct glsl_type
*type
)
606 switch (type
->base_type
) {
609 case GLSL_TYPE_FLOAT
:
611 if (type
->is_matrix()) {
612 return type
->matrix_columns
;
614 /* Regardless of size of vector, it gets a vec4. This is bad
615 * packing for things like floats, but otherwise arrays become a
616 * mess. Hopefully a later pass over the code can pack scalars
617 * down if appropriate.
621 case GLSL_TYPE_ARRAY
:
622 assert(type
->length
> 0);
623 return type_size(type
->fields
.array
) * type
->length
;
624 case GLSL_TYPE_STRUCT
:
626 for (i
= 0; i
< type
->length
; i
++) {
627 size
+= type_size(type
->fields
.structure
[i
].type
);
630 case GLSL_TYPE_SUBROUTINE
:
633 case GLSL_TYPE_SAMPLER
:
634 /* Samplers take up no register space, since they're baked in at
638 case GLSL_TYPE_ATOMIC_UINT
:
640 case GLSL_TYPE_IMAGE
:
641 return DIV_ROUND_UP(BRW_IMAGE_PARAM_SIZE
, 4);
643 case GLSL_TYPE_DOUBLE
:
644 case GLSL_TYPE_ERROR
:
645 case GLSL_TYPE_INTERFACE
:
646 unreachable("not reached");
652 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
657 this->reg
= v
->alloc
.allocate(v
->type_size(type
));
659 if (type
->is_array() || type
->is_record()) {
660 this->swizzle
= BRW_SWIZZLE_NOOP
;
662 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
665 this->type
= brw_type_for_base_type(type
);
668 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
675 this->reg
= v
->alloc
.allocate(v
->type_size(type
) * size
);
677 this->swizzle
= BRW_SWIZZLE_NOOP
;
679 this->type
= brw_type_for_base_type(type
);
682 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
687 this->reg
= v
->alloc
.allocate(v
->type_size(type
));
689 if (type
->is_array() || type
->is_record()) {
690 this->writemask
= WRITEMASK_XYZW
;
692 this->writemask
= (1 << type
->vector_elements
) - 1;
695 this->type
= brw_type_for_base_type(type
);
699 vec4_visitor::setup_vector_uniform_values(const gl_constant_value
*values
,
702 static const gl_constant_value zero
= { 0 };
704 for (unsigned i
= 0; i
< n
; ++i
)
705 stage_prog_data
->param
[4 * uniforms
+ i
] = &values
[i
];
707 for (unsigned i
= n
; i
< 4; ++i
)
708 stage_prog_data
->param
[4 * uniforms
+ i
] = &zero
;
710 uniform_vector_size
[uniforms
++] = n
;
713 /* Our support for uniforms is piggy-backed on the struct
714 * gl_fragment_program, because that's where the values actually
715 * get stored, rather than in some global gl_shader_program uniform
719 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
721 int namelen
= strlen(ir
->name
);
723 /* The data for our (non-builtin) uniforms is stored in a series of
724 * gl_uniform_driver_storage structs for each subcomponent that
725 * glGetUniformLocation() could name. We know it's been set up in the same
726 * order we'd walk the type, so walk the list of storage and find anything
727 * with our name, or the prefix of a component that starts with our name.
729 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
730 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
732 if (storage
->builtin
)
735 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
736 (storage
->name
[namelen
] != 0 &&
737 storage
->name
[namelen
] != '.' &&
738 storage
->name
[namelen
] != '[')) {
742 const unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
743 storage
->type
->matrix_columns
);
744 const unsigned vector_size
= storage
->type
->vector_elements
;
746 for (unsigned s
= 0; s
< vector_count
; s
++)
747 setup_vector_uniform_values(&storage
->storage
[s
* vector_size
],
753 vec4_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
755 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
756 assert(this->uniforms
< uniform_array_size
);
757 this->uniform_vector_size
[this->uniforms
] = 4;
758 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
759 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
760 for (int j
= 0; j
< 4; ++j
) {
761 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
762 (gl_constant_value
*) &clip_planes
[i
][j
];
768 /* Our support for builtin uniforms is even scarier than non-builtin.
769 * It sits on top of the PROG_STATE_VAR parameters that are
770 * automatically updated from GL context state.
773 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
775 const ir_state_slot
*const slots
= ir
->get_state_slots();
776 assert(slots
!= NULL
);
778 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
779 /* This state reference has already been setup by ir_to_mesa,
780 * but we'll get the same index back here. We can reference
781 * ParameterValues directly, since unlike brw_fs.cpp, we never
782 * add new state references during compile.
784 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
785 (gl_state_index
*)slots
[i
].tokens
);
786 gl_constant_value
*values
=
787 &this->prog
->Parameters
->ParameterValues
[index
][0];
789 assert(this->uniforms
< uniform_array_size
);
791 for (unsigned j
= 0; j
< 4; j
++)
792 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
793 &values
[GET_SWZ(slots
[i
].swizzle
, j
)];
795 this->uniform_vector_size
[this->uniforms
] =
796 (ir
->type
->is_scalar() || ir
->type
->is_vector() ||
797 ir
->type
->is_matrix() ? ir
->type
->vector_elements
: 4);
804 vec4_visitor::variable_storage(ir_variable
*var
)
806 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
810 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
811 enum brw_predicate
*predicate
)
813 ir_expression
*expr
= ir
->as_expression();
815 *predicate
= BRW_PREDICATE_NORMAL
;
817 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
819 vec4_instruction
*inst
;
821 assert(expr
->get_num_operands() <= 3);
822 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
823 expr
->operands
[i
]->accept(this);
824 op
[i
] = this->result
;
826 resolve_ud_negate(&op
[i
]);
829 switch (expr
->operation
) {
830 case ir_unop_logic_not
:
831 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
832 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
835 case ir_binop_logic_xor
:
836 if (devinfo
->gen
<= 5) {
837 src_reg temp
= src_reg(this, ir
->type
);
838 emit(XOR(dst_reg(temp
), op
[0], op
[1]));
839 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
841 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
843 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
846 case ir_binop_logic_or
:
847 if (devinfo
->gen
<= 5) {
848 src_reg temp
= src_reg(this, ir
->type
);
849 emit(OR(dst_reg(temp
), op
[0], op
[1]));
850 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
852 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
854 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
857 case ir_binop_logic_and
:
858 if (devinfo
->gen
<= 5) {
859 src_reg temp
= src_reg(this, ir
->type
);
860 emit(AND(dst_reg(temp
), op
[0], op
[1]));
861 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
863 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
865 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
869 if (devinfo
->gen
>= 6) {
870 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
872 inst
= emit(MOV(dst_null_f(), op
[0]));
873 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
878 if (devinfo
->gen
>= 6) {
879 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
881 inst
= emit(MOV(dst_null_d(), op
[0]));
882 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
886 case ir_binop_all_equal
:
887 if (devinfo
->gen
<= 5) {
888 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
889 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
891 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
892 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
895 case ir_binop_any_nequal
:
896 if (devinfo
->gen
<= 5) {
897 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
898 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
900 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
901 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
905 if (devinfo
->gen
<= 5) {
906 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
908 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
909 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
912 case ir_binop_greater
:
913 case ir_binop_gequal
:
915 case ir_binop_lequal
:
917 case ir_binop_nequal
:
918 if (devinfo
->gen
<= 5) {
919 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
920 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
922 emit(CMP(dst_null_d(), op
[0], op
[1],
923 brw_conditional_for_comparison(expr
->operation
)));
926 case ir_triop_csel
: {
927 /* Expand the boolean condition into the flag register. */
928 inst
= emit(MOV(dst_null_d(), op
[0]));
929 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
931 /* Select which boolean to return. */
932 dst_reg
temp(this, expr
->operands
[1]->type
);
933 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
934 inst
->predicate
= BRW_PREDICATE_NORMAL
;
936 /* Expand the result to a condition code. */
937 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
938 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
943 unreachable("not reached");
950 resolve_ud_negate(&this->result
);
952 vec4_instruction
*inst
= emit(AND(dst_null_d(), this->result
, src_reg(1)));
953 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
957 * Emit a gen6 IF statement with the comparison folded into the IF
961 vec4_visitor::emit_if_gen6(ir_if
*ir
)
963 ir_expression
*expr
= ir
->condition
->as_expression();
965 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
969 assert(expr
->get_num_operands() <= 3);
970 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
971 expr
->operands
[i
]->accept(this);
972 op
[i
] = this->result
;
975 switch (expr
->operation
) {
976 case ir_unop_logic_not
:
977 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
980 case ir_binop_logic_xor
:
981 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
984 case ir_binop_logic_or
:
985 temp
= dst_reg(this, glsl_type::bool_type
);
986 emit(OR(temp
, op
[0], op
[1]));
987 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
990 case ir_binop_logic_and
:
991 temp
= dst_reg(this, glsl_type::bool_type
);
992 emit(AND(temp
, op
[0], op
[1]));
993 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
997 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1001 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1004 case ir_binop_greater
:
1005 case ir_binop_gequal
:
1007 case ir_binop_lequal
:
1008 case ir_binop_equal
:
1009 case ir_binop_nequal
:
1010 emit(IF(op
[0], op
[1],
1011 brw_conditional_for_comparison(expr
->operation
)));
1014 case ir_binop_all_equal
:
1015 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1016 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
1019 case ir_binop_any_nequal
:
1020 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1021 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1025 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1026 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1029 case ir_triop_csel
: {
1030 /* Expand the boolean condition into the flag register. */
1031 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
1032 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1034 /* Select which boolean to return. */
1035 dst_reg
temp(this, expr
->operands
[1]->type
);
1036 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
1037 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1039 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
1044 unreachable("not reached");
1049 ir
->condition
->accept(this);
1051 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
1055 vec4_visitor::visit(ir_variable
*ir
)
1057 dst_reg
*reg
= NULL
;
1059 if (variable_storage(ir
))
1062 switch (ir
->data
.mode
) {
1063 case ir_var_shader_in
:
1064 assert(ir
->data
.location
!= -1);
1065 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
1068 case ir_var_shader_out
:
1069 assert(ir
->data
.location
!= -1);
1070 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1072 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1073 output_reg
[ir
->data
.location
+ i
] = *reg
;
1074 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
1075 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
1080 case ir_var_temporary
:
1081 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1084 case ir_var_uniform
:
1085 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1087 /* Thanks to the lower_ubo_reference pass, we will see only
1088 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1089 * variables, so no need for them to be in variable_ht.
1091 * Some uniforms, such as samplers and atomic counters, have no actual
1092 * storage, so we should ignore them.
1094 if (ir
->is_in_buffer_block() || type_size(ir
->type
) == 0)
1097 /* Track how big the whole uniform variable is, in case we need to put a
1098 * copy of its data into pull constants for array access.
1100 assert(this->uniforms
< uniform_array_size
);
1101 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1103 if (!strncmp(ir
->name
, "gl_", 3)) {
1104 setup_builtin_uniform_values(ir
);
1106 setup_uniform_values(ir
);
1110 case ir_var_system_value
:
1111 reg
= make_reg_for_system_value(ir
->data
.location
, ir
->type
);
1115 unreachable("not reached");
1118 reg
->type
= brw_type_for_base_type(ir
->type
);
1119 hash_table_insert(this->variable_ht
, reg
, ir
);
1123 vec4_visitor::visit(ir_loop
*ir
)
1125 /* We don't want debugging output to print the whole body of the
1126 * loop as the annotation.
1128 this->base_ir
= NULL
;
1130 emit(BRW_OPCODE_DO
);
1132 visit_instructions(&ir
->body_instructions
);
1134 emit(BRW_OPCODE_WHILE
);
1138 vec4_visitor::visit(ir_loop_jump
*ir
)
1141 case ir_loop_jump::jump_break
:
1142 emit(BRW_OPCODE_BREAK
);
1144 case ir_loop_jump::jump_continue
:
1145 emit(BRW_OPCODE_CONTINUE
);
1152 vec4_visitor::visit(ir_function_signature
*)
1154 unreachable("not reached");
1158 vec4_visitor::visit(ir_function
*ir
)
1160 /* Ignore function bodies other than main() -- we shouldn't see calls to
1161 * them since they should all be inlined.
1163 if (strcmp(ir
->name
, "main") == 0) {
1164 const ir_function_signature
*sig
;
1167 sig
= ir
->matching_signature(NULL
, &empty
, false);
1171 visit_instructions(&sig
->body
);
1176 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1178 /* 3-src instructions were introduced in gen6. */
1179 if (devinfo
->gen
< 6)
1182 /* MAD can only handle floating-point data. */
1183 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1188 bool mul_negate
, mul_abs
;
1190 for (int i
= 0; i
< 2; i
++) {
1194 mul
= ir
->operands
[i
]->as_expression();
1195 nonmul
= ir
->operands
[1 - i
];
1197 if (mul
&& mul
->operation
== ir_unop_abs
) {
1198 mul
= mul
->operands
[0]->as_expression();
1200 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
1201 mul
= mul
->operands
[0]->as_expression();
1205 if (mul
&& mul
->operation
== ir_binop_mul
)
1209 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1212 nonmul
->accept(this);
1213 src_reg src0
= fix_3src_operand(this->result
);
1215 mul
->operands
[0]->accept(this);
1216 src_reg src1
= fix_3src_operand(this->result
);
1217 src1
.negate
^= mul_negate
;
1220 src1
.negate
= false;
1222 mul
->operands
[1]->accept(this);
1223 src_reg src2
= fix_3src_operand(this->result
);
1226 src2
.negate
= false;
1228 this->result
= src_reg(this, ir
->type
);
1229 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1235 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1237 /* This optimization relies on CMP setting the destination to 0 when
1238 * false. Early hardware only sets the least significant bit, and
1239 * leaves the other bits undefined. So we can't use it.
1241 if (devinfo
->gen
< 6)
1244 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1249 switch (cmp
->operation
) {
1251 case ir_binop_greater
:
1252 case ir_binop_lequal
:
1253 case ir_binop_gequal
:
1254 case ir_binop_equal
:
1255 case ir_binop_nequal
:
1262 cmp
->operands
[0]->accept(this);
1263 const src_reg cmp_src0
= this->result
;
1265 cmp
->operands
[1]->accept(this);
1266 const src_reg cmp_src1
= this->result
;
1268 this->result
= src_reg(this, ir
->type
);
1270 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1271 brw_conditional_for_comparison(cmp
->operation
)));
1273 /* If the comparison is false, this->result will just happen to be zero.
1275 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1276 this->result
, src_reg(1.0f
));
1277 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1278 inst
->predicate_inverse
= true;
1284 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1285 src_reg src0
, src_reg src1
)
1287 vec4_instruction
*inst
;
1289 if (devinfo
->gen
>= 6) {
1290 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1291 inst
->conditional_mod
= conditionalmod
;
1293 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1295 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1296 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1303 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1304 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1306 if (devinfo
->gen
>= 6) {
1307 /* Note that the instruction's argument order is reversed from GLSL
1310 return emit(LRP(dst
, fix_3src_operand(a
), fix_3src_operand(y
),
1311 fix_3src_operand(x
)));
1313 /* Earlier generations don't support three source operations, so we
1314 * need to emit x*(1-a) + y*a.
1316 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1317 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1318 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1319 y_times_a
.writemask
= dst
.writemask
;
1320 one_minus_a
.writemask
= dst
.writemask
;
1321 x_times_one_minus_a
.writemask
= dst
.writemask
;
1323 emit(MUL(y_times_a
, y
, a
));
1324 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1325 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1326 return emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1331 * Emits the instructions needed to perform a pull constant load. before_block
1332 * and before_inst can be NULL in which case the instruction will be appended
1333 * to the end of the instruction list.
1336 vec4_visitor::emit_pull_constant_load_reg(dst_reg dst
,
1339 bblock_t
*before_block
,
1340 vec4_instruction
*before_inst
)
1342 assert((before_inst
== NULL
&& before_block
== NULL
) ||
1343 (before_inst
&& before_block
));
1345 vec4_instruction
*pull
;
1347 if (devinfo
->gen
>= 9) {
1348 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
1349 src_reg
header(this, glsl_type::uvec4_type
, 2);
1352 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
1356 emit_before(before_block
, before_inst
, pull
);
1360 dst_reg index_reg
= retype(offset(dst_reg(header
), 1),
1362 pull
= MOV(writemask(index_reg
, WRITEMASK_X
), offset_reg
);
1365 emit_before(before_block
, before_inst
, pull
);
1369 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1374 pull
->header_size
= 1;
1375 } else if (devinfo
->gen
>= 7) {
1376 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1378 grf_offset
.type
= offset_reg
.type
;
1380 pull
= MOV(grf_offset
, offset_reg
);
1383 emit_before(before_block
, before_inst
, pull
);
1387 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1390 src_reg(grf_offset
));
1393 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
1397 pull
->base_mrf
= 14;
1402 emit_before(before_block
, before_inst
, pull
);
1408 vec4_visitor::emit_uniformize(const src_reg
&src
)
1410 const src_reg
chan_index(this, glsl_type::uint_type
);
1411 const dst_reg dst
= retype(dst_reg(this, glsl_type::uint_type
),
1414 emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, dst_reg(chan_index
))
1415 ->force_writemask_all
= true;
1416 emit(SHADER_OPCODE_BROADCAST
, dst
, src
, chan_index
)
1417 ->force_writemask_all
= true;
1419 return src_reg(dst
);
1423 vec4_visitor::visit(ir_expression
*ir
)
1425 unsigned int operand
;
1426 src_reg op
[ARRAY_SIZE(ir
->operands
)];
1427 vec4_instruction
*inst
;
1429 if (ir
->operation
== ir_binop_add
) {
1430 if (try_emit_mad(ir
))
1434 if (ir
->operation
== ir_unop_b2f
) {
1435 if (try_emit_b2f_of_compare(ir
))
1439 /* Storage for our result. Ideally for an assignment we'd be using
1440 * the actual storage for the result here, instead.
1442 dst_reg
result_dst(this, ir
->type
);
1443 src_reg
result_src(result_dst
);
1445 if (ir
->operation
== ir_triop_csel
) {
1446 ir
->operands
[1]->accept(this);
1447 op
[1] = this->result
;
1448 ir
->operands
[2]->accept(this);
1449 op
[2] = this->result
;
1451 enum brw_predicate predicate
;
1452 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1453 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1454 inst
->predicate
= predicate
;
1455 this->result
= result_src
;
1459 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1460 this->result
.file
= BAD_FILE
;
1461 ir
->operands
[operand
]->accept(this);
1462 if (this->result
.file
== BAD_FILE
) {
1463 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1464 ir
->operands
[operand
]->fprint(stderr
);
1467 op
[operand
] = this->result
;
1469 /* Matrix expression operands should have been broken down to vector
1470 * operations already.
1472 assert(!ir
->operands
[operand
]->type
->is_matrix());
1475 /* If nothing special happens, this is the result. */
1476 this->result
= result_src
;
1478 switch (ir
->operation
) {
1479 case ir_unop_logic_not
:
1480 emit(NOT(result_dst
, op
[0]));
1483 op
[0].negate
= !op
[0].negate
;
1484 emit(MOV(result_dst
, op
[0]));
1488 op
[0].negate
= false;
1489 emit(MOV(result_dst
, op
[0]));
1493 if (ir
->type
->is_float()) {
1494 /* AND(val, 0x80000000) gives the sign bit.
1496 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1499 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1501 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1502 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1503 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1505 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1506 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1508 this->result
.type
= BRW_REGISTER_TYPE_F
;
1510 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1511 * -> non-negative val generates 0x00000000.
1512 * Predicated OR sets 1 if val is positive.
1514 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1516 emit(ASR(result_dst
, op
[0], src_reg(31)));
1518 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1519 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1524 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1528 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1531 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1535 unreachable("not reached: should be handled by ir_explog_to_explog2");
1537 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1540 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1544 case ir_unop_dFdx_coarse
:
1545 case ir_unop_dFdx_fine
:
1547 case ir_unop_dFdy_coarse
:
1548 case ir_unop_dFdy_fine
:
1549 unreachable("derivatives not valid in vertex shader");
1551 case ir_unop_bitfield_reverse
:
1552 emit(BFREV(result_dst
, op
[0]));
1554 case ir_unop_bit_count
:
1555 emit(CBIT(result_dst
, op
[0]));
1557 case ir_unop_find_msb
: {
1558 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1560 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1561 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1563 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1564 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1565 * subtract the result from 31 to convert the MSB count into an LSB count.
1568 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1569 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1570 emit(MOV(result_dst
, temp
));
1572 src_reg src_tmp
= src_reg(result_dst
);
1573 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1575 src_tmp
.negate
= true;
1576 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1577 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1580 case ir_unop_find_lsb
:
1581 emit(FBL(result_dst
, op
[0]));
1583 case ir_unop_saturate
:
1584 inst
= emit(MOV(result_dst
, op
[0]));
1585 inst
->saturate
= true;
1589 unreachable("not reached: should be handled by lower_noise");
1591 case ir_unop_subroutine_to_int
:
1592 emit(MOV(result_dst
, op
[0]));
1596 emit(ADD(result_dst
, op
[0], op
[1]));
1599 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1602 if (devinfo
->gen
< 8 && ir
->type
->is_integer()) {
1603 /* For integer multiplication, the MUL uses the low 16 bits of one of
1604 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1605 * accumulates in the contribution of the upper 16 bits of that
1606 * operand. If we can determine that one of the args is in the low
1607 * 16 bits, though, we can just emit a single MUL.
1609 if (ir
->operands
[0]->is_uint16_constant()) {
1610 if (devinfo
->gen
< 7)
1611 emit(MUL(result_dst
, op
[0], op
[1]));
1613 emit(MUL(result_dst
, op
[1], op
[0]));
1614 } else if (ir
->operands
[1]->is_uint16_constant()) {
1615 if (devinfo
->gen
< 7)
1616 emit(MUL(result_dst
, op
[1], op
[0]));
1618 emit(MUL(result_dst
, op
[0], op
[1]));
1620 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1622 emit(MUL(acc
, op
[0], op
[1]));
1623 emit(MACH(dst_null_d(), op
[0], op
[1]));
1624 emit(MOV(result_dst
, src_reg(acc
)));
1627 emit(MUL(result_dst
, op
[0], op
[1]));
1630 case ir_binop_imul_high
: {
1631 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1633 emit(MUL(acc
, op
[0], op
[1]));
1634 emit(MACH(result_dst
, op
[0], op
[1]));
1638 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1639 assert(ir
->type
->is_integer());
1640 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1643 case ir_binop_carry
:
1644 unreachable("Should have been lowered by carry_to_arith().");
1646 case ir_binop_borrow
:
1647 unreachable("Should have been lowered by borrow_to_arith().");
1650 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1651 assert(ir
->type
->is_integer());
1652 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1656 case ir_binop_greater
:
1657 case ir_binop_lequal
:
1658 case ir_binop_gequal
:
1659 case ir_binop_equal
:
1660 case ir_binop_nequal
: {
1661 if (devinfo
->gen
<= 5) {
1662 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1663 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1665 emit(CMP(result_dst
, op
[0], op
[1],
1666 brw_conditional_for_comparison(ir
->operation
)));
1670 case ir_binop_all_equal
:
1671 if (devinfo
->gen
<= 5) {
1672 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1673 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1676 /* "==" operator producing a scalar boolean. */
1677 if (ir
->operands
[0]->type
->is_vector() ||
1678 ir
->operands
[1]->type
->is_vector()) {
1679 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1680 emit(MOV(result_dst
, src_reg(0)));
1681 inst
= emit(MOV(result_dst
, src_reg(~0)));
1682 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1684 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1687 case ir_binop_any_nequal
:
1688 if (devinfo
->gen
<= 5) {
1689 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1690 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1693 /* "!=" operator producing a scalar boolean. */
1694 if (ir
->operands
[0]->type
->is_vector() ||
1695 ir
->operands
[1]->type
->is_vector()) {
1696 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1698 emit(MOV(result_dst
, src_reg(0)));
1699 inst
= emit(MOV(result_dst
, src_reg(~0)));
1700 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1702 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1707 if (devinfo
->gen
<= 5) {
1708 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1710 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1711 emit(MOV(result_dst
, src_reg(0)));
1713 inst
= emit(MOV(result_dst
, src_reg(~0)));
1714 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1717 case ir_binop_logic_xor
:
1718 emit(XOR(result_dst
, op
[0], op
[1]));
1721 case ir_binop_logic_or
:
1722 emit(OR(result_dst
, op
[0], op
[1]));
1725 case ir_binop_logic_and
:
1726 emit(AND(result_dst
, op
[0], op
[1]));
1730 assert(ir
->operands
[0]->type
->is_vector());
1731 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1732 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1736 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1739 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1742 case ir_unop_bitcast_i2f
:
1743 case ir_unop_bitcast_u2f
:
1744 this->result
= op
[0];
1745 this->result
.type
= BRW_REGISTER_TYPE_F
;
1748 case ir_unop_bitcast_f2i
:
1749 this->result
= op
[0];
1750 this->result
.type
= BRW_REGISTER_TYPE_D
;
1753 case ir_unop_bitcast_f2u
:
1754 this->result
= op
[0];
1755 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1764 emit(MOV(result_dst
, op
[0]));
1768 if (devinfo
->gen
<= 5) {
1769 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1771 emit(MOV(result_dst
, negate(op
[0])));
1774 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1777 emit(CMP(result_dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1781 emit(RNDZ(result_dst
, op
[0]));
1783 case ir_unop_ceil
: {
1784 src_reg tmp
= src_reg(this, ir
->type
);
1785 op
[0].negate
= !op
[0].negate
;
1786 emit(RNDD(dst_reg(tmp
), op
[0]));
1788 emit(MOV(result_dst
, tmp
));
1792 inst
= emit(RNDD(result_dst
, op
[0]));
1795 inst
= emit(FRC(result_dst
, op
[0]));
1797 case ir_unop_round_even
:
1798 emit(RNDE(result_dst
, op
[0]));
1802 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1805 emit_minmax(BRW_CONDITIONAL_GE
, result_dst
, op
[0], op
[1]);
1809 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1812 case ir_unop_bit_not
:
1813 inst
= emit(NOT(result_dst
, op
[0]));
1815 case ir_binop_bit_and
:
1816 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1818 case ir_binop_bit_xor
:
1819 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1821 case ir_binop_bit_or
:
1822 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1825 case ir_binop_lshift
:
1826 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1829 case ir_binop_rshift
:
1830 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1831 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1833 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1837 emit(BFI1(result_dst
, op
[0], op
[1]));
1840 case ir_binop_ubo_load
: {
1841 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1842 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1843 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1846 /* Now, load the vector from that offset. */
1847 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1849 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1850 packed_consts
.type
= result
.type
;
1853 if (const_uniform_block
) {
1854 /* The block index is a constant, so just emit the binding table entry
1857 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1858 const_uniform_block
->value
.u
[0]);
1860 /* The block index is not a constant. Evaluate the index expression
1861 * per-channel and add the base UBO index; we have to select a value
1862 * from any live channel.
1864 surf_index
= src_reg(this, glsl_type::uint_type
);
1865 emit(ADD(dst_reg(surf_index
), op
[0],
1866 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1867 surf_index
= emit_uniformize(surf_index
);
1869 /* Assume this may touch any UBO. It would be nice to provide
1870 * a tighter bound, but the array information is already lowered away.
1872 brw_mark_surface_used(&prog_data
->base
,
1873 prog_data
->base
.binding_table
.ubo_start
+
1874 shader_prog
->NumUniformBlocks
- 1);
1877 if (const_offset_ir
) {
1878 if (devinfo
->gen
>= 8) {
1879 /* Store the offset in a GRF so we can send-from-GRF. */
1880 offset
= src_reg(this, glsl_type::int_type
);
1881 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1883 /* Immediates are fine on older generations since they'll be moved
1884 * to a (potentially fake) MRF at the generator level.
1886 offset
= src_reg(const_offset
/ 16);
1889 offset
= src_reg(this, glsl_type::uint_type
);
1890 emit(SHR(dst_reg(offset
), op
[1], src_reg(4u)));
1893 emit_pull_constant_load_reg(dst_reg(packed_consts
),
1896 NULL
, NULL
/* before_block/inst */);
1898 packed_consts
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
1899 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1900 const_offset
% 16 / 4,
1901 const_offset
% 16 / 4,
1902 const_offset
% 16 / 4);
1904 /* UBO bools are any nonzero int. We need to convert them to 0/~0. */
1905 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1906 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1907 BRW_CONDITIONAL_NZ
));
1909 emit(MOV(result_dst
, packed_consts
));
1914 case ir_binop_vector_extract
:
1915 unreachable("should have been lowered by vec_index_to_cond_assign");
1918 op
[0] = fix_3src_operand(op
[0]);
1919 op
[1] = fix_3src_operand(op
[1]);
1920 op
[2] = fix_3src_operand(op
[2]);
1921 /* Note that the instruction's argument order is reversed from GLSL
1924 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1928 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1932 unreachable("already handled above");
1936 op
[0] = fix_3src_operand(op
[0]);
1937 op
[1] = fix_3src_operand(op
[1]);
1938 op
[2] = fix_3src_operand(op
[2]);
1939 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1942 case ir_triop_bitfield_extract
:
1943 op
[0] = fix_3src_operand(op
[0]);
1944 op
[1] = fix_3src_operand(op
[1]);
1945 op
[2] = fix_3src_operand(op
[2]);
1946 /* Note that the instruction's argument order is reversed from GLSL
1949 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1952 case ir_triop_vector_insert
:
1953 unreachable("should have been lowered by lower_vector_insert");
1955 case ir_quadop_bitfield_insert
:
1956 unreachable("not reached: should be handled by "
1957 "bitfield_insert_to_bfm_bfi\n");
1959 case ir_quadop_vector
:
1960 unreachable("not reached: should be handled by lower_quadop_vector");
1962 case ir_unop_pack_half_2x16
:
1963 emit_pack_half_2x16(result_dst
, op
[0]);
1965 case ir_unop_unpack_half_2x16
:
1966 emit_unpack_half_2x16(result_dst
, op
[0]);
1968 case ir_unop_unpack_unorm_4x8
:
1969 emit_unpack_unorm_4x8(result_dst
, op
[0]);
1971 case ir_unop_unpack_snorm_4x8
:
1972 emit_unpack_snorm_4x8(result_dst
, op
[0]);
1974 case ir_unop_pack_unorm_4x8
:
1975 emit_pack_unorm_4x8(result_dst
, op
[0]);
1977 case ir_unop_pack_snorm_4x8
:
1978 emit_pack_snorm_4x8(result_dst
, op
[0]);
1980 case ir_unop_pack_snorm_2x16
:
1981 case ir_unop_pack_unorm_2x16
:
1982 case ir_unop_unpack_snorm_2x16
:
1983 case ir_unop_unpack_unorm_2x16
:
1984 unreachable("not reached: should be handled by lower_packing_builtins");
1985 case ir_unop_unpack_half_2x16_split_x
:
1986 case ir_unop_unpack_half_2x16_split_y
:
1987 case ir_binop_pack_half_2x16_split
:
1988 case ir_unop_interpolate_at_centroid
:
1989 case ir_binop_interpolate_at_sample
:
1990 case ir_binop_interpolate_at_offset
:
1991 unreachable("not reached: should not occur in vertex shader");
1992 case ir_binop_ldexp
:
1993 unreachable("not reached: should be handled by ldexp_to_arith()");
2001 case ir_unop_pack_double_2x32
:
2002 case ir_unop_unpack_double_2x32
:
2003 case ir_unop_frexp_sig
:
2004 case ir_unop_frexp_exp
:
2005 unreachable("fp64 todo");
2011 vec4_visitor::visit(ir_swizzle
*ir
)
2013 /* Note that this is only swizzles in expressions, not those on the left
2014 * hand side of an assignment, which do write masking. See ir_assignment
2017 const unsigned swz
= brw_compose_swizzle(
2018 brw_swizzle_for_size(ir
->type
->vector_elements
),
2019 BRW_SWIZZLE4(ir
->mask
.x
, ir
->mask
.y
, ir
->mask
.z
, ir
->mask
.w
));
2021 ir
->val
->accept(this);
2022 this->result
= swizzle(this->result
, swz
);
2026 vec4_visitor::visit(ir_dereference_variable
*ir
)
2028 const struct glsl_type
*type
= ir
->type
;
2029 dst_reg
*reg
= variable_storage(ir
->var
);
2032 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
2033 this->result
= src_reg(brw_null_reg());
2037 this->result
= src_reg(*reg
);
2039 /* System values get their swizzle from the dst_reg writemask */
2040 if (ir
->var
->data
.mode
== ir_var_system_value
)
2043 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
2044 this->result
.swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2049 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
2051 /* Under normal circumstances array elements are stored consecutively, so
2052 * the stride is equal to the size of the array element.
2054 return type_size(ir
->type
);
2059 vec4_visitor::visit(ir_dereference_array
*ir
)
2061 ir_constant
*constant_index
;
2063 int array_stride
= compute_array_stride(ir
);
2065 constant_index
= ir
->array_index
->constant_expression_value();
2067 ir
->array
->accept(this);
2070 if (constant_index
) {
2071 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
2073 /* Variable index array dereference. It eats the "vec4" of the
2074 * base of the array and an index that offsets the Mesa register
2077 ir
->array_index
->accept(this);
2081 if (array_stride
== 1) {
2082 index_reg
= this->result
;
2084 index_reg
= src_reg(this, glsl_type::int_type
);
2086 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
2090 src_reg temp
= src_reg(this, glsl_type::int_type
);
2092 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
2097 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
2098 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2101 /* If the type is smaller than a vec4, replicate the last channel out. */
2102 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2103 src
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2105 src
.swizzle
= BRW_SWIZZLE_NOOP
;
2106 src
.type
= brw_type_for_base_type(ir
->type
);
2112 vec4_visitor::visit(ir_dereference_record
*ir
)
2115 const glsl_type
*struct_type
= ir
->record
->type
;
2118 ir
->record
->accept(this);
2120 for (i
= 0; i
< struct_type
->length
; i
++) {
2121 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2123 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2126 /* If the type is smaller than a vec4, replicate the last channel out. */
2127 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2128 this->result
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2130 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
2131 this->result
.type
= brw_type_for_base_type(ir
->type
);
2133 this->result
.reg_offset
+= offset
;
2137 * We want to be careful in assignment setup to hit the actual storage
2138 * instead of potentially using a temporary like we might with the
2139 * ir_dereference handler.
2142 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
2144 /* The LHS must be a dereference. If the LHS is a variable indexed array
2145 * access of a vector, it must be separated into a series conditional moves
2146 * before reaching this point (see ir_vec_index_to_cond_assign).
2148 assert(ir
->as_dereference());
2149 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2151 assert(!deref_array
->array
->type
->is_vector());
2154 /* Use the rvalue deref handler for the most part. We'll ignore
2155 * swizzles in it and write swizzles using writemask, though.
2158 return dst_reg(v
->result
);
2162 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
2163 const struct glsl_type
*type
,
2164 enum brw_predicate predicate
)
2166 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2167 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2168 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
2173 if (type
->is_array()) {
2174 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2175 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
2180 if (type
->is_matrix()) {
2181 const struct glsl_type
*vec_type
;
2183 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2184 type
->vector_elements
, 1);
2186 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2187 emit_block_move(dst
, src
, vec_type
, predicate
);
2192 assert(type
->is_scalar() || type
->is_vector());
2194 dst
->type
= brw_type_for_base_type(type
);
2195 src
->type
= dst
->type
;
2197 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2199 src
->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2201 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2202 inst
->predicate
= predicate
;
2209 /* If the RHS processing resulted in an instruction generating a
2210 * temporary value, and it would be easy to rewrite the instruction to
2211 * generate its result right into the LHS instead, do so. This ends
2212 * up reliably removing instructions where it can be tricky to do so
2213 * later without real UD chain information.
2216 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2219 vec4_instruction
*pre_rhs_inst
,
2220 vec4_instruction
*last_rhs_inst
)
2222 /* This could be supported, but it would take more smarts. */
2226 if (pre_rhs_inst
== last_rhs_inst
)
2227 return false; /* No instructions generated to work with. */
2229 /* Make sure the last instruction generated our source reg. */
2230 if (src
.file
!= GRF
||
2231 src
.file
!= last_rhs_inst
->dst
.file
||
2232 src
.reg
!= last_rhs_inst
->dst
.reg
||
2233 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2237 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2240 /* Check that that last instruction fully initialized the channels
2241 * we want to use, in the order we want to use them. We could
2242 * potentially reswizzle the operands of many instructions so that
2243 * we could handle out of order channels, but don't yet.
2246 for (unsigned i
= 0; i
< 4; i
++) {
2247 if (dst
.writemask
& (1 << i
)) {
2248 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2251 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2256 /* Success! Rewrite the instruction. */
2257 last_rhs_inst
->dst
.file
= dst
.file
;
2258 last_rhs_inst
->dst
.reg
= dst
.reg
;
2259 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2260 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2261 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2267 vec4_visitor::visit(ir_assignment
*ir
)
2269 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2270 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2272 if (!ir
->lhs
->type
->is_scalar() &&
2273 !ir
->lhs
->type
->is_vector()) {
2274 ir
->rhs
->accept(this);
2275 src_reg src
= this->result
;
2277 if (ir
->condition
) {
2278 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2281 /* emit_block_move doesn't account for swizzles in the source register.
2282 * This should be ok, since the source register is a structure or an
2283 * array, and those can't be swizzled. But double-check to be sure.
2285 assert(src
.swizzle
==
2286 (ir
->rhs
->type
->is_matrix()
2287 ? brw_swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2288 : BRW_SWIZZLE_NOOP
));
2290 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2294 /* Now we're down to just a scalar/vector with writemasks. */
2297 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2298 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2300 ir
->rhs
->accept(this);
2302 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2307 assert(ir
->lhs
->type
->is_vector() ||
2308 ir
->lhs
->type
->is_scalar());
2309 dst
.writemask
= ir
->write_mask
;
2311 /* Swizzle a small RHS vector into the channels being written.
2313 * glsl ir treats write_mask as dictating how many channels are
2314 * present on the RHS while in our instructions we need to make
2315 * those channels appear in the slots of the vec4 they're written to.
2317 for (int i
= 0; i
< 4; i
++)
2318 swizzles
[i
] = (ir
->write_mask
& (1 << i
) ? src_chan
++ : 0);
2320 src_reg src
= swizzle(this->result
,
2321 BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2322 swizzles
[2], swizzles
[3]));
2324 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2328 if (ir
->condition
) {
2329 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2332 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2333 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2334 inst
->predicate
= predicate
;
2342 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2344 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2345 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2346 emit_constant_values(dst
, field_value
);
2351 if (ir
->type
->is_array()) {
2352 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2353 emit_constant_values(dst
, ir
->array_elements
[i
]);
2358 if (ir
->type
->is_matrix()) {
2359 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2360 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2362 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2363 dst
->writemask
= 1 << j
;
2364 dst
->type
= BRW_REGISTER_TYPE_F
;
2366 emit(MOV(*dst
, src_reg(vec
[j
])));
2373 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2375 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2376 if (!(remaining_writemask
& (1 << i
)))
2379 dst
->writemask
= 1 << i
;
2380 dst
->type
= brw_type_for_base_type(ir
->type
);
2382 /* Find other components that match the one we're about to
2383 * write. Emits fewer instructions for things like vec4(0.5,
2386 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2387 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2388 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2389 dst
->writemask
|= (1 << j
);
2391 /* u, i, and f storage all line up, so no need for a
2392 * switch case for comparing each type.
2394 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2395 dst
->writemask
|= (1 << j
);
2399 switch (ir
->type
->base_type
) {
2400 case GLSL_TYPE_FLOAT
:
2401 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2404 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2406 case GLSL_TYPE_UINT
:
2407 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2409 case GLSL_TYPE_BOOL
:
2410 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
] != 0 ? ~0 : 0)));
2413 unreachable("Non-float/uint/int/bool constant");
2416 remaining_writemask
&= ~dst
->writemask
;
2422 vec4_visitor::visit(ir_constant
*ir
)
2424 dst_reg dst
= dst_reg(this, ir
->type
);
2425 this->result
= src_reg(dst
);
2427 emit_constant_values(&dst
, ir
);
2431 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2433 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2434 ir
->actual_parameters
.get_head());
2435 ir_variable
*location
= deref
->variable_referenced();
2436 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2437 location
->data
.binding
);
2439 /* Calculate the surface offset */
2440 src_reg
offset(this, glsl_type::uint_type
);
2441 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2443 deref_array
->array_index
->accept(this);
2445 src_reg
tmp(this, glsl_type::uint_type
);
2446 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2447 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2449 offset
= location
->data
.atomic
.offset
;
2452 /* Emit the appropriate machine instruction */
2453 const char *callee
= ir
->callee
->function_name();
2454 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2456 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2457 emit_untyped_surface_read(surf_index
, dst
, offset
);
2459 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2460 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2461 src_reg(), src_reg());
2463 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2464 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2465 src_reg(), src_reg());
2468 brw_mark_surface_used(stage_prog_data
, surf_index
);
2472 vec4_visitor::visit(ir_call
*ir
)
2474 const char *callee
= ir
->callee
->function_name();
2476 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2477 !strcmp("__intrinsic_atomic_increment", callee
) ||
2478 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2479 visit_atomic_counter_intrinsic(ir
);
2481 unreachable("Unsupported intrinsic.");
2486 vec4_visitor::emit_mcs_fetch(const glsl_type
*coordinate_type
,
2487 src_reg coordinate
, src_reg sampler
)
2489 vec4_instruction
*inst
=
2490 new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
,
2491 dst_reg(this, glsl_type::uvec4_type
));
2493 inst
->src
[1] = sampler
;
2497 if (devinfo
->gen
>= 9) {
2498 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
2499 vec4_instruction
*header_inst
= new(mem_ctx
)
2500 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
2501 dst_reg(MRF
, inst
->base_mrf
));
2506 inst
->header_size
= 1;
2507 param_base
= inst
->base_mrf
+ 1;
2510 param_base
= inst
->base_mrf
;
2513 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2514 int coord_mask
= (1 << coordinate_type
->vector_elements
) - 1;
2515 int zero_mask
= 0xf & ~coord_mask
;
2517 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, coord_mask
),
2520 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, zero_mask
),
2524 return src_reg(inst
->dst
);
2528 vec4_visitor::is_high_sampler(src_reg sampler
)
2530 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
2533 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2537 vec4_visitor::emit_texture(ir_texture_opcode op
,
2539 const glsl_type
*dest_type
,
2541 int coord_components
,
2542 src_reg shadow_comparitor
,
2543 src_reg lod
, src_reg lod2
,
2544 src_reg sample_index
,
2545 uint32_t constant_offset
,
2546 src_reg offset_value
,
2550 src_reg sampler_reg
)
2554 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2555 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2556 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2557 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2558 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2559 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2560 case ir_tg4
: opcode
= offset_value
.file
!= BAD_FILE
2561 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2562 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2564 unreachable("TXB is not valid for vertex shaders.");
2566 unreachable("LOD is not valid for vertex shaders.");
2568 unreachable("Unrecognized tex op");
2571 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(
2572 opcode
, dst_reg(this, dest_type
));
2574 inst
->offset
= constant_offset
;
2576 /* The message header is necessary for:
2578 * - Gen9+ for selecting SIMD4x2
2580 * - Gather channel selection
2581 * - Sampler indices too large to fit in a 4-bit value.
2584 (devinfo
->gen
< 5 || devinfo
->gen
>= 9 ||
2585 inst
->offset
!= 0 || op
== ir_tg4
||
2586 is_high_sampler(sampler_reg
)) ? 1 : 0;
2588 inst
->mlen
= inst
->header_size
+ 1; /* always at least one */
2589 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2590 inst
->shadow_compare
= shadow_comparitor
.file
!= BAD_FILE
;
2592 inst
->src
[1] = sampler_reg
;
2594 /* MRF for the first parameter */
2595 int param_base
= inst
->base_mrf
+ inst
->header_size
;
2597 if (op
== ir_txs
|| op
== ir_query_levels
) {
2598 int writemask
= devinfo
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2599 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, writemask
), lod
));
2601 /* Load the coordinate */
2602 /* FINISHME: gl_clamp_mask and saturate */
2603 int coord_mask
= (1 << coord_components
) - 1;
2604 int zero_mask
= 0xf & ~coord_mask
;
2606 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, coord_mask
),
2609 if (zero_mask
!= 0) {
2610 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, zero_mask
),
2613 /* Load the shadow comparitor */
2614 if (shadow_comparitor
.file
!= BAD_FILE
&& op
!= ir_txd
&& (op
!= ir_tg4
|| offset_value
.file
== BAD_FILE
)) {
2615 emit(MOV(dst_reg(MRF
, param_base
+ 1, shadow_comparitor
.type
,
2617 shadow_comparitor
));
2621 /* Load the LOD info */
2622 if (op
== ir_tex
|| op
== ir_txl
) {
2624 if (devinfo
->gen
>= 5) {
2625 mrf
= param_base
+ 1;
2626 if (shadow_comparitor
.file
!= BAD_FILE
) {
2627 writemask
= WRITEMASK_Y
;
2628 /* mlen already incremented */
2630 writemask
= WRITEMASK_X
;
2633 } else /* devinfo->gen == 4 */ {
2635 writemask
= WRITEMASK_W
;
2637 lod
.swizzle
= BRW_SWIZZLE_XXXX
;
2638 emit(MOV(dst_reg(MRF
, mrf
, lod
.type
, writemask
), lod
));
2639 } else if (op
== ir_txf
) {
2640 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, WRITEMASK_W
), lod
));
2641 } else if (op
== ir_txf_ms
) {
2642 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index
.type
, WRITEMASK_X
),
2644 if (devinfo
->gen
>= 7) {
2645 /* MCS data is in the first channel of `mcs`, but we need to get it into
2646 * the .y channel of the second vec4 of params, so replicate .x across
2647 * the whole vec4 and then mask off everything except .y
2649 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2650 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2654 } else if (op
== ir_txd
) {
2655 const brw_reg_type type
= lod
.type
;
2657 if (devinfo
->gen
>= 5) {
2658 lod
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2659 lod2
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2660 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), lod
));
2661 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), lod2
));
2664 if (dest_type
->vector_elements
== 3 || shadow_comparitor
.file
!= BAD_FILE
) {
2665 lod
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2666 lod2
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2667 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), lod
));
2668 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), lod2
));
2671 if (shadow_comparitor
.file
!= BAD_FILE
) {
2672 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2673 shadow_comparitor
.type
, WRITEMASK_Z
),
2674 shadow_comparitor
));
2677 } else /* devinfo->gen == 4 */ {
2678 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), lod
));
2679 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), lod2
));
2682 } else if (op
== ir_tg4
&& offset_value
.file
!= BAD_FILE
) {
2683 if (shadow_comparitor
.file
!= BAD_FILE
) {
2684 emit(MOV(dst_reg(MRF
, param_base
, shadow_comparitor
.type
, WRITEMASK_W
),
2685 shadow_comparitor
));
2688 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2696 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2697 * spec requires layers.
2699 if (op
== ir_txs
&& is_cube_array
) {
2700 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2701 writemask(inst
->dst
, WRITEMASK_Z
),
2702 src_reg(inst
->dst
), src_reg(6));
2705 if (devinfo
->gen
== 6 && op
== ir_tg4
) {
2706 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2709 swizzle_result(op
, dest
,
2710 src_reg(inst
->dst
), sampler
, dest_type
);
2714 vec4_visitor::visit(ir_texture
*ir
)
2717 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2719 ir_rvalue
*nonconst_sampler_index
=
2720 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2722 /* Handle non-constant sampler array indexing */
2723 src_reg sampler_reg
;
2724 if (nonconst_sampler_index
) {
2725 /* The highest sampler which may be used by this operation is
2726 * the last element of the array. Mark it here, because the generator
2727 * doesn't have enough information to determine the bound.
2729 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2730 ->array
->type
->array_size();
2732 uint32_t max_used
= sampler
+ array_size
- 1;
2733 if (ir
->op
== ir_tg4
&& devinfo
->gen
< 8) {
2734 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2736 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2739 brw_mark_surface_used(&prog_data
->base
, max_used
);
2741 /* Emit code to evaluate the actual indexing expression */
2742 nonconst_sampler_index
->accept(this);
2743 src_reg
temp(this, glsl_type::uint_type
);
2744 emit(ADD(dst_reg(temp
), this->result
, src_reg(sampler
)));
2745 sampler_reg
= emit_uniformize(temp
);
2747 /* Single sampler, or constant array index; the indexing expression
2748 * is just an immediate.
2750 sampler_reg
= src_reg(sampler
);
2753 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2754 * emitting anything other than setting up the constant result.
2756 if (ir
->op
== ir_tg4
) {
2757 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2758 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2759 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2760 dst_reg
result(this, ir
->type
);
2761 this->result
= src_reg(result
);
2762 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2767 /* Should be lowered by do_lower_texture_projection */
2768 assert(!ir
->projector
);
2770 /* Should be lowered */
2771 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2773 /* Generate code to compute all the subexpression trees. This has to be
2774 * done before loading any values into MRFs for the sampler message since
2775 * generating these values may involve SEND messages that need the MRFs.
2778 int coord_components
= 0;
2779 if (ir
->coordinate
) {
2780 coord_components
= ir
->coordinate
->type
->vector_elements
;
2781 ir
->coordinate
->accept(this);
2782 coordinate
= this->result
;
2785 src_reg shadow_comparitor
;
2786 if (ir
->shadow_comparitor
) {
2787 ir
->shadow_comparitor
->accept(this);
2788 shadow_comparitor
= this->result
;
2791 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2792 src_reg offset_value
;
2793 if (has_nonconstant_offset
) {
2794 ir
->offset
->accept(this);
2795 offset_value
= src_reg(this->result
);
2798 src_reg lod
, lod2
, sample_index
, mcs
;
2801 lod
= src_reg(0.0f
);
2806 ir
->lod_info
.lod
->accept(this);
2809 case ir_query_levels
:
2813 ir
->lod_info
.sample_index
->accept(this);
2814 sample_index
= this->result
;
2816 if (devinfo
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2817 mcs
= emit_mcs_fetch(ir
->coordinate
->type
, coordinate
, sampler_reg
);
2822 ir
->lod_info
.grad
.dPdx
->accept(this);
2825 ir
->lod_info
.grad
.dPdy
->accept(this);
2826 lod2
= this->result
;
2834 uint32_t constant_offset
= 0;
2835 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2837 brw_texture_offset(ir
->offset
->as_constant()->value
.i
,
2838 ir
->offset
->type
->vector_elements
);
2841 /* Stuff the channel select bits in the top of the texture offset */
2842 if (ir
->op
== ir_tg4
)
2844 gather_channel( ir
->lod_info
.component
->as_constant()->value
.i
[0],
2847 glsl_type
const *type
= ir
->sampler
->type
;
2848 bool is_cube_array
= type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2849 type
->sampler_array
;
2851 this->result
= src_reg(this, ir
->type
);
2852 dst_reg dest
= dst_reg(this->result
);
2854 emit_texture(ir
->op
, dest
, ir
->type
, coordinate
, coord_components
,
2856 lod
, lod2
, sample_index
,
2857 constant_offset
, offset_value
,
2858 mcs
, is_cube_array
, sampler
, sampler_reg
);
2862 * Apply workarounds for Gen6 gather with UINT/SINT
2865 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2870 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2871 dst_reg dst_f
= dst
;
2872 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2874 /* Convert from UNORM to UINT */
2875 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2876 emit(MOV(dst
, src_reg(dst_f
)));
2879 /* Reinterpret the UINT value as a signed INT value by
2880 * shifting the sign bit into place, then shifting back
2883 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2884 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2889 * Set up the gather channel based on the swizzle, for gather4.
2892 vec4_visitor::gather_channel(unsigned gather_component
, uint32_t sampler
)
2894 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], gather_component
);
2896 case SWIZZLE_X
: return 0;
2898 /* gather4 sampler is broken for green channel on RG32F --
2899 * we must ask for blue instead.
2901 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2904 case SWIZZLE_Z
: return 2;
2905 case SWIZZLE_W
: return 3;
2907 unreachable("Not reached"); /* zero, one swizzles handled already */
2912 vec4_visitor::swizzle_result(ir_texture_opcode op
, dst_reg dest
,
2913 src_reg orig_val
, uint32_t sampler
,
2914 const glsl_type
*dest_type
)
2916 int s
= key
->tex
.swizzles
[sampler
];
2918 dst_reg swizzled_result
= dest
;
2920 if (op
== ir_query_levels
) {
2921 /* # levels is in .w */
2922 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2923 emit(MOV(swizzled_result
, orig_val
));
2927 if (op
== ir_txs
|| dest_type
== glsl_type::float_type
2928 || s
== SWIZZLE_NOOP
|| op
== ir_tg4
) {
2929 emit(MOV(swizzled_result
, orig_val
));
2934 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2935 int swizzle
[4] = {0};
2937 for (int i
= 0; i
< 4; i
++) {
2938 switch (GET_SWZ(s
, i
)) {
2940 zero_mask
|= (1 << i
);
2943 one_mask
|= (1 << i
);
2946 copy_mask
|= (1 << i
);
2947 swizzle
[i
] = GET_SWZ(s
, i
);
2953 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2954 swizzled_result
.writemask
= copy_mask
;
2955 emit(MOV(swizzled_result
, orig_val
));
2959 swizzled_result
.writemask
= zero_mask
;
2960 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2964 swizzled_result
.writemask
= one_mask
;
2965 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2970 vec4_visitor::visit(ir_return
*)
2972 unreachable("not reached");
2976 vec4_visitor::visit(ir_discard
*)
2978 unreachable("not reached");
2982 vec4_visitor::visit(ir_if
*ir
)
2984 /* Don't point the annotation at the if statement, because then it plus
2985 * the then and else blocks get printed.
2987 this->base_ir
= ir
->condition
;
2989 if (devinfo
->gen
== 6) {
2992 enum brw_predicate predicate
;
2993 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2994 emit(IF(predicate
));
2997 visit_instructions(&ir
->then_instructions
);
2999 if (!ir
->else_instructions
.is_empty()) {
3000 this->base_ir
= ir
->condition
;
3001 emit(BRW_OPCODE_ELSE
);
3003 visit_instructions(&ir
->else_instructions
);
3006 this->base_ir
= ir
->condition
;
3007 emit(BRW_OPCODE_ENDIF
);
3011 vec4_visitor::gs_emit_vertex(int stream_id
)
3013 unreachable("not reached");
3017 vec4_visitor::visit(ir_emit_vertex
*)
3019 unreachable("not reached");
3023 vec4_visitor::gs_end_primitive()
3025 unreachable("not reached");
3030 vec4_visitor::visit(ir_end_primitive
*)
3032 unreachable("not reached");
3036 vec4_visitor::visit(ir_barrier
*)
3038 unreachable("not reached");
3042 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
3043 dst_reg dst
, src_reg offset
,
3044 src_reg src0
, src_reg src1
)
3048 /* Set the atomic operation offset. */
3049 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
3052 /* Set the atomic operation arguments. */
3053 if (src0
.file
!= BAD_FILE
) {
3054 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
3058 if (src1
.file
!= BAD_FILE
) {
3059 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
3063 /* Emit the instruction. Note that this maps to the normal SIMD8
3064 * untyped atomic message on Ivy Bridge, but that's OK because
3065 * unused channels will be masked out.
3067 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
3069 src_reg(surf_index
), src_reg(atomic_op
));
3074 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
3077 /* Set the surface read offset. */
3078 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
3080 /* Emit the instruction. Note that this maps to the normal SIMD8
3081 * untyped surface read message, but that's OK because unused
3082 * channels will be masked out.
3084 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
,
3086 src_reg(surf_index
), src_reg(1));
3091 vec4_visitor::emit_ndc_computation()
3093 /* Get the position */
3094 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
3096 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
3097 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
3098 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
3100 current_annotation
= "NDC";
3101 dst_reg ndc_w
= ndc
;
3102 ndc_w
.writemask
= WRITEMASK_W
;
3103 src_reg pos_w
= pos
;
3104 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
3105 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
3107 dst_reg ndc_xyz
= ndc
;
3108 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
3110 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
3114 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
3116 if (devinfo
->gen
< 6 &&
3117 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
3118 key
->userclip_active
|| devinfo
->has_negative_rhw_bug
)) {
3119 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
3120 dst_reg header1_w
= header1
;
3121 header1_w
.writemask
= WRITEMASK_W
;
3123 emit(MOV(header1
, 0u));
3125 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3126 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
3128 current_annotation
= "Point size";
3129 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
3130 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
3133 if (key
->userclip_active
) {
3134 current_annotation
= "Clipping flags";
3135 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
3136 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
3138 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3139 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
3140 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
3142 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3143 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
3144 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
3145 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
3148 /* i965 clipping workaround:
3149 * 1) Test for -ve rhw
3151 * set ndc = (0,0,0,0)
3154 * Later, clipping will detect ucp[6] and ensure the primitive is
3155 * clipped against all fixed planes.
3157 if (devinfo
->has_negative_rhw_bug
) {
3158 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
3159 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
3160 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
3161 vec4_instruction
*inst
;
3162 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
3163 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3164 output_reg
[BRW_VARYING_SLOT_NDC
].type
= BRW_REGISTER_TYPE_F
;
3165 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
3166 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3169 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
3170 } else if (devinfo
->gen
< 6) {
3171 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
3173 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
3174 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3175 dst_reg reg_w
= reg
;
3176 reg_w
.writemask
= WRITEMASK_W
;
3177 src_reg reg_as_src
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
3178 reg_as_src
.type
= reg_w
.type
;
3179 reg_as_src
.swizzle
= brw_swizzle_for_size(1);
3180 emit(MOV(reg_w
, reg_as_src
));
3182 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
3183 dst_reg reg_y
= reg
;
3184 reg_y
.writemask
= WRITEMASK_Y
;
3185 reg_y
.type
= BRW_REGISTER_TYPE_D
;
3186 output_reg
[VARYING_SLOT_LAYER
].type
= reg_y
.type
;
3187 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
3189 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
3190 dst_reg reg_z
= reg
;
3191 reg_z
.writemask
= WRITEMASK_Z
;
3192 reg_z
.type
= BRW_REGISTER_TYPE_D
;
3193 output_reg
[VARYING_SLOT_VIEWPORT
].type
= reg_z
.type
;
3194 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
3200 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
3202 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3204 * "If a linked set of shaders forming the vertex stage contains no
3205 * static write to gl_ClipVertex or gl_ClipDistance, but the
3206 * application has requested clipping against user clip planes through
3207 * the API, then the coordinate written to gl_Position is used for
3208 * comparison against the user clip planes."
3210 * This function is only called if the shader didn't write to
3211 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3212 * if the user wrote to it; otherwise we use gl_Position.
3214 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3215 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
3216 clip_vertex
= VARYING_SLOT_POS
;
3219 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
3221 reg
.writemask
= 1 << i
;
3223 src_reg(output_reg
[clip_vertex
]),
3224 src_reg(this->userplane
[i
+ offset
])));
3229 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
3231 assert(varying
< VARYING_SLOT_MAX
);
3232 assert(output_reg
[varying
].type
== reg
.type
);
3233 current_annotation
= output_reg_annotation
[varying
];
3234 /* Copy the register, saturating if necessary */
3235 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
3239 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
3241 reg
.type
= BRW_REGISTER_TYPE_F
;
3242 output_reg
[varying
].type
= reg
.type
;
3245 case VARYING_SLOT_PSIZ
:
3247 /* PSIZ is always in slot 0, and is coupled with other flags. */
3248 current_annotation
= "indices, point width, clip flags";
3249 emit_psiz_and_flags(reg
);
3252 case BRW_VARYING_SLOT_NDC
:
3253 current_annotation
= "NDC";
3254 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
3256 case VARYING_SLOT_POS
:
3257 current_annotation
= "gl_Position";
3258 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
3260 case VARYING_SLOT_EDGE
:
3261 /* This is present when doing unfilled polygons. We're supposed to copy
3262 * the edge flag from the user-provided vertex array
3263 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3264 * of that attribute (starts as 1.0f). This is then used in clipping to
3265 * determine which edges should be drawn as wireframe.
3267 current_annotation
= "edge flag";
3268 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3269 glsl_type::float_type
, WRITEMASK_XYZW
))));
3271 case BRW_VARYING_SLOT_PAD
:
3272 /* No need to write to this slot */
3274 case VARYING_SLOT_COL0
:
3275 case VARYING_SLOT_COL1
:
3276 case VARYING_SLOT_BFC0
:
3277 case VARYING_SLOT_BFC1
: {
3278 /* These built-in varyings are only supported in compatibility mode,
3279 * and we only support GS in core profile. So, this must be a vertex
3282 assert(stage
== MESA_SHADER_VERTEX
);
3283 vec4_instruction
*inst
= emit_generic_urb_slot(reg
, varying
);
3284 if (((struct brw_vs_prog_key
*) key
)->clamp_vertex_color
)
3285 inst
->saturate
= true;
3290 emit_generic_urb_slot(reg
, varying
);
3296 align_interleaved_urb_mlen(const struct brw_device_info
*devinfo
, int mlen
)
3298 if (devinfo
->gen
>= 6) {
3299 /* URB data written (does not include the message header reg) must
3300 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3301 * section 5.4.3.2.2: URB_INTERLEAVED.
3303 * URB entries are allocated on a multiple of 1024 bits, so an
3304 * extra 128 bits written here to make the end align to 256 is
3307 if ((mlen
% 2) != 1)
3316 * Generates the VUE payload plus the necessary URB write instructions to
3319 * The VUE layout is documented in Volume 2a.
3322 vec4_visitor::emit_vertex()
3324 /* MRF 0 is reserved for the debugger, so start with message header
3329 /* In the process of generating our URB write message contents, we
3330 * may need to unspill a register or load from an array. Those
3331 * reads would use MRFs 14-15.
3333 int max_usable_mrf
= 13;
3335 /* The following assertion verifies that max_usable_mrf causes an
3336 * even-numbered amount of URB write data, which will meet gen6's
3337 * requirements for length alignment.
3339 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3341 /* First mrf is the g0-based message header containing URB handles and
3344 emit_urb_write_header(mrf
++);
3346 if (devinfo
->gen
< 6) {
3347 emit_ndc_computation();
3350 /* Lower legacy ff and ClipVertex clipping to clip distances */
3351 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3352 current_annotation
= "user clip distances";
3354 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3355 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3357 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3358 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3361 /* We may need to split this up into several URB writes, so do them in a
3365 bool complete
= false;
3367 /* URB offset is in URB row increments, and each of our MRFs is half of
3368 * one of those, since we're doing interleaved writes.
3370 int offset
= slot
/ 2;
3373 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3374 emit_urb_slot(dst_reg(MRF
, mrf
++),
3375 prog_data
->vue_map
.slot_to_varying
[slot
]);
3377 /* If this was max_usable_mrf, we can't fit anything more into this
3380 if (mrf
> max_usable_mrf
) {
3386 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3387 current_annotation
= "URB write";
3388 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3389 inst
->base_mrf
= base_mrf
;
3390 inst
->mlen
= align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
);
3391 inst
->offset
+= offset
;
3397 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3398 src_reg
*reladdr
, int reg_offset
)
3400 /* Because we store the values to scratch interleaved like our
3401 * vertex data, we need to scale the vec4 index by 2.
3403 int message_header_scale
= 2;
3405 /* Pre-gen6, the message header uses byte offsets instead of vec4
3406 * (16-byte) offset units.
3408 if (devinfo
->gen
< 6)
3409 message_header_scale
*= 16;
3412 src_reg index
= src_reg(this, glsl_type::int_type
);
3414 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3415 src_reg(reg_offset
)));
3416 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3417 src_reg(message_header_scale
)));
3421 return src_reg(reg_offset
* message_header_scale
);
3426 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3427 src_reg
*reladdr
, int reg_offset
)
3430 src_reg index
= src_reg(this, glsl_type::int_type
);
3432 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3433 src_reg(reg_offset
)));
3435 /* Pre-gen6, the message header uses byte offsets instead of vec4
3436 * (16-byte) offset units.
3438 if (devinfo
->gen
< 6) {
3439 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3443 } else if (devinfo
->gen
>= 8) {
3444 /* Store the offset in a GRF so we can send-from-GRF. */
3445 src_reg offset
= src_reg(this, glsl_type::int_type
);
3446 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3449 int message_header_scale
= devinfo
->gen
< 6 ? 16 : 1;
3450 return src_reg(reg_offset
* message_header_scale
);
3455 * Emits an instruction before @inst to load the value named by @orig_src
3456 * from scratch space at @base_offset to @temp.
3458 * @base_offset is measured in 32-byte units (the size of a register).
3461 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3462 dst_reg temp
, src_reg orig_src
,
3465 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3466 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3469 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3473 * Emits an instruction after @inst to store the value to be written
3474 * to @orig_dst to scratch space at @base_offset, from @temp.
3476 * @base_offset is measured in 32-byte units (the size of a register).
3479 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3482 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3483 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3486 /* Create a temporary register to store *inst's result in.
3488 * We have to be careful in MOVing from our temporary result register in
3489 * the scratch write. If we swizzle from channels of the temporary that
3490 * weren't initialized, it will confuse live interval analysis, which will
3491 * make spilling fail to make progress.
3493 const src_reg temp
= swizzle(retype(src_reg(this, glsl_type::vec4_type
),
3495 brw_swizzle_for_mask(inst
->dst
.writemask
));
3496 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3497 inst
->dst
.writemask
));
3498 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3499 if (inst
->opcode
!= BRW_OPCODE_SEL
)
3500 write
->predicate
= inst
->predicate
;
3501 write
->ir
= inst
->ir
;
3502 write
->annotation
= inst
->annotation
;
3503 inst
->insert_after(block
, write
);
3505 inst
->dst
.file
= temp
.file
;
3506 inst
->dst
.reg
= temp
.reg
;
3507 inst
->dst
.reg_offset
= temp
.reg_offset
;
3508 inst
->dst
.reladdr
= NULL
;
3512 * Checks if \p src and/or \p src.reladdr require a scratch read, and if so,
3513 * adds the scratch read(s) before \p inst. The function also checks for
3514 * recursive reladdr scratch accesses, issuing the corresponding scratch
3515 * loads and rewriting reladdr references accordingly.
3517 * \return \p src if it did not require a scratch load, otherwise, the
3518 * register holding the result of the scratch load that the caller should
3519 * use to rewrite src.
3522 vec4_visitor::emit_resolve_reladdr(int scratch_loc
[], bblock_t
*block
,
3523 vec4_instruction
*inst
, src_reg src
)
3525 /* Resolve recursive reladdr scratch access by calling ourselves
3529 *src
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3532 /* Now handle scratch access on src */
3533 if (src
.file
== GRF
&& scratch_loc
[src
.reg
] != -1) {
3534 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3535 emit_scratch_read(block
, inst
, temp
, src
, scratch_loc
[src
.reg
]);
3537 src
.reg_offset
= temp
.reg_offset
;
3545 * We can't generally support array access in GRF space, because a
3546 * single instruction's destination can only span 2 contiguous
3547 * registers. So, we send all GRF arrays that get variable index
3548 * access to scratch space.
3551 vec4_visitor::move_grf_array_access_to_scratch()
3553 int scratch_loc
[this->alloc
.count
];
3554 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3556 /* First, calculate the set of virtual GRFs that need to be punted
3557 * to scratch due to having any array access on them, and where in
3560 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3561 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
) {
3562 if (scratch_loc
[inst
->dst
.reg
] == -1) {
3563 scratch_loc
[inst
->dst
.reg
] = last_scratch
;
3564 last_scratch
+= this->alloc
.sizes
[inst
->dst
.reg
];
3567 for (src_reg
*iter
= inst
->dst
.reladdr
;
3569 iter
= iter
->reladdr
) {
3570 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3571 scratch_loc
[iter
->reg
] = last_scratch
;
3572 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3577 for (int i
= 0 ; i
< 3; i
++) {
3578 for (src_reg
*iter
= &inst
->src
[i
];
3580 iter
= iter
->reladdr
) {
3581 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3582 scratch_loc
[iter
->reg
] = last_scratch
;
3583 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3589 /* Now, for anything that will be accessed through scratch, rewrite
3590 * it to load/store. Note that this is a _safe list walk, because
3591 * we may generate a new scratch_write instruction after the one
3594 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3595 /* Set up the annotation tracking for new generated instructions. */
3597 current_annotation
= inst
->annotation
;
3599 /* First handle scratch access on the dst. Notice we have to handle
3600 * the case where the dst's reladdr also points to scratch space.
3602 if (inst
->dst
.reladdr
)
3603 *inst
->dst
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3604 *inst
->dst
.reladdr
);
3606 /* Now that we have handled any (possibly recursive) reladdr scratch
3607 * accesses for dst we can safely do the scratch write for dst itself
3609 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1)
3610 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3612 /* Now handle scratch access on any src. In this case, since inst->src[i]
3613 * already is a src_reg, we can just call emit_resolve_reladdr with
3614 * inst->src[i] and it will take care of handling scratch loads for
3615 * both src and src.reladdr (recursively).
3617 for (int i
= 0 ; i
< 3; i
++) {
3618 inst
->src
[i
] = emit_resolve_reladdr(scratch_loc
, block
, inst
,
3625 * Emits an instruction before @inst to load the value named by @orig_src
3626 * from the pull constant buffer (surface) at @base_offset to @temp.
3629 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3630 dst_reg temp
, src_reg orig_src
,
3633 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3634 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3635 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3638 emit_pull_constant_load_reg(temp
,
3645 * Implements array access of uniforms by inserting a
3646 * PULL_CONSTANT_LOAD instruction.
3648 * Unlike temporary GRF array access (where we don't support it due to
3649 * the difficulty of doing relative addressing on instruction
3650 * destinations), we could potentially do array access of uniforms
3651 * that were loaded in GRF space as push constants. In real-world
3652 * usage we've seen, though, the arrays being used are always larger
3653 * than we could load as push constants, so just always move all
3654 * uniform array access out to a pull constant buffer.
3657 vec4_visitor::move_uniform_array_access_to_pull_constants()
3659 int pull_constant_loc
[this->uniforms
];
3660 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3661 bool nested_reladdr
;
3663 /* Walk through and find array access of uniforms. Put a copy of that
3664 * uniform in the pull constant buffer.
3666 * Note that we don't move constant-indexed accesses to arrays. No
3667 * testing has been done of the performance impact of this choice.
3670 nested_reladdr
= false;
3672 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3673 for (int i
= 0 ; i
< 3; i
++) {
3674 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3677 int uniform
= inst
->src
[i
].reg
;
3679 if (inst
->src
[i
].reladdr
->reladdr
)
3680 nested_reladdr
= true; /* will need another pass */
3682 /* If this array isn't already present in the pull constant buffer,
3685 if (pull_constant_loc
[uniform
] == -1) {
3686 const gl_constant_value
**values
=
3687 &stage_prog_data
->param
[uniform
* 4];
3689 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3691 assert(uniform
< uniform_array_size
);
3692 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3693 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3698 /* Set up the annotation tracking for new generated instructions. */
3700 current_annotation
= inst
->annotation
;
3702 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3704 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3705 pull_constant_loc
[uniform
]);
3707 inst
->src
[i
].file
= temp
.file
;
3708 inst
->src
[i
].reg
= temp
.reg
;
3709 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3710 inst
->src
[i
].reladdr
= NULL
;
3713 } while (nested_reladdr
);
3715 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3716 * no need to track them as larger-than-vec4 objects. This will be
3717 * relied on in cutting out unused uniform vectors from push
3720 split_uniform_registers();
3724 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3726 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3730 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3731 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3736 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3738 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3739 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3742 vec4_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, src_reg
*reg
)
3744 assert(devinfo
->gen
<= 5);
3746 if (!rvalue
->type
->is_boolean())
3749 src_reg and_result
= src_reg(this, rvalue
->type
);
3750 src_reg neg_result
= src_reg(this, rvalue
->type
);
3751 emit(AND(dst_reg(and_result
), *reg
, src_reg(1)));
3752 emit(MOV(dst_reg(neg_result
), negate(and_result
)));
3756 vec4_visitor::vec4_visitor(const struct brw_compiler
*compiler
,
3758 struct gl_program
*prog
,
3759 const struct brw_vue_prog_key
*key
,
3760 struct brw_vue_prog_data
*prog_data
,
3761 struct gl_shader_program
*shader_prog
,
3762 gl_shader_stage stage
,
3765 int shader_time_index
)
3766 : backend_shader(compiler
, log_data
, mem_ctx
,
3767 shader_prog
, prog
, &prog_data
->base
, stage
),
3769 prog_data(prog_data
),
3770 sanity_param_count(0),
3772 first_non_payload_grf(0),
3773 need_all_constants_in_pull_buffer(false),
3774 no_spills(no_spills
),
3775 shader_time_index(shader_time_index
),
3778 this->failed
= false;
3780 this->base_ir
= NULL
;
3781 this->current_annotation
= NULL
;
3782 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3784 this->variable_ht
= hash_table_ctor(0,
3785 hash_table_pointer_hash
,
3786 hash_table_pointer_compare
);
3788 this->virtual_grf_start
= NULL
;
3789 this->virtual_grf_end
= NULL
;
3790 this->live_intervals
= NULL
;
3792 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3796 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3797 * at least one. See setup_uniforms() in brw_vec4.cpp.
3799 this->uniform_array_size
= 1;
3801 this->uniform_array_size
=
3802 MAX2(DIV_ROUND_UP(stage_prog_data
->nr_params
, 4), 1);
3805 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3806 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3809 vec4_visitor::~vec4_visitor()
3811 hash_table_dtor(this->variable_ht
);
3816 vec4_visitor::fail(const char *format
, ...)
3826 va_start(va
, format
);
3827 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3829 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
3831 this->fail_msg
= msg
;
3833 if (debug_enabled
) {
3834 fprintf(stderr
, "%s", msg
);
3838 } /* namespace brw */