2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
31 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
32 const src_reg
&src0
, const src_reg
&src1
,
35 this->opcode
= opcode
;
40 this->saturate
= false;
41 this->force_writemask_all
= false;
42 this->no_dd_clear
= false;
43 this->no_dd_check
= false;
44 this->writes_accumulator
= false;
45 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
47 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
48 this->shadow_compare
= false;
50 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
51 this->header_present
= false;
55 this->annotation
= NULL
;
59 vec4_visitor::emit(vec4_instruction
*inst
)
61 inst
->ir
= this->base_ir
;
62 inst
->annotation
= this->current_annotation
;
64 this->instructions
.push_tail(inst
);
70 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
71 vec4_instruction
*new_inst
)
73 new_inst
->ir
= inst
->ir
;
74 new_inst
->annotation
= inst
->annotation
;
76 inst
->insert_before(block
, new_inst
);
82 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
83 const src_reg
&src1
, const src_reg
&src2
)
85 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
90 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
93 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
97 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
99 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
103 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
105 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
109 vec4_visitor::emit(enum opcode opcode
)
111 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
116 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
118 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
123 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
124 const src_reg &src1) \
126 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
130 #define ALU2_ACC(op) \
132 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
133 const src_reg &src1) \
135 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
136 BRW_OPCODE_##op, dst, src0, src1); \
137 inst->writes_accumulator = true; \
143 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
144 const src_reg &src1, const src_reg &src2) \
146 assert(brw->gen >= 6); \
147 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
184 /** Gen4 predicated IF. */
186 vec4_visitor::IF(enum brw_predicate predicate
)
188 vec4_instruction
*inst
;
190 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
191 inst
->predicate
= predicate
;
196 /** Gen6 IF with embedded comparison. */
198 vec4_visitor::IF(src_reg src0
, src_reg src1
,
199 enum brw_conditional_mod condition
)
201 assert(brw
->gen
== 6);
203 vec4_instruction
*inst
;
205 resolve_ud_negate(&src0
);
206 resolve_ud_negate(&src1
);
208 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
210 inst
->conditional_mod
= condition
;
216 * CMP: Sets the low bit of the destination channels with the result
217 * of the comparison, while the upper bits are undefined, and updates
218 * the flag register with the packed 16 bits of the result.
221 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
222 enum brw_conditional_mod condition
)
224 vec4_instruction
*inst
;
226 /* Take the instruction:
228 * CMP null<d> src0<f> src1<f>
230 * Original gen4 does type conversion to the destination type before
231 * comparison, producing garbage results for floating point comparisons.
233 * The destination type doesn't matter on newer generations, so we set the
234 * type to match src0 so we can compact the instruction.
236 dst
.type
= src0
.type
;
237 if (dst
.file
== HW_REG
)
238 dst
.fixed_hw_reg
.type
= dst
.type
;
240 resolve_ud_negate(&src0
);
241 resolve_ud_negate(&src1
);
243 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
244 inst
->conditional_mod
= condition
;
250 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
252 vec4_instruction
*inst
;
254 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
263 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
264 const src_reg
&index
)
266 vec4_instruction
*inst
;
268 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
277 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
279 static enum opcode dot_opcodes
[] = {
280 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
283 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
287 vec4_visitor::fix_3src_operand(src_reg src
)
289 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
290 * able to use vertical stride of zero to replicate the vec4 uniform, like
292 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
294 * But you can't, since vertical stride is always four in three-source
295 * instructions. Instead, insert a MOV instruction to do the replication so
296 * that the three-source instruction can consume it.
299 /* The MOV is only needed if the source is a uniform or immediate. */
300 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
303 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
306 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
307 expanded
.type
= src
.type
;
308 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
309 return src_reg(expanded
);
313 vec4_visitor::fix_math_operand(src_reg src
)
315 if (brw
->gen
< 6 || brw
->gen
>= 8 || src
.file
== BAD_FILE
)
318 /* The gen6 math instruction ignores the source modifiers --
319 * swizzle, abs, negate, and at least some parts of the register
320 * region description.
322 * Rather than trying to enumerate all these cases, *always* expand the
323 * operand to a temp GRF for gen6.
325 * For gen7, keep the operand as-is, except if immediate, which gen7 still
329 if (brw
->gen
== 7 && src
.file
!= IMM
)
332 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
333 expanded
.type
= src
.type
;
334 emit(MOV(expanded
, src
));
335 return src_reg(expanded
);
339 vec4_visitor::emit_math(enum opcode opcode
,
341 const src_reg
&src0
, const src_reg
&src1
)
343 vec4_instruction
*math
=
344 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
346 if (brw
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
347 /* MATH on Gen6 must be align1, so we can't do writemasks. */
348 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
349 math
->dst
.type
= dst
.type
;
350 emit(MOV(dst
, src_reg(math
->dst
)));
351 } else if (brw
->gen
< 6) {
353 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
358 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
361 unreachable("ir_unop_pack_half_2x16 should be lowered");
364 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
365 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
367 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
369 * Because this instruction does not have a 16-bit floating-point type,
370 * the destination data type must be Word (W).
372 * The destination must be DWord-aligned and specify a horizontal stride
373 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
374 * each destination channel and the upper word is not modified.
376 * The above restriction implies that the f32to16 instruction must use
377 * align1 mode, because only in align1 mode is it possible to specify
378 * horizontal stride. We choose here to defy the hardware docs and emit
379 * align16 instructions.
381 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
382 * instructions. I was partially successful in that the code passed all
383 * tests. However, the code was dubiously correct and fragile, and the
384 * tests were not harsh enough to probe that frailty. Not trusting the
385 * code, I chose instead to remain in align16 mode in defiance of the hw
388 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
389 * simulator, emitting a f32to16 in align16 mode with UD as destination
390 * data type is safe. The behavior differs from that specified in the PRM
391 * in that the upper word of each destination channel is cleared to 0.
394 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
395 src_reg
tmp_src(tmp_dst
);
398 /* Verify the undocumented behavior on which the following instructions
399 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
400 * then the result of the bit-or instruction below will be incorrect.
402 * You should inspect the disasm output in order to verify that the MOV is
403 * not optimized away.
405 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
408 /* Give tmp the form below, where "." means untouched.
411 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
413 * That the upper word of each write-channel be 0 is required for the
414 * following bit-shift and bit-or instructions to work. Note that this
415 * relies on the undocumented hardware behavior mentioned above.
417 tmp_dst
.writemask
= WRITEMASK_XY
;
418 emit(F32TO16(tmp_dst
, src0
));
420 /* Give the write-channels of dst the form:
423 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
424 emit(SHL(dst
, tmp_src
, src_reg(16u)));
426 /* Finally, give the write-channels of dst the form of packHalf2x16's
430 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
431 emit(OR(dst
, src_reg(dst
), tmp_src
));
435 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
438 unreachable("ir_unop_unpack_half_2x16 should be lowered");
441 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
442 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
444 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
446 * Because this instruction does not have a 16-bit floating-point type,
447 * the source data type must be Word (W). The destination type must be
450 * To use W as the source data type, we must adjust horizontal strides,
451 * which is only possible in align1 mode. All my [chadv] attempts at
452 * emitting align1 instructions for unpackHalf2x16 failed to pass the
453 * Piglit tests, so I gave up.
455 * I've verified that, on gen7 hardware and the simulator, it is safe to
456 * emit f16to32 in align16 mode with UD as source data type.
459 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
460 src_reg
tmp_src(tmp_dst
);
462 tmp_dst
.writemask
= WRITEMASK_X
;
463 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
465 tmp_dst
.writemask
= WRITEMASK_Y
;
466 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
468 dst
.writemask
= WRITEMASK_XY
;
469 emit(F16TO32(dst
, tmp_src
));
473 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
475 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
476 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
477 * is not suitable to generate the shift values, but we can use the packed
478 * vector float and a type-converting MOV.
480 dst_reg
shift(this, glsl_type::uvec4_type
);
481 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
483 dst_reg
shifted(this, glsl_type::uvec4_type
);
484 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
485 emit(SHR(shifted
, src0
, src_reg(shift
)));
487 shifted
.type
= BRW_REGISTER_TYPE_UB
;
488 dst_reg
f(this, glsl_type::vec4_type
);
489 emit(MOV(f
, src_reg(shifted
)));
491 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
495 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
497 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
498 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
499 * is not suitable to generate the shift values, but we can use the packed
500 * vector float and a type-converting MOV.
502 dst_reg
shift(this, glsl_type::uvec4_type
);
503 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
505 dst_reg
shifted(this, glsl_type::uvec4_type
);
506 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
507 emit(SHR(shifted
, src0
, src_reg(shift
)));
509 shifted
.type
= BRW_REGISTER_TYPE_B
;
510 dst_reg
f(this, glsl_type::vec4_type
);
511 emit(MOV(f
, src_reg(shifted
)));
513 dst_reg
scaled(this, glsl_type::vec4_type
);
514 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
516 dst_reg
max(this, glsl_type::vec4_type
);
517 emit_minmax(BRW_CONDITIONAL_G
, max
, src_reg(scaled
), src_reg(-1.0f
));
518 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
522 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
524 dst_reg
saturated(this, glsl_type::vec4_type
);
525 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
526 inst
->saturate
= true;
528 dst_reg
scaled(this, glsl_type::vec4_type
);
529 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
531 dst_reg
rounded(this, glsl_type::vec4_type
);
532 emit(RNDE(rounded
, src_reg(scaled
)));
534 dst_reg
u(this, glsl_type::uvec4_type
);
535 emit(MOV(u
, src_reg(rounded
)));
538 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
542 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
544 dst_reg
max(this, glsl_type::vec4_type
);
545 emit_minmax(BRW_CONDITIONAL_G
, max
, src0
, src_reg(-1.0f
));
547 dst_reg
min(this, glsl_type::vec4_type
);
548 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
550 dst_reg
scaled(this, glsl_type::vec4_type
);
551 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
553 dst_reg
rounded(this, glsl_type::vec4_type
);
554 emit(RNDE(rounded
, src_reg(scaled
)));
556 dst_reg
i(this, glsl_type::ivec4_type
);
557 emit(MOV(i
, src_reg(rounded
)));
560 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
564 vec4_visitor::visit_instructions(const exec_list
*list
)
566 foreach_in_list(ir_instruction
, ir
, list
) {
574 type_size(const struct glsl_type
*type
)
579 switch (type
->base_type
) {
582 case GLSL_TYPE_FLOAT
:
584 if (type
->is_matrix()) {
585 return type
->matrix_columns
;
587 /* Regardless of size of vector, it gets a vec4. This is bad
588 * packing for things like floats, but otherwise arrays become a
589 * mess. Hopefully a later pass over the code can pack scalars
590 * down if appropriate.
594 case GLSL_TYPE_ARRAY
:
595 assert(type
->length
> 0);
596 return type_size(type
->fields
.array
) * type
->length
;
597 case GLSL_TYPE_STRUCT
:
599 for (i
= 0; i
< type
->length
; i
++) {
600 size
+= type_size(type
->fields
.structure
[i
].type
);
603 case GLSL_TYPE_SAMPLER
:
604 /* Samplers take up no register space, since they're baked in at
608 case GLSL_TYPE_ATOMIC_UINT
:
610 case GLSL_TYPE_IMAGE
:
612 case GLSL_TYPE_ERROR
:
613 case GLSL_TYPE_INTERFACE
:
614 unreachable("not reached");
620 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
625 this->reg
= v
->alloc
.allocate(type_size(type
));
627 if (type
->is_array() || type
->is_record()) {
628 this->swizzle
= BRW_SWIZZLE_NOOP
;
630 this->swizzle
= swizzle_for_size(type
->vector_elements
);
633 this->type
= brw_type_for_base_type(type
);
636 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
643 this->reg
= v
->alloc
.allocate(type_size(type
) * size
);
645 this->swizzle
= BRW_SWIZZLE_NOOP
;
647 this->type
= brw_type_for_base_type(type
);
650 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
655 this->reg
= v
->alloc
.allocate(type_size(type
));
657 if (type
->is_array() || type
->is_record()) {
658 this->writemask
= WRITEMASK_XYZW
;
660 this->writemask
= (1 << type
->vector_elements
) - 1;
663 this->type
= brw_type_for_base_type(type
);
666 /* Our support for uniforms is piggy-backed on the struct
667 * gl_fragment_program, because that's where the values actually
668 * get stored, rather than in some global gl_shader_program uniform
672 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
674 int namelen
= strlen(ir
->name
);
676 /* The data for our (non-builtin) uniforms is stored in a series of
677 * gl_uniform_driver_storage structs for each subcomponent that
678 * glGetUniformLocation() could name. We know it's been set up in the same
679 * order we'd walk the type, so walk the list of storage and find anything
680 * with our name, or the prefix of a component that starts with our name.
682 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
683 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
685 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
686 (storage
->name
[namelen
] != 0 &&
687 storage
->name
[namelen
] != '.' &&
688 storage
->name
[namelen
] != '[')) {
692 gl_constant_value
*components
= storage
->storage
;
693 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
694 storage
->type
->matrix_columns
);
696 for (unsigned s
= 0; s
< vector_count
; s
++) {
697 assert(uniforms
< uniform_array_size
);
698 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
701 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
702 stage_prog_data
->param
[uniforms
* 4 + i
] = components
;
706 static gl_constant_value zero
= { 0.0 };
707 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
716 vec4_visitor::setup_uniform_clipplane_values()
718 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
720 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
721 assert(this->uniforms
< uniform_array_size
);
722 this->uniform_vector_size
[this->uniforms
] = 4;
723 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
724 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
725 for (int j
= 0; j
< 4; ++j
) {
726 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
727 (gl_constant_value
*) &clip_planes
[i
][j
];
733 /* Our support for builtin uniforms is even scarier than non-builtin.
734 * It sits on top of the PROG_STATE_VAR parameters that are
735 * automatically updated from GL context state.
738 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
740 const ir_state_slot
*const slots
= ir
->get_state_slots();
741 assert(slots
!= NULL
);
743 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
744 /* This state reference has already been setup by ir_to_mesa,
745 * but we'll get the same index back here. We can reference
746 * ParameterValues directly, since unlike brw_fs.cpp, we never
747 * add new state references during compile.
749 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
750 (gl_state_index
*)slots
[i
].tokens
);
751 gl_constant_value
*values
=
752 &this->prog
->Parameters
->ParameterValues
[index
][0];
754 assert(this->uniforms
< uniform_array_size
);
755 this->uniform_vector_size
[this->uniforms
] = 0;
756 /* Add each of the unique swizzled channels of the element.
757 * This will end up matching the size of the glsl_type of this field.
760 for (unsigned int j
= 0; j
< 4; j
++) {
761 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
764 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
765 assert(this->uniforms
< uniform_array_size
);
766 if (swiz
<= last_swiz
)
767 this->uniform_vector_size
[this->uniforms
]++;
774 vec4_visitor::variable_storage(ir_variable
*var
)
776 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
780 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
781 enum brw_predicate
*predicate
)
783 ir_expression
*expr
= ir
->as_expression();
785 *predicate
= BRW_PREDICATE_NORMAL
;
787 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
789 vec4_instruction
*inst
;
791 assert(expr
->get_num_operands() <= 3);
792 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
793 expr
->operands
[i
]->accept(this);
794 op
[i
] = this->result
;
796 resolve_ud_negate(&op
[i
]);
799 switch (expr
->operation
) {
800 case ir_unop_logic_not
:
801 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
802 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
805 case ir_binop_logic_xor
:
807 src_reg temp
= src_reg(this, ir
->type
);
808 emit(XOR(dst_reg(temp
), op
[0], op
[1]));
809 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
811 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
813 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
816 case ir_binop_logic_or
:
818 src_reg temp
= src_reg(this, ir
->type
);
819 emit(OR(dst_reg(temp
), op
[0], op
[1]));
820 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
822 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
824 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
827 case ir_binop_logic_and
:
829 src_reg temp
= src_reg(this, ir
->type
);
830 emit(AND(dst_reg(temp
), op
[0], op
[1]));
831 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
833 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
835 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
840 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
842 inst
= emit(MOV(dst_null_f(), op
[0]));
843 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
849 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
851 inst
= emit(MOV(dst_null_d(), op
[0]));
852 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
856 case ir_binop_all_equal
:
858 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
859 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
861 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
862 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
865 case ir_binop_any_nequal
:
867 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
868 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
870 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
871 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
876 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
878 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
879 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
882 case ir_binop_greater
:
883 case ir_binop_gequal
:
885 case ir_binop_lequal
:
887 case ir_binop_nequal
:
889 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
890 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
892 emit(CMP(dst_null_d(), op
[0], op
[1],
893 brw_conditional_for_comparison(expr
->operation
)));
896 case ir_triop_csel
: {
897 /* Expand the boolean condition into the flag register. */
898 inst
= emit(MOV(dst_null_d(), op
[0]));
899 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
901 /* Select which boolean to return. */
902 dst_reg
temp(this, expr
->operands
[1]->type
);
903 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
904 inst
->predicate
= BRW_PREDICATE_NORMAL
;
906 /* Expand the result to a condition code. */
907 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
908 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
913 unreachable("not reached");
920 resolve_ud_negate(&this->result
);
922 vec4_instruction
*inst
= emit(AND(dst_null_d(), this->result
, src_reg(1)));
923 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
927 * Emit a gen6 IF statement with the comparison folded into the IF
931 vec4_visitor::emit_if_gen6(ir_if
*ir
)
933 ir_expression
*expr
= ir
->condition
->as_expression();
935 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
939 assert(expr
->get_num_operands() <= 3);
940 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
941 expr
->operands
[i
]->accept(this);
942 op
[i
] = this->result
;
945 switch (expr
->operation
) {
946 case ir_unop_logic_not
:
947 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
950 case ir_binop_logic_xor
:
951 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
954 case ir_binop_logic_or
:
955 temp
= dst_reg(this, glsl_type::bool_type
);
956 emit(OR(temp
, op
[0], op
[1]));
957 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
960 case ir_binop_logic_and
:
961 temp
= dst_reg(this, glsl_type::bool_type
);
962 emit(AND(temp
, op
[0], op
[1]));
963 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
967 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
971 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
974 case ir_binop_greater
:
975 case ir_binop_gequal
:
977 case ir_binop_lequal
:
979 case ir_binop_nequal
:
980 emit(IF(op
[0], op
[1],
981 brw_conditional_for_comparison(expr
->operation
)));
984 case ir_binop_all_equal
:
985 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
986 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
989 case ir_binop_any_nequal
:
990 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
991 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
995 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
996 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
999 case ir_triop_csel
: {
1000 /* Expand the boolean condition into the flag register. */
1001 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
1002 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1004 /* Select which boolean to return. */
1005 dst_reg
temp(this, expr
->operands
[1]->type
);
1006 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
1007 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1009 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
1014 unreachable("not reached");
1019 ir
->condition
->accept(this);
1021 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
1025 vec4_visitor::visit(ir_variable
*ir
)
1027 dst_reg
*reg
= NULL
;
1029 if (variable_storage(ir
))
1032 switch (ir
->data
.mode
) {
1033 case ir_var_shader_in
:
1034 assert(ir
->data
.location
!= -1);
1035 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
1038 case ir_var_shader_out
:
1039 assert(ir
->data
.location
!= -1);
1040 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1042 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1043 output_reg
[ir
->data
.location
+ i
] = *reg
;
1044 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
1045 output_reg
[ir
->data
.location
+ i
].type
=
1046 brw_type_for_base_type(ir
->type
->get_scalar_type());
1047 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
1052 case ir_var_temporary
:
1053 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1056 case ir_var_uniform
:
1057 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1059 /* Thanks to the lower_ubo_reference pass, we will see only
1060 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1061 * variables, so no need for them to be in variable_ht.
1063 * Some uniforms, such as samplers and atomic counters, have no actual
1064 * storage, so we should ignore them.
1066 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
1069 /* Track how big the whole uniform variable is, in case we need to put a
1070 * copy of its data into pull constants for array access.
1072 assert(this->uniforms
< uniform_array_size
);
1073 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1075 if (!strncmp(ir
->name
, "gl_", 3)) {
1076 setup_builtin_uniform_values(ir
);
1078 setup_uniform_values(ir
);
1082 case ir_var_system_value
:
1083 reg
= make_reg_for_system_value(ir
);
1087 unreachable("not reached");
1090 reg
->type
= brw_type_for_base_type(ir
->type
);
1091 hash_table_insert(this->variable_ht
, reg
, ir
);
1095 vec4_visitor::visit(ir_loop
*ir
)
1097 /* We don't want debugging output to print the whole body of the
1098 * loop as the annotation.
1100 this->base_ir
= NULL
;
1102 emit(BRW_OPCODE_DO
);
1104 visit_instructions(&ir
->body_instructions
);
1106 emit(BRW_OPCODE_WHILE
);
1110 vec4_visitor::visit(ir_loop_jump
*ir
)
1113 case ir_loop_jump::jump_break
:
1114 emit(BRW_OPCODE_BREAK
);
1116 case ir_loop_jump::jump_continue
:
1117 emit(BRW_OPCODE_CONTINUE
);
1124 vec4_visitor::visit(ir_function_signature
*)
1126 unreachable("not reached");
1130 vec4_visitor::visit(ir_function
*ir
)
1132 /* Ignore function bodies other than main() -- we shouldn't see calls to
1133 * them since they should all be inlined.
1135 if (strcmp(ir
->name
, "main") == 0) {
1136 const ir_function_signature
*sig
;
1139 sig
= ir
->matching_signature(NULL
, &empty
, false);
1143 visit_instructions(&sig
->body
);
1148 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1150 /* 3-src instructions were introduced in gen6. */
1154 /* MAD can only handle floating-point data. */
1155 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1158 ir_rvalue
*nonmul
= ir
->operands
[1];
1159 ir_expression
*mul
= ir
->operands
[0]->as_expression();
1161 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
1162 nonmul
= ir
->operands
[0];
1163 mul
= ir
->operands
[1]->as_expression();
1165 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1169 nonmul
->accept(this);
1170 src_reg src0
= fix_3src_operand(this->result
);
1172 mul
->operands
[0]->accept(this);
1173 src_reg src1
= fix_3src_operand(this->result
);
1175 mul
->operands
[1]->accept(this);
1176 src_reg src2
= fix_3src_operand(this->result
);
1178 this->result
= src_reg(this, ir
->type
);
1179 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1185 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1187 /* This optimization relies on CMP setting the destination to 0 when
1188 * false. Early hardware only sets the least significant bit, and
1189 * leaves the other bits undefined. So we can't use it.
1194 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1199 switch (cmp
->operation
) {
1201 case ir_binop_greater
:
1202 case ir_binop_lequal
:
1203 case ir_binop_gequal
:
1204 case ir_binop_equal
:
1205 case ir_binop_nequal
:
1212 cmp
->operands
[0]->accept(this);
1213 const src_reg cmp_src0
= this->result
;
1215 cmp
->operands
[1]->accept(this);
1216 const src_reg cmp_src1
= this->result
;
1218 this->result
= src_reg(this, ir
->type
);
1220 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1221 brw_conditional_for_comparison(cmp
->operation
)));
1223 /* If the comparison is false, this->result will just happen to be zero.
1225 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1226 this->result
, src_reg(1.0f
));
1227 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1228 inst
->predicate_inverse
= true;
1234 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1235 src_reg src0
, src_reg src1
)
1237 vec4_instruction
*inst
;
1239 if (brw
->gen
>= 6) {
1240 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1241 inst
->conditional_mod
= conditionalmod
;
1243 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1245 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1246 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1251 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1252 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1254 if (brw
->gen
>= 6) {
1255 /* Note that the instruction's argument order is reversed from GLSL
1259 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1261 /* Earlier generations don't support three source operations, so we
1262 * need to emit x*(1-a) + y*a.
1264 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1265 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1266 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1267 y_times_a
.writemask
= dst
.writemask
;
1268 one_minus_a
.writemask
= dst
.writemask
;
1269 x_times_one_minus_a
.writemask
= dst
.writemask
;
1271 emit(MUL(y_times_a
, y
, a
));
1272 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1273 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1274 emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1279 vec4_visitor::visit(ir_expression
*ir
)
1281 unsigned int operand
;
1282 src_reg op
[Elements(ir
->operands
)];
1283 vec4_instruction
*inst
;
1285 if (ir
->operation
== ir_binop_add
) {
1286 if (try_emit_mad(ir
))
1290 if (ir
->operation
== ir_unop_b2f
) {
1291 if (try_emit_b2f_of_compare(ir
))
1295 /* Storage for our result. Ideally for an assignment we'd be using
1296 * the actual storage for the result here, instead.
1298 dst_reg
result_dst(this, ir
->type
);
1299 src_reg
result_src(result_dst
);
1301 if (ir
->operation
== ir_triop_csel
) {
1302 ir
->operands
[1]->accept(this);
1303 op
[1] = this->result
;
1304 ir
->operands
[2]->accept(this);
1305 op
[2] = this->result
;
1307 enum brw_predicate predicate
;
1308 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1309 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1310 inst
->predicate
= predicate
;
1311 this->result
= result_src
;
1315 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1316 this->result
.file
= BAD_FILE
;
1317 ir
->operands
[operand
]->accept(this);
1318 if (this->result
.file
== BAD_FILE
) {
1319 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1320 ir
->operands
[operand
]->fprint(stderr
);
1323 op
[operand
] = this->result
;
1325 /* Matrix expression operands should have been broken down to vector
1326 * operations already.
1328 assert(!ir
->operands
[operand
]->type
->is_matrix());
1331 /* If nothing special happens, this is the result. */
1332 this->result
= result_src
;
1334 switch (ir
->operation
) {
1335 case ir_unop_logic_not
:
1336 emit(NOT(result_dst
, op
[0]));
1339 op
[0].negate
= !op
[0].negate
;
1340 emit(MOV(result_dst
, op
[0]));
1344 op
[0].negate
= false;
1345 emit(MOV(result_dst
, op
[0]));
1349 if (ir
->type
->is_float()) {
1350 /* AND(val, 0x80000000) gives the sign bit.
1352 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1355 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1357 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1358 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1359 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1361 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1362 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1364 this->result
.type
= BRW_REGISTER_TYPE_F
;
1366 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1367 * -> non-negative val generates 0x00000000.
1368 * Predicated OR sets 1 if val is positive.
1370 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1372 emit(ASR(result_dst
, op
[0], src_reg(31)));
1374 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1375 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1380 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1384 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1387 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1391 unreachable("not reached: should be handled by ir_explog_to_explog2");
1393 case ir_unop_sin_reduced
:
1394 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1397 case ir_unop_cos_reduced
:
1398 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1402 case ir_unop_dFdx_coarse
:
1403 case ir_unop_dFdx_fine
:
1405 case ir_unop_dFdy_coarse
:
1406 case ir_unop_dFdy_fine
:
1407 unreachable("derivatives not valid in vertex shader");
1409 case ir_unop_bitfield_reverse
:
1410 emit(BFREV(result_dst
, op
[0]));
1412 case ir_unop_bit_count
:
1413 emit(CBIT(result_dst
, op
[0]));
1415 case ir_unop_find_msb
: {
1416 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1418 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1419 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1421 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1422 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1423 * subtract the result from 31 to convert the MSB count into an LSB count.
1426 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1427 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1428 emit(MOV(result_dst
, temp
));
1430 src_reg src_tmp
= src_reg(result_dst
);
1431 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1433 src_tmp
.negate
= true;
1434 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1435 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1438 case ir_unop_find_lsb
:
1439 emit(FBL(result_dst
, op
[0]));
1441 case ir_unop_saturate
:
1442 inst
= emit(MOV(result_dst
, op
[0]));
1443 inst
->saturate
= true;
1447 unreachable("not reached: should be handled by lower_noise");
1450 emit(ADD(result_dst
, op
[0], op
[1]));
1453 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1456 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
1457 /* For integer multiplication, the MUL uses the low 16 bits of one of
1458 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1459 * accumulates in the contribution of the upper 16 bits of that
1460 * operand. If we can determine that one of the args is in the low
1461 * 16 bits, though, we can just emit a single MUL.
1463 if (ir
->operands
[0]->is_uint16_constant()) {
1465 emit(MUL(result_dst
, op
[0], op
[1]));
1467 emit(MUL(result_dst
, op
[1], op
[0]));
1468 } else if (ir
->operands
[1]->is_uint16_constant()) {
1470 emit(MUL(result_dst
, op
[1], op
[0]));
1472 emit(MUL(result_dst
, op
[0], op
[1]));
1474 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1476 emit(MUL(acc
, op
[0], op
[1]));
1477 emit(MACH(dst_null_d(), op
[0], op
[1]));
1478 emit(MOV(result_dst
, src_reg(acc
)));
1481 emit(MUL(result_dst
, op
[0], op
[1]));
1484 case ir_binop_imul_high
: {
1485 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1487 emit(MUL(acc
, op
[0], op
[1]));
1488 emit(MACH(result_dst
, op
[0], op
[1]));
1492 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1493 assert(ir
->type
->is_integer());
1494 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1496 case ir_binop_carry
: {
1497 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1499 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1500 emit(MOV(result_dst
, src_reg(acc
)));
1503 case ir_binop_borrow
: {
1504 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1506 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1507 emit(MOV(result_dst
, src_reg(acc
)));
1511 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1512 assert(ir
->type
->is_integer());
1513 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1517 case ir_binop_greater
:
1518 case ir_binop_lequal
:
1519 case ir_binop_gequal
:
1520 case ir_binop_equal
:
1521 case ir_binop_nequal
: {
1522 if (brw
->gen
<= 5) {
1523 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1524 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1526 emit(CMP(result_dst
, op
[0], op
[1],
1527 brw_conditional_for_comparison(ir
->operation
)));
1531 case ir_binop_all_equal
:
1532 /* "==" operator producing a scalar boolean. */
1533 if (ir
->operands
[0]->type
->is_vector() ||
1534 ir
->operands
[1]->type
->is_vector()) {
1535 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1536 emit(MOV(result_dst
, src_reg(0)));
1537 inst
= emit(MOV(result_dst
, src_reg((int)ctx
->Const
.UniformBooleanTrue
)));
1538 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1540 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1543 case ir_binop_any_nequal
:
1544 /* "!=" operator producing a scalar boolean. */
1545 if (ir
->operands
[0]->type
->is_vector() ||
1546 ir
->operands
[1]->type
->is_vector()) {
1547 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1549 emit(MOV(result_dst
, src_reg(0)));
1550 inst
= emit(MOV(result_dst
, src_reg((int)ctx
->Const
.UniformBooleanTrue
)));
1551 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1553 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1558 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1559 emit(MOV(result_dst
, src_reg(0)));
1561 inst
= emit(MOV(result_dst
, src_reg((int)ctx
->Const
.UniformBooleanTrue
)));
1562 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1565 case ir_binop_logic_xor
:
1566 emit(XOR(result_dst
, op
[0], op
[1]));
1569 case ir_binop_logic_or
:
1570 emit(OR(result_dst
, op
[0], op
[1]));
1573 case ir_binop_logic_and
:
1574 emit(AND(result_dst
, op
[0], op
[1]));
1578 assert(ir
->operands
[0]->type
->is_vector());
1579 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1580 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1584 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1587 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1590 case ir_unop_bitcast_i2f
:
1591 case ir_unop_bitcast_u2f
:
1592 this->result
= op
[0];
1593 this->result
.type
= BRW_REGISTER_TYPE_F
;
1596 case ir_unop_bitcast_f2i
:
1597 this->result
= op
[0];
1598 this->result
.type
= BRW_REGISTER_TYPE_D
;
1601 case ir_unop_bitcast_f2u
:
1602 this->result
= op
[0];
1603 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1612 emit(MOV(result_dst
, op
[0]));
1615 emit(AND(result_dst
, op
[0], src_reg(1)));
1618 if (brw
->gen
<= 5) {
1619 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1621 op
[0].type
= BRW_REGISTER_TYPE_D
;
1622 result_dst
.type
= BRW_REGISTER_TYPE_D
;
1623 emit(AND(result_dst
, op
[0], src_reg(0x3f800000u
)));
1624 result_dst
.type
= BRW_REGISTER_TYPE_F
;
1627 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1630 emit(AND(result_dst
, op
[0], src_reg(1)));
1634 emit(RNDZ(result_dst
, op
[0]));
1636 case ir_unop_ceil
: {
1637 src_reg tmp
= src_reg(this, ir
->type
);
1638 op
[0].negate
= !op
[0].negate
;
1639 emit(RNDD(dst_reg(tmp
), op
[0]));
1641 emit(MOV(result_dst
, tmp
));
1645 inst
= emit(RNDD(result_dst
, op
[0]));
1648 inst
= emit(FRC(result_dst
, op
[0]));
1650 case ir_unop_round_even
:
1651 emit(RNDE(result_dst
, op
[0]));
1655 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1658 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1662 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1665 case ir_unop_bit_not
:
1666 inst
= emit(NOT(result_dst
, op
[0]));
1668 case ir_binop_bit_and
:
1669 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1671 case ir_binop_bit_xor
:
1672 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1674 case ir_binop_bit_or
:
1675 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1678 case ir_binop_lshift
:
1679 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1682 case ir_binop_rshift
:
1683 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1684 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1686 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1690 emit(BFI1(result_dst
, op
[0], op
[1]));
1693 case ir_binop_ubo_load
: {
1694 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1695 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1696 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1699 /* Now, load the vector from that offset. */
1700 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1702 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1703 packed_consts
.type
= result
.type
;
1706 if (const_uniform_block
) {
1707 /* The block index is a constant, so just emit the binding table entry
1710 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1711 const_uniform_block
->value
.u
[0]);
1713 /* The block index is not a constant. Evaluate the index expression
1714 * per-channel and add the base UBO index; the generator will select
1715 * a value from any live channel.
1717 surf_index
= src_reg(this, glsl_type::uint_type
);
1718 emit(ADD(dst_reg(surf_index
), op
[0],
1719 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1721 /* Assume this may touch any UBO. It would be nice to provide
1722 * a tighter bound, but the array information is already lowered away.
1724 brw_mark_surface_used(&prog_data
->base
,
1725 prog_data
->base
.binding_table
.ubo_start
+
1726 shader_prog
->NumUniformBlocks
- 1);
1729 if (const_offset_ir
) {
1730 if (brw
->gen
>= 8) {
1731 /* Store the offset in a GRF so we can send-from-GRF. */
1732 offset
= src_reg(this, glsl_type::int_type
);
1733 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1735 /* Immediates are fine on older generations since they'll be moved
1736 * to a (potentially fake) MRF at the generator level.
1738 offset
= src_reg(const_offset
/ 16);
1741 offset
= src_reg(this, glsl_type::uint_type
);
1742 emit(SHR(dst_reg(offset
), op
[1], src_reg(4)));
1745 if (brw
->gen
>= 7) {
1746 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1747 grf_offset
.type
= offset
.type
;
1749 emit(MOV(grf_offset
, offset
));
1751 emit(new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1752 dst_reg(packed_consts
),
1754 src_reg(grf_offset
)));
1756 vec4_instruction
*pull
=
1757 emit(new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
1758 dst_reg(packed_consts
),
1761 pull
->base_mrf
= 14;
1765 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1766 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1767 const_offset
% 16 / 4,
1768 const_offset
% 16 / 4,
1769 const_offset
% 16 / 4);
1771 /* UBO bools are any nonzero int. We need to convert them to use the
1772 * value of true stored in ctx->Const.UniformBooleanTrue.
1774 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1775 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1776 BRW_CONDITIONAL_NZ
));
1778 emit(MOV(result_dst
, packed_consts
));
1783 case ir_binop_vector_extract
:
1784 unreachable("should have been lowered by vec_index_to_cond_assign");
1787 op
[0] = fix_3src_operand(op
[0]);
1788 op
[1] = fix_3src_operand(op
[1]);
1789 op
[2] = fix_3src_operand(op
[2]);
1790 /* Note that the instruction's argument order is reversed from GLSL
1793 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1797 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1801 unreachable("already handled above");
1805 op
[0] = fix_3src_operand(op
[0]);
1806 op
[1] = fix_3src_operand(op
[1]);
1807 op
[2] = fix_3src_operand(op
[2]);
1808 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1811 case ir_triop_bitfield_extract
:
1812 op
[0] = fix_3src_operand(op
[0]);
1813 op
[1] = fix_3src_operand(op
[1]);
1814 op
[2] = fix_3src_operand(op
[2]);
1815 /* Note that the instruction's argument order is reversed from GLSL
1818 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1821 case ir_triop_vector_insert
:
1822 unreachable("should have been lowered by lower_vector_insert");
1824 case ir_quadop_bitfield_insert
:
1825 unreachable("not reached: should be handled by "
1826 "bitfield_insert_to_bfm_bfi\n");
1828 case ir_quadop_vector
:
1829 unreachable("not reached: should be handled by lower_quadop_vector");
1831 case ir_unop_pack_half_2x16
:
1832 emit_pack_half_2x16(result_dst
, op
[0]);
1834 case ir_unop_unpack_half_2x16
:
1835 emit_unpack_half_2x16(result_dst
, op
[0]);
1837 case ir_unop_unpack_unorm_4x8
:
1838 emit_unpack_unorm_4x8(result_dst
, op
[0]);
1840 case ir_unop_unpack_snorm_4x8
:
1841 emit_unpack_snorm_4x8(result_dst
, op
[0]);
1843 case ir_unop_pack_unorm_4x8
:
1844 emit_pack_unorm_4x8(result_dst
, op
[0]);
1846 case ir_unop_pack_snorm_4x8
:
1847 emit_pack_snorm_4x8(result_dst
, op
[0]);
1849 case ir_unop_pack_snorm_2x16
:
1850 case ir_unop_pack_unorm_2x16
:
1851 case ir_unop_unpack_snorm_2x16
:
1852 case ir_unop_unpack_unorm_2x16
:
1853 unreachable("not reached: should be handled by lower_packing_builtins");
1854 case ir_unop_unpack_half_2x16_split_x
:
1855 case ir_unop_unpack_half_2x16_split_y
:
1856 case ir_binop_pack_half_2x16_split
:
1857 case ir_unop_interpolate_at_centroid
:
1858 case ir_binop_interpolate_at_sample
:
1859 case ir_binop_interpolate_at_offset
:
1860 unreachable("not reached: should not occur in vertex shader");
1861 case ir_binop_ldexp
:
1862 unreachable("not reached: should be handled by ldexp_to_arith()");
1868 vec4_visitor::visit(ir_swizzle
*ir
)
1874 /* Note that this is only swizzles in expressions, not those on the left
1875 * hand side of an assignment, which do write masking. See ir_assignment
1879 ir
->val
->accept(this);
1881 assert(src
.file
!= BAD_FILE
);
1883 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1886 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1889 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1892 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1895 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1899 for (; i
< 4; i
++) {
1900 /* Replicate the last channel out. */
1901 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1904 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1910 vec4_visitor::visit(ir_dereference_variable
*ir
)
1912 const struct glsl_type
*type
= ir
->type
;
1913 dst_reg
*reg
= variable_storage(ir
->var
);
1916 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1917 this->result
= src_reg(brw_null_reg());
1921 this->result
= src_reg(*reg
);
1923 /* System values get their swizzle from the dst_reg writemask */
1924 if (ir
->var
->data
.mode
== ir_var_system_value
)
1927 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1928 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1933 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1935 /* Under normal circumstances array elements are stored consecutively, so
1936 * the stride is equal to the size of the array element.
1938 return type_size(ir
->type
);
1943 vec4_visitor::visit(ir_dereference_array
*ir
)
1945 ir_constant
*constant_index
;
1947 int array_stride
= compute_array_stride(ir
);
1949 constant_index
= ir
->array_index
->constant_expression_value();
1951 ir
->array
->accept(this);
1954 if (constant_index
) {
1955 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1957 /* Variable index array dereference. It eats the "vec4" of the
1958 * base of the array and an index that offsets the Mesa register
1961 ir
->array_index
->accept(this);
1965 if (array_stride
== 1) {
1966 index_reg
= this->result
;
1968 index_reg
= src_reg(this, glsl_type::int_type
);
1970 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1974 src_reg temp
= src_reg(this, glsl_type::int_type
);
1976 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1981 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1982 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1985 /* If the type is smaller than a vec4, replicate the last channel out. */
1986 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1987 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1989 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1990 src
.type
= brw_type_for_base_type(ir
->type
);
1996 vec4_visitor::visit(ir_dereference_record
*ir
)
1999 const glsl_type
*struct_type
= ir
->record
->type
;
2002 ir
->record
->accept(this);
2004 for (i
= 0; i
< struct_type
->length
; i
++) {
2005 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2007 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2010 /* If the type is smaller than a vec4, replicate the last channel out. */
2011 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2012 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2014 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
2015 this->result
.type
= brw_type_for_base_type(ir
->type
);
2017 this->result
.reg_offset
+= offset
;
2021 * We want to be careful in assignment setup to hit the actual storage
2022 * instead of potentially using a temporary like we might with the
2023 * ir_dereference handler.
2026 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
2028 /* The LHS must be a dereference. If the LHS is a variable indexed array
2029 * access of a vector, it must be separated into a series conditional moves
2030 * before reaching this point (see ir_vec_index_to_cond_assign).
2032 assert(ir
->as_dereference());
2033 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2035 assert(!deref_array
->array
->type
->is_vector());
2038 /* Use the rvalue deref handler for the most part. We'll ignore
2039 * swizzles in it and write swizzles using writemask, though.
2042 return dst_reg(v
->result
);
2046 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
2047 const struct glsl_type
*type
,
2048 enum brw_predicate predicate
)
2050 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2051 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2052 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
2057 if (type
->is_array()) {
2058 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2059 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
2064 if (type
->is_matrix()) {
2065 const struct glsl_type
*vec_type
;
2067 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2068 type
->vector_elements
, 1);
2070 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2071 emit_block_move(dst
, src
, vec_type
, predicate
);
2076 assert(type
->is_scalar() || type
->is_vector());
2078 dst
->type
= brw_type_for_base_type(type
);
2079 src
->type
= dst
->type
;
2081 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2083 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
2085 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2086 inst
->predicate
= predicate
;
2093 /* If the RHS processing resulted in an instruction generating a
2094 * temporary value, and it would be easy to rewrite the instruction to
2095 * generate its result right into the LHS instead, do so. This ends
2096 * up reliably removing instructions where it can be tricky to do so
2097 * later without real UD chain information.
2100 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2103 vec4_instruction
*pre_rhs_inst
,
2104 vec4_instruction
*last_rhs_inst
)
2106 /* This could be supported, but it would take more smarts. */
2110 if (pre_rhs_inst
== last_rhs_inst
)
2111 return false; /* No instructions generated to work with. */
2113 /* Make sure the last instruction generated our source reg. */
2114 if (src
.file
!= GRF
||
2115 src
.file
!= last_rhs_inst
->dst
.file
||
2116 src
.reg
!= last_rhs_inst
->dst
.reg
||
2117 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2121 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2124 /* Check that that last instruction fully initialized the channels
2125 * we want to use, in the order we want to use them. We could
2126 * potentially reswizzle the operands of many instructions so that
2127 * we could handle out of order channels, but don't yet.
2130 for (unsigned i
= 0; i
< 4; i
++) {
2131 if (dst
.writemask
& (1 << i
)) {
2132 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2135 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2140 /* Success! Rewrite the instruction. */
2141 last_rhs_inst
->dst
.file
= dst
.file
;
2142 last_rhs_inst
->dst
.reg
= dst
.reg
;
2143 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2144 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2145 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2151 vec4_visitor::visit(ir_assignment
*ir
)
2153 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2154 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2156 if (!ir
->lhs
->type
->is_scalar() &&
2157 !ir
->lhs
->type
->is_vector()) {
2158 ir
->rhs
->accept(this);
2159 src_reg src
= this->result
;
2161 if (ir
->condition
) {
2162 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2165 /* emit_block_move doesn't account for swizzles in the source register.
2166 * This should be ok, since the source register is a structure or an
2167 * array, and those can't be swizzled. But double-check to be sure.
2169 assert(src
.swizzle
==
2170 (ir
->rhs
->type
->is_matrix()
2171 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2172 : BRW_SWIZZLE_NOOP
));
2174 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2178 /* Now we're down to just a scalar/vector with writemasks. */
2181 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2182 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2184 ir
->rhs
->accept(this);
2186 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2188 src_reg src
= this->result
;
2191 int first_enabled_chan
= 0;
2194 assert(ir
->lhs
->type
->is_vector() ||
2195 ir
->lhs
->type
->is_scalar());
2196 dst
.writemask
= ir
->write_mask
;
2198 for (int i
= 0; i
< 4; i
++) {
2199 if (dst
.writemask
& (1 << i
)) {
2200 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2205 /* Swizzle a small RHS vector into the channels being written.
2207 * glsl ir treats write_mask as dictating how many channels are
2208 * present on the RHS while in our instructions we need to make
2209 * those channels appear in the slots of the vec4 they're written to.
2211 for (int i
= 0; i
< 4; i
++) {
2212 if (dst
.writemask
& (1 << i
))
2213 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2215 swizzles
[i
] = first_enabled_chan
;
2217 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2218 swizzles
[2], swizzles
[3]);
2220 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2224 if (ir
->condition
) {
2225 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2228 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2229 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2230 inst
->predicate
= predicate
;
2238 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2240 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2241 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2242 emit_constant_values(dst
, field_value
);
2247 if (ir
->type
->is_array()) {
2248 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2249 emit_constant_values(dst
, ir
->array_elements
[i
]);
2254 if (ir
->type
->is_matrix()) {
2255 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2256 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2258 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2259 dst
->writemask
= 1 << j
;
2260 dst
->type
= BRW_REGISTER_TYPE_F
;
2262 emit(MOV(*dst
, src_reg(vec
[j
])));
2269 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2271 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2272 if (!(remaining_writemask
& (1 << i
)))
2275 dst
->writemask
= 1 << i
;
2276 dst
->type
= brw_type_for_base_type(ir
->type
);
2278 /* Find other components that match the one we're about to
2279 * write. Emits fewer instructions for things like vec4(0.5,
2282 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2283 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2284 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2285 dst
->writemask
|= (1 << j
);
2287 /* u, i, and f storage all line up, so no need for a
2288 * switch case for comparing each type.
2290 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2291 dst
->writemask
|= (1 << j
);
2295 switch (ir
->type
->base_type
) {
2296 case GLSL_TYPE_FLOAT
:
2297 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2300 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2302 case GLSL_TYPE_UINT
:
2303 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2305 case GLSL_TYPE_BOOL
:
2307 src_reg(ir
->value
.b
[i
] != 0 ? (int)ctx
->Const
.UniformBooleanTrue
2311 unreachable("Non-float/uint/int/bool constant");
2314 remaining_writemask
&= ~dst
->writemask
;
2320 vec4_visitor::visit(ir_constant
*ir
)
2322 dst_reg dst
= dst_reg(this, ir
->type
);
2323 this->result
= src_reg(dst
);
2325 emit_constant_values(&dst
, ir
);
2329 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2331 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2332 ir
->actual_parameters
.get_head());
2333 ir_variable
*location
= deref
->variable_referenced();
2334 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2335 location
->data
.binding
);
2337 /* Calculate the surface offset */
2338 src_reg
offset(this, glsl_type::uint_type
);
2339 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2341 deref_array
->array_index
->accept(this);
2343 src_reg
tmp(this, glsl_type::uint_type
);
2344 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2345 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2347 offset
= location
->data
.atomic
.offset
;
2350 /* Emit the appropriate machine instruction */
2351 const char *callee
= ir
->callee
->function_name();
2352 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2354 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2355 emit_untyped_surface_read(surf_index
, dst
, offset
);
2357 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2358 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2359 src_reg(), src_reg());
2361 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2362 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2363 src_reg(), src_reg());
2368 vec4_visitor::visit(ir_call
*ir
)
2370 const char *callee
= ir
->callee
->function_name();
2372 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2373 !strcmp("__intrinsic_atomic_increment", callee
) ||
2374 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2375 visit_atomic_counter_intrinsic(ir
);
2377 unreachable("Unsupported intrinsic.");
2382 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
)
2384 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
);
2387 inst
->dst
= dst_reg(this, glsl_type::uvec4_type
);
2388 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2390 inst
->src
[1] = sampler
;
2392 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2393 int param_base
= inst
->base_mrf
;
2394 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2395 int zero_mask
= 0xf & ~coord_mask
;
2397 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2400 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2404 return src_reg(inst
->dst
);
2408 is_high_sampler(struct brw_context
*brw
, src_reg sampler
)
2410 if (brw
->gen
< 8 && !brw
->is_haswell
)
2413 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2417 vec4_visitor::visit(ir_texture
*ir
)
2420 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2422 ir_rvalue
*nonconst_sampler_index
=
2423 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2425 /* Handle non-constant sampler array indexing */
2426 src_reg sampler_reg
;
2427 if (nonconst_sampler_index
) {
2428 /* The highest sampler which may be used by this operation is
2429 * the last element of the array. Mark it here, because the generator
2430 * doesn't have enough information to determine the bound.
2432 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2433 ->array
->type
->array_size();
2435 uint32_t max_used
= sampler
+ array_size
- 1;
2436 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
2437 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2439 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2442 brw_mark_surface_used(&prog_data
->base
, max_used
);
2444 /* Emit code to evaluate the actual indexing expression */
2445 nonconst_sampler_index
->accept(this);
2446 dst_reg
temp(this, glsl_type::uint_type
);
2447 emit(ADD(temp
, this->result
, src_reg(sampler
)))
2448 ->force_writemask_all
= true;
2449 sampler_reg
= src_reg(temp
);
2451 /* Single sampler, or constant array index; the indexing expression
2452 * is just an immediate.
2454 sampler_reg
= src_reg(sampler
);
2457 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2458 * emitting anything other than setting up the constant result.
2460 if (ir
->op
== ir_tg4
) {
2461 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2462 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2463 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2464 dst_reg
result(this, ir
->type
);
2465 this->result
= src_reg(result
);
2466 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2471 /* Should be lowered by do_lower_texture_projection */
2472 assert(!ir
->projector
);
2474 /* Should be lowered */
2475 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2477 /* Generate code to compute all the subexpression trees. This has to be
2478 * done before loading any values into MRFs for the sampler message since
2479 * generating these values may involve SEND messages that need the MRFs.
2482 if (ir
->coordinate
) {
2483 ir
->coordinate
->accept(this);
2484 coordinate
= this->result
;
2487 src_reg shadow_comparitor
;
2488 if (ir
->shadow_comparitor
) {
2489 ir
->shadow_comparitor
->accept(this);
2490 shadow_comparitor
= this->result
;
2493 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2494 src_reg offset_value
;
2495 if (has_nonconstant_offset
) {
2496 ir
->offset
->accept(this);
2497 offset_value
= src_reg(this->result
);
2500 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2501 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2504 lod
= src_reg(0.0f
);
2505 lod_type
= glsl_type::float_type
;
2510 ir
->lod_info
.lod
->accept(this);
2512 lod_type
= ir
->lod_info
.lod
->type
;
2514 case ir_query_levels
:
2516 lod_type
= glsl_type::int_type
;
2519 ir
->lod_info
.sample_index
->accept(this);
2520 sample_index
= this->result
;
2521 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2523 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2524 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
2529 ir
->lod_info
.grad
.dPdx
->accept(this);
2530 dPdx
= this->result
;
2532 ir
->lod_info
.grad
.dPdy
->accept(this);
2533 dPdy
= this->result
;
2535 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2545 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2546 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2547 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2548 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2549 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2550 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2551 case ir_tg4
: opcode
= has_nonconstant_offset
2552 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2553 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2555 unreachable("TXB is not valid for vertex shaders.");
2557 unreachable("LOD is not valid for vertex shaders.");
2559 unreachable("Unrecognized tex op");
2562 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(opcode
);
2564 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2566 brw_texture_offset(ctx
, ir
->offset
->as_constant()->value
.i
,
2567 ir
->offset
->type
->vector_elements
);
2570 /* Stuff the channel select bits in the top of the texture offset */
2571 if (ir
->op
== ir_tg4
)
2572 inst
->offset
|= gather_channel(ir
, sampler
) << 16;
2574 /* The message header is necessary for:
2576 * - Gen9+ for selecting SIMD4x2
2578 * - Gather channel selection
2579 * - Sampler indices too large to fit in a 4-bit value.
2581 inst
->header_present
=
2582 brw
->gen
< 5 || brw
->gen
>= 9 ||
2583 inst
->offset
!= 0 || ir
->op
== ir_tg4
||
2584 is_high_sampler(brw
, sampler_reg
);
2586 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2587 inst
->dst
= dst_reg(this, ir
->type
);
2588 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2589 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2591 inst
->src
[1] = sampler_reg
;
2593 /* MRF for the first parameter */
2594 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2596 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2597 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2598 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2600 /* Load the coordinate */
2601 /* FINISHME: gl_clamp_mask and saturate */
2602 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2603 int zero_mask
= 0xf & ~coord_mask
;
2605 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2608 if (zero_mask
!= 0) {
2609 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2612 /* Load the shadow comparitor */
2613 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2614 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2616 shadow_comparitor
));
2620 /* Load the LOD info */
2621 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2623 if (brw
->gen
>= 5) {
2624 mrf
= param_base
+ 1;
2625 if (ir
->shadow_comparitor
) {
2626 writemask
= WRITEMASK_Y
;
2627 /* mlen already incremented */
2629 writemask
= WRITEMASK_X
;
2632 } else /* brw->gen == 4 */ {
2634 writemask
= WRITEMASK_W
;
2636 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2637 } else if (ir
->op
== ir_txf
) {
2638 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2639 } else if (ir
->op
== ir_txf_ms
) {
2640 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2642 if (brw
->gen
>= 7) {
2643 /* MCS data is in the first channel of `mcs`, but we need to get it into
2644 * the .y channel of the second vec4 of params, so replicate .x across
2645 * the whole vec4 and then mask off everything except .y
2647 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2648 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2652 } else if (ir
->op
== ir_txd
) {
2653 const glsl_type
*type
= lod_type
;
2655 if (brw
->gen
>= 5) {
2656 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2657 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2658 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2659 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2662 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2663 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2664 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2665 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2666 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2669 if (ir
->shadow_comparitor
) {
2670 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2671 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2672 shadow_comparitor
));
2675 } else /* brw->gen == 4 */ {
2676 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2677 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2680 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2681 if (ir
->shadow_comparitor
) {
2682 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2683 shadow_comparitor
));
2686 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2694 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2695 * spec requires layers.
2697 if (ir
->op
== ir_txs
) {
2698 glsl_type
const *type
= ir
->sampler
->type
;
2699 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2700 type
->sampler_array
) {
2701 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2702 writemask(inst
->dst
, WRITEMASK_Z
),
2703 src_reg(inst
->dst
), src_reg(6));
2707 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2708 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2711 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2715 * Apply workarounds for Gen6 gather with UINT/SINT
2718 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2723 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2724 dst_reg dst_f
= dst
;
2725 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2727 /* Convert from UNORM to UINT */
2728 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2729 emit(MOV(dst
, src_reg(dst_f
)));
2732 /* Reinterpret the UINT value as a signed INT value by
2733 * shifting the sign bit into place, then shifting back
2736 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2737 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2742 * Set up the gather channel based on the swizzle, for gather4.
2745 vec4_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2747 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2748 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2750 case SWIZZLE_X
: return 0;
2752 /* gather4 sampler is broken for green channel on RG32F --
2753 * we must ask for blue instead.
2755 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2758 case SWIZZLE_Z
: return 2;
2759 case SWIZZLE_W
: return 3;
2761 unreachable("Not reached"); /* zero, one swizzles handled already */
2766 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
)
2768 int s
= key
->tex
.swizzles
[sampler
];
2770 this->result
= src_reg(this, ir
->type
);
2771 dst_reg
swizzled_result(this->result
);
2773 if (ir
->op
== ir_query_levels
) {
2774 /* # levels is in .w */
2775 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2776 emit(MOV(swizzled_result
, orig_val
));
2780 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2781 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2782 emit(MOV(swizzled_result
, orig_val
));
2787 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2788 int swizzle
[4] = {0};
2790 for (int i
= 0; i
< 4; i
++) {
2791 switch (GET_SWZ(s
, i
)) {
2793 zero_mask
|= (1 << i
);
2796 one_mask
|= (1 << i
);
2799 copy_mask
|= (1 << i
);
2800 swizzle
[i
] = GET_SWZ(s
, i
);
2806 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2807 swizzled_result
.writemask
= copy_mask
;
2808 emit(MOV(swizzled_result
, orig_val
));
2812 swizzled_result
.writemask
= zero_mask
;
2813 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2817 swizzled_result
.writemask
= one_mask
;
2818 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2823 vec4_visitor::visit(ir_return
*)
2825 unreachable("not reached");
2829 vec4_visitor::visit(ir_discard
*)
2831 unreachable("not reached");
2835 vec4_visitor::visit(ir_if
*ir
)
2837 /* Don't point the annotation at the if statement, because then it plus
2838 * the then and else blocks get printed.
2840 this->base_ir
= ir
->condition
;
2842 if (brw
->gen
== 6) {
2845 enum brw_predicate predicate
;
2846 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2847 emit(IF(predicate
));
2850 visit_instructions(&ir
->then_instructions
);
2852 if (!ir
->else_instructions
.is_empty()) {
2853 this->base_ir
= ir
->condition
;
2854 emit(BRW_OPCODE_ELSE
);
2856 visit_instructions(&ir
->else_instructions
);
2859 this->base_ir
= ir
->condition
;
2860 emit(BRW_OPCODE_ENDIF
);
2864 vec4_visitor::visit(ir_emit_vertex
*)
2866 unreachable("not reached");
2870 vec4_visitor::visit(ir_end_primitive
*)
2872 unreachable("not reached");
2876 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2877 dst_reg dst
, src_reg offset
,
2878 src_reg src0
, src_reg src1
)
2882 /* Set the atomic operation offset. */
2883 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2886 /* Set the atomic operation arguments. */
2887 if (src0
.file
!= BAD_FILE
) {
2888 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2892 if (src1
.file
!= BAD_FILE
) {
2893 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2897 /* Emit the instruction. Note that this maps to the normal SIMD8
2898 * untyped atomic message on Ivy Bridge, but that's OK because
2899 * unused channels will be masked out.
2901 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2902 src_reg(atomic_op
), src_reg(surf_index
));
2908 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
2911 /* Set the surface read offset. */
2912 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
2914 /* Emit the instruction. Note that this maps to the normal SIMD8
2915 * untyped surface read message, but that's OK because unused
2916 * channels will be masked out.
2918 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
,
2919 dst
, src_reg(surf_index
));
2925 vec4_visitor::emit_ndc_computation()
2927 /* Get the position */
2928 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2930 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2931 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2932 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2934 current_annotation
= "NDC";
2935 dst_reg ndc_w
= ndc
;
2936 ndc_w
.writemask
= WRITEMASK_W
;
2937 src_reg pos_w
= pos
;
2938 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2939 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2941 dst_reg ndc_xyz
= ndc
;
2942 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2944 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2948 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
2951 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2952 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2953 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2954 dst_reg header1_w
= header1
;
2955 header1_w
.writemask
= WRITEMASK_W
;
2957 emit(MOV(header1
, 0u));
2959 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2960 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2962 current_annotation
= "Point size";
2963 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2964 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2967 if (key
->userclip_active
) {
2968 current_annotation
= "Clipping flags";
2969 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
2970 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
2972 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2973 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
2974 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
2976 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2977 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
2978 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
2979 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
2982 /* i965 clipping workaround:
2983 * 1) Test for -ve rhw
2985 * set ndc = (0,0,0,0)
2988 * Later, clipping will detect ucp[6] and ensure the primitive is
2989 * clipped against all fixed planes.
2991 if (brw
->has_negative_rhw_bug
) {
2992 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2993 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2994 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2995 vec4_instruction
*inst
;
2996 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2997 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2998 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
2999 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3002 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
3003 } else if (brw
->gen
< 6) {
3004 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
3006 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
3007 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3008 dst_reg reg_w
= reg
;
3009 reg_w
.writemask
= WRITEMASK_W
;
3010 emit(MOV(reg_w
, src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
3012 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
3013 dst_reg reg_y
= reg
;
3014 reg_y
.writemask
= WRITEMASK_Y
;
3015 reg_y
.type
= BRW_REGISTER_TYPE_D
;
3016 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
3018 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
3019 dst_reg reg_z
= reg
;
3020 reg_z
.writemask
= WRITEMASK_Z
;
3021 reg_z
.type
= BRW_REGISTER_TYPE_D
;
3022 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
3028 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
3030 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3032 * "If a linked set of shaders forming the vertex stage contains no
3033 * static write to gl_ClipVertex or gl_ClipDistance, but the
3034 * application has requested clipping against user clip planes through
3035 * the API, then the coordinate written to gl_Position is used for
3036 * comparison against the user clip planes."
3038 * This function is only called if the shader didn't write to
3039 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3040 * if the user wrote to it; otherwise we use gl_Position.
3042 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3043 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
3044 clip_vertex
= VARYING_SLOT_POS
;
3047 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
3049 reg
.writemask
= 1 << i
;
3051 src_reg(output_reg
[clip_vertex
]),
3052 src_reg(this->userplane
[i
+ offset
])));
3057 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
3059 assert (varying
< VARYING_SLOT_MAX
);
3060 reg
.type
= output_reg
[varying
].type
;
3061 current_annotation
= output_reg_annotation
[varying
];
3062 /* Copy the register, saturating if necessary */
3063 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
3067 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
3069 reg
.type
= BRW_REGISTER_TYPE_F
;
3072 case VARYING_SLOT_PSIZ
:
3074 /* PSIZ is always in slot 0, and is coupled with other flags. */
3075 current_annotation
= "indices, point width, clip flags";
3076 emit_psiz_and_flags(reg
);
3079 case BRW_VARYING_SLOT_NDC
:
3080 current_annotation
= "NDC";
3081 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
3083 case VARYING_SLOT_POS
:
3084 current_annotation
= "gl_Position";
3085 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
3087 case VARYING_SLOT_EDGE
:
3088 /* This is present when doing unfilled polygons. We're supposed to copy
3089 * the edge flag from the user-provided vertex array
3090 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3091 * of that attribute (starts as 1.0f). This is then used in clipping to
3092 * determine which edges should be drawn as wireframe.
3094 current_annotation
= "edge flag";
3095 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3096 glsl_type::float_type
, WRITEMASK_XYZW
))));
3098 case BRW_VARYING_SLOT_PAD
:
3099 /* No need to write to this slot */
3101 case VARYING_SLOT_COL0
:
3102 case VARYING_SLOT_COL1
:
3103 case VARYING_SLOT_BFC0
:
3104 case VARYING_SLOT_BFC1
: {
3105 /* These built-in varyings are only supported in compatibility mode,
3106 * and we only support GS in core profile. So, this must be a vertex
3109 assert(stage
== MESA_SHADER_VERTEX
);
3110 vec4_instruction
*inst
= emit_generic_urb_slot(reg
, varying
);
3111 if (((struct brw_vs_prog_key
*) key
)->clamp_vertex_color
)
3112 inst
->saturate
= true;
3117 emit_generic_urb_slot(reg
, varying
);
3123 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
3125 if (brw
->gen
>= 6) {
3126 /* URB data written (does not include the message header reg) must
3127 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3128 * section 5.4.3.2.2: URB_INTERLEAVED.
3130 * URB entries are allocated on a multiple of 1024 bits, so an
3131 * extra 128 bits written here to make the end align to 256 is
3134 if ((mlen
% 2) != 1)
3143 * Generates the VUE payload plus the necessary URB write instructions to
3146 * The VUE layout is documented in Volume 2a.
3149 vec4_visitor::emit_vertex()
3151 /* MRF 0 is reserved for the debugger, so start with message header
3156 /* In the process of generating our URB write message contents, we
3157 * may need to unspill a register or load from an array. Those
3158 * reads would use MRFs 14-15.
3160 int max_usable_mrf
= 13;
3162 /* The following assertion verifies that max_usable_mrf causes an
3163 * even-numbered amount of URB write data, which will meet gen6's
3164 * requirements for length alignment.
3166 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3168 /* First mrf is the g0-based message header containing URB handles and
3171 emit_urb_write_header(mrf
++);
3174 emit_ndc_computation();
3177 /* Lower legacy ff and ClipVertex clipping to clip distances */
3178 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3179 current_annotation
= "user clip distances";
3181 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3182 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3184 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3185 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3188 /* We may need to split this up into several URB writes, so do them in a
3192 bool complete
= false;
3194 /* URB offset is in URB row increments, and each of our MRFs is half of
3195 * one of those, since we're doing interleaved writes.
3197 int offset
= slot
/ 2;
3200 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3201 emit_urb_slot(dst_reg(MRF
, mrf
++),
3202 prog_data
->vue_map
.slot_to_varying
[slot
]);
3204 /* If this was max_usable_mrf, we can't fit anything more into this
3207 if (mrf
> max_usable_mrf
) {
3213 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3214 current_annotation
= "URB write";
3215 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3216 inst
->base_mrf
= base_mrf
;
3217 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
3218 inst
->offset
+= offset
;
3224 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3225 src_reg
*reladdr
, int reg_offset
)
3227 /* Because we store the values to scratch interleaved like our
3228 * vertex data, we need to scale the vec4 index by 2.
3230 int message_header_scale
= 2;
3232 /* Pre-gen6, the message header uses byte offsets instead of vec4
3233 * (16-byte) offset units.
3236 message_header_scale
*= 16;
3239 src_reg index
= src_reg(this, glsl_type::int_type
);
3241 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3242 src_reg(reg_offset
)));
3243 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3244 src_reg(message_header_scale
)));
3248 return src_reg(reg_offset
* message_header_scale
);
3253 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3254 src_reg
*reladdr
, int reg_offset
)
3257 src_reg index
= src_reg(this, glsl_type::int_type
);
3259 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3260 src_reg(reg_offset
)));
3262 /* Pre-gen6, the message header uses byte offsets instead of vec4
3263 * (16-byte) offset units.
3266 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3270 } else if (brw
->gen
>= 8) {
3271 /* Store the offset in a GRF so we can send-from-GRF. */
3272 src_reg offset
= src_reg(this, glsl_type::int_type
);
3273 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3276 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
3277 return src_reg(reg_offset
* message_header_scale
);
3282 * Emits an instruction before @inst to load the value named by @orig_src
3283 * from scratch space at @base_offset to @temp.
3285 * @base_offset is measured in 32-byte units (the size of a register).
3288 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3289 dst_reg temp
, src_reg orig_src
,
3292 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3293 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3296 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3300 * Emits an instruction after @inst to store the value to be written
3301 * to @orig_dst to scratch space at @base_offset, from @temp.
3303 * @base_offset is measured in 32-byte units (the size of a register).
3306 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3309 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3310 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3313 /* Create a temporary register to store *inst's result in.
3315 * We have to be careful in MOVing from our temporary result register in
3316 * the scratch write. If we swizzle from channels of the temporary that
3317 * weren't initialized, it will confuse live interval analysis, which will
3318 * make spilling fail to make progress.
3320 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
3321 temp
.type
= inst
->dst
.type
;
3322 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
3324 for (int i
= 0; i
< 4; i
++)
3325 if (inst
->dst
.writemask
& (1 << i
))
3328 swizzles
[i
] = first_writemask_chan
;
3329 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3330 swizzles
[2], swizzles
[3]);
3332 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3333 inst
->dst
.writemask
));
3334 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3335 write
->predicate
= inst
->predicate
;
3336 write
->ir
= inst
->ir
;
3337 write
->annotation
= inst
->annotation
;
3338 inst
->insert_after(block
, write
);
3340 inst
->dst
.file
= temp
.file
;
3341 inst
->dst
.reg
= temp
.reg
;
3342 inst
->dst
.reg_offset
= temp
.reg_offset
;
3343 inst
->dst
.reladdr
= NULL
;
3347 * We can't generally support array access in GRF space, because a
3348 * single instruction's destination can only span 2 contiguous
3349 * registers. So, we send all GRF arrays that get variable index
3350 * access to scratch space.
3353 vec4_visitor::move_grf_array_access_to_scratch()
3355 int scratch_loc
[this->alloc
.count
];
3356 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3358 /* First, calculate the set of virtual GRFs that need to be punted
3359 * to scratch due to having any array access on them, and where in
3362 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3363 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3364 scratch_loc
[inst
->dst
.reg
] == -1) {
3365 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3366 c
->last_scratch
+= this->alloc
.sizes
[inst
->dst
.reg
];
3369 for (int i
= 0 ; i
< 3; i
++) {
3370 src_reg
*src
= &inst
->src
[i
];
3372 if (src
->file
== GRF
&& src
->reladdr
&&
3373 scratch_loc
[src
->reg
] == -1) {
3374 scratch_loc
[src
->reg
] = c
->last_scratch
;
3375 c
->last_scratch
+= this->alloc
.sizes
[src
->reg
];
3380 /* Now, for anything that will be accessed through scratch, rewrite
3381 * it to load/store. Note that this is a _safe list walk, because
3382 * we may generate a new scratch_write instruction after the one
3385 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3386 /* Set up the annotation tracking for new generated instructions. */
3388 current_annotation
= inst
->annotation
;
3390 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3391 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3394 for (int i
= 0 ; i
< 3; i
++) {
3395 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3398 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3400 emit_scratch_read(block
, inst
, temp
, inst
->src
[i
],
3401 scratch_loc
[inst
->src
[i
].reg
]);
3403 inst
->src
[i
].file
= temp
.file
;
3404 inst
->src
[i
].reg
= temp
.reg
;
3405 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3406 inst
->src
[i
].reladdr
= NULL
;
3412 * Emits an instruction before @inst to load the value named by @orig_src
3413 * from the pull constant buffer (surface) at @base_offset to @temp.
3416 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3417 dst_reg temp
, src_reg orig_src
,
3420 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3421 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3422 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3424 vec4_instruction
*load
;
3426 if (brw
->gen
>= 7) {
3427 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3428 grf_offset
.type
= offset
.type
;
3429 emit_before(block
, inst
, MOV(grf_offset
, offset
));
3431 load
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3432 temp
, index
, src_reg(grf_offset
));
3434 load
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
3435 temp
, index
, offset
);
3436 load
->base_mrf
= 14;
3439 emit_before(block
, inst
, load
);
3443 * Implements array access of uniforms by inserting a
3444 * PULL_CONSTANT_LOAD instruction.
3446 * Unlike temporary GRF array access (where we don't support it due to
3447 * the difficulty of doing relative addressing on instruction
3448 * destinations), we could potentially do array access of uniforms
3449 * that were loaded in GRF space as push constants. In real-world
3450 * usage we've seen, though, the arrays being used are always larger
3451 * than we could load as push constants, so just always move all
3452 * uniform array access out to a pull constant buffer.
3455 vec4_visitor::move_uniform_array_access_to_pull_constants()
3457 int pull_constant_loc
[this->uniforms
];
3458 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3459 bool nested_reladdr
;
3461 /* Walk through and find array access of uniforms. Put a copy of that
3462 * uniform in the pull constant buffer.
3464 * Note that we don't move constant-indexed accesses to arrays. No
3465 * testing has been done of the performance impact of this choice.
3468 nested_reladdr
= false;
3470 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3471 for (int i
= 0 ; i
< 3; i
++) {
3472 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3475 int uniform
= inst
->src
[i
].reg
;
3477 if (inst
->src
[i
].reladdr
->reladdr
)
3478 nested_reladdr
= true; /* will need another pass */
3480 /* If this array isn't already present in the pull constant buffer,
3483 if (pull_constant_loc
[uniform
] == -1) {
3484 const gl_constant_value
**values
=
3485 &stage_prog_data
->param
[uniform
* 4];
3487 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3489 assert(uniform
< uniform_array_size
);
3490 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3491 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3496 /* Set up the annotation tracking for new generated instructions. */
3498 current_annotation
= inst
->annotation
;
3500 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3502 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3503 pull_constant_loc
[uniform
]);
3505 inst
->src
[i
].file
= temp
.file
;
3506 inst
->src
[i
].reg
= temp
.reg
;
3507 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3508 inst
->src
[i
].reladdr
= NULL
;
3511 } while (nested_reladdr
);
3513 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3514 * no need to track them as larger-than-vec4 objects. This will be
3515 * relied on in cutting out unused uniform vectors from push
3518 split_uniform_registers();
3522 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3524 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3528 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3529 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3534 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3536 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3537 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3540 vec4_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, src_reg
*reg
)
3542 assert(brw
->gen
<= 5);
3544 if (!rvalue
->type
->is_boolean())
3547 src_reg and_result
= src_reg(this, rvalue
->type
);
3548 src_reg neg_result
= src_reg(this, rvalue
->type
);
3549 emit(AND(dst_reg(and_result
), *reg
, src_reg(1)));
3550 emit(MOV(dst_reg(neg_result
), negate(and_result
)));
3554 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3555 struct brw_vec4_compile
*c
,
3556 struct gl_program
*prog
,
3557 const struct brw_vue_prog_key
*key
,
3558 struct brw_vue_prog_data
*prog_data
,
3559 struct gl_shader_program
*shader_prog
,
3560 gl_shader_stage stage
,
3564 shader_time_shader_type st_base
,
3565 shader_time_shader_type st_written
,
3566 shader_time_shader_type st_reset
)
3567 : backend_visitor(brw
, shader_prog
, prog
, &prog_data
->base
, stage
),
3570 prog_data(prog_data
),
3571 sanity_param_count(0),
3573 first_non_payload_grf(0),
3574 need_all_constants_in_pull_buffer(false),
3575 debug_flag(debug_flag
),
3576 no_spills(no_spills
),
3578 st_written(st_written
),
3581 this->mem_ctx
= mem_ctx
;
3582 this->failed
= false;
3584 this->base_ir
= NULL
;
3585 this->current_annotation
= NULL
;
3586 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3588 this->variable_ht
= hash_table_ctor(0,
3589 hash_table_pointer_hash
,
3590 hash_table_pointer_compare
);
3592 this->virtual_grf_start
= NULL
;
3593 this->virtual_grf_end
= NULL
;
3594 this->live_intervals
= NULL
;
3596 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3600 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3601 * at least one. See setup_uniforms() in brw_vec4.cpp.
3603 this->uniform_array_size
= 1;
3605 this->uniform_array_size
= MAX2(stage_prog_data
->nr_params
, 1);
3608 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3609 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3612 vec4_visitor::~vec4_visitor()
3614 hash_table_dtor(this->variable_ht
);
3619 vec4_visitor::fail(const char *format
, ...)
3629 va_start(va
, format
);
3630 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3632 msg
= ralloc_asprintf(mem_ctx
, "vec4 compile failed: %s\n", msg
);
3634 this->fail_msg
= msg
;
3637 fprintf(stderr
, "%s", msg
);
3641 } /* namespace brw */