2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
32 src_reg::src_reg(dst_reg reg
)
36 this->file
= reg
.file
;
38 this->reg_offset
= reg
.reg_offset
;
39 this->type
= reg
.type
;
40 this->reladdr
= reg
.reladdr
;
41 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
47 for (int i
= 0; i
< 4; i
++) {
48 if (!(reg
.writemask
& (1 << i
)))
51 swizzles
[next_chan
++] = last
= i
;
54 for (; next_chan
< 4; next_chan
++) {
55 swizzles
[next_chan
] = last
;
58 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
59 swizzles
[2], swizzles
[3]);
62 dst_reg::dst_reg(src_reg reg
)
66 this->file
= reg
.file
;
68 this->reg_offset
= reg
.reg_offset
;
69 this->type
= reg
.type
;
70 this->writemask
= WRITEMASK_XYZW
;
71 this->reladdr
= reg
.reladdr
;
72 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
76 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
77 src_reg src0
, src_reg src1
, src_reg src2
)
79 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction();
81 inst
->opcode
= opcode
;
86 inst
->ir
= this->base_ir
;
87 inst
->annotation
= this->current_annotation
;
89 this->instructions
.push_tail(inst
);
96 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
98 return emit(opcode
, dst
, src0
, src1
, src_reg());
102 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
104 assert(dst
.writemask
!= 0);
105 return emit(opcode
, dst
, src0
, src_reg(), src_reg());
109 vec4_visitor::emit(enum opcode opcode
)
111 return emit(opcode
, dst_reg(), src_reg(), src_reg(), src_reg());
115 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
117 static enum opcode dot_opcodes
[] = {
118 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
121 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
125 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
127 /* The gen6 math instruction ignores the source modifiers --
128 * swizzle, abs, negate, and at least some parts of the register
129 * region description.
131 src_reg temp_src
= src_reg(this, glsl_type::vec4_type
);
132 emit(BRW_OPCODE_MOV
, dst_reg(temp_src
), src
);
134 if (dst
.writemask
!= WRITEMASK_XYZW
) {
135 /* The gen6 math instruction must be align1, so we can't do
138 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
140 emit(opcode
, temp_dst
, temp_src
);
142 emit(BRW_OPCODE_MOV
, dst
, src_reg(temp_dst
));
144 emit(opcode
, dst
, temp_src
);
149 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
151 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
157 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
160 case SHADER_OPCODE_RCP
:
161 case SHADER_OPCODE_RSQ
:
162 case SHADER_OPCODE_SQRT
:
163 case SHADER_OPCODE_EXP2
:
164 case SHADER_OPCODE_LOG2
:
165 case SHADER_OPCODE_SIN
:
166 case SHADER_OPCODE_COS
:
169 assert(!"not reached: bad math opcode");
173 if (intel
->gen
>= 6) {
174 return emit_math1_gen6(opcode
, dst
, src
);
176 return emit_math1_gen4(opcode
, dst
, src
);
181 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
182 dst_reg dst
, src_reg src0
, src_reg src1
)
186 /* The gen6 math instruction ignores the source modifiers --
187 * swizzle, abs, negate, and at least some parts of the register
188 * region description. Move the sources to temporaries to make it
192 expanded
= src_reg(this, glsl_type::vec4_type
);
193 emit(BRW_OPCODE_MOV
, dst_reg(expanded
), src0
);
196 expanded
= src_reg(this, glsl_type::vec4_type
);
197 emit(BRW_OPCODE_MOV
, dst_reg(expanded
), src1
);
200 if (dst
.writemask
!= WRITEMASK_XYZW
) {
201 /* The gen6 math instruction must be align1, so we can't do
204 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
206 emit(opcode
, temp_dst
, src0
, src1
);
208 emit(BRW_OPCODE_MOV
, dst
, src_reg(temp_dst
));
210 emit(opcode
, dst
, src0
, src1
);
215 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
216 dst_reg dst
, src_reg src0
, src_reg src1
)
218 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
224 vec4_visitor::emit_math(enum opcode opcode
,
225 dst_reg dst
, src_reg src0
, src_reg src1
)
227 assert(opcode
== SHADER_OPCODE_POW
);
229 if (intel
->gen
>= 6) {
230 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
232 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
237 vec4_visitor::visit_instructions(const exec_list
*list
)
239 foreach_list(node
, list
) {
240 ir_instruction
*ir
= (ir_instruction
*)node
;
249 type_size(const struct glsl_type
*type
)
254 switch (type
->base_type
) {
257 case GLSL_TYPE_FLOAT
:
259 if (type
->is_matrix()) {
260 return type
->matrix_columns
;
262 /* Regardless of size of vector, it gets a vec4. This is bad
263 * packing for things like floats, but otherwise arrays become a
264 * mess. Hopefully a later pass over the code can pack scalars
265 * down if appropriate.
269 case GLSL_TYPE_ARRAY
:
270 assert(type
->length
> 0);
271 return type_size(type
->fields
.array
) * type
->length
;
272 case GLSL_TYPE_STRUCT
:
274 for (i
= 0; i
< type
->length
; i
++) {
275 size
+= type_size(type
->fields
.structure
[i
].type
);
278 case GLSL_TYPE_SAMPLER
:
279 /* Samplers take up one slot in UNIFORMS[], but they're baked in
290 vec4_visitor::virtual_grf_alloc(int size
)
292 if (virtual_grf_array_size
<= virtual_grf_count
) {
293 if (virtual_grf_array_size
== 0)
294 virtual_grf_array_size
= 16;
296 virtual_grf_array_size
*= 2;
297 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
298 virtual_grf_array_size
);
300 virtual_grf_sizes
[virtual_grf_count
] = size
;
301 return virtual_grf_count
++;
304 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
309 this->reg
= v
->virtual_grf_alloc(type_size(type
));
311 if (type
->is_array() || type
->is_record()) {
312 this->swizzle
= BRW_SWIZZLE_NOOP
;
314 this->swizzle
= swizzle_for_size(type
->vector_elements
);
317 this->type
= brw_type_for_base_type(type
);
320 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
325 this->reg
= v
->virtual_grf_alloc(type_size(type
));
327 if (type
->is_array() || type
->is_record()) {
328 this->writemask
= WRITEMASK_XYZW
;
330 this->writemask
= (1 << type
->vector_elements
) - 1;
333 this->type
= brw_type_for_base_type(type
);
336 /* Our support for uniforms is piggy-backed on the struct
337 * gl_fragment_program, because that's where the values actually
338 * get stored, rather than in some global gl_shader_program uniform
342 vec4_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
344 unsigned int offset
= 0;
345 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[loc
][0].f
;
347 if (type
->is_matrix()) {
348 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
349 type
->vector_elements
,
352 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
353 offset
+= setup_uniform_values(loc
+ offset
, column
);
359 switch (type
->base_type
) {
360 case GLSL_TYPE_FLOAT
:
364 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
365 int slot
= this->uniforms
* 4 + i
;
366 switch (type
->base_type
) {
367 case GLSL_TYPE_FLOAT
:
368 c
->prog_data
.param_convert
[slot
] = PARAM_NO_CONVERT
;
371 c
->prog_data
.param_convert
[slot
] = PARAM_CONVERT_F2U
;
374 c
->prog_data
.param_convert
[slot
] = PARAM_CONVERT_F2I
;
377 c
->prog_data
.param_convert
[slot
] = PARAM_CONVERT_F2B
;
380 assert(!"not reached");
381 c
->prog_data
.param_convert
[slot
] = PARAM_NO_CONVERT
;
384 c
->prog_data
.param
[slot
] = &values
[i
];
387 for (unsigned int i
= type
->vector_elements
; i
< 4; i
++) {
388 c
->prog_data
.param_convert
[this->uniforms
* 4 + i
] =
390 c
->prog_data
.param
[this->uniforms
* 4 + i
] = NULL
;
393 this->uniform_size
[this->uniforms
] = type
->vector_elements
;
398 case GLSL_TYPE_STRUCT
:
399 for (unsigned int i
= 0; i
< type
->length
; i
++) {
400 offset
+= setup_uniform_values(loc
+ offset
,
401 type
->fields
.structure
[i
].type
);
405 case GLSL_TYPE_ARRAY
:
406 for (unsigned int i
= 0; i
< type
->length
; i
++) {
407 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
411 case GLSL_TYPE_SAMPLER
:
412 /* The sampler takes up a slot, but we don't use any values from it. */
416 assert(!"not reached");
421 /* Our support for builtin uniforms is even scarier than non-builtin.
422 * It sits on top of the PROG_STATE_VAR parameters that are
423 * automatically updated from GL context state.
426 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
428 const ir_state_slot
*const slots
= ir
->state_slots
;
429 assert(ir
->state_slots
!= NULL
);
431 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
432 /* This state reference has already been setup by ir_to_mesa,
433 * but we'll get the same index back here. We can reference
434 * ParameterValues directly, since unlike brw_fs.cpp, we never
435 * add new state references during compile.
437 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
438 (gl_state_index
*)slots
[i
].tokens
);
439 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
441 this->uniform_size
[this->uniforms
] = 0;
442 /* Add each of the unique swizzled channels of the element.
443 * This will end up matching the size of the glsl_type of this field.
446 for (unsigned int j
= 0; j
< 4; j
++) {
447 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
450 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
451 c
->prog_data
.param_convert
[this->uniforms
* 4 + j
] = PARAM_NO_CONVERT
;
452 if (swiz
<= last_swiz
)
453 this->uniform_size
[this->uniforms
]++;
460 vec4_visitor::variable_storage(ir_variable
*var
)
462 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
466 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
468 ir_expression
*expr
= ir
->as_expression();
472 vec4_instruction
*inst
;
474 assert(expr
->get_num_operands() <= 2);
475 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
476 assert(expr
->operands
[i
]->type
->is_scalar());
478 expr
->operands
[i
]->accept(this);
479 op
[i
] = this->result
;
482 switch (expr
->operation
) {
483 case ir_unop_logic_not
:
484 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], src_reg(1));
485 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
488 case ir_binop_logic_xor
:
489 inst
= emit(BRW_OPCODE_XOR
, dst_null_d(), op
[0], op
[1]);
490 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
493 case ir_binop_logic_or
:
494 inst
= emit(BRW_OPCODE_OR
, dst_null_d(), op
[0], op
[1]);
495 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
498 case ir_binop_logic_and
:
499 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], op
[1]);
500 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
504 if (intel
->gen
>= 6) {
505 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0.0f
));
507 inst
= emit(BRW_OPCODE_MOV
, dst_null_f(), op
[0]);
509 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
513 if (intel
->gen
>= 6) {
514 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
516 inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), op
[0]);
518 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
521 case ir_binop_greater
:
522 case ir_binop_gequal
:
524 case ir_binop_lequal
:
526 case ir_binop_all_equal
:
527 case ir_binop_nequal
:
528 case ir_binop_any_nequal
:
529 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
530 inst
->conditional_mod
=
531 brw_conditional_for_comparison(expr
->operation
);
535 assert(!"not reached");
543 if (intel
->gen
>= 6) {
544 vec4_instruction
*inst
= emit(BRW_OPCODE_AND
, dst_null_d(),
545 this->result
, src_reg(1));
546 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
548 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), this->result
);
549 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
554 * Emit a gen6 IF statement with the comparison folded into the IF
558 vec4_visitor::emit_if_gen6(ir_if
*ir
)
560 ir_expression
*expr
= ir
->condition
->as_expression();
564 vec4_instruction
*inst
;
567 assert(expr
->get_num_operands() <= 2);
568 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
569 expr
->operands
[i
]->accept(this);
570 op
[i
] = this->result
;
573 switch (expr
->operation
) {
574 case ir_unop_logic_not
:
575 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
576 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
579 case ir_binop_logic_xor
:
580 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
581 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
584 case ir_binop_logic_or
:
585 temp
= dst_reg(this, glsl_type::bool_type
);
586 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
587 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
588 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
591 case ir_binop_logic_and
:
592 temp
= dst_reg(this, glsl_type::bool_type
);
593 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
594 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
595 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
599 inst
= emit(BRW_OPCODE_IF
, dst_null_f(), op
[0], src_reg(0));
600 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
604 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
605 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
608 case ir_binop_greater
:
609 case ir_binop_gequal
:
611 case ir_binop_lequal
:
613 case ir_binop_nequal
:
614 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
615 inst
->conditional_mod
=
616 brw_conditional_for_comparison(expr
->operation
);
619 case ir_binop_all_equal
:
620 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
621 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
623 inst
= emit(BRW_OPCODE_IF
);
624 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
627 case ir_binop_any_nequal
:
628 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
629 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
631 inst
= emit(BRW_OPCODE_IF
);
632 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
636 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
637 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
639 inst
= emit(BRW_OPCODE_IF
);
640 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
644 assert(!"not reached");
645 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
646 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
652 ir
->condition
->accept(this);
654 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
, dst_null_d(),
655 this->result
, src_reg(0));
656 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
660 vec4_visitor::visit(ir_variable
*ir
)
664 if (variable_storage(ir
))
669 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
673 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
675 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
676 output_reg
[ir
->location
+ i
] = *reg
;
677 output_reg
[ir
->location
+ i
].reg_offset
= i
;
678 output_reg
[ir
->location
+ i
].type
= BRW_REGISTER_TYPE_F
;
683 case ir_var_temporary
:
684 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
688 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
690 if (!strncmp(ir
->name
, "gl_", 3)) {
691 setup_builtin_uniform_values(ir
);
693 setup_uniform_values(ir
->location
, ir
->type
);
698 assert(!"not reached");
701 reg
->type
= brw_type_for_base_type(ir
->type
);
702 hash_table_insert(this->variable_ht
, reg
, ir
);
706 vec4_visitor::visit(ir_loop
*ir
)
710 /* We don't want debugging output to print the whole body of the
711 * loop as the annotation.
713 this->base_ir
= NULL
;
715 if (ir
->counter
!= NULL
) {
716 this->base_ir
= ir
->counter
;
717 ir
->counter
->accept(this);
718 counter
= *(variable_storage(ir
->counter
));
720 if (ir
->from
!= NULL
) {
721 this->base_ir
= ir
->from
;
722 ir
->from
->accept(this);
724 emit(BRW_OPCODE_MOV
, counter
, this->result
);
731 this->base_ir
= ir
->to
;
732 ir
->to
->accept(this);
734 vec4_instruction
*inst
= emit(BRW_OPCODE_CMP
, dst_null_d(),
735 src_reg(counter
), this->result
);
736 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
738 inst
= emit(BRW_OPCODE_BREAK
);
739 inst
->predicate
= BRW_PREDICATE_NORMAL
;
742 visit_instructions(&ir
->body_instructions
);
746 this->base_ir
= ir
->increment
;
747 ir
->increment
->accept(this);
748 emit(BRW_OPCODE_ADD
, counter
, src_reg(counter
), this->result
);
751 emit(BRW_OPCODE_WHILE
);
755 vec4_visitor::visit(ir_loop_jump
*ir
)
758 case ir_loop_jump::jump_break
:
759 emit(BRW_OPCODE_BREAK
);
761 case ir_loop_jump::jump_continue
:
762 emit(BRW_OPCODE_CONTINUE
);
769 vec4_visitor::visit(ir_function_signature
*ir
)
776 vec4_visitor::visit(ir_function
*ir
)
778 /* Ignore function bodies other than main() -- we shouldn't see calls to
779 * them since they should all be inlined.
781 if (strcmp(ir
->name
, "main") == 0) {
782 const ir_function_signature
*sig
;
785 sig
= ir
->matching_signature(&empty
);
789 visit_instructions(&sig
->body
);
794 vec4_visitor::try_emit_sat(ir_expression
*ir
)
796 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
800 sat_src
->accept(this);
801 src_reg src
= this->result
;
803 this->result
= src_reg(this, ir
->type
);
804 vec4_instruction
*inst
;
805 inst
= emit(BRW_OPCODE_MOV
, dst_reg(this->result
), src
);
806 inst
->saturate
= true;
812 vec4_visitor::emit_bool_comparison(unsigned int op
,
813 dst_reg dst
, src_reg src0
, src_reg src1
)
815 /* original gen4 does destination conversion before comparison. */
817 dst
.type
= src0
.type
;
819 vec4_instruction
*inst
= emit(BRW_OPCODE_CMP
, dst
, src0
, src1
);
820 inst
->conditional_mod
= brw_conditional_for_comparison(op
);
822 dst
.type
= BRW_REGISTER_TYPE_D
;
823 emit(BRW_OPCODE_AND
, dst
, src_reg(dst
), src_reg(0x1));
827 vec4_visitor::visit(ir_expression
*ir
)
829 unsigned int operand
;
830 src_reg op
[Elements(ir
->operands
)];
833 vec4_instruction
*inst
;
835 if (try_emit_sat(ir
))
838 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
839 this->result
.file
= BAD_FILE
;
840 ir
->operands
[operand
]->accept(this);
841 if (this->result
.file
== BAD_FILE
) {
842 printf("Failed to get tree for expression operand:\n");
843 ir
->operands
[operand
]->print();
846 op
[operand
] = this->result
;
848 /* Matrix expression operands should have been broken down to vector
849 * operations already.
851 assert(!ir
->operands
[operand
]->type
->is_matrix());
854 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
855 if (ir
->operands
[1]) {
856 vector_elements
= MAX2(vector_elements
,
857 ir
->operands
[1]->type
->vector_elements
);
860 this->result
.file
= BAD_FILE
;
862 /* Storage for our result. Ideally for an assignment we'd be using
863 * the actual storage for the result here, instead.
865 result_src
= src_reg(this, ir
->type
);
866 /* convenience for the emit functions below. */
867 result_dst
= dst_reg(result_src
);
868 /* If nothing special happens, this is the result. */
869 this->result
= result_src
;
870 /* Limit writes to the channels that will be used by result_src later.
871 * This does limit this temp's use as a temporary for multi-instruction
874 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
876 switch (ir
->operation
) {
877 case ir_unop_logic_not
:
878 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
879 * ones complement of the whole register, not just bit 0.
881 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], src_reg(1));
884 op
[0].negate
= !op
[0].negate
;
885 this->result
= op
[0];
889 op
[0].negate
= false;
890 this->result
= op
[0];
894 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0.0f
));
896 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
897 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
898 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1.0f
));
899 inst
->predicate
= BRW_PREDICATE_NORMAL
;
901 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
902 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
903 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(-1.0f
));
904 inst
->predicate
= BRW_PREDICATE_NORMAL
;
909 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
913 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
916 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
920 assert(!"not reached: should be handled by ir_explog_to_explog2");
923 case ir_unop_sin_reduced
:
924 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
927 case ir_unop_cos_reduced
:
928 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
933 assert(!"derivatives not valid in vertex shader");
937 assert(!"not reached: should be handled by lower_noise");
941 emit(BRW_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
944 assert(!"not reached: should be handled by ir_sub_to_add_neg");
948 if (ir
->type
->is_integer()) {
949 /* For integer multiplication, the MUL uses the low 16 bits
950 * of one of the operands (src0 on gen6, src1 on gen7). The
951 * MACH accumulates in the contribution of the upper 16 bits
954 * FINISHME: Emit just the MUL if we know an operand is small
957 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
959 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
960 emit(BRW_OPCODE_MACH
, dst_null_d(), op
[0], op
[1]);
961 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(acc
));
963 emit(BRW_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
967 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
969 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
973 case ir_binop_greater
:
974 case ir_binop_lequal
:
975 case ir_binop_gequal
:
977 case ir_binop_nequal
: {
978 dst_reg temp
= result_dst
;
979 /* original gen4 does implicit conversion before comparison. */
981 temp
.type
= op
[0].type
;
983 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
984 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
985 emit(BRW_OPCODE_AND
, result_dst
, this->result
, src_reg(0x1));
989 case ir_binop_all_equal
:
990 /* "==" operator producing a scalar boolean. */
991 if (ir
->operands
[0]->type
->is_vector() ||
992 ir
->operands
[1]->type
->is_vector()) {
993 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
994 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
996 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
997 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
998 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1000 dst_reg temp
= result_dst
;
1001 /* original gen4 does implicit conversion before comparison. */
1003 temp
.type
= op
[0].type
;
1005 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
1006 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1007 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
1010 case ir_binop_any_nequal
:
1011 /* "!=" operator producing a scalar boolean. */
1012 if (ir
->operands
[0]->type
->is_vector() ||
1013 ir
->operands
[1]->type
->is_vector()) {
1014 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
1015 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1017 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1018 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1019 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1021 dst_reg temp
= result_dst
;
1022 /* original gen4 does implicit conversion before comparison. */
1024 temp
.type
= op
[0].type
;
1026 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
1027 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1028 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
1033 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
1034 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1036 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1038 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1039 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1042 case ir_binop_logic_xor
:
1043 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1046 case ir_binop_logic_or
:
1047 emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1050 case ir_binop_logic_and
:
1051 emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1055 assert(ir
->operands
[0]->type
->is_vector());
1056 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1057 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1061 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1064 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1073 emit(BRW_OPCODE_MOV
, result_dst
, op
[0]);
1077 dst_reg temp
= result_dst
;
1078 /* original gen4 does implicit conversion before comparison. */
1080 temp
.type
= op
[0].type
;
1082 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], src_reg(0.0f
));
1083 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1084 inst
= emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(1));
1089 emit(BRW_OPCODE_RNDZ
, result_dst
, op
[0]);
1092 op
[0].negate
= !op
[0].negate
;
1093 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1094 this->result
.negate
= true;
1097 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1100 inst
= emit(BRW_OPCODE_FRC
, result_dst
, op
[0]);
1102 case ir_unop_round_even
:
1103 emit(BRW_OPCODE_RNDE
, result_dst
, op
[0]);
1107 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1108 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1110 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1111 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1114 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1115 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1117 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1118 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1122 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1125 case ir_unop_bit_not
:
1126 inst
= emit(BRW_OPCODE_NOT
, result_dst
, op
[0]);
1128 case ir_binop_bit_and
:
1129 inst
= emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1131 case ir_binop_bit_xor
:
1132 inst
= emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1134 case ir_binop_bit_or
:
1135 inst
= emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1138 case ir_binop_lshift
:
1139 case ir_binop_rshift
:
1140 assert(!"GLSL 1.30 features unsupported");
1143 case ir_quadop_vector
:
1144 assert(!"not reached: should be handled by lower_quadop_vector");
1151 vec4_visitor::visit(ir_swizzle
*ir
)
1157 /* Note that this is only swizzles in expressions, not those on the left
1158 * hand side of an assignment, which do write masking. See ir_assignment
1162 ir
->val
->accept(this);
1164 assert(src
.file
!= BAD_FILE
);
1166 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1169 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1172 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1175 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1178 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1182 for (; i
< 4; i
++) {
1183 /* Replicate the last channel out. */
1184 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1187 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1193 vec4_visitor::visit(ir_dereference_variable
*ir
)
1195 const struct glsl_type
*type
= ir
->type
;
1196 dst_reg
*reg
= variable_storage(ir
->var
);
1199 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1200 this->result
= src_reg(brw_null_reg());
1204 this->result
= src_reg(*reg
);
1206 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1207 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1211 vec4_visitor::visit(ir_dereference_array
*ir
)
1213 ir_constant
*constant_index
;
1215 int element_size
= type_size(ir
->type
);
1217 constant_index
= ir
->array_index
->constant_expression_value();
1219 ir
->array
->accept(this);
1222 if (constant_index
) {
1223 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1225 /* Variable index array dereference. It eats the "vec4" of the
1226 * base of the array and an index that offsets the Mesa register
1229 ir
->array_index
->accept(this);
1233 if (element_size
== 1) {
1234 index_reg
= this->result
;
1236 index_reg
= src_reg(this, glsl_type::int_type
);
1238 emit(BRW_OPCODE_MUL
, dst_reg(index_reg
),
1239 this->result
, src_reg(element_size
));
1243 src_reg temp
= src_reg(this, glsl_type::int_type
);
1245 emit(BRW_OPCODE_ADD
, dst_reg(temp
), *src
.reladdr
, index_reg
);
1250 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1251 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1254 /* If the type is smaller than a vec4, replicate the last channel out. */
1255 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1256 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1258 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1259 src
.type
= brw_type_for_base_type(ir
->type
);
1265 vec4_visitor::visit(ir_dereference_record
*ir
)
1268 const glsl_type
*struct_type
= ir
->record
->type
;
1271 ir
->record
->accept(this);
1273 for (i
= 0; i
< struct_type
->length
; i
++) {
1274 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1276 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1279 /* If the type is smaller than a vec4, replicate the last channel out. */
1280 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1281 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1283 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1284 this->result
.type
= brw_type_for_base_type(ir
->type
);
1286 this->result
.reg_offset
+= offset
;
1290 * We want to be careful in assignment setup to hit the actual storage
1291 * instead of potentially using a temporary like we might with the
1292 * ir_dereference handler.
1295 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1297 /* The LHS must be a dereference. If the LHS is a variable indexed array
1298 * access of a vector, it must be separated into a series conditional moves
1299 * before reaching this point (see ir_vec_index_to_cond_assign).
1301 assert(ir
->as_dereference());
1302 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1304 assert(!deref_array
->array
->type
->is_vector());
1307 /* Use the rvalue deref handler for the most part. We'll ignore
1308 * swizzles in it and write swizzles using writemask, though.
1311 return dst_reg(v
->result
);
1315 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1316 const struct glsl_type
*type
, bool predicated
)
1318 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1319 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1320 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicated
);
1325 if (type
->is_array()) {
1326 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1327 emit_block_move(dst
, src
, type
->fields
.array
, predicated
);
1332 if (type
->is_matrix()) {
1333 const struct glsl_type
*vec_type
;
1335 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1336 type
->vector_elements
, 1);
1338 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1339 emit_block_move(dst
, src
, vec_type
, predicated
);
1344 assert(type
->is_scalar() || type
->is_vector());
1346 dst
->type
= brw_type_for_base_type(type
);
1347 src
->type
= dst
->type
;
1349 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1351 /* Do we need to worry about swizzling a swizzle? */
1352 assert(src
->swizzle
= BRW_SWIZZLE_NOOP
);
1353 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1355 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, *dst
, *src
);
1357 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1364 /* If the RHS processing resulted in an instruction generating a
1365 * temporary value, and it would be easy to rewrite the instruction to
1366 * generate its result right into the LHS instead, do so. This ends
1367 * up reliably removing instructions where it can be tricky to do so
1368 * later without real UD chain information.
1371 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1374 vec4_instruction
*pre_rhs_inst
,
1375 vec4_instruction
*last_rhs_inst
)
1377 /* This could be supported, but it would take more smarts. */
1381 if (pre_rhs_inst
== last_rhs_inst
)
1382 return false; /* No instructions generated to work with. */
1384 /* Make sure the last instruction generated our source reg. */
1385 if (src
.file
!= GRF
||
1386 src
.file
!= last_rhs_inst
->dst
.file
||
1387 src
.reg
!= last_rhs_inst
->dst
.reg
||
1388 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1392 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1395 /* Check that that last instruction fully initialized the channels
1396 * we want to use, in the order we want to use them. We could
1397 * potentially reswizzle the operands of many instructions so that
1398 * we could handle out of order channels, but don't yet.
1400 for (int i
= 0; i
< 4; i
++) {
1401 if (dst
.writemask
& (1 << i
)) {
1402 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1405 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1410 /* Success! Rewrite the instruction. */
1411 last_rhs_inst
->dst
.file
= dst
.file
;
1412 last_rhs_inst
->dst
.reg
= dst
.reg
;
1413 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1414 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1415 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1421 vec4_visitor::visit(ir_assignment
*ir
)
1423 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1425 if (!ir
->lhs
->type
->is_scalar() &&
1426 !ir
->lhs
->type
->is_vector()) {
1427 ir
->rhs
->accept(this);
1428 src_reg src
= this->result
;
1430 if (ir
->condition
) {
1431 emit_bool_to_cond_code(ir
->condition
);
1434 emit_block_move(&dst
, &src
, ir
->rhs
->type
, ir
->condition
!= NULL
);
1438 /* Now we're down to just a scalar/vector with writemasks. */
1441 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1442 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1444 ir
->rhs
->accept(this);
1446 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1448 src_reg src
= this->result
;
1451 int first_enabled_chan
= 0;
1454 assert(ir
->lhs
->type
->is_vector() ||
1455 ir
->lhs
->type
->is_scalar());
1456 dst
.writemask
= ir
->write_mask
;
1458 for (int i
= 0; i
< 4; i
++) {
1459 if (dst
.writemask
& (1 << i
)) {
1460 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1465 /* Swizzle a small RHS vector into the channels being written.
1467 * glsl ir treats write_mask as dictating how many channels are
1468 * present on the RHS while in our instructions we need to make
1469 * those channels appear in the slots of the vec4 they're written to.
1471 for (int i
= 0; i
< 4; i
++) {
1472 if (dst
.writemask
& (1 << i
))
1473 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1475 swizzles
[i
] = first_enabled_chan
;
1477 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1478 swizzles
[2], swizzles
[3]);
1480 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
1484 if (ir
->condition
) {
1485 emit_bool_to_cond_code(ir
->condition
);
1488 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1489 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst
, src
);
1492 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1500 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
1502 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1503 foreach_list(node
, &ir
->components
) {
1504 ir_constant
*field_value
= (ir_constant
*)node
;
1506 emit_constant_values(dst
, field_value
);
1511 if (ir
->type
->is_array()) {
1512 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1513 emit_constant_values(dst
, ir
->array_elements
[i
]);
1518 if (ir
->type
->is_matrix()) {
1519 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1520 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
1521 dst
->writemask
= 1 << j
;
1522 dst
->type
= BRW_REGISTER_TYPE_F
;
1524 emit(BRW_OPCODE_MOV
, *dst
,
1525 src_reg(ir
->value
.f
[i
* ir
->type
->vector_elements
+ j
]));
1532 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1533 dst
->writemask
= 1 << i
;
1534 dst
->type
= brw_type_for_base_type(ir
->type
);
1536 switch (ir
->type
->base_type
) {
1537 case GLSL_TYPE_FLOAT
:
1538 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.f
[i
]));
1541 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.i
[i
]));
1543 case GLSL_TYPE_UINT
:
1544 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.u
[i
]));
1546 case GLSL_TYPE_BOOL
:
1547 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.b
[i
]));
1550 assert(!"Non-float/uint/int/bool constant");
1558 vec4_visitor::visit(ir_constant
*ir
)
1560 dst_reg dst
= dst_reg(this, ir
->type
);
1561 this->result
= src_reg(dst
);
1563 emit_constant_values(&dst
, ir
);
1567 vec4_visitor::visit(ir_call
*ir
)
1569 assert(!"not reached");
1573 vec4_visitor::visit(ir_texture
*ir
)
1575 /* FINISHME: Implement vertex texturing.
1577 * With 0 vertex samplers available, the linker will reject
1578 * programs that do vertex texturing, but after our visitor has
1584 vec4_visitor::visit(ir_return
*ir
)
1586 assert(!"not reached");
1590 vec4_visitor::visit(ir_discard
*ir
)
1592 assert(!"not reached");
1596 vec4_visitor::visit(ir_if
*ir
)
1598 /* Don't point the annotation at the if statement, because then it plus
1599 * the then and else blocks get printed.
1601 this->base_ir
= ir
->condition
;
1603 if (intel
->gen
== 6) {
1606 emit_bool_to_cond_code(ir
->condition
);
1607 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
);
1608 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1611 visit_instructions(&ir
->then_instructions
);
1613 if (!ir
->else_instructions
.is_empty()) {
1614 this->base_ir
= ir
->condition
;
1615 emit(BRW_OPCODE_ELSE
);
1617 visit_instructions(&ir
->else_instructions
);
1620 this->base_ir
= ir
->condition
;
1621 emit(BRW_OPCODE_ENDIF
);
1625 vec4_visitor::emit_vue_header_gen4(int header_mrf
)
1627 /* Get the position */
1628 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
1630 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1631 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1633 current_annotation
= "NDC";
1634 dst_reg ndc_w
= ndc
;
1635 ndc_w
.writemask
= WRITEMASK_W
;
1636 src_reg pos_w
= pos
;
1637 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1638 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1640 dst_reg ndc_xyz
= ndc
;
1641 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1643 emit(BRW_OPCODE_MUL
, ndc_xyz
, pos
, src_reg(ndc_w
));
1645 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1646 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
) {
1647 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1650 emit(BRW_OPCODE_MOV
, header1
, 0u);
1652 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1653 assert(!"finishme: psiz");
1656 header1
.writemask
= WRITEMASK_W
;
1657 emit(BRW_OPCODE_MUL
, header1
, psiz
, 1u << 11);
1658 emit(BRW_OPCODE_AND
, header1
, src_reg(header1
), 0x7ff << 8);
1661 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1662 vec4_instruction
*inst
;
1664 inst
= emit(BRW_OPCODE_DP4
, dst_reg(brw_null_reg()),
1665 pos
, src_reg(c
->userplane
[i
]));
1666 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1668 emit(BRW_OPCODE_OR
, header1
, src_reg(header1
), 1u << i
);
1669 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1672 /* i965 clipping workaround:
1673 * 1) Test for -ve rhw
1675 * set ndc = (0,0,0,0)
1678 * Later, clipping will detect ucp[6] and ensure the primitive is
1679 * clipped against all fixed planes.
1681 if (brw
->has_negative_rhw_bug
) {
1685 vec8(brw_null_reg()),
1687 brw_swizzle1(ndc
, 3),
1690 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1691 brw_MOV(p
, ndc
, brw_imm_f(0));
1692 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1696 header1
.writemask
= WRITEMASK_XYZW
;
1697 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(header1
));
1699 emit(BRW_OPCODE_MOV
, retype(brw_message_reg(header_mrf
++),
1700 BRW_REGISTER_TYPE_UD
), 0u);
1703 if (intel
->gen
== 5) {
1704 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
1705 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1706 * dword 4-7 (m2) is the ndc position (set above)
1707 * dword 8-11 (m3) of the vertex header is the 4D space position
1708 * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
1709 * m6 is a pad so that the vertex element data is aligned
1710 * m7 is the first vertex data we fill.
1712 current_annotation
= "NDC";
1713 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1715 current_annotation
= "gl_Position";
1716 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1718 /* user clip distance. */
1721 /* Pad so that vertex element data is aligned. */
1724 /* There are 8 dwords in VUE header pre-Ironlake:
1725 * dword 0-3 (m1) is indices, point width, clip flags.
1726 * dword 4-7 (m2) is ndc position (set above)
1728 * dword 8-11 (m3) is the first vertex data.
1730 current_annotation
= "NDC";
1731 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1733 current_annotation
= "gl_Position";
1734 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1741 vec4_visitor::emit_vue_header_gen6(int header_mrf
)
1745 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
1746 * dword 0-3 (m2) of the header is indices, point width, clip flags.
1747 * dword 4-7 (m3) is the 4D space position
1748 * dword 8-15 (m4,m5) of the vertex header is the user clip distance if
1751 * m4 or 6 is the first vertex element data we fill.
1754 current_annotation
= "indices, point width, clip flags";
1755 reg
= brw_message_reg(header_mrf
++);
1756 emit(BRW_OPCODE_MOV
, retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0));
1757 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1758 emit(BRW_OPCODE_MOV
, brw_writemask(reg
, WRITEMASK_W
),
1759 src_reg(output_reg
[VERT_RESULT_PSIZ
]));
1762 current_annotation
= "gl_Position";
1763 emit(BRW_OPCODE_MOV
,
1764 brw_message_reg(header_mrf
++), src_reg(output_reg
[VERT_RESULT_HPOS
]));
1766 current_annotation
= "user clip distances";
1767 if (c
->key
.nr_userclip
) {
1768 for (int i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1771 m
= brw_message_reg(header_mrf
);
1773 m
= brw_message_reg(header_mrf
+ 1);
1775 emit(BRW_OPCODE_DP4
,
1776 dst_reg(brw_writemask(m
, 1 << (i
& 3))),
1777 src_reg(c
->userplane
[i
]));
1782 current_annotation
= NULL
;
1788 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
1790 struct intel_context
*intel
= &brw
->intel
;
1792 if (intel
->gen
>= 6) {
1793 /* URB data written (does not include the message header reg) must
1794 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1795 * section 5.4.3.2.2: URB_INTERLEAVED.
1797 * URB entries are allocated on a multiple of 1024 bits, so an
1798 * extra 128 bits written here to make the end align to 256 is
1801 if ((mlen
% 2) != 1)
1809 * Generates the VUE payload plus the 1 or 2 URB write instructions to
1810 * complete the VS thread.
1812 * The VUE layout is documented in Volume 2a.
1815 vec4_visitor::emit_urb_writes()
1817 /* MRF 0 is reserved for the debugger, so start with message header
1823 uint64_t outputs_remaining
= c
->prog_data
.outputs_written
;
1824 /* In the process of generating our URB write message contents, we
1825 * may need to unspill a register or load from an array. Those
1826 * reads would use MRFs 14-15.
1828 int max_usable_mrf
= 13;
1830 /* FINISHME: edgeflag */
1832 /* First mrf is the g0-based message header containing URB handles and such,
1833 * which is implied in VS_OPCODE_URB_WRITE.
1837 if (intel
->gen
>= 6) {
1838 mrf
= emit_vue_header_gen6(mrf
);
1840 mrf
= emit_vue_header_gen4(mrf
);
1843 /* Set up the VUE data for the first URB write */
1845 for (attr
= 0; attr
< VERT_RESULT_MAX
; attr
++) {
1846 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1849 outputs_remaining
&= ~BITFIELD64_BIT(attr
);
1851 /* This is set up in the VUE header. */
1852 if (attr
== VERT_RESULT_HPOS
)
1855 /* This is loaded into the VUE header, and thus doesn't occupy
1856 * an attribute slot.
1858 if (attr
== VERT_RESULT_PSIZ
)
1861 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, brw_message_reg(mrf
++),
1862 src_reg(output_reg
[attr
]));
1864 if ((attr
== VERT_RESULT_COL0
||
1865 attr
== VERT_RESULT_COL1
||
1866 attr
== VERT_RESULT_BFC0
||
1867 attr
== VERT_RESULT_BFC1
) &&
1868 c
->key
.clamp_vertex_color
) {
1869 inst
->saturate
= true;
1872 /* If this was MRF 15, we can't fit anything more into this URB
1873 * WRITE. Note that base_mrf of 1 means that MRF 15 is an
1874 * even-numbered amount of URB write data, which will meet
1875 * gen6's requirements for length alignment.
1877 if (mrf
> max_usable_mrf
) {
1883 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
1884 inst
->base_mrf
= base_mrf
;
1885 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1886 inst
->eot
= !outputs_remaining
;
1888 urb_entry_size
= mrf
- base_mrf
;
1890 /* Optional second URB write */
1891 if (outputs_remaining
) {
1894 for (; attr
< VERT_RESULT_MAX
; attr
++) {
1895 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1898 assert(mrf
< max_usable_mrf
);
1900 emit(BRW_OPCODE_MOV
, brw_message_reg(mrf
++), src_reg(output_reg
[attr
]));
1903 inst
= emit(VS_OPCODE_URB_WRITE
);
1904 inst
->base_mrf
= base_mrf
;
1905 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1907 /* URB destination offset. In the previous write, we got MRFs
1908 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
1909 * URB row increments, and each of our MRFs is half of one of
1910 * those, since we're doing interleaved writes.
1912 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
1914 urb_entry_size
+= mrf
- base_mrf
;
1917 if (intel
->gen
== 6)
1918 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 8) / 8;
1920 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 4) / 4;
1924 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
1925 src_reg
*reladdr
, int reg_offset
)
1927 /* Because we store the values to scratch interleaved like our
1928 * vertex data, we need to scale the vec4 index by 2.
1930 int message_header_scale
= 2;
1932 /* Pre-gen6, the message header uses byte offsets instead of vec4
1933 * (16-byte) offset units.
1936 message_header_scale
*= 16;
1939 src_reg index
= src_reg(this, glsl_type::int_type
);
1941 vec4_instruction
*add
= emit(BRW_OPCODE_ADD
,
1944 src_reg(reg_offset
));
1945 /* Move our new instruction from the tail to its correct place. */
1947 inst
->insert_before(add
);
1949 vec4_instruction
*mul
= emit(BRW_OPCODE_MUL
, dst_reg(index
),
1950 index
, src_reg(message_header_scale
));
1952 inst
->insert_before(mul
);
1956 return src_reg(reg_offset
* message_header_scale
);
1961 * Emits an instruction before @inst to load the value named by @orig_src
1962 * from scratch space at @base_offset to @temp.
1965 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
1966 dst_reg temp
, src_reg orig_src
,
1969 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
1970 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
1972 vec4_instruction
*scratch_read_inst
= emit(VS_OPCODE_SCRATCH_READ
,
1975 scratch_read_inst
->base_mrf
= 14;
1976 scratch_read_inst
->mlen
= 1;
1977 /* Move our instruction from the tail to its correct place. */
1978 scratch_read_inst
->remove();
1979 inst
->insert_before(scratch_read_inst
);
1983 * Emits an instruction after @inst to store the value to be written
1984 * to @orig_dst to scratch space at @base_offset, from @temp.
1987 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
,
1988 src_reg temp
, dst_reg orig_dst
,
1991 int reg_offset
= base_offset
+ orig_dst
.reg_offset
;
1992 src_reg index
= get_scratch_offset(inst
, orig_dst
.reladdr
, reg_offset
);
1994 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
1995 orig_dst
.writemask
));
1996 vec4_instruction
*scratch_write_inst
= emit(VS_OPCODE_SCRATCH_WRITE
,
1998 scratch_write_inst
->base_mrf
= 13;
1999 scratch_write_inst
->mlen
= 2;
2000 scratch_write_inst
->predicate
= inst
->predicate
;
2001 /* Move our instruction from the tail to its correct place. */
2002 scratch_write_inst
->remove();
2003 inst
->insert_after(scratch_write_inst
);
2007 * We can't generally support array access in GRF space, because a
2008 * single instruction's destination can only span 2 contiguous
2009 * registers. So, we send all GRF arrays that get variable index
2010 * access to scratch space.
2013 vec4_visitor::move_grf_array_access_to_scratch()
2015 int scratch_loc
[this->virtual_grf_count
];
2017 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2018 scratch_loc
[i
] = -1;
2021 /* First, calculate the set of virtual GRFs that need to be punted
2022 * to scratch due to having any array access on them, and where in
2025 foreach_list(node
, &this->instructions
) {
2026 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2028 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2029 scratch_loc
[inst
->dst
.reg
] == -1) {
2030 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2031 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
] * 8 * 4;
2034 for (int i
= 0 ; i
< 3; i
++) {
2035 src_reg
*src
= &inst
->src
[i
];
2037 if (src
->file
== GRF
&& src
->reladdr
&&
2038 scratch_loc
[src
->reg
] == -1) {
2039 scratch_loc
[src
->reg
] = c
->last_scratch
;
2040 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
] * 8 * 4;
2045 /* Now, for anything that will be accessed through scratch, rewrite
2046 * it to load/store. Note that this is a _safe list walk, because
2047 * we may generate a new scratch_write instruction after the one
2050 foreach_list_safe(node
, &this->instructions
) {
2051 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2053 /* Set up the annotation tracking for new generated instructions. */
2055 current_annotation
= inst
->annotation
;
2057 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2058 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2060 emit_scratch_write(inst
, temp
, inst
->dst
, scratch_loc
[inst
->dst
.reg
]);
2062 inst
->dst
.file
= temp
.file
;
2063 inst
->dst
.reg
= temp
.reg
;
2064 inst
->dst
.reg_offset
= temp
.reg_offset
;
2065 inst
->dst
.reladdr
= NULL
;
2068 for (int i
= 0 ; i
< 3; i
++) {
2069 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2072 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2074 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2075 scratch_loc
[inst
->src
[i
].reg
]);
2077 inst
->src
[i
].file
= temp
.file
;
2078 inst
->src
[i
].reg
= temp
.reg
;
2079 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2080 inst
->src
[i
].reladdr
= NULL
;
2086 vec4_visitor::vec4_visitor(struct brw_vs_compile
*c
,
2087 struct gl_shader_program
*prog
,
2088 struct brw_shader
*shader
)
2093 this->intel
= &brw
->intel
;
2094 this->ctx
= &intel
->ctx
;
2096 this->shader
= shader
;
2098 this->mem_ctx
= ralloc_context(NULL
);
2099 this->failed
= false;
2101 this->base_ir
= NULL
;
2102 this->current_annotation
= NULL
;
2105 this->vp
= prog
->VertexProgram
;
2106 this->prog_data
= &c
->prog_data
;
2108 this->variable_ht
= hash_table_ctor(0,
2109 hash_table_pointer_hash
,
2110 hash_table_pointer_compare
);
2112 this->virtual_grf_def
= NULL
;
2113 this->virtual_grf_use
= NULL
;
2114 this->virtual_grf_sizes
= NULL
;
2115 this->virtual_grf_count
= 0;
2116 this->virtual_grf_array_size
= 0;
2117 this->live_intervals_valid
= false;
2121 this->variable_ht
= hash_table_ctor(0,
2122 hash_table_pointer_hash
,
2123 hash_table_pointer_compare
);
2126 vec4_visitor::~vec4_visitor()
2128 ralloc_free(this->mem_ctx
);
2129 hash_table_dtor(this->variable_ht
);
2134 vec4_visitor::fail(const char *format
, ...)
2144 va_start(va
, format
);
2145 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
2147 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
2149 this->fail_msg
= msg
;
2151 if (INTEL_DEBUG
& DEBUG_VS
) {
2152 fprintf(stderr
, "%s", msg
);
2156 } /* namespace brw */