2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
31 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
32 const src_reg
&src0
, const src_reg
&src1
,
35 this->opcode
= opcode
;
40 this->saturate
= false;
41 this->force_writemask_all
= false;
42 this->no_dd_clear
= false;
43 this->no_dd_check
= false;
44 this->writes_accumulator
= false;
45 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
46 this->predicate
= BRW_PREDICATE_NONE
;
47 this->predicate_inverse
= false;
49 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
50 this->shadow_compare
= false;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_size
= 0;
54 this->flag_subreg
= 0;
58 this->annotation
= NULL
;
62 vec4_visitor::emit(vec4_instruction
*inst
)
64 inst
->ir
= this->base_ir
;
65 inst
->annotation
= this->current_annotation
;
67 this->instructions
.push_tail(inst
);
73 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
74 vec4_instruction
*new_inst
)
76 new_inst
->ir
= inst
->ir
;
77 new_inst
->annotation
= inst
->annotation
;
79 inst
->insert_before(block
, new_inst
);
85 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
86 const src_reg
&src1
, const src_reg
&src2
)
88 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
93 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
96 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
100 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
102 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
106 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
108 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
112 vec4_visitor::emit(enum opcode opcode
)
114 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
119 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
121 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
126 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
127 const src_reg &src1) \
129 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
133 #define ALU2_ACC(op) \
135 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
136 const src_reg &src1) \
138 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
139 BRW_OPCODE_##op, dst, src0, src1); \
140 inst->writes_accumulator = true; \
146 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
147 const src_reg &src1, const src_reg &src2) \
149 assert(devinfo->gen >= 6); \
150 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
187 /** Gen4 predicated IF. */
189 vec4_visitor::IF(enum brw_predicate predicate
)
191 vec4_instruction
*inst
;
193 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
199 /** Gen6 IF with embedded comparison. */
201 vec4_visitor::IF(src_reg src0
, src_reg src1
,
202 enum brw_conditional_mod condition
)
204 assert(devinfo
->gen
== 6);
206 vec4_instruction
*inst
;
208 resolve_ud_negate(&src0
);
209 resolve_ud_negate(&src1
);
211 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
213 inst
->conditional_mod
= condition
;
219 * CMP: Sets the low bit of the destination channels with the result
220 * of the comparison, while the upper bits are undefined, and updates
221 * the flag register with the packed 16 bits of the result.
224 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
225 enum brw_conditional_mod condition
)
227 vec4_instruction
*inst
;
229 /* Take the instruction:
231 * CMP null<d> src0<f> src1<f>
233 * Original gen4 does type conversion to the destination type before
234 * comparison, producing garbage results for floating point comparisons.
236 * The destination type doesn't matter on newer generations, so we set the
237 * type to match src0 so we can compact the instruction.
239 dst
.type
= src0
.type
;
240 if (dst
.file
== HW_REG
)
241 dst
.fixed_hw_reg
.type
= dst
.type
;
243 resolve_ud_negate(&src0
);
244 resolve_ud_negate(&src1
);
246 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
247 inst
->conditional_mod
= condition
;
253 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
255 vec4_instruction
*inst
;
257 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
266 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
267 const src_reg
&index
)
269 vec4_instruction
*inst
;
271 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
280 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
282 static enum opcode dot_opcodes
[] = {
283 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
286 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
290 vec4_visitor::fix_3src_operand(src_reg src
)
292 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
293 * able to use vertical stride of zero to replicate the vec4 uniform, like
295 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
297 * But you can't, since vertical stride is always four in three-source
298 * instructions. Instead, insert a MOV instruction to do the replication so
299 * that the three-source instruction can consume it.
302 /* The MOV is only needed if the source is a uniform or immediate. */
303 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
306 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
309 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
310 expanded
.type
= src
.type
;
311 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
312 return src_reg(expanded
);
316 vec4_visitor::fix_math_operand(src_reg src
)
318 if (devinfo
->gen
< 6 || devinfo
->gen
>= 8 || src
.file
== BAD_FILE
)
321 /* The gen6 math instruction ignores the source modifiers --
322 * swizzle, abs, negate, and at least some parts of the register
323 * region description.
325 * Rather than trying to enumerate all these cases, *always* expand the
326 * operand to a temp GRF for gen6.
328 * For gen7, keep the operand as-is, except if immediate, which gen7 still
332 if (devinfo
->gen
== 7 && src
.file
!= IMM
)
335 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
336 expanded
.type
= src
.type
;
337 emit(MOV(expanded
, src
));
338 return src_reg(expanded
);
342 vec4_visitor::emit_math(enum opcode opcode
,
344 const src_reg
&src0
, const src_reg
&src1
)
346 vec4_instruction
*math
=
347 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
349 if (devinfo
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
350 /* MATH on Gen6 must be align1, so we can't do writemasks. */
351 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
352 math
->dst
.type
= dst
.type
;
353 emit(MOV(dst
, src_reg(math
->dst
)));
354 } else if (devinfo
->gen
< 6) {
356 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
361 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
363 if (devinfo
->gen
< 7) {
364 unreachable("ir_unop_pack_half_2x16 should be lowered");
367 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
368 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
370 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
372 * Because this instruction does not have a 16-bit floating-point type,
373 * the destination data type must be Word (W).
375 * The destination must be DWord-aligned and specify a horizontal stride
376 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
377 * each destination channel and the upper word is not modified.
379 * The above restriction implies that the f32to16 instruction must use
380 * align1 mode, because only in align1 mode is it possible to specify
381 * horizontal stride. We choose here to defy the hardware docs and emit
382 * align16 instructions.
384 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
385 * instructions. I was partially successful in that the code passed all
386 * tests. However, the code was dubiously correct and fragile, and the
387 * tests were not harsh enough to probe that frailty. Not trusting the
388 * code, I chose instead to remain in align16 mode in defiance of the hw
391 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
392 * simulator, emitting a f32to16 in align16 mode with UD as destination
393 * data type is safe. The behavior differs from that specified in the PRM
394 * in that the upper word of each destination channel is cleared to 0.
397 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
398 src_reg
tmp_src(tmp_dst
);
401 /* Verify the undocumented behavior on which the following instructions
402 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
403 * then the result of the bit-or instruction below will be incorrect.
405 * You should inspect the disasm output in order to verify that the MOV is
406 * not optimized away.
408 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
411 /* Give tmp the form below, where "." means untouched.
414 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
416 * That the upper word of each write-channel be 0 is required for the
417 * following bit-shift and bit-or instructions to work. Note that this
418 * relies on the undocumented hardware behavior mentioned above.
420 tmp_dst
.writemask
= WRITEMASK_XY
;
421 emit(F32TO16(tmp_dst
, src0
));
423 /* Give the write-channels of dst the form:
426 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
427 emit(SHL(dst
, tmp_src
, src_reg(16u)));
429 /* Finally, give the write-channels of dst the form of packHalf2x16's
433 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
434 emit(OR(dst
, src_reg(dst
), tmp_src
));
438 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
440 if (devinfo
->gen
< 7) {
441 unreachable("ir_unop_unpack_half_2x16 should be lowered");
444 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
445 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
447 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
449 * Because this instruction does not have a 16-bit floating-point type,
450 * the source data type must be Word (W). The destination type must be
453 * To use W as the source data type, we must adjust horizontal strides,
454 * which is only possible in align1 mode. All my [chadv] attempts at
455 * emitting align1 instructions for unpackHalf2x16 failed to pass the
456 * Piglit tests, so I gave up.
458 * I've verified that, on gen7 hardware and the simulator, it is safe to
459 * emit f16to32 in align16 mode with UD as source data type.
462 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
463 src_reg
tmp_src(tmp_dst
);
465 tmp_dst
.writemask
= WRITEMASK_X
;
466 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
468 tmp_dst
.writemask
= WRITEMASK_Y
;
469 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
471 dst
.writemask
= WRITEMASK_XY
;
472 emit(F16TO32(dst
, tmp_src
));
476 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
478 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
479 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
480 * is not suitable to generate the shift values, but we can use the packed
481 * vector float and a type-converting MOV.
483 dst_reg
shift(this, glsl_type::uvec4_type
);
484 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
486 dst_reg
shifted(this, glsl_type::uvec4_type
);
487 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
488 emit(SHR(shifted
, src0
, src_reg(shift
)));
490 shifted
.type
= BRW_REGISTER_TYPE_UB
;
491 dst_reg
f(this, glsl_type::vec4_type
);
492 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
494 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
498 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
500 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
501 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
502 * is not suitable to generate the shift values, but we can use the packed
503 * vector float and a type-converting MOV.
505 dst_reg
shift(this, glsl_type::uvec4_type
);
506 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
508 dst_reg
shifted(this, glsl_type::uvec4_type
);
509 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
510 emit(SHR(shifted
, src0
, src_reg(shift
)));
512 shifted
.type
= BRW_REGISTER_TYPE_B
;
513 dst_reg
f(this, glsl_type::vec4_type
);
514 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
516 dst_reg
scaled(this, glsl_type::vec4_type
);
517 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
519 dst_reg
max(this, glsl_type::vec4_type
);
520 emit_minmax(BRW_CONDITIONAL_GE
, max
, src_reg(scaled
), src_reg(-1.0f
));
521 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
525 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
527 dst_reg
saturated(this, glsl_type::vec4_type
);
528 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
529 inst
->saturate
= true;
531 dst_reg
scaled(this, glsl_type::vec4_type
);
532 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
534 dst_reg
rounded(this, glsl_type::vec4_type
);
535 emit(RNDE(rounded
, src_reg(scaled
)));
537 dst_reg
u(this, glsl_type::uvec4_type
);
538 emit(MOV(u
, src_reg(rounded
)));
541 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
545 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
547 dst_reg
max(this, glsl_type::vec4_type
);
548 emit_minmax(BRW_CONDITIONAL_GE
, max
, src0
, src_reg(-1.0f
));
550 dst_reg
min(this, glsl_type::vec4_type
);
551 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
553 dst_reg
scaled(this, glsl_type::vec4_type
);
554 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
556 dst_reg
rounded(this, glsl_type::vec4_type
);
557 emit(RNDE(rounded
, src_reg(scaled
)));
559 dst_reg
i(this, glsl_type::ivec4_type
);
560 emit(MOV(i
, src_reg(rounded
)));
563 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
567 vec4_visitor::visit_instructions(const exec_list
*list
)
569 foreach_in_list(ir_instruction
, ir
, list
) {
577 type_size(const struct glsl_type
*type
)
582 switch (type
->base_type
) {
585 case GLSL_TYPE_FLOAT
:
587 if (type
->is_matrix()) {
588 return type
->matrix_columns
;
590 /* Regardless of size of vector, it gets a vec4. This is bad
591 * packing for things like floats, but otherwise arrays become a
592 * mess. Hopefully a later pass over the code can pack scalars
593 * down if appropriate.
597 case GLSL_TYPE_ARRAY
:
598 assert(type
->length
> 0);
599 return type_size(type
->fields
.array
) * type
->length
;
600 case GLSL_TYPE_STRUCT
:
602 for (i
= 0; i
< type
->length
; i
++) {
603 size
+= type_size(type
->fields
.structure
[i
].type
);
606 case GLSL_TYPE_SUBROUTINE
:
609 case GLSL_TYPE_SAMPLER
:
610 /* Samplers take up no register space, since they're baked in at
614 case GLSL_TYPE_ATOMIC_UINT
:
616 case GLSL_TYPE_IMAGE
:
618 case GLSL_TYPE_DOUBLE
:
619 case GLSL_TYPE_ERROR
:
620 case GLSL_TYPE_INTERFACE
:
621 unreachable("not reached");
627 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
632 this->reg
= v
->alloc
.allocate(type_size(type
));
634 if (type
->is_array() || type
->is_record()) {
635 this->swizzle
= BRW_SWIZZLE_NOOP
;
637 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
640 this->type
= brw_type_for_base_type(type
);
643 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
650 this->reg
= v
->alloc
.allocate(type_size(type
) * size
);
652 this->swizzle
= BRW_SWIZZLE_NOOP
;
654 this->type
= brw_type_for_base_type(type
);
657 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
662 this->reg
= v
->alloc
.allocate(type_size(type
));
664 if (type
->is_array() || type
->is_record()) {
665 this->writemask
= WRITEMASK_XYZW
;
667 this->writemask
= (1 << type
->vector_elements
) - 1;
670 this->type
= brw_type_for_base_type(type
);
674 vec4_visitor::setup_vector_uniform_values(const gl_constant_value
*values
,
677 static const gl_constant_value zero
= { 0 };
679 for (unsigned i
= 0; i
< n
; ++i
)
680 stage_prog_data
->param
[4 * uniforms
+ i
] = &values
[i
];
682 for (unsigned i
= n
; i
< 4; ++i
)
683 stage_prog_data
->param
[4 * uniforms
+ i
] = &zero
;
685 uniform_vector_size
[uniforms
++] = n
;
688 /* Our support for uniforms is piggy-backed on the struct
689 * gl_fragment_program, because that's where the values actually
690 * get stored, rather than in some global gl_shader_program uniform
694 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
696 int namelen
= strlen(ir
->name
);
698 /* The data for our (non-builtin) uniforms is stored in a series of
699 * gl_uniform_driver_storage structs for each subcomponent that
700 * glGetUniformLocation() could name. We know it's been set up in the same
701 * order we'd walk the type, so walk the list of storage and find anything
702 * with our name, or the prefix of a component that starts with our name.
704 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
705 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
707 if (storage
->builtin
)
710 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
711 (storage
->name
[namelen
] != 0 &&
712 storage
->name
[namelen
] != '.' &&
713 storage
->name
[namelen
] != '[')) {
717 const unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
718 storage
->type
->matrix_columns
);
719 const unsigned vector_size
= storage
->type
->vector_elements
;
721 for (unsigned s
= 0; s
< vector_count
; s
++)
722 setup_vector_uniform_values(&storage
->storage
[s
* vector_size
],
728 vec4_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
730 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
731 assert(this->uniforms
< uniform_array_size
);
732 this->uniform_vector_size
[this->uniforms
] = 4;
733 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
734 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
735 for (int j
= 0; j
< 4; ++j
) {
736 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
737 (gl_constant_value
*) &clip_planes
[i
][j
];
743 /* Our support for builtin uniforms is even scarier than non-builtin.
744 * It sits on top of the PROG_STATE_VAR parameters that are
745 * automatically updated from GL context state.
748 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
750 const ir_state_slot
*const slots
= ir
->get_state_slots();
751 assert(slots
!= NULL
);
753 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
754 /* This state reference has already been setup by ir_to_mesa,
755 * but we'll get the same index back here. We can reference
756 * ParameterValues directly, since unlike brw_fs.cpp, we never
757 * add new state references during compile.
759 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
760 (gl_state_index
*)slots
[i
].tokens
);
761 gl_constant_value
*values
=
762 &this->prog
->Parameters
->ParameterValues
[index
][0];
764 assert(this->uniforms
< uniform_array_size
);
766 for (unsigned j
= 0; j
< 4; j
++)
767 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
768 &values
[GET_SWZ(slots
[i
].swizzle
, j
)];
770 this->uniform_vector_size
[this->uniforms
] =
771 (ir
->type
->is_scalar() || ir
->type
->is_vector() ||
772 ir
->type
->is_matrix() ? ir
->type
->vector_elements
: 4);
779 vec4_visitor::variable_storage(ir_variable
*var
)
781 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
785 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
786 enum brw_predicate
*predicate
)
788 ir_expression
*expr
= ir
->as_expression();
790 *predicate
= BRW_PREDICATE_NORMAL
;
792 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
794 vec4_instruction
*inst
;
796 assert(expr
->get_num_operands() <= 3);
797 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
798 expr
->operands
[i
]->accept(this);
799 op
[i
] = this->result
;
801 resolve_ud_negate(&op
[i
]);
804 switch (expr
->operation
) {
805 case ir_unop_logic_not
:
806 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
807 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
810 case ir_binop_logic_xor
:
811 if (devinfo
->gen
<= 5) {
812 src_reg temp
= src_reg(this, ir
->type
);
813 emit(XOR(dst_reg(temp
), op
[0], op
[1]));
814 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
816 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
818 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
821 case ir_binop_logic_or
:
822 if (devinfo
->gen
<= 5) {
823 src_reg temp
= src_reg(this, ir
->type
);
824 emit(OR(dst_reg(temp
), op
[0], op
[1]));
825 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
827 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
829 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
832 case ir_binop_logic_and
:
833 if (devinfo
->gen
<= 5) {
834 src_reg temp
= src_reg(this, ir
->type
);
835 emit(AND(dst_reg(temp
), op
[0], op
[1]));
836 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
838 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
840 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
844 if (devinfo
->gen
>= 6) {
845 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
847 inst
= emit(MOV(dst_null_f(), op
[0]));
848 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
853 if (devinfo
->gen
>= 6) {
854 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
856 inst
= emit(MOV(dst_null_d(), op
[0]));
857 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
861 case ir_binop_all_equal
:
862 if (devinfo
->gen
<= 5) {
863 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
864 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
866 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
867 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
870 case ir_binop_any_nequal
:
871 if (devinfo
->gen
<= 5) {
872 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
873 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
875 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
876 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
880 if (devinfo
->gen
<= 5) {
881 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
883 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
884 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
887 case ir_binop_greater
:
888 case ir_binop_gequal
:
890 case ir_binop_lequal
:
892 case ir_binop_nequal
:
893 if (devinfo
->gen
<= 5) {
894 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
895 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
897 emit(CMP(dst_null_d(), op
[0], op
[1],
898 brw_conditional_for_comparison(expr
->operation
)));
901 case ir_triop_csel
: {
902 /* Expand the boolean condition into the flag register. */
903 inst
= emit(MOV(dst_null_d(), op
[0]));
904 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
906 /* Select which boolean to return. */
907 dst_reg
temp(this, expr
->operands
[1]->type
);
908 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
909 inst
->predicate
= BRW_PREDICATE_NORMAL
;
911 /* Expand the result to a condition code. */
912 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
913 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
918 unreachable("not reached");
925 resolve_ud_negate(&this->result
);
927 vec4_instruction
*inst
= emit(AND(dst_null_d(), this->result
, src_reg(1)));
928 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
932 * Emit a gen6 IF statement with the comparison folded into the IF
936 vec4_visitor::emit_if_gen6(ir_if
*ir
)
938 ir_expression
*expr
= ir
->condition
->as_expression();
940 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
944 assert(expr
->get_num_operands() <= 3);
945 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
946 expr
->operands
[i
]->accept(this);
947 op
[i
] = this->result
;
950 switch (expr
->operation
) {
951 case ir_unop_logic_not
:
952 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
955 case ir_binop_logic_xor
:
956 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
959 case ir_binop_logic_or
:
960 temp
= dst_reg(this, glsl_type::bool_type
);
961 emit(OR(temp
, op
[0], op
[1]));
962 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
965 case ir_binop_logic_and
:
966 temp
= dst_reg(this, glsl_type::bool_type
);
967 emit(AND(temp
, op
[0], op
[1]));
968 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
972 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
976 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
979 case ir_binop_greater
:
980 case ir_binop_gequal
:
982 case ir_binop_lequal
:
984 case ir_binop_nequal
:
985 emit(IF(op
[0], op
[1],
986 brw_conditional_for_comparison(expr
->operation
)));
989 case ir_binop_all_equal
:
990 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
991 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
994 case ir_binop_any_nequal
:
995 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
996 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1000 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1001 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1004 case ir_triop_csel
: {
1005 /* Expand the boolean condition into the flag register. */
1006 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
1007 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1009 /* Select which boolean to return. */
1010 dst_reg
temp(this, expr
->operands
[1]->type
);
1011 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
1012 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1014 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
1019 unreachable("not reached");
1024 ir
->condition
->accept(this);
1026 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
1030 vec4_visitor::visit(ir_variable
*ir
)
1032 dst_reg
*reg
= NULL
;
1034 if (variable_storage(ir
))
1037 switch (ir
->data
.mode
) {
1038 case ir_var_shader_in
:
1039 assert(ir
->data
.location
!= -1);
1040 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
1043 case ir_var_shader_out
:
1044 assert(ir
->data
.location
!= -1);
1045 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1047 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1048 output_reg
[ir
->data
.location
+ i
] = *reg
;
1049 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
1050 output_reg
[ir
->data
.location
+ i
].type
=
1051 brw_type_for_base_type(ir
->type
->get_scalar_type());
1052 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
1057 case ir_var_temporary
:
1058 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1061 case ir_var_uniform
:
1062 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1064 /* Thanks to the lower_ubo_reference pass, we will see only
1065 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1066 * variables, so no need for them to be in variable_ht.
1068 * Some uniforms, such as samplers and atomic counters, have no actual
1069 * storage, so we should ignore them.
1071 if (ir
->is_in_buffer_block() || type_size(ir
->type
) == 0)
1074 /* Track how big the whole uniform variable is, in case we need to put a
1075 * copy of its data into pull constants for array access.
1077 assert(this->uniforms
< uniform_array_size
);
1078 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1080 if (!strncmp(ir
->name
, "gl_", 3)) {
1081 setup_builtin_uniform_values(ir
);
1083 setup_uniform_values(ir
);
1087 case ir_var_system_value
:
1088 reg
= make_reg_for_system_value(ir
);
1092 unreachable("not reached");
1095 reg
->type
= brw_type_for_base_type(ir
->type
);
1096 hash_table_insert(this->variable_ht
, reg
, ir
);
1100 vec4_visitor::visit(ir_loop
*ir
)
1102 /* We don't want debugging output to print the whole body of the
1103 * loop as the annotation.
1105 this->base_ir
= NULL
;
1107 emit(BRW_OPCODE_DO
);
1109 visit_instructions(&ir
->body_instructions
);
1111 emit(BRW_OPCODE_WHILE
);
1115 vec4_visitor::visit(ir_loop_jump
*ir
)
1118 case ir_loop_jump::jump_break
:
1119 emit(BRW_OPCODE_BREAK
);
1121 case ir_loop_jump::jump_continue
:
1122 emit(BRW_OPCODE_CONTINUE
);
1129 vec4_visitor::visit(ir_function_signature
*)
1131 unreachable("not reached");
1135 vec4_visitor::visit(ir_function
*ir
)
1137 /* Ignore function bodies other than main() -- we shouldn't see calls to
1138 * them since they should all be inlined.
1140 if (strcmp(ir
->name
, "main") == 0) {
1141 const ir_function_signature
*sig
;
1144 sig
= ir
->matching_signature(NULL
, &empty
, false);
1148 visit_instructions(&sig
->body
);
1153 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1155 /* 3-src instructions were introduced in gen6. */
1156 if (devinfo
->gen
< 6)
1159 /* MAD can only handle floating-point data. */
1160 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1165 bool mul_negate
, mul_abs
;
1167 for (int i
= 0; i
< 2; i
++) {
1171 mul
= ir
->operands
[i
]->as_expression();
1172 nonmul
= ir
->operands
[1 - i
];
1174 if (mul
&& mul
->operation
== ir_unop_abs
) {
1175 mul
= mul
->operands
[0]->as_expression();
1177 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
1178 mul
= mul
->operands
[0]->as_expression();
1182 if (mul
&& mul
->operation
== ir_binop_mul
)
1186 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1189 nonmul
->accept(this);
1190 src_reg src0
= fix_3src_operand(this->result
);
1192 mul
->operands
[0]->accept(this);
1193 src_reg src1
= fix_3src_operand(this->result
);
1194 src1
.negate
^= mul_negate
;
1197 src1
.negate
= false;
1199 mul
->operands
[1]->accept(this);
1200 src_reg src2
= fix_3src_operand(this->result
);
1203 src2
.negate
= false;
1205 this->result
= src_reg(this, ir
->type
);
1206 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1212 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1214 /* This optimization relies on CMP setting the destination to 0 when
1215 * false. Early hardware only sets the least significant bit, and
1216 * leaves the other bits undefined. So we can't use it.
1218 if (devinfo
->gen
< 6)
1221 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1226 switch (cmp
->operation
) {
1228 case ir_binop_greater
:
1229 case ir_binop_lequal
:
1230 case ir_binop_gequal
:
1231 case ir_binop_equal
:
1232 case ir_binop_nequal
:
1239 cmp
->operands
[0]->accept(this);
1240 const src_reg cmp_src0
= this->result
;
1242 cmp
->operands
[1]->accept(this);
1243 const src_reg cmp_src1
= this->result
;
1245 this->result
= src_reg(this, ir
->type
);
1247 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1248 brw_conditional_for_comparison(cmp
->operation
)));
1250 /* If the comparison is false, this->result will just happen to be zero.
1252 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1253 this->result
, src_reg(1.0f
));
1254 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1255 inst
->predicate_inverse
= true;
1261 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1262 src_reg src0
, src_reg src1
)
1264 vec4_instruction
*inst
;
1266 if (devinfo
->gen
>= 6) {
1267 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1268 inst
->conditional_mod
= conditionalmod
;
1270 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1272 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1273 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1278 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1279 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1281 if (devinfo
->gen
>= 6) {
1282 /* Note that the instruction's argument order is reversed from GLSL
1286 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1288 /* Earlier generations don't support three source operations, so we
1289 * need to emit x*(1-a) + y*a.
1291 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1292 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1293 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1294 y_times_a
.writemask
= dst
.writemask
;
1295 one_minus_a
.writemask
= dst
.writemask
;
1296 x_times_one_minus_a
.writemask
= dst
.writemask
;
1298 emit(MUL(y_times_a
, y
, a
));
1299 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1300 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1301 emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1306 * Emits the instructions needed to perform a pull constant load. before_block
1307 * and before_inst can be NULL in which case the instruction will be appended
1308 * to the end of the instruction list.
1311 vec4_visitor::emit_pull_constant_load_reg(dst_reg dst
,
1314 bblock_t
*before_block
,
1315 vec4_instruction
*before_inst
)
1317 assert((before_inst
== NULL
&& before_block
== NULL
) ||
1318 (before_inst
&& before_block
));
1320 vec4_instruction
*pull
;
1322 if (devinfo
->gen
>= 9) {
1323 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
1324 src_reg
header(this, glsl_type::uvec4_type
, 2);
1327 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
1331 emit_before(before_block
, before_inst
, pull
);
1335 dst_reg index_reg
= retype(offset(dst_reg(header
), 1),
1337 pull
= MOV(writemask(index_reg
, WRITEMASK_X
), offset_reg
);
1340 emit_before(before_block
, before_inst
, pull
);
1344 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1349 pull
->header_size
= 1;
1350 } else if (devinfo
->gen
>= 7) {
1351 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1353 grf_offset
.type
= offset_reg
.type
;
1355 pull
= MOV(grf_offset
, offset_reg
);
1358 emit_before(before_block
, before_inst
, pull
);
1362 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1365 src_reg(grf_offset
));
1368 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
1372 pull
->base_mrf
= 14;
1377 emit_before(before_block
, before_inst
, pull
);
1383 vec4_visitor::emit_uniformize(const src_reg
&src
)
1385 const src_reg
chan_index(this, glsl_type::uint_type
);
1386 const dst_reg dst
= retype(dst_reg(this, glsl_type::uint_type
),
1389 emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, dst_reg(chan_index
))
1390 ->force_writemask_all
= true;
1391 emit(SHADER_OPCODE_BROADCAST
, dst
, src
, chan_index
)
1392 ->force_writemask_all
= true;
1394 return src_reg(dst
);
1398 vec4_visitor::visit(ir_expression
*ir
)
1400 unsigned int operand
;
1401 src_reg op
[ARRAY_SIZE(ir
->operands
)];
1402 vec4_instruction
*inst
;
1404 if (ir
->operation
== ir_binop_add
) {
1405 if (try_emit_mad(ir
))
1409 if (ir
->operation
== ir_unop_b2f
) {
1410 if (try_emit_b2f_of_compare(ir
))
1414 /* Storage for our result. Ideally for an assignment we'd be using
1415 * the actual storage for the result here, instead.
1417 dst_reg
result_dst(this, ir
->type
);
1418 src_reg
result_src(result_dst
);
1420 if (ir
->operation
== ir_triop_csel
) {
1421 ir
->operands
[1]->accept(this);
1422 op
[1] = this->result
;
1423 ir
->operands
[2]->accept(this);
1424 op
[2] = this->result
;
1426 enum brw_predicate predicate
;
1427 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1428 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1429 inst
->predicate
= predicate
;
1430 this->result
= result_src
;
1434 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1435 this->result
.file
= BAD_FILE
;
1436 ir
->operands
[operand
]->accept(this);
1437 if (this->result
.file
== BAD_FILE
) {
1438 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1439 ir
->operands
[operand
]->fprint(stderr
);
1442 op
[operand
] = this->result
;
1444 /* Matrix expression operands should have been broken down to vector
1445 * operations already.
1447 assert(!ir
->operands
[operand
]->type
->is_matrix());
1450 /* If nothing special happens, this is the result. */
1451 this->result
= result_src
;
1453 switch (ir
->operation
) {
1454 case ir_unop_logic_not
:
1455 emit(NOT(result_dst
, op
[0]));
1458 op
[0].negate
= !op
[0].negate
;
1459 emit(MOV(result_dst
, op
[0]));
1463 op
[0].negate
= false;
1464 emit(MOV(result_dst
, op
[0]));
1468 if (ir
->type
->is_float()) {
1469 /* AND(val, 0x80000000) gives the sign bit.
1471 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1474 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1476 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1477 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1478 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1480 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1481 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1483 this->result
.type
= BRW_REGISTER_TYPE_F
;
1485 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1486 * -> non-negative val generates 0x00000000.
1487 * Predicated OR sets 1 if val is positive.
1489 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1491 emit(ASR(result_dst
, op
[0], src_reg(31)));
1493 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1494 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1499 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1503 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1506 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1510 unreachable("not reached: should be handled by ir_explog_to_explog2");
1512 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1515 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1519 case ir_unop_dFdx_coarse
:
1520 case ir_unop_dFdx_fine
:
1522 case ir_unop_dFdy_coarse
:
1523 case ir_unop_dFdy_fine
:
1524 unreachable("derivatives not valid in vertex shader");
1526 case ir_unop_bitfield_reverse
:
1527 emit(BFREV(result_dst
, op
[0]));
1529 case ir_unop_bit_count
:
1530 emit(CBIT(result_dst
, op
[0]));
1532 case ir_unop_find_msb
: {
1533 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1535 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1536 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1538 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1539 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1540 * subtract the result from 31 to convert the MSB count into an LSB count.
1543 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1544 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1545 emit(MOV(result_dst
, temp
));
1547 src_reg src_tmp
= src_reg(result_dst
);
1548 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1550 src_tmp
.negate
= true;
1551 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1552 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1555 case ir_unop_find_lsb
:
1556 emit(FBL(result_dst
, op
[0]));
1558 case ir_unop_saturate
:
1559 inst
= emit(MOV(result_dst
, op
[0]));
1560 inst
->saturate
= true;
1564 unreachable("not reached: should be handled by lower_noise");
1566 case ir_unop_subroutine_to_int
:
1567 emit(MOV(result_dst
, op
[0]));
1571 emit(ADD(result_dst
, op
[0], op
[1]));
1574 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1577 if (devinfo
->gen
< 8 && ir
->type
->is_integer()) {
1578 /* For integer multiplication, the MUL uses the low 16 bits of one of
1579 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1580 * accumulates in the contribution of the upper 16 bits of that
1581 * operand. If we can determine that one of the args is in the low
1582 * 16 bits, though, we can just emit a single MUL.
1584 if (ir
->operands
[0]->is_uint16_constant()) {
1585 if (devinfo
->gen
< 7)
1586 emit(MUL(result_dst
, op
[0], op
[1]));
1588 emit(MUL(result_dst
, op
[1], op
[0]));
1589 } else if (ir
->operands
[1]->is_uint16_constant()) {
1590 if (devinfo
->gen
< 7)
1591 emit(MUL(result_dst
, op
[1], op
[0]));
1593 emit(MUL(result_dst
, op
[0], op
[1]));
1595 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1597 emit(MUL(acc
, op
[0], op
[1]));
1598 emit(MACH(dst_null_d(), op
[0], op
[1]));
1599 emit(MOV(result_dst
, src_reg(acc
)));
1602 emit(MUL(result_dst
, op
[0], op
[1]));
1605 case ir_binop_imul_high
: {
1606 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1608 emit(MUL(acc
, op
[0], op
[1]));
1609 emit(MACH(result_dst
, op
[0], op
[1]));
1613 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1614 assert(ir
->type
->is_integer());
1615 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1618 case ir_binop_carry
:
1619 unreachable("Should have been lowered by carry_to_arith().");
1621 case ir_binop_borrow
:
1622 unreachable("Should have been lowered by borrow_to_arith().");
1625 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1626 assert(ir
->type
->is_integer());
1627 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1631 case ir_binop_greater
:
1632 case ir_binop_lequal
:
1633 case ir_binop_gequal
:
1634 case ir_binop_equal
:
1635 case ir_binop_nequal
: {
1636 if (devinfo
->gen
<= 5) {
1637 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1638 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1640 emit(CMP(result_dst
, op
[0], op
[1],
1641 brw_conditional_for_comparison(ir
->operation
)));
1645 case ir_binop_all_equal
:
1646 if (devinfo
->gen
<= 5) {
1647 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1648 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1651 /* "==" operator producing a scalar boolean. */
1652 if (ir
->operands
[0]->type
->is_vector() ||
1653 ir
->operands
[1]->type
->is_vector()) {
1654 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1655 emit(MOV(result_dst
, src_reg(0)));
1656 inst
= emit(MOV(result_dst
, src_reg(~0)));
1657 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1659 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1662 case ir_binop_any_nequal
:
1663 if (devinfo
->gen
<= 5) {
1664 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1665 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1668 /* "!=" operator producing a scalar boolean. */
1669 if (ir
->operands
[0]->type
->is_vector() ||
1670 ir
->operands
[1]->type
->is_vector()) {
1671 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1673 emit(MOV(result_dst
, src_reg(0)));
1674 inst
= emit(MOV(result_dst
, src_reg(~0)));
1675 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1677 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1682 if (devinfo
->gen
<= 5) {
1683 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1685 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1686 emit(MOV(result_dst
, src_reg(0)));
1688 inst
= emit(MOV(result_dst
, src_reg(~0)));
1689 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1692 case ir_binop_logic_xor
:
1693 emit(XOR(result_dst
, op
[0], op
[1]));
1696 case ir_binop_logic_or
:
1697 emit(OR(result_dst
, op
[0], op
[1]));
1700 case ir_binop_logic_and
:
1701 emit(AND(result_dst
, op
[0], op
[1]));
1705 assert(ir
->operands
[0]->type
->is_vector());
1706 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1707 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1711 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1714 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1717 case ir_unop_bitcast_i2f
:
1718 case ir_unop_bitcast_u2f
:
1719 this->result
= op
[0];
1720 this->result
.type
= BRW_REGISTER_TYPE_F
;
1723 case ir_unop_bitcast_f2i
:
1724 this->result
= op
[0];
1725 this->result
.type
= BRW_REGISTER_TYPE_D
;
1728 case ir_unop_bitcast_f2u
:
1729 this->result
= op
[0];
1730 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1739 emit(MOV(result_dst
, op
[0]));
1743 if (devinfo
->gen
<= 5) {
1744 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1746 emit(MOV(result_dst
, negate(op
[0])));
1749 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1752 emit(CMP(result_dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1756 emit(RNDZ(result_dst
, op
[0]));
1758 case ir_unop_ceil
: {
1759 src_reg tmp
= src_reg(this, ir
->type
);
1760 op
[0].negate
= !op
[0].negate
;
1761 emit(RNDD(dst_reg(tmp
), op
[0]));
1763 emit(MOV(result_dst
, tmp
));
1767 inst
= emit(RNDD(result_dst
, op
[0]));
1770 inst
= emit(FRC(result_dst
, op
[0]));
1772 case ir_unop_round_even
:
1773 emit(RNDE(result_dst
, op
[0]));
1777 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1780 emit_minmax(BRW_CONDITIONAL_GE
, result_dst
, op
[0], op
[1]);
1784 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1787 case ir_unop_bit_not
:
1788 inst
= emit(NOT(result_dst
, op
[0]));
1790 case ir_binop_bit_and
:
1791 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1793 case ir_binop_bit_xor
:
1794 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1796 case ir_binop_bit_or
:
1797 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1800 case ir_binop_lshift
:
1801 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1804 case ir_binop_rshift
:
1805 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1806 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1808 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1812 emit(BFI1(result_dst
, op
[0], op
[1]));
1815 case ir_binop_ubo_load
: {
1816 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1817 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1818 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1821 /* Now, load the vector from that offset. */
1822 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1824 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1825 packed_consts
.type
= result
.type
;
1828 if (const_uniform_block
) {
1829 /* The block index is a constant, so just emit the binding table entry
1832 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1833 const_uniform_block
->value
.u
[0]);
1835 /* The block index is not a constant. Evaluate the index expression
1836 * per-channel and add the base UBO index; we have to select a value
1837 * from any live channel.
1839 surf_index
= src_reg(this, glsl_type::uint_type
);
1840 emit(ADD(dst_reg(surf_index
), op
[0],
1841 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1842 surf_index
= emit_uniformize(surf_index
);
1844 /* Assume this may touch any UBO. It would be nice to provide
1845 * a tighter bound, but the array information is already lowered away.
1847 brw_mark_surface_used(&prog_data
->base
,
1848 prog_data
->base
.binding_table
.ubo_start
+
1849 shader_prog
->NumUniformBlocks
- 1);
1852 if (const_offset_ir
) {
1853 if (devinfo
->gen
>= 8) {
1854 /* Store the offset in a GRF so we can send-from-GRF. */
1855 offset
= src_reg(this, glsl_type::int_type
);
1856 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1858 /* Immediates are fine on older generations since they'll be moved
1859 * to a (potentially fake) MRF at the generator level.
1861 offset
= src_reg(const_offset
/ 16);
1864 offset
= src_reg(this, glsl_type::uint_type
);
1865 emit(SHR(dst_reg(offset
), op
[1], src_reg(4u)));
1868 emit_pull_constant_load_reg(dst_reg(packed_consts
),
1871 NULL
, NULL
/* before_block/inst */);
1873 packed_consts
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
1874 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1875 const_offset
% 16 / 4,
1876 const_offset
% 16 / 4,
1877 const_offset
% 16 / 4);
1879 /* UBO bools are any nonzero int. We need to convert them to 0/~0. */
1880 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1881 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1882 BRW_CONDITIONAL_NZ
));
1884 emit(MOV(result_dst
, packed_consts
));
1889 case ir_binop_vector_extract
:
1890 unreachable("should have been lowered by vec_index_to_cond_assign");
1893 op
[0] = fix_3src_operand(op
[0]);
1894 op
[1] = fix_3src_operand(op
[1]);
1895 op
[2] = fix_3src_operand(op
[2]);
1896 /* Note that the instruction's argument order is reversed from GLSL
1899 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1903 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1907 unreachable("already handled above");
1911 op
[0] = fix_3src_operand(op
[0]);
1912 op
[1] = fix_3src_operand(op
[1]);
1913 op
[2] = fix_3src_operand(op
[2]);
1914 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1917 case ir_triop_bitfield_extract
:
1918 op
[0] = fix_3src_operand(op
[0]);
1919 op
[1] = fix_3src_operand(op
[1]);
1920 op
[2] = fix_3src_operand(op
[2]);
1921 /* Note that the instruction's argument order is reversed from GLSL
1924 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1927 case ir_triop_vector_insert
:
1928 unreachable("should have been lowered by lower_vector_insert");
1930 case ir_quadop_bitfield_insert
:
1931 unreachable("not reached: should be handled by "
1932 "bitfield_insert_to_bfm_bfi\n");
1934 case ir_quadop_vector
:
1935 unreachable("not reached: should be handled by lower_quadop_vector");
1937 case ir_unop_pack_half_2x16
:
1938 emit_pack_half_2x16(result_dst
, op
[0]);
1940 case ir_unop_unpack_half_2x16
:
1941 emit_unpack_half_2x16(result_dst
, op
[0]);
1943 case ir_unop_unpack_unorm_4x8
:
1944 emit_unpack_unorm_4x8(result_dst
, op
[0]);
1946 case ir_unop_unpack_snorm_4x8
:
1947 emit_unpack_snorm_4x8(result_dst
, op
[0]);
1949 case ir_unop_pack_unorm_4x8
:
1950 emit_pack_unorm_4x8(result_dst
, op
[0]);
1952 case ir_unop_pack_snorm_4x8
:
1953 emit_pack_snorm_4x8(result_dst
, op
[0]);
1955 case ir_unop_pack_snorm_2x16
:
1956 case ir_unop_pack_unorm_2x16
:
1957 case ir_unop_unpack_snorm_2x16
:
1958 case ir_unop_unpack_unorm_2x16
:
1959 unreachable("not reached: should be handled by lower_packing_builtins");
1960 case ir_unop_unpack_half_2x16_split_x
:
1961 case ir_unop_unpack_half_2x16_split_y
:
1962 case ir_binop_pack_half_2x16_split
:
1963 case ir_unop_interpolate_at_centroid
:
1964 case ir_binop_interpolate_at_sample
:
1965 case ir_binop_interpolate_at_offset
:
1966 unreachable("not reached: should not occur in vertex shader");
1967 case ir_binop_ldexp
:
1968 unreachable("not reached: should be handled by ldexp_to_arith()");
1976 case ir_unop_pack_double_2x32
:
1977 case ir_unop_unpack_double_2x32
:
1978 case ir_unop_frexp_sig
:
1979 case ir_unop_frexp_exp
:
1980 unreachable("fp64 todo");
1986 vec4_visitor::visit(ir_swizzle
*ir
)
1988 /* Note that this is only swizzles in expressions, not those on the left
1989 * hand side of an assignment, which do write masking. See ir_assignment
1992 const unsigned swz
= brw_compose_swizzle(
1993 brw_swizzle_for_size(ir
->type
->vector_elements
),
1994 BRW_SWIZZLE4(ir
->mask
.x
, ir
->mask
.y
, ir
->mask
.z
, ir
->mask
.w
));
1996 ir
->val
->accept(this);
1997 this->result
= swizzle(this->result
, swz
);
2001 vec4_visitor::visit(ir_dereference_variable
*ir
)
2003 const struct glsl_type
*type
= ir
->type
;
2004 dst_reg
*reg
= variable_storage(ir
->var
);
2007 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
2008 this->result
= src_reg(brw_null_reg());
2012 this->result
= src_reg(*reg
);
2014 /* System values get their swizzle from the dst_reg writemask */
2015 if (ir
->var
->data
.mode
== ir_var_system_value
)
2018 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
2019 this->result
.swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2024 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
2026 /* Under normal circumstances array elements are stored consecutively, so
2027 * the stride is equal to the size of the array element.
2029 return type_size(ir
->type
);
2034 vec4_visitor::visit(ir_dereference_array
*ir
)
2036 ir_constant
*constant_index
;
2038 int array_stride
= compute_array_stride(ir
);
2040 constant_index
= ir
->array_index
->constant_expression_value();
2042 ir
->array
->accept(this);
2045 if (constant_index
) {
2046 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
2048 /* Variable index array dereference. It eats the "vec4" of the
2049 * base of the array and an index that offsets the Mesa register
2052 ir
->array_index
->accept(this);
2056 if (array_stride
== 1) {
2057 index_reg
= this->result
;
2059 index_reg
= src_reg(this, glsl_type::int_type
);
2061 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
2065 src_reg temp
= src_reg(this, glsl_type::int_type
);
2067 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
2072 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
2073 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2076 /* If the type is smaller than a vec4, replicate the last channel out. */
2077 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2078 src
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2080 src
.swizzle
= BRW_SWIZZLE_NOOP
;
2081 src
.type
= brw_type_for_base_type(ir
->type
);
2087 vec4_visitor::visit(ir_dereference_record
*ir
)
2090 const glsl_type
*struct_type
= ir
->record
->type
;
2093 ir
->record
->accept(this);
2095 for (i
= 0; i
< struct_type
->length
; i
++) {
2096 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2098 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2101 /* If the type is smaller than a vec4, replicate the last channel out. */
2102 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2103 this->result
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2105 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
2106 this->result
.type
= brw_type_for_base_type(ir
->type
);
2108 this->result
.reg_offset
+= offset
;
2112 * We want to be careful in assignment setup to hit the actual storage
2113 * instead of potentially using a temporary like we might with the
2114 * ir_dereference handler.
2117 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
2119 /* The LHS must be a dereference. If the LHS is a variable indexed array
2120 * access of a vector, it must be separated into a series conditional moves
2121 * before reaching this point (see ir_vec_index_to_cond_assign).
2123 assert(ir
->as_dereference());
2124 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2126 assert(!deref_array
->array
->type
->is_vector());
2129 /* Use the rvalue deref handler for the most part. We'll ignore
2130 * swizzles in it and write swizzles using writemask, though.
2133 return dst_reg(v
->result
);
2137 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
2138 const struct glsl_type
*type
,
2139 enum brw_predicate predicate
)
2141 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2142 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2143 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
2148 if (type
->is_array()) {
2149 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2150 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
2155 if (type
->is_matrix()) {
2156 const struct glsl_type
*vec_type
;
2158 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2159 type
->vector_elements
, 1);
2161 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2162 emit_block_move(dst
, src
, vec_type
, predicate
);
2167 assert(type
->is_scalar() || type
->is_vector());
2169 dst
->type
= brw_type_for_base_type(type
);
2170 src
->type
= dst
->type
;
2172 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2174 src
->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2176 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2177 inst
->predicate
= predicate
;
2184 /* If the RHS processing resulted in an instruction generating a
2185 * temporary value, and it would be easy to rewrite the instruction to
2186 * generate its result right into the LHS instead, do so. This ends
2187 * up reliably removing instructions where it can be tricky to do so
2188 * later without real UD chain information.
2191 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2194 vec4_instruction
*pre_rhs_inst
,
2195 vec4_instruction
*last_rhs_inst
)
2197 /* This could be supported, but it would take more smarts. */
2201 if (pre_rhs_inst
== last_rhs_inst
)
2202 return false; /* No instructions generated to work with. */
2204 /* Make sure the last instruction generated our source reg. */
2205 if (src
.file
!= GRF
||
2206 src
.file
!= last_rhs_inst
->dst
.file
||
2207 src
.reg
!= last_rhs_inst
->dst
.reg
||
2208 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2212 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2215 /* Check that that last instruction fully initialized the channels
2216 * we want to use, in the order we want to use them. We could
2217 * potentially reswizzle the operands of many instructions so that
2218 * we could handle out of order channels, but don't yet.
2221 for (unsigned i
= 0; i
< 4; i
++) {
2222 if (dst
.writemask
& (1 << i
)) {
2223 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2226 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2231 /* Success! Rewrite the instruction. */
2232 last_rhs_inst
->dst
.file
= dst
.file
;
2233 last_rhs_inst
->dst
.reg
= dst
.reg
;
2234 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2235 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2236 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2242 vec4_visitor::visit(ir_assignment
*ir
)
2244 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2245 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2247 if (!ir
->lhs
->type
->is_scalar() &&
2248 !ir
->lhs
->type
->is_vector()) {
2249 ir
->rhs
->accept(this);
2250 src_reg src
= this->result
;
2252 if (ir
->condition
) {
2253 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2256 /* emit_block_move doesn't account for swizzles in the source register.
2257 * This should be ok, since the source register is a structure or an
2258 * array, and those can't be swizzled. But double-check to be sure.
2260 assert(src
.swizzle
==
2261 (ir
->rhs
->type
->is_matrix()
2262 ? brw_swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2263 : BRW_SWIZZLE_NOOP
));
2265 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2269 /* Now we're down to just a scalar/vector with writemasks. */
2272 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2273 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2275 ir
->rhs
->accept(this);
2277 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2282 assert(ir
->lhs
->type
->is_vector() ||
2283 ir
->lhs
->type
->is_scalar());
2284 dst
.writemask
= ir
->write_mask
;
2286 /* Swizzle a small RHS vector into the channels being written.
2288 * glsl ir treats write_mask as dictating how many channels are
2289 * present on the RHS while in our instructions we need to make
2290 * those channels appear in the slots of the vec4 they're written to.
2292 for (int i
= 0; i
< 4; i
++)
2293 swizzles
[i
] = (ir
->write_mask
& (1 << i
) ? src_chan
++ : 0);
2295 src_reg src
= swizzle(this->result
,
2296 BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2297 swizzles
[2], swizzles
[3]));
2299 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2303 if (ir
->condition
) {
2304 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2307 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2308 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2309 inst
->predicate
= predicate
;
2317 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2319 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2320 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2321 emit_constant_values(dst
, field_value
);
2326 if (ir
->type
->is_array()) {
2327 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2328 emit_constant_values(dst
, ir
->array_elements
[i
]);
2333 if (ir
->type
->is_matrix()) {
2334 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2335 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2337 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2338 dst
->writemask
= 1 << j
;
2339 dst
->type
= BRW_REGISTER_TYPE_F
;
2341 emit(MOV(*dst
, src_reg(vec
[j
])));
2348 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2350 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2351 if (!(remaining_writemask
& (1 << i
)))
2354 dst
->writemask
= 1 << i
;
2355 dst
->type
= brw_type_for_base_type(ir
->type
);
2357 /* Find other components that match the one we're about to
2358 * write. Emits fewer instructions for things like vec4(0.5,
2361 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2362 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2363 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2364 dst
->writemask
|= (1 << j
);
2366 /* u, i, and f storage all line up, so no need for a
2367 * switch case for comparing each type.
2369 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2370 dst
->writemask
|= (1 << j
);
2374 switch (ir
->type
->base_type
) {
2375 case GLSL_TYPE_FLOAT
:
2376 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2379 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2381 case GLSL_TYPE_UINT
:
2382 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2384 case GLSL_TYPE_BOOL
:
2385 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
] != 0 ? ~0 : 0)));
2388 unreachable("Non-float/uint/int/bool constant");
2391 remaining_writemask
&= ~dst
->writemask
;
2397 vec4_visitor::visit(ir_constant
*ir
)
2399 dst_reg dst
= dst_reg(this, ir
->type
);
2400 this->result
= src_reg(dst
);
2402 emit_constant_values(&dst
, ir
);
2406 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2408 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2409 ir
->actual_parameters
.get_head());
2410 ir_variable
*location
= deref
->variable_referenced();
2411 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2412 location
->data
.binding
);
2414 /* Calculate the surface offset */
2415 src_reg
offset(this, glsl_type::uint_type
);
2416 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2418 deref_array
->array_index
->accept(this);
2420 src_reg
tmp(this, glsl_type::uint_type
);
2421 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2422 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2424 offset
= location
->data
.atomic
.offset
;
2427 /* Emit the appropriate machine instruction */
2428 const char *callee
= ir
->callee
->function_name();
2429 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2431 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2432 emit_untyped_surface_read(surf_index
, dst
, offset
);
2434 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2435 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2436 src_reg(), src_reg());
2438 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2439 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2440 src_reg(), src_reg());
2443 brw_mark_surface_used(stage_prog_data
, surf_index
);
2447 vec4_visitor::visit(ir_call
*ir
)
2449 const char *callee
= ir
->callee
->function_name();
2451 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2452 !strcmp("__intrinsic_atomic_increment", callee
) ||
2453 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2454 visit_atomic_counter_intrinsic(ir
);
2456 unreachable("Unsupported intrinsic.");
2461 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
)
2463 vec4_instruction
*inst
=
2464 new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
,
2465 dst_reg(this, glsl_type::uvec4_type
));
2467 inst
->src
[1] = sampler
;
2471 if (devinfo
->gen
>= 9) {
2472 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
2473 vec4_instruction
*header_inst
= new(mem_ctx
)
2474 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
2475 dst_reg(MRF
, inst
->base_mrf
));
2480 inst
->header_size
= 1;
2481 param_base
= inst
->base_mrf
+ 1;
2484 param_base
= inst
->base_mrf
;
2487 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2488 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2489 int zero_mask
= 0xf & ~coord_mask
;
2491 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2494 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2498 return src_reg(inst
->dst
);
2502 is_high_sampler(const struct brw_device_info
*devinfo
, src_reg sampler
)
2504 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
2507 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2511 vec4_visitor::visit(ir_texture
*ir
)
2514 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2516 ir_rvalue
*nonconst_sampler_index
=
2517 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2519 /* Handle non-constant sampler array indexing */
2520 src_reg sampler_reg
;
2521 if (nonconst_sampler_index
) {
2522 /* The highest sampler which may be used by this operation is
2523 * the last element of the array. Mark it here, because the generator
2524 * doesn't have enough information to determine the bound.
2526 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2527 ->array
->type
->array_size();
2529 uint32_t max_used
= sampler
+ array_size
- 1;
2530 if (ir
->op
== ir_tg4
&& devinfo
->gen
< 8) {
2531 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2533 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2536 brw_mark_surface_used(&prog_data
->base
, max_used
);
2538 /* Emit code to evaluate the actual indexing expression */
2539 nonconst_sampler_index
->accept(this);
2540 src_reg
temp(this, glsl_type::uint_type
);
2541 emit(ADD(dst_reg(temp
), this->result
, src_reg(sampler
)));
2542 sampler_reg
= emit_uniformize(temp
);
2544 /* Single sampler, or constant array index; the indexing expression
2545 * is just an immediate.
2547 sampler_reg
= src_reg(sampler
);
2550 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2551 * emitting anything other than setting up the constant result.
2553 if (ir
->op
== ir_tg4
) {
2554 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2555 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2556 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2557 dst_reg
result(this, ir
->type
);
2558 this->result
= src_reg(result
);
2559 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2564 /* Should be lowered by do_lower_texture_projection */
2565 assert(!ir
->projector
);
2567 /* Should be lowered */
2568 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2570 /* Generate code to compute all the subexpression trees. This has to be
2571 * done before loading any values into MRFs for the sampler message since
2572 * generating these values may involve SEND messages that need the MRFs.
2575 if (ir
->coordinate
) {
2576 ir
->coordinate
->accept(this);
2577 coordinate
= this->result
;
2580 src_reg shadow_comparitor
;
2581 if (ir
->shadow_comparitor
) {
2582 ir
->shadow_comparitor
->accept(this);
2583 shadow_comparitor
= this->result
;
2586 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2587 src_reg offset_value
;
2588 if (has_nonconstant_offset
) {
2589 ir
->offset
->accept(this);
2590 offset_value
= src_reg(this->result
);
2593 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2594 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2597 lod
= src_reg(0.0f
);
2598 lod_type
= glsl_type::float_type
;
2603 ir
->lod_info
.lod
->accept(this);
2605 lod_type
= ir
->lod_info
.lod
->type
;
2607 case ir_query_levels
:
2609 lod_type
= glsl_type::int_type
;
2612 ir
->lod_info
.sample_index
->accept(this);
2613 sample_index
= this->result
;
2614 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2616 if (devinfo
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2617 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
2622 ir
->lod_info
.grad
.dPdx
->accept(this);
2623 dPdx
= this->result
;
2625 ir
->lod_info
.grad
.dPdy
->accept(this);
2626 dPdy
= this->result
;
2628 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2638 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2639 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2640 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2641 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2642 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2643 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2644 case ir_tg4
: opcode
= has_nonconstant_offset
2645 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2646 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2648 unreachable("TXB is not valid for vertex shaders.");
2650 unreachable("LOD is not valid for vertex shaders.");
2652 unreachable("Unrecognized tex op");
2655 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(
2656 opcode
, dst_reg(this, ir
->type
));
2658 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2660 brw_texture_offset(ir
->offset
->as_constant()->value
.i
,
2661 ir
->offset
->type
->vector_elements
);
2664 /* Stuff the channel select bits in the top of the texture offset */
2665 if (ir
->op
== ir_tg4
)
2666 inst
->offset
|= gather_channel(ir
, sampler
) << 16;
2668 /* The message header is necessary for:
2670 * - Gen9+ for selecting SIMD4x2
2672 * - Gather channel selection
2673 * - Sampler indices too large to fit in a 4-bit value.
2676 (devinfo
->gen
< 5 || devinfo
->gen
>= 9 ||
2677 inst
->offset
!= 0 || ir
->op
== ir_tg4
||
2678 is_high_sampler(devinfo
, sampler_reg
)) ? 1 : 0;
2680 inst
->mlen
= inst
->header_size
+ 1; /* always at least one */
2681 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2682 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2684 inst
->src
[1] = sampler_reg
;
2686 /* MRF for the first parameter */
2687 int param_base
= inst
->base_mrf
+ inst
->header_size
;
2689 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2690 int writemask
= devinfo
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2691 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2693 /* Load the coordinate */
2694 /* FINISHME: gl_clamp_mask and saturate */
2695 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2696 int zero_mask
= 0xf & ~coord_mask
;
2698 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2701 if (zero_mask
!= 0) {
2702 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2705 /* Load the shadow comparitor */
2706 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2707 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2709 shadow_comparitor
));
2713 /* Load the LOD info */
2714 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2716 if (devinfo
->gen
>= 5) {
2717 mrf
= param_base
+ 1;
2718 if (ir
->shadow_comparitor
) {
2719 writemask
= WRITEMASK_Y
;
2720 /* mlen already incremented */
2722 writemask
= WRITEMASK_X
;
2725 } else /* devinfo->gen == 4 */ {
2727 writemask
= WRITEMASK_W
;
2729 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2730 } else if (ir
->op
== ir_txf
) {
2731 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2732 } else if (ir
->op
== ir_txf_ms
) {
2733 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2735 if (devinfo
->gen
>= 7) {
2736 /* MCS data is in the first channel of `mcs`, but we need to get it into
2737 * the .y channel of the second vec4 of params, so replicate .x across
2738 * the whole vec4 and then mask off everything except .y
2740 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2741 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2745 } else if (ir
->op
== ir_txd
) {
2746 const glsl_type
*type
= lod_type
;
2748 if (devinfo
->gen
>= 5) {
2749 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2750 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2751 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2752 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2755 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2756 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2757 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2758 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2759 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2762 if (ir
->shadow_comparitor
) {
2763 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2764 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2765 shadow_comparitor
));
2768 } else /* devinfo->gen == 4 */ {
2769 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2770 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2773 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2774 if (ir
->shadow_comparitor
) {
2775 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2776 shadow_comparitor
));
2779 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2787 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2788 * spec requires layers.
2790 if (ir
->op
== ir_txs
) {
2791 glsl_type
const *type
= ir
->sampler
->type
;
2792 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2793 type
->sampler_array
) {
2794 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2795 writemask(inst
->dst
, WRITEMASK_Z
),
2796 src_reg(inst
->dst
), src_reg(6));
2800 if (devinfo
->gen
== 6 && ir
->op
== ir_tg4
) {
2801 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2804 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2808 * Apply workarounds for Gen6 gather with UINT/SINT
2811 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2816 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2817 dst_reg dst_f
= dst
;
2818 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2820 /* Convert from UNORM to UINT */
2821 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2822 emit(MOV(dst
, src_reg(dst_f
)));
2825 /* Reinterpret the UINT value as a signed INT value by
2826 * shifting the sign bit into place, then shifting back
2829 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2830 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2835 * Set up the gather channel based on the swizzle, for gather4.
2838 vec4_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2840 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2841 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2843 case SWIZZLE_X
: return 0;
2845 /* gather4 sampler is broken for green channel on RG32F --
2846 * we must ask for blue instead.
2848 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2851 case SWIZZLE_Z
: return 2;
2852 case SWIZZLE_W
: return 3;
2854 unreachable("Not reached"); /* zero, one swizzles handled already */
2859 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
)
2861 int s
= key
->tex
.swizzles
[sampler
];
2863 this->result
= src_reg(this, ir
->type
);
2864 dst_reg
swizzled_result(this->result
);
2866 if (ir
->op
== ir_query_levels
) {
2867 /* # levels is in .w */
2868 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2869 emit(MOV(swizzled_result
, orig_val
));
2873 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2874 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2875 emit(MOV(swizzled_result
, orig_val
));
2880 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2881 int swizzle
[4] = {0};
2883 for (int i
= 0; i
< 4; i
++) {
2884 switch (GET_SWZ(s
, i
)) {
2886 zero_mask
|= (1 << i
);
2889 one_mask
|= (1 << i
);
2892 copy_mask
|= (1 << i
);
2893 swizzle
[i
] = GET_SWZ(s
, i
);
2899 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2900 swizzled_result
.writemask
= copy_mask
;
2901 emit(MOV(swizzled_result
, orig_val
));
2905 swizzled_result
.writemask
= zero_mask
;
2906 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2910 swizzled_result
.writemask
= one_mask
;
2911 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2916 vec4_visitor::visit(ir_return
*)
2918 unreachable("not reached");
2922 vec4_visitor::visit(ir_discard
*)
2924 unreachable("not reached");
2928 vec4_visitor::visit(ir_if
*ir
)
2930 /* Don't point the annotation at the if statement, because then it plus
2931 * the then and else blocks get printed.
2933 this->base_ir
= ir
->condition
;
2935 if (devinfo
->gen
== 6) {
2938 enum brw_predicate predicate
;
2939 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2940 emit(IF(predicate
));
2943 visit_instructions(&ir
->then_instructions
);
2945 if (!ir
->else_instructions
.is_empty()) {
2946 this->base_ir
= ir
->condition
;
2947 emit(BRW_OPCODE_ELSE
);
2949 visit_instructions(&ir
->else_instructions
);
2952 this->base_ir
= ir
->condition
;
2953 emit(BRW_OPCODE_ENDIF
);
2957 vec4_visitor::visit(ir_emit_vertex
*)
2959 unreachable("not reached");
2963 vec4_visitor::visit(ir_end_primitive
*)
2965 unreachable("not reached");
2969 vec4_visitor::visit(ir_barrier
*)
2971 unreachable("not reached");
2975 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2976 dst_reg dst
, src_reg offset
,
2977 src_reg src0
, src_reg src1
)
2981 /* Set the atomic operation offset. */
2982 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2985 /* Set the atomic operation arguments. */
2986 if (src0
.file
!= BAD_FILE
) {
2987 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2991 if (src1
.file
!= BAD_FILE
) {
2992 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2996 /* Emit the instruction. Note that this maps to the normal SIMD8
2997 * untyped atomic message on Ivy Bridge, but that's OK because
2998 * unused channels will be masked out.
3000 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
3002 src_reg(surf_index
), src_reg(atomic_op
));
3007 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
3010 /* Set the surface read offset. */
3011 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
3013 /* Emit the instruction. Note that this maps to the normal SIMD8
3014 * untyped surface read message, but that's OK because unused
3015 * channels will be masked out.
3017 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
,
3019 src_reg(surf_index
), src_reg(1));
3024 vec4_visitor::emit_ndc_computation()
3026 /* Get the position */
3027 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
3029 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
3030 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
3031 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
3033 current_annotation
= "NDC";
3034 dst_reg ndc_w
= ndc
;
3035 ndc_w
.writemask
= WRITEMASK_W
;
3036 src_reg pos_w
= pos
;
3037 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
3038 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
3040 dst_reg ndc_xyz
= ndc
;
3041 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
3043 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
3047 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
3049 if (devinfo
->gen
< 6 &&
3050 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
3051 key
->userclip_active
|| devinfo
->has_negative_rhw_bug
)) {
3052 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
3053 dst_reg header1_w
= header1
;
3054 header1_w
.writemask
= WRITEMASK_W
;
3056 emit(MOV(header1
, 0u));
3058 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3059 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
3061 current_annotation
= "Point size";
3062 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
3063 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
3066 if (key
->userclip_active
) {
3067 current_annotation
= "Clipping flags";
3068 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
3069 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
3071 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3072 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
3073 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
3075 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3076 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
3077 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
3078 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
3081 /* i965 clipping workaround:
3082 * 1) Test for -ve rhw
3084 * set ndc = (0,0,0,0)
3087 * Later, clipping will detect ucp[6] and ensure the primitive is
3088 * clipped against all fixed planes.
3090 if (devinfo
->has_negative_rhw_bug
) {
3091 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
3092 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
3093 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
3094 vec4_instruction
*inst
;
3095 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
3096 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3097 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
3098 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3101 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
3102 } else if (devinfo
->gen
< 6) {
3103 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
3105 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
3106 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3107 dst_reg reg_w
= reg
;
3108 reg_w
.writemask
= WRITEMASK_W
;
3109 emit(MOV(reg_w
, src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
3111 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
3112 dst_reg reg_y
= reg
;
3113 reg_y
.writemask
= WRITEMASK_Y
;
3114 reg_y
.type
= BRW_REGISTER_TYPE_D
;
3115 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
3117 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
3118 dst_reg reg_z
= reg
;
3119 reg_z
.writemask
= WRITEMASK_Z
;
3120 reg_z
.type
= BRW_REGISTER_TYPE_D
;
3121 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
3127 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
3129 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3131 * "If a linked set of shaders forming the vertex stage contains no
3132 * static write to gl_ClipVertex or gl_ClipDistance, but the
3133 * application has requested clipping against user clip planes through
3134 * the API, then the coordinate written to gl_Position is used for
3135 * comparison against the user clip planes."
3137 * This function is only called if the shader didn't write to
3138 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3139 * if the user wrote to it; otherwise we use gl_Position.
3141 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3142 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
3143 clip_vertex
= VARYING_SLOT_POS
;
3146 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
3148 reg
.writemask
= 1 << i
;
3150 src_reg(output_reg
[clip_vertex
]),
3151 src_reg(this->userplane
[i
+ offset
])));
3156 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
3158 assert (varying
< VARYING_SLOT_MAX
);
3159 reg
.type
= output_reg
[varying
].type
;
3160 current_annotation
= output_reg_annotation
[varying
];
3161 /* Copy the register, saturating if necessary */
3162 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
3166 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
3168 reg
.type
= BRW_REGISTER_TYPE_F
;
3171 case VARYING_SLOT_PSIZ
:
3173 /* PSIZ is always in slot 0, and is coupled with other flags. */
3174 current_annotation
= "indices, point width, clip flags";
3175 emit_psiz_and_flags(reg
);
3178 case BRW_VARYING_SLOT_NDC
:
3179 current_annotation
= "NDC";
3180 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
3182 case VARYING_SLOT_POS
:
3183 current_annotation
= "gl_Position";
3184 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
3186 case VARYING_SLOT_EDGE
:
3187 /* This is present when doing unfilled polygons. We're supposed to copy
3188 * the edge flag from the user-provided vertex array
3189 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3190 * of that attribute (starts as 1.0f). This is then used in clipping to
3191 * determine which edges should be drawn as wireframe.
3193 current_annotation
= "edge flag";
3194 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3195 glsl_type::float_type
, WRITEMASK_XYZW
))));
3197 case BRW_VARYING_SLOT_PAD
:
3198 /* No need to write to this slot */
3200 case VARYING_SLOT_COL0
:
3201 case VARYING_SLOT_COL1
:
3202 case VARYING_SLOT_BFC0
:
3203 case VARYING_SLOT_BFC1
: {
3204 /* These built-in varyings are only supported in compatibility mode,
3205 * and we only support GS in core profile. So, this must be a vertex
3208 assert(stage
== MESA_SHADER_VERTEX
);
3209 vec4_instruction
*inst
= emit_generic_urb_slot(reg
, varying
);
3210 if (((struct brw_vs_prog_key
*) key
)->clamp_vertex_color
)
3211 inst
->saturate
= true;
3216 emit_generic_urb_slot(reg
, varying
);
3222 align_interleaved_urb_mlen(const struct brw_device_info
*devinfo
, int mlen
)
3224 if (devinfo
->gen
>= 6) {
3225 /* URB data written (does not include the message header reg) must
3226 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3227 * section 5.4.3.2.2: URB_INTERLEAVED.
3229 * URB entries are allocated on a multiple of 1024 bits, so an
3230 * extra 128 bits written here to make the end align to 256 is
3233 if ((mlen
% 2) != 1)
3242 * Generates the VUE payload plus the necessary URB write instructions to
3245 * The VUE layout is documented in Volume 2a.
3248 vec4_visitor::emit_vertex()
3250 /* MRF 0 is reserved for the debugger, so start with message header
3255 /* In the process of generating our URB write message contents, we
3256 * may need to unspill a register or load from an array. Those
3257 * reads would use MRFs 14-15.
3259 int max_usable_mrf
= 13;
3261 /* The following assertion verifies that max_usable_mrf causes an
3262 * even-numbered amount of URB write data, which will meet gen6's
3263 * requirements for length alignment.
3265 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3267 /* First mrf is the g0-based message header containing URB handles and
3270 emit_urb_write_header(mrf
++);
3272 if (devinfo
->gen
< 6) {
3273 emit_ndc_computation();
3276 /* Lower legacy ff and ClipVertex clipping to clip distances */
3277 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3278 current_annotation
= "user clip distances";
3280 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3281 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3283 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3284 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3287 /* We may need to split this up into several URB writes, so do them in a
3291 bool complete
= false;
3293 /* URB offset is in URB row increments, and each of our MRFs is half of
3294 * one of those, since we're doing interleaved writes.
3296 int offset
= slot
/ 2;
3299 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3300 emit_urb_slot(dst_reg(MRF
, mrf
++),
3301 prog_data
->vue_map
.slot_to_varying
[slot
]);
3303 /* If this was max_usable_mrf, we can't fit anything more into this
3306 if (mrf
> max_usable_mrf
) {
3312 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3313 current_annotation
= "URB write";
3314 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3315 inst
->base_mrf
= base_mrf
;
3316 inst
->mlen
= align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
);
3317 inst
->offset
+= offset
;
3323 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3324 src_reg
*reladdr
, int reg_offset
)
3326 /* Because we store the values to scratch interleaved like our
3327 * vertex data, we need to scale the vec4 index by 2.
3329 int message_header_scale
= 2;
3331 /* Pre-gen6, the message header uses byte offsets instead of vec4
3332 * (16-byte) offset units.
3334 if (devinfo
->gen
< 6)
3335 message_header_scale
*= 16;
3338 src_reg index
= src_reg(this, glsl_type::int_type
);
3340 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3341 src_reg(reg_offset
)));
3342 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3343 src_reg(message_header_scale
)));
3347 return src_reg(reg_offset
* message_header_scale
);
3352 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3353 src_reg
*reladdr
, int reg_offset
)
3356 src_reg index
= src_reg(this, glsl_type::int_type
);
3358 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3359 src_reg(reg_offset
)));
3361 /* Pre-gen6, the message header uses byte offsets instead of vec4
3362 * (16-byte) offset units.
3364 if (devinfo
->gen
< 6) {
3365 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3369 } else if (devinfo
->gen
>= 8) {
3370 /* Store the offset in a GRF so we can send-from-GRF. */
3371 src_reg offset
= src_reg(this, glsl_type::int_type
);
3372 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3375 int message_header_scale
= devinfo
->gen
< 6 ? 16 : 1;
3376 return src_reg(reg_offset
* message_header_scale
);
3381 * Emits an instruction before @inst to load the value named by @orig_src
3382 * from scratch space at @base_offset to @temp.
3384 * @base_offset is measured in 32-byte units (the size of a register).
3387 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3388 dst_reg temp
, src_reg orig_src
,
3391 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3392 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3395 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3399 * Emits an instruction after @inst to store the value to be written
3400 * to @orig_dst to scratch space at @base_offset, from @temp.
3402 * @base_offset is measured in 32-byte units (the size of a register).
3405 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3408 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3409 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3412 /* Create a temporary register to store *inst's result in.
3414 * We have to be careful in MOVing from our temporary result register in
3415 * the scratch write. If we swizzle from channels of the temporary that
3416 * weren't initialized, it will confuse live interval analysis, which will
3417 * make spilling fail to make progress.
3419 const src_reg temp
= swizzle(retype(src_reg(this, glsl_type::vec4_type
),
3421 brw_swizzle_for_mask(inst
->dst
.writemask
));
3422 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3423 inst
->dst
.writemask
));
3424 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3425 write
->predicate
= inst
->predicate
;
3426 write
->ir
= inst
->ir
;
3427 write
->annotation
= inst
->annotation
;
3428 inst
->insert_after(block
, write
);
3430 inst
->dst
.file
= temp
.file
;
3431 inst
->dst
.reg
= temp
.reg
;
3432 inst
->dst
.reg_offset
= temp
.reg_offset
;
3433 inst
->dst
.reladdr
= NULL
;
3437 * Checks if \p src and/or \p src.reladdr require a scratch read, and if so,
3438 * adds the scratch read(s) before \p inst. The function also checks for
3439 * recursive reladdr scratch accesses, issuing the corresponding scratch
3440 * loads and rewriting reladdr references accordingly.
3442 * \return \p src if it did not require a scratch load, otherwise, the
3443 * register holding the result of the scratch load that the caller should
3444 * use to rewrite src.
3447 vec4_visitor::emit_resolve_reladdr(int scratch_loc
[], bblock_t
*block
,
3448 vec4_instruction
*inst
, src_reg src
)
3450 /* Resolve recursive reladdr scratch access by calling ourselves
3454 *src
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3457 /* Now handle scratch access on src */
3458 if (src
.file
== GRF
&& scratch_loc
[src
.reg
] != -1) {
3459 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3460 emit_scratch_read(block
, inst
, temp
, src
, scratch_loc
[src
.reg
]);
3462 src
.reg_offset
= temp
.reg_offset
;
3470 * We can't generally support array access in GRF space, because a
3471 * single instruction's destination can only span 2 contiguous
3472 * registers. So, we send all GRF arrays that get variable index
3473 * access to scratch space.
3476 vec4_visitor::move_grf_array_access_to_scratch()
3478 int scratch_loc
[this->alloc
.count
];
3479 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3481 /* First, calculate the set of virtual GRFs that need to be punted
3482 * to scratch due to having any array access on them, and where in
3485 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3486 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
) {
3487 if (scratch_loc
[inst
->dst
.reg
] == -1) {
3488 scratch_loc
[inst
->dst
.reg
] = last_scratch
;
3489 last_scratch
+= this->alloc
.sizes
[inst
->dst
.reg
];
3492 for (src_reg
*iter
= inst
->dst
.reladdr
;
3494 iter
= iter
->reladdr
) {
3495 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3496 scratch_loc
[iter
->reg
] = last_scratch
;
3497 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3502 for (int i
= 0 ; i
< 3; i
++) {
3503 for (src_reg
*iter
= &inst
->src
[i
];
3505 iter
= iter
->reladdr
) {
3506 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3507 scratch_loc
[iter
->reg
] = last_scratch
;
3508 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3514 /* Now, for anything that will be accessed through scratch, rewrite
3515 * it to load/store. Note that this is a _safe list walk, because
3516 * we may generate a new scratch_write instruction after the one
3519 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3520 /* Set up the annotation tracking for new generated instructions. */
3522 current_annotation
= inst
->annotation
;
3524 /* First handle scratch access on the dst. Notice we have to handle
3525 * the case where the dst's reladdr also points to scratch space.
3527 if (inst
->dst
.reladdr
)
3528 *inst
->dst
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3529 *inst
->dst
.reladdr
);
3531 /* Now that we have handled any (possibly recursive) reladdr scratch
3532 * accesses for dst we can safely do the scratch write for dst itself
3534 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1)
3535 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3537 /* Now handle scratch access on any src. In this case, since inst->src[i]
3538 * already is a src_reg, we can just call emit_resolve_reladdr with
3539 * inst->src[i] and it will take care of handling scratch loads for
3540 * both src and src.reladdr (recursively).
3542 for (int i
= 0 ; i
< 3; i
++) {
3543 inst
->src
[i
] = emit_resolve_reladdr(scratch_loc
, block
, inst
,
3550 * Emits an instruction before @inst to load the value named by @orig_src
3551 * from the pull constant buffer (surface) at @base_offset to @temp.
3554 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3555 dst_reg temp
, src_reg orig_src
,
3558 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3559 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3560 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3563 emit_pull_constant_load_reg(temp
,
3570 * Implements array access of uniforms by inserting a
3571 * PULL_CONSTANT_LOAD instruction.
3573 * Unlike temporary GRF array access (where we don't support it due to
3574 * the difficulty of doing relative addressing on instruction
3575 * destinations), we could potentially do array access of uniforms
3576 * that were loaded in GRF space as push constants. In real-world
3577 * usage we've seen, though, the arrays being used are always larger
3578 * than we could load as push constants, so just always move all
3579 * uniform array access out to a pull constant buffer.
3582 vec4_visitor::move_uniform_array_access_to_pull_constants()
3584 int pull_constant_loc
[this->uniforms
];
3585 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3586 bool nested_reladdr
;
3588 /* Walk through and find array access of uniforms. Put a copy of that
3589 * uniform in the pull constant buffer.
3591 * Note that we don't move constant-indexed accesses to arrays. No
3592 * testing has been done of the performance impact of this choice.
3595 nested_reladdr
= false;
3597 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3598 for (int i
= 0 ; i
< 3; i
++) {
3599 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3602 int uniform
= inst
->src
[i
].reg
;
3604 if (inst
->src
[i
].reladdr
->reladdr
)
3605 nested_reladdr
= true; /* will need another pass */
3607 /* If this array isn't already present in the pull constant buffer,
3610 if (pull_constant_loc
[uniform
] == -1) {
3611 const gl_constant_value
**values
=
3612 &stage_prog_data
->param
[uniform
* 4];
3614 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3616 assert(uniform
< uniform_array_size
);
3617 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3618 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3623 /* Set up the annotation tracking for new generated instructions. */
3625 current_annotation
= inst
->annotation
;
3627 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3629 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3630 pull_constant_loc
[uniform
]);
3632 inst
->src
[i
].file
= temp
.file
;
3633 inst
->src
[i
].reg
= temp
.reg
;
3634 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3635 inst
->src
[i
].reladdr
= NULL
;
3638 } while (nested_reladdr
);
3640 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3641 * no need to track them as larger-than-vec4 objects. This will be
3642 * relied on in cutting out unused uniform vectors from push
3645 split_uniform_registers();
3649 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3651 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3655 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3656 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3661 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3663 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3664 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3667 vec4_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, src_reg
*reg
)
3669 assert(devinfo
->gen
<= 5);
3671 if (!rvalue
->type
->is_boolean())
3674 src_reg and_result
= src_reg(this, rvalue
->type
);
3675 src_reg neg_result
= src_reg(this, rvalue
->type
);
3676 emit(AND(dst_reg(and_result
), *reg
, src_reg(1)));
3677 emit(MOV(dst_reg(neg_result
), negate(and_result
)));
3681 vec4_visitor::vec4_visitor(const struct brw_compiler
*compiler
,
3683 struct gl_program
*prog
,
3684 const struct brw_vue_prog_key
*key
,
3685 struct brw_vue_prog_data
*prog_data
,
3686 struct gl_shader_program
*shader_prog
,
3687 gl_shader_stage stage
,
3690 int shader_time_index
)
3691 : backend_shader(compiler
, log_data
, mem_ctx
,
3692 shader_prog
, prog
, &prog_data
->base
, stage
),
3694 prog_data(prog_data
),
3695 sanity_param_count(0),
3697 first_non_payload_grf(0),
3698 need_all_constants_in_pull_buffer(false),
3699 no_spills(no_spills
),
3700 shader_time_index(shader_time_index
),
3703 this->failed
= false;
3705 this->base_ir
= NULL
;
3706 this->current_annotation
= NULL
;
3707 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3709 this->variable_ht
= hash_table_ctor(0,
3710 hash_table_pointer_hash
,
3711 hash_table_pointer_compare
);
3713 this->virtual_grf_start
= NULL
;
3714 this->virtual_grf_end
= NULL
;
3715 this->live_intervals
= NULL
;
3717 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3721 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3722 * at least one. See setup_uniforms() in brw_vec4.cpp.
3724 this->uniform_array_size
= 1;
3726 this->uniform_array_size
=
3727 MAX2(DIV_ROUND_UP(stage_prog_data
->nr_params
, 4), 1);
3730 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3731 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3734 vec4_visitor::~vec4_visitor()
3736 hash_table_dtor(this->variable_ht
);
3741 vec4_visitor::fail(const char *format
, ...)
3751 va_start(va
, format
);
3752 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3754 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
3756 this->fail_msg
= msg
;
3758 if (debug_enabled
) {
3759 fprintf(stderr
, "%s", msg
);
3763 } /* namespace brw */