2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
32 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
33 enum opcode opcode
, dst_reg dst
,
34 src_reg src0
, src_reg src1
, src_reg src2
)
36 this->opcode
= opcode
;
41 this->saturate
= false;
42 this->force_writemask_all
= false;
43 this->no_dd_clear
= false;
44 this->no_dd_check
= false;
45 this->writes_accumulator
= false;
46 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
48 this->texture_offset
= 0;
50 this->shadow_compare
= false;
51 this->ir
= v
->base_ir
;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_present
= false;
57 this->annotation
= v
->current_annotation
;
61 vec4_visitor::emit(vec4_instruction
*inst
)
63 this->instructions
.push_tail(inst
);
69 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
71 new_inst
->ir
= inst
->ir
;
72 new_inst
->annotation
= inst
->annotation
;
74 inst
->insert_before(new_inst
);
80 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
81 src_reg src0
, src_reg src1
, src_reg src2
)
83 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
89 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
91 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
95 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
97 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
101 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
)
103 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
));
107 vec4_visitor::emit(enum opcode opcode
)
109 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
114 vec4_visitor::op(dst_reg dst, src_reg src0) \
116 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
122 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
124 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
128 #define ALU2_ACC(op) \
130 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
132 vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, \
133 BRW_OPCODE_##op, dst, src0, src1); \
134 inst->writes_accumulator = true; \
140 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1, src_reg src2)\
142 assert(brw->gen >= 6); \
143 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
180 /** Gen4 predicated IF. */
182 vec4_visitor::IF(uint32_t predicate
)
184 vec4_instruction
*inst
;
186 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
187 inst
->predicate
= predicate
;
192 /** Gen6 IF with embedded comparison. */
194 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
196 assert(brw
->gen
== 6);
198 vec4_instruction
*inst
;
200 resolve_ud_negate(&src0
);
201 resolve_ud_negate(&src1
);
203 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
205 inst
->conditional_mod
= condition
;
211 * CMP: Sets the low bit of the destination channels with the result
212 * of the comparison, while the upper bits are undefined, and updates
213 * the flag register with the packed 16 bits of the result.
216 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
218 vec4_instruction
*inst
;
220 /* original gen4 does type conversion to the destination type
221 * before before comparison, producing garbage results for floating
225 dst
.type
= src0
.type
;
226 if (dst
.file
== HW_REG
)
227 dst
.fixed_hw_reg
.type
= dst
.type
;
230 resolve_ud_negate(&src0
);
231 resolve_ud_negate(&src1
);
233 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
234 inst
->conditional_mod
= condition
;
240 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
242 vec4_instruction
*inst
;
244 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_READ
,
253 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
255 vec4_instruction
*inst
;
257 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
266 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
268 static enum opcode dot_opcodes
[] = {
269 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
272 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
276 vec4_visitor::fix_3src_operand(src_reg src
)
278 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
279 * able to use vertical stride of zero to replicate the vec4 uniform, like
281 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
283 * But you can't, since vertical stride is always four in three-source
284 * instructions. Instead, insert a MOV instruction to do the replication so
285 * that the three-source instruction can consume it.
288 /* The MOV is only needed if the source is a uniform or immediate. */
289 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
292 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
295 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
296 expanded
.type
= src
.type
;
297 emit(MOV(expanded
, src
));
298 return src_reg(expanded
);
302 vec4_visitor::fix_math_operand(src_reg src
)
304 /* The gen6 math instruction ignores the source modifiers --
305 * swizzle, abs, negate, and at least some parts of the register
306 * region description.
308 * Rather than trying to enumerate all these cases, *always* expand the
309 * operand to a temp GRF for gen6.
311 * For gen7, keep the operand as-is, except if immediate, which gen7 still
315 if (brw
->gen
== 7 && src
.file
!= IMM
)
318 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
319 expanded
.type
= src
.type
;
320 emit(MOV(expanded
, src
));
321 return src_reg(expanded
);
325 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
327 src
= fix_math_operand(src
);
329 if (dst
.writemask
!= WRITEMASK_XYZW
) {
330 /* The gen6 math instruction must be align1, so we can't do
333 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
335 emit(opcode
, temp_dst
, src
);
337 emit(MOV(dst
, src_reg(temp_dst
)));
339 emit(opcode
, dst
, src
);
344 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
346 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
352 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
355 case SHADER_OPCODE_RCP
:
356 case SHADER_OPCODE_RSQ
:
357 case SHADER_OPCODE_SQRT
:
358 case SHADER_OPCODE_EXP2
:
359 case SHADER_OPCODE_LOG2
:
360 case SHADER_OPCODE_SIN
:
361 case SHADER_OPCODE_COS
:
364 assert(!"not reached: bad math opcode");
369 return emit_math1_gen6(opcode
, dst
, src
);
371 return emit_math1_gen4(opcode
, dst
, src
);
376 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
377 dst_reg dst
, src_reg src0
, src_reg src1
)
379 src0
= fix_math_operand(src0
);
380 src1
= fix_math_operand(src1
);
382 if (dst
.writemask
!= WRITEMASK_XYZW
) {
383 /* The gen6 math instruction must be align1, so we can't do
386 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
387 temp_dst
.type
= dst
.type
;
389 emit(opcode
, temp_dst
, src0
, src1
);
391 emit(MOV(dst
, src_reg(temp_dst
)));
393 emit(opcode
, dst
, src0
, src1
);
398 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
399 dst_reg dst
, src_reg src0
, src_reg src1
)
401 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
407 vec4_visitor::emit_math(enum opcode opcode
,
408 dst_reg dst
, src_reg src0
, src_reg src1
)
411 case SHADER_OPCODE_POW
:
412 case SHADER_OPCODE_INT_QUOTIENT
:
413 case SHADER_OPCODE_INT_REMAINDER
:
416 assert(!"not reached: unsupported binary math opcode");
421 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
423 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
428 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
431 assert(!"ir_unop_pack_half_2x16 should be lowered");
433 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
434 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
436 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
438 * Because this instruction does not have a 16-bit floating-point type,
439 * the destination data type must be Word (W).
441 * The destination must be DWord-aligned and specify a horizontal stride
442 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
443 * each destination channel and the upper word is not modified.
445 * The above restriction implies that the f32to16 instruction must use
446 * align1 mode, because only in align1 mode is it possible to specify
447 * horizontal stride. We choose here to defy the hardware docs and emit
448 * align16 instructions.
450 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
451 * instructions. I was partially successful in that the code passed all
452 * tests. However, the code was dubiously correct and fragile, and the
453 * tests were not harsh enough to probe that frailty. Not trusting the
454 * code, I chose instead to remain in align16 mode in defiance of the hw
457 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
458 * simulator, emitting a f32to16 in align16 mode with UD as destination
459 * data type is safe. The behavior differs from that specified in the PRM
460 * in that the upper word of each destination channel is cleared to 0.
463 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
464 src_reg
tmp_src(tmp_dst
);
467 /* Verify the undocumented behavior on which the following instructions
468 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
469 * then the result of the bit-or instruction below will be incorrect.
471 * You should inspect the disasm output in order to verify that the MOV is
472 * not optimized away.
474 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
477 /* Give tmp the form below, where "." means untouched.
480 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
482 * That the upper word of each write-channel be 0 is required for the
483 * following bit-shift and bit-or instructions to work. Note that this
484 * relies on the undocumented hardware behavior mentioned above.
486 tmp_dst
.writemask
= WRITEMASK_XY
;
487 emit(F32TO16(tmp_dst
, src0
));
489 /* Give the write-channels of dst the form:
492 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
493 emit(SHL(dst
, tmp_src
, src_reg(16u)));
495 /* Finally, give the write-channels of dst the form of packHalf2x16's
499 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
500 emit(OR(dst
, src_reg(dst
), tmp_src
));
504 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
507 assert(!"ir_unop_unpack_half_2x16 should be lowered");
509 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
510 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
512 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
514 * Because this instruction does not have a 16-bit floating-point type,
515 * the source data type must be Word (W). The destination type must be
518 * To use W as the source data type, we must adjust horizontal strides,
519 * which is only possible in align1 mode. All my [chadv] attempts at
520 * emitting align1 instructions for unpackHalf2x16 failed to pass the
521 * Piglit tests, so I gave up.
523 * I've verified that, on gen7 hardware and the simulator, it is safe to
524 * emit f16to32 in align16 mode with UD as source data type.
527 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
528 src_reg
tmp_src(tmp_dst
);
530 tmp_dst
.writemask
= WRITEMASK_X
;
531 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
533 tmp_dst
.writemask
= WRITEMASK_Y
;
534 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
536 dst
.writemask
= WRITEMASK_XY
;
537 emit(F16TO32(dst
, tmp_src
));
541 vec4_visitor::visit_instructions(const exec_list
*list
)
543 foreach_list(node
, list
) {
544 ir_instruction
*ir
= (ir_instruction
*)node
;
553 type_size(const struct glsl_type
*type
)
558 switch (type
->base_type
) {
561 case GLSL_TYPE_FLOAT
:
563 if (type
->is_matrix()) {
564 return type
->matrix_columns
;
566 /* Regardless of size of vector, it gets a vec4. This is bad
567 * packing for things like floats, but otherwise arrays become a
568 * mess. Hopefully a later pass over the code can pack scalars
569 * down if appropriate.
573 case GLSL_TYPE_ARRAY
:
574 assert(type
->length
> 0);
575 return type_size(type
->fields
.array
) * type
->length
;
576 case GLSL_TYPE_STRUCT
:
578 for (i
= 0; i
< type
->length
; i
++) {
579 size
+= type_size(type
->fields
.structure
[i
].type
);
582 case GLSL_TYPE_SAMPLER
:
583 /* Samplers take up one slot in UNIFORMS[], but they're baked in
587 case GLSL_TYPE_ATOMIC_UINT
:
589 case GLSL_TYPE_IMAGE
:
591 case GLSL_TYPE_ERROR
:
592 case GLSL_TYPE_INTERFACE
:
601 vec4_visitor::virtual_grf_alloc(int size
)
603 if (virtual_grf_array_size
<= virtual_grf_count
) {
604 if (virtual_grf_array_size
== 0)
605 virtual_grf_array_size
= 16;
607 virtual_grf_array_size
*= 2;
608 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
609 virtual_grf_array_size
);
610 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
611 virtual_grf_array_size
);
613 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
614 virtual_grf_reg_count
+= size
;
615 virtual_grf_sizes
[virtual_grf_count
] = size
;
616 return virtual_grf_count
++;
619 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
624 this->reg
= v
->virtual_grf_alloc(type_size(type
));
626 if (type
->is_array() || type
->is_record()) {
627 this->swizzle
= BRW_SWIZZLE_NOOP
;
629 this->swizzle
= swizzle_for_size(type
->vector_elements
);
632 this->type
= brw_type_for_base_type(type
);
635 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
640 this->reg
= v
->virtual_grf_alloc(type_size(type
));
642 if (type
->is_array() || type
->is_record()) {
643 this->writemask
= WRITEMASK_XYZW
;
645 this->writemask
= (1 << type
->vector_elements
) - 1;
648 this->type
= brw_type_for_base_type(type
);
651 /* Our support for uniforms is piggy-backed on the struct
652 * gl_fragment_program, because that's where the values actually
653 * get stored, rather than in some global gl_shader_program uniform
657 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
659 int namelen
= strlen(ir
->name
);
661 /* The data for our (non-builtin) uniforms is stored in a series of
662 * gl_uniform_driver_storage structs for each subcomponent that
663 * glGetUniformLocation() could name. We know it's been set up in the same
664 * order we'd walk the type, so walk the list of storage and find anything
665 * with our name, or the prefix of a component that starts with our name.
667 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
668 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
670 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
671 (storage
->name
[namelen
] != 0 &&
672 storage
->name
[namelen
] != '.' &&
673 storage
->name
[namelen
] != '[')) {
677 gl_constant_value
*components
= storage
->storage
;
678 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
679 storage
->type
->matrix_columns
);
681 for (unsigned s
= 0; s
< vector_count
; s
++) {
682 assert(uniforms
< uniform_array_size
);
683 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
686 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
687 stage_prog_data
->param
[uniforms
* 4 + i
] = &components
->f
;
691 static float zero
= 0;
692 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
701 vec4_visitor::setup_uniform_clipplane_values()
703 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
705 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
706 assert(this->uniforms
< uniform_array_size
);
707 this->uniform_vector_size
[this->uniforms
] = 4;
708 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
709 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
710 for (int j
= 0; j
< 4; ++j
) {
711 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
717 /* Our support for builtin uniforms is even scarier than non-builtin.
718 * It sits on top of the PROG_STATE_VAR parameters that are
719 * automatically updated from GL context state.
722 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
724 const ir_state_slot
*const slots
= ir
->state_slots
;
725 assert(ir
->state_slots
!= NULL
);
727 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
728 /* This state reference has already been setup by ir_to_mesa,
729 * but we'll get the same index back here. We can reference
730 * ParameterValues directly, since unlike brw_fs.cpp, we never
731 * add new state references during compile.
733 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
734 (gl_state_index
*)slots
[i
].tokens
);
735 float *values
= &this->prog
->Parameters
->ParameterValues
[index
][0].f
;
737 assert(this->uniforms
< uniform_array_size
);
738 this->uniform_vector_size
[this->uniforms
] = 0;
739 /* Add each of the unique swizzled channels of the element.
740 * This will end up matching the size of the glsl_type of this field.
743 for (unsigned int j
= 0; j
< 4; j
++) {
744 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
747 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
748 assert(this->uniforms
< uniform_array_size
);
749 if (swiz
<= last_swiz
)
750 this->uniform_vector_size
[this->uniforms
]++;
757 vec4_visitor::variable_storage(ir_variable
*var
)
759 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
763 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
)
765 ir_expression
*expr
= ir
->as_expression();
767 *predicate
= BRW_PREDICATE_NORMAL
;
771 vec4_instruction
*inst
;
773 assert(expr
->get_num_operands() <= 2);
774 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
775 expr
->operands
[i
]->accept(this);
776 op
[i
] = this->result
;
778 resolve_ud_negate(&op
[i
]);
781 switch (expr
->operation
) {
782 case ir_unop_logic_not
:
783 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
784 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
787 case ir_binop_logic_xor
:
788 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
789 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
792 case ir_binop_logic_or
:
793 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
794 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
797 case ir_binop_logic_and
:
798 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
799 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
804 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
806 inst
= emit(MOV(dst_null_f(), op
[0]));
807 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
813 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
815 inst
= emit(MOV(dst_null_d(), op
[0]));
816 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
820 case ir_binop_all_equal
:
821 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
822 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
825 case ir_binop_any_nequal
:
826 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
827 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
831 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
832 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
835 case ir_binop_greater
:
836 case ir_binop_gequal
:
838 case ir_binop_lequal
:
840 case ir_binop_nequal
:
841 emit(CMP(dst_null_d(), op
[0], op
[1],
842 brw_conditional_for_comparison(expr
->operation
)));
846 assert(!"not reached");
854 resolve_ud_negate(&this->result
);
857 vec4_instruction
*inst
= emit(AND(dst_null_d(),
858 this->result
, src_reg(1)));
859 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
861 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
862 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
867 * Emit a gen6 IF statement with the comparison folded into the IF
871 vec4_visitor::emit_if_gen6(ir_if
*ir
)
873 ir_expression
*expr
= ir
->condition
->as_expression();
879 assert(expr
->get_num_operands() <= 2);
880 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
881 expr
->operands
[i
]->accept(this);
882 op
[i
] = this->result
;
885 switch (expr
->operation
) {
886 case ir_unop_logic_not
:
887 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
890 case ir_binop_logic_xor
:
891 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
894 case ir_binop_logic_or
:
895 temp
= dst_reg(this, glsl_type::bool_type
);
896 emit(OR(temp
, op
[0], op
[1]));
897 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
900 case ir_binop_logic_and
:
901 temp
= dst_reg(this, glsl_type::bool_type
);
902 emit(AND(temp
, op
[0], op
[1]));
903 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
907 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
911 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
914 case ir_binop_greater
:
915 case ir_binop_gequal
:
917 case ir_binop_lequal
:
919 case ir_binop_nequal
:
920 emit(IF(op
[0], op
[1],
921 brw_conditional_for_comparison(expr
->operation
)));
924 case ir_binop_all_equal
:
925 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
926 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
929 case ir_binop_any_nequal
:
930 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
931 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
935 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
936 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
940 assert(!"not reached");
941 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
947 ir
->condition
->accept(this);
949 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
953 vec4_visitor::visit(ir_variable
*ir
)
957 if (variable_storage(ir
))
960 switch (ir
->data
.mode
) {
961 case ir_var_shader_in
:
962 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
965 case ir_var_shader_out
:
966 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
968 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
969 output_reg
[ir
->data
.location
+ i
] = *reg
;
970 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
971 output_reg
[ir
->data
.location
+ i
].type
=
972 brw_type_for_base_type(ir
->type
->get_scalar_type());
973 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
978 case ir_var_temporary
:
979 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
983 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
985 /* Thanks to the lower_ubo_reference pass, we will see only
986 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
987 * variables, so no need for them to be in variable_ht.
989 * Atomic counters take no uniform storage, no need to do
992 if (ir
->is_in_uniform_block() || ir
->type
->contains_atomic())
995 /* Track how big the whole uniform variable is, in case we need to put a
996 * copy of its data into pull constants for array access.
998 assert(this->uniforms
< uniform_array_size
);
999 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1001 if (!strncmp(ir
->name
, "gl_", 3)) {
1002 setup_builtin_uniform_values(ir
);
1004 setup_uniform_values(ir
);
1008 case ir_var_system_value
:
1009 reg
= make_reg_for_system_value(ir
);
1013 assert(!"not reached");
1016 reg
->type
= brw_type_for_base_type(ir
->type
);
1017 hash_table_insert(this->variable_ht
, reg
, ir
);
1021 vec4_visitor::visit(ir_loop
*ir
)
1023 /* We don't want debugging output to print the whole body of the
1024 * loop as the annotation.
1026 this->base_ir
= NULL
;
1028 emit(BRW_OPCODE_DO
);
1030 visit_instructions(&ir
->body_instructions
);
1032 emit(BRW_OPCODE_WHILE
);
1036 vec4_visitor::visit(ir_loop_jump
*ir
)
1039 case ir_loop_jump::jump_break
:
1040 emit(BRW_OPCODE_BREAK
);
1042 case ir_loop_jump::jump_continue
:
1043 emit(BRW_OPCODE_CONTINUE
);
1050 vec4_visitor::visit(ir_function_signature
*ir
)
1057 vec4_visitor::visit(ir_function
*ir
)
1059 /* Ignore function bodies other than main() -- we shouldn't see calls to
1060 * them since they should all be inlined.
1062 if (strcmp(ir
->name
, "main") == 0) {
1063 const ir_function_signature
*sig
;
1066 sig
= ir
->matching_signature(NULL
, &empty
);
1070 visit_instructions(&sig
->body
);
1075 vec4_visitor::try_emit_sat(ir_expression
*ir
)
1077 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
1081 sat_src
->accept(this);
1082 src_reg src
= this->result
;
1084 this->result
= src_reg(this, ir
->type
);
1085 vec4_instruction
*inst
;
1086 inst
= emit(MOV(dst_reg(this->result
), src
));
1087 inst
->saturate
= true;
1093 vec4_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
1095 /* 3-src instructions were introduced in gen6. */
1099 /* MAD can only handle floating-point data. */
1100 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1103 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
1104 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
1106 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1109 nonmul
->accept(this);
1110 src_reg src0
= fix_3src_operand(this->result
);
1112 mul
->operands
[0]->accept(this);
1113 src_reg src1
= fix_3src_operand(this->result
);
1115 mul
->operands
[1]->accept(this);
1116 src_reg src2
= fix_3src_operand(this->result
);
1118 this->result
= src_reg(this, ir
->type
);
1119 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1125 vec4_visitor::emit_bool_comparison(unsigned int op
,
1126 dst_reg dst
, src_reg src0
, src_reg src1
)
1128 /* original gen4 does destination conversion before comparison. */
1130 dst
.type
= src0
.type
;
1132 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
1134 dst
.type
= BRW_REGISTER_TYPE_D
;
1135 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
1139 vec4_visitor::emit_minmax(uint32_t conditionalmod
, dst_reg dst
,
1140 src_reg src0
, src_reg src1
)
1142 vec4_instruction
*inst
;
1144 if (brw
->gen
>= 6) {
1145 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1146 inst
->conditional_mod
= conditionalmod
;
1148 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1150 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1151 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1156 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1157 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1159 if (brw
->gen
>= 6) {
1160 /* Note that the instruction's argument order is reversed from GLSL
1164 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1166 /* Earlier generations don't support three source operations, so we
1167 * need to emit x*(1-a) + y*a.
1169 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1170 one_minus_a
.writemask
= dst
.writemask
;
1172 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1173 vec4_instruction
*mul
= emit(MUL(dst_null_f(), y
, a
));
1174 mul
->writes_accumulator
= true;
1175 emit(MAC(dst
, x
, src_reg(one_minus_a
)));
1180 vec4_visitor::visit(ir_expression
*ir
)
1182 unsigned int operand
;
1183 src_reg op
[Elements(ir
->operands
)];
1186 vec4_instruction
*inst
;
1188 if (try_emit_sat(ir
))
1191 if (ir
->operation
== ir_binop_add
) {
1192 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
1196 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1197 this->result
.file
= BAD_FILE
;
1198 ir
->operands
[operand
]->accept(this);
1199 if (this->result
.file
== BAD_FILE
) {
1200 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1201 ir
->operands
[operand
]->fprint(stderr
);
1204 op
[operand
] = this->result
;
1206 /* Matrix expression operands should have been broken down to vector
1207 * operations already.
1209 assert(!ir
->operands
[operand
]->type
->is_matrix());
1212 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1213 if (ir
->operands
[1]) {
1214 vector_elements
= MAX2(vector_elements
,
1215 ir
->operands
[1]->type
->vector_elements
);
1218 this->result
.file
= BAD_FILE
;
1220 /* Storage for our result. Ideally for an assignment we'd be using
1221 * the actual storage for the result here, instead.
1223 result_src
= src_reg(this, ir
->type
);
1224 /* convenience for the emit functions below. */
1225 result_dst
= dst_reg(result_src
);
1226 /* If nothing special happens, this is the result. */
1227 this->result
= result_src
;
1228 /* Limit writes to the channels that will be used by result_src later.
1229 * This does limit this temp's use as a temporary for multi-instruction
1232 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1234 switch (ir
->operation
) {
1235 case ir_unop_logic_not
:
1236 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1237 * ones complement of the whole register, not just bit 0.
1239 emit(XOR(result_dst
, op
[0], src_reg(1)));
1242 op
[0].negate
= !op
[0].negate
;
1243 emit(MOV(result_dst
, op
[0]));
1247 op
[0].negate
= false;
1248 emit(MOV(result_dst
, op
[0]));
1252 if (ir
->type
->is_float()) {
1253 /* AND(val, 0x80000000) gives the sign bit.
1255 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1258 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1260 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1261 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1262 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1264 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1265 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1267 this->result
.type
= BRW_REGISTER_TYPE_F
;
1269 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1270 * -> non-negative val generates 0x00000000.
1271 * Predicated OR sets 1 if val is positive.
1273 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1275 emit(ASR(result_dst
, op
[0], src_reg(31)));
1277 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1278 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1283 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1287 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1290 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1294 assert(!"not reached: should be handled by ir_explog_to_explog2");
1297 case ir_unop_sin_reduced
:
1298 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1301 case ir_unop_cos_reduced
:
1302 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1307 assert(!"derivatives not valid in vertex shader");
1310 case ir_unop_bitfield_reverse
:
1311 emit(BFREV(result_dst
, op
[0]));
1313 case ir_unop_bit_count
:
1314 emit(CBIT(result_dst
, op
[0]));
1316 case ir_unop_find_msb
: {
1317 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1319 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1320 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1322 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1323 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1324 * subtract the result from 31 to convert the MSB count into an LSB count.
1327 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1328 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1329 emit(MOV(result_dst
, temp
));
1331 src_reg src_tmp
= src_reg(result_dst
);
1332 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1334 src_tmp
.negate
= true;
1335 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1336 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1339 case ir_unop_find_lsb
:
1340 emit(FBL(result_dst
, op
[0]));
1344 assert(!"not reached: should be handled by lower_noise");
1348 emit(ADD(result_dst
, op
[0], op
[1]));
1351 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1355 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
1356 /* For integer multiplication, the MUL uses the low 16 bits of one of
1357 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1358 * accumulates in the contribution of the upper 16 bits of that
1359 * operand. If we can determine that one of the args is in the low
1360 * 16 bits, though, we can just emit a single MUL.
1362 if (ir
->operands
[0]->is_uint16_constant()) {
1364 emit(MUL(result_dst
, op
[0], op
[1]));
1366 emit(MUL(result_dst
, op
[1], op
[0]));
1367 } else if (ir
->operands
[1]->is_uint16_constant()) {
1369 emit(MUL(result_dst
, op
[1], op
[0]));
1371 emit(MUL(result_dst
, op
[0], op
[1]));
1373 struct brw_reg acc
= retype(brw_acc_reg(), result_dst
.type
);
1375 emit(MUL(acc
, op
[0], op
[1]));
1376 emit(MACH(dst_null_d(), op
[0], op
[1]));
1377 emit(MOV(result_dst
, src_reg(acc
)));
1380 emit(MUL(result_dst
, op
[0], op
[1]));
1383 case ir_binop_imul_high
: {
1384 struct brw_reg acc
= retype(brw_acc_reg(), result_dst
.type
);
1386 emit(MUL(acc
, op
[0], op
[1]));
1387 emit(MACH(result_dst
, op
[0], op
[1]));
1391 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1392 assert(ir
->type
->is_integer());
1393 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1395 case ir_binop_carry
: {
1396 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
1398 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1399 emit(MOV(result_dst
, src_reg(acc
)));
1402 case ir_binop_borrow
: {
1403 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
1405 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1406 emit(MOV(result_dst
, src_reg(acc
)));
1410 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1411 assert(ir
->type
->is_integer());
1412 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1416 case ir_binop_greater
:
1417 case ir_binop_lequal
:
1418 case ir_binop_gequal
:
1419 case ir_binop_equal
:
1420 case ir_binop_nequal
: {
1421 emit(CMP(result_dst
, op
[0], op
[1],
1422 brw_conditional_for_comparison(ir
->operation
)));
1423 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1427 case ir_binop_all_equal
:
1428 /* "==" operator producing a scalar boolean. */
1429 if (ir
->operands
[0]->type
->is_vector() ||
1430 ir
->operands
[1]->type
->is_vector()) {
1431 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1432 emit(MOV(result_dst
, src_reg(0)));
1433 inst
= emit(MOV(result_dst
, src_reg(1)));
1434 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1436 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1437 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1440 case ir_binop_any_nequal
:
1441 /* "!=" operator producing a scalar boolean. */
1442 if (ir
->operands
[0]->type
->is_vector() ||
1443 ir
->operands
[1]->type
->is_vector()) {
1444 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1446 emit(MOV(result_dst
, src_reg(0)));
1447 inst
= emit(MOV(result_dst
, src_reg(1)));
1448 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1450 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1451 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1456 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1457 emit(MOV(result_dst
, src_reg(0)));
1459 inst
= emit(MOV(result_dst
, src_reg(1)));
1460 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1463 case ir_binop_logic_xor
:
1464 emit(XOR(result_dst
, op
[0], op
[1]));
1467 case ir_binop_logic_or
:
1468 emit(OR(result_dst
, op
[0], op
[1]));
1471 case ir_binop_logic_and
:
1472 emit(AND(result_dst
, op
[0], op
[1]));
1476 assert(ir
->operands
[0]->type
->is_vector());
1477 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1478 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1482 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1485 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1488 case ir_unop_bitcast_i2f
:
1489 case ir_unop_bitcast_u2f
:
1490 this->result
= op
[0];
1491 this->result
.type
= BRW_REGISTER_TYPE_F
;
1494 case ir_unop_bitcast_f2i
:
1495 this->result
= op
[0];
1496 this->result
.type
= BRW_REGISTER_TYPE_D
;
1499 case ir_unop_bitcast_f2u
:
1500 this->result
= op
[0];
1501 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1512 emit(MOV(result_dst
, op
[0]));
1516 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1517 emit(AND(result_dst
, result_src
, src_reg(1)));
1522 emit(RNDZ(result_dst
, op
[0]));
1525 op
[0].negate
= !op
[0].negate
;
1526 inst
= emit(RNDD(result_dst
, op
[0]));
1527 this->result
.negate
= true;
1530 inst
= emit(RNDD(result_dst
, op
[0]));
1533 inst
= emit(FRC(result_dst
, op
[0]));
1535 case ir_unop_round_even
:
1536 emit(RNDE(result_dst
, op
[0]));
1540 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1543 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1547 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1550 case ir_unop_bit_not
:
1551 inst
= emit(NOT(result_dst
, op
[0]));
1553 case ir_binop_bit_and
:
1554 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1556 case ir_binop_bit_xor
:
1557 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1559 case ir_binop_bit_or
:
1560 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1563 case ir_binop_lshift
:
1564 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1567 case ir_binop_rshift
:
1568 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1569 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1571 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1575 emit(BFI1(result_dst
, op
[0], op
[1]));
1578 case ir_binop_ubo_load
: {
1579 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
1580 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1581 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1584 /* Now, load the vector from that offset. */
1585 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1587 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1588 packed_consts
.type
= result
.type
;
1589 src_reg surf_index
=
1590 src_reg(prog_data
->base
.binding_table
.ubo_start
+ uniform_block
->value
.u
[0]);
1591 if (const_offset_ir
) {
1592 if (brw
->gen
>= 8) {
1593 /* Store the offset in a GRF so we can send-from-GRF. */
1594 offset
= src_reg(this, glsl_type::int_type
);
1595 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1597 /* Immediates are fine on older generations since they'll be moved
1598 * to a (potentially fake) MRF at the generator level.
1600 offset
= src_reg(const_offset
/ 16);
1603 offset
= src_reg(this, glsl_type::uint_type
);
1604 emit(SHR(dst_reg(offset
), op
[1], src_reg(4)));
1607 if (brw
->gen
>= 7) {
1608 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1609 grf_offset
.type
= offset
.type
;
1611 emit(MOV(grf_offset
, offset
));
1613 emit(new(mem_ctx
) vec4_instruction(this,
1614 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1615 dst_reg(packed_consts
),
1617 src_reg(grf_offset
)));
1619 vec4_instruction
*pull
=
1620 emit(new(mem_ctx
) vec4_instruction(this,
1621 VS_OPCODE_PULL_CONSTANT_LOAD
,
1622 dst_reg(packed_consts
),
1625 pull
->base_mrf
= 14;
1629 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1630 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1631 const_offset
% 16 / 4,
1632 const_offset
% 16 / 4,
1633 const_offset
% 16 / 4);
1635 /* UBO bools are any nonzero int. We store bools as either 0 or 1. */
1636 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1637 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1638 BRW_CONDITIONAL_NZ
));
1639 emit(AND(result_dst
, result
, src_reg(0x1)));
1641 emit(MOV(result_dst
, packed_consts
));
1646 case ir_binop_vector_extract
:
1647 assert(!"should have been lowered by vec_index_to_cond_assign");
1651 op
[0] = fix_3src_operand(op
[0]);
1652 op
[1] = fix_3src_operand(op
[1]);
1653 op
[2] = fix_3src_operand(op
[2]);
1654 /* Note that the instruction's argument order is reversed from GLSL
1657 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1661 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1665 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1666 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1667 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1671 op
[0] = fix_3src_operand(op
[0]);
1672 op
[1] = fix_3src_operand(op
[1]);
1673 op
[2] = fix_3src_operand(op
[2]);
1674 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1677 case ir_triop_bitfield_extract
:
1678 op
[0] = fix_3src_operand(op
[0]);
1679 op
[1] = fix_3src_operand(op
[1]);
1680 op
[2] = fix_3src_operand(op
[2]);
1681 /* Note that the instruction's argument order is reversed from GLSL
1684 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1687 case ir_triop_vector_insert
:
1688 assert(!"should have been lowered by lower_vector_insert");
1691 case ir_quadop_bitfield_insert
:
1692 assert(!"not reached: should be handled by "
1693 "bitfield_insert_to_bfm_bfi\n");
1696 case ir_quadop_vector
:
1697 assert(!"not reached: should be handled by lower_quadop_vector");
1700 case ir_unop_pack_half_2x16
:
1701 emit_pack_half_2x16(result_dst
, op
[0]);
1703 case ir_unop_unpack_half_2x16
:
1704 emit_unpack_half_2x16(result_dst
, op
[0]);
1706 case ir_unop_pack_snorm_2x16
:
1707 case ir_unop_pack_snorm_4x8
:
1708 case ir_unop_pack_unorm_2x16
:
1709 case ir_unop_pack_unorm_4x8
:
1710 case ir_unop_unpack_snorm_2x16
:
1711 case ir_unop_unpack_snorm_4x8
:
1712 case ir_unop_unpack_unorm_2x16
:
1713 case ir_unop_unpack_unorm_4x8
:
1714 assert(!"not reached: should be handled by lower_packing_builtins");
1716 case ir_unop_unpack_half_2x16_split_x
:
1717 case ir_unop_unpack_half_2x16_split_y
:
1718 case ir_binop_pack_half_2x16_split
:
1719 assert(!"not reached: should not occur in vertex shader");
1721 case ir_binop_ldexp
:
1722 assert(!"not reached: should be handled by ldexp_to_arith()");
1729 vec4_visitor::visit(ir_swizzle
*ir
)
1735 /* Note that this is only swizzles in expressions, not those on the left
1736 * hand side of an assignment, which do write masking. See ir_assignment
1740 ir
->val
->accept(this);
1742 assert(src
.file
!= BAD_FILE
);
1744 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1747 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1750 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1753 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1756 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1760 for (; i
< 4; i
++) {
1761 /* Replicate the last channel out. */
1762 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1765 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1771 vec4_visitor::visit(ir_dereference_variable
*ir
)
1773 const struct glsl_type
*type
= ir
->type
;
1774 dst_reg
*reg
= variable_storage(ir
->var
);
1777 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1778 this->result
= src_reg(brw_null_reg());
1782 this->result
= src_reg(*reg
);
1784 /* System values get their swizzle from the dst_reg writemask */
1785 if (ir
->var
->data
.mode
== ir_var_system_value
)
1788 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1789 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1794 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1796 /* Under normal circumstances array elements are stored consecutively, so
1797 * the stride is equal to the size of the array element.
1799 return type_size(ir
->type
);
1804 vec4_visitor::visit(ir_dereference_array
*ir
)
1806 ir_constant
*constant_index
;
1808 int array_stride
= compute_array_stride(ir
);
1810 constant_index
= ir
->array_index
->constant_expression_value();
1812 ir
->array
->accept(this);
1815 if (constant_index
) {
1816 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1818 /* Variable index array dereference. It eats the "vec4" of the
1819 * base of the array and an index that offsets the Mesa register
1822 ir
->array_index
->accept(this);
1826 if (array_stride
== 1) {
1827 index_reg
= this->result
;
1829 index_reg
= src_reg(this, glsl_type::int_type
);
1831 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1835 src_reg temp
= src_reg(this, glsl_type::int_type
);
1837 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1842 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1843 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1846 /* If the type is smaller than a vec4, replicate the last channel out. */
1847 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1848 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1850 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1851 src
.type
= brw_type_for_base_type(ir
->type
);
1857 vec4_visitor::visit(ir_dereference_record
*ir
)
1860 const glsl_type
*struct_type
= ir
->record
->type
;
1863 ir
->record
->accept(this);
1865 for (i
= 0; i
< struct_type
->length
; i
++) {
1866 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1868 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1871 /* If the type is smaller than a vec4, replicate the last channel out. */
1872 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1873 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1875 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1876 this->result
.type
= brw_type_for_base_type(ir
->type
);
1878 this->result
.reg_offset
+= offset
;
1882 * We want to be careful in assignment setup to hit the actual storage
1883 * instead of potentially using a temporary like we might with the
1884 * ir_dereference handler.
1887 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1889 /* The LHS must be a dereference. If the LHS is a variable indexed array
1890 * access of a vector, it must be separated into a series conditional moves
1891 * before reaching this point (see ir_vec_index_to_cond_assign).
1893 assert(ir
->as_dereference());
1894 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1896 assert(!deref_array
->array
->type
->is_vector());
1899 /* Use the rvalue deref handler for the most part. We'll ignore
1900 * swizzles in it and write swizzles using writemask, though.
1903 return dst_reg(v
->result
);
1907 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1908 const struct glsl_type
*type
, uint32_t predicate
)
1910 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1911 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1912 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1917 if (type
->is_array()) {
1918 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1919 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1924 if (type
->is_matrix()) {
1925 const struct glsl_type
*vec_type
;
1927 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1928 type
->vector_elements
, 1);
1930 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1931 emit_block_move(dst
, src
, vec_type
, predicate
);
1936 assert(type
->is_scalar() || type
->is_vector());
1938 dst
->type
= brw_type_for_base_type(type
);
1939 src
->type
= dst
->type
;
1941 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1943 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1945 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1946 inst
->predicate
= predicate
;
1953 /* If the RHS processing resulted in an instruction generating a
1954 * temporary value, and it would be easy to rewrite the instruction to
1955 * generate its result right into the LHS instead, do so. This ends
1956 * up reliably removing instructions where it can be tricky to do so
1957 * later without real UD chain information.
1960 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1963 vec4_instruction
*pre_rhs_inst
,
1964 vec4_instruction
*last_rhs_inst
)
1966 /* This could be supported, but it would take more smarts. */
1970 if (pre_rhs_inst
== last_rhs_inst
)
1971 return false; /* No instructions generated to work with. */
1973 /* Make sure the last instruction generated our source reg. */
1974 if (src
.file
!= GRF
||
1975 src
.file
!= last_rhs_inst
->dst
.file
||
1976 src
.reg
!= last_rhs_inst
->dst
.reg
||
1977 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1981 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1984 /* Check that that last instruction fully initialized the channels
1985 * we want to use, in the order we want to use them. We could
1986 * potentially reswizzle the operands of many instructions so that
1987 * we could handle out of order channels, but don't yet.
1990 for (unsigned i
= 0; i
< 4; i
++) {
1991 if (dst
.writemask
& (1 << i
)) {
1992 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1995 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2000 /* Success! Rewrite the instruction. */
2001 last_rhs_inst
->dst
.file
= dst
.file
;
2002 last_rhs_inst
->dst
.reg
= dst
.reg
;
2003 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2004 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2005 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2011 vec4_visitor::visit(ir_assignment
*ir
)
2013 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2014 uint32_t predicate
= BRW_PREDICATE_NONE
;
2016 if (!ir
->lhs
->type
->is_scalar() &&
2017 !ir
->lhs
->type
->is_vector()) {
2018 ir
->rhs
->accept(this);
2019 src_reg src
= this->result
;
2021 if (ir
->condition
) {
2022 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2025 /* emit_block_move doesn't account for swizzles in the source register.
2026 * This should be ok, since the source register is a structure or an
2027 * array, and those can't be swizzled. But double-check to be sure.
2029 assert(src
.swizzle
==
2030 (ir
->rhs
->type
->is_matrix()
2031 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2032 : BRW_SWIZZLE_NOOP
));
2034 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2038 /* Now we're down to just a scalar/vector with writemasks. */
2041 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2042 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2044 ir
->rhs
->accept(this);
2046 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2048 src_reg src
= this->result
;
2051 int first_enabled_chan
= 0;
2054 assert(ir
->lhs
->type
->is_vector() ||
2055 ir
->lhs
->type
->is_scalar());
2056 dst
.writemask
= ir
->write_mask
;
2058 for (int i
= 0; i
< 4; i
++) {
2059 if (dst
.writemask
& (1 << i
)) {
2060 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2065 /* Swizzle a small RHS vector into the channels being written.
2067 * glsl ir treats write_mask as dictating how many channels are
2068 * present on the RHS while in our instructions we need to make
2069 * those channels appear in the slots of the vec4 they're written to.
2071 for (int i
= 0; i
< 4; i
++) {
2072 if (dst
.writemask
& (1 << i
))
2073 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2075 swizzles
[i
] = first_enabled_chan
;
2077 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2078 swizzles
[2], swizzles
[3]);
2080 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2084 if (ir
->condition
) {
2085 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2088 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2089 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2090 inst
->predicate
= predicate
;
2098 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2100 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2101 foreach_list(node
, &ir
->components
) {
2102 ir_constant
*field_value
= (ir_constant
*)node
;
2104 emit_constant_values(dst
, field_value
);
2109 if (ir
->type
->is_array()) {
2110 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2111 emit_constant_values(dst
, ir
->array_elements
[i
]);
2116 if (ir
->type
->is_matrix()) {
2117 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2118 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2120 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2121 dst
->writemask
= 1 << j
;
2122 dst
->type
= BRW_REGISTER_TYPE_F
;
2124 emit(MOV(*dst
, src_reg(vec
[j
])));
2131 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2133 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2134 if (!(remaining_writemask
& (1 << i
)))
2137 dst
->writemask
= 1 << i
;
2138 dst
->type
= brw_type_for_base_type(ir
->type
);
2140 /* Find other components that match the one we're about to
2141 * write. Emits fewer instructions for things like vec4(0.5,
2144 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2145 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2146 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2147 dst
->writemask
|= (1 << j
);
2149 /* u, i, and f storage all line up, so no need for a
2150 * switch case for comparing each type.
2152 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2153 dst
->writemask
|= (1 << j
);
2157 switch (ir
->type
->base_type
) {
2158 case GLSL_TYPE_FLOAT
:
2159 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2162 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2164 case GLSL_TYPE_UINT
:
2165 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2167 case GLSL_TYPE_BOOL
:
2168 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
2171 assert(!"Non-float/uint/int/bool constant");
2175 remaining_writemask
&= ~dst
->writemask
;
2181 vec4_visitor::visit(ir_constant
*ir
)
2183 dst_reg dst
= dst_reg(this, ir
->type
);
2184 this->result
= src_reg(dst
);
2186 emit_constant_values(&dst
, ir
);
2190 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2192 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2193 ir
->actual_parameters
.get_head());
2194 ir_variable
*location
= deref
->variable_referenced();
2195 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2196 location
->data
.atomic
.buffer_index
);
2198 /* Calculate the surface offset */
2199 src_reg
offset(this, glsl_type::uint_type
);
2200 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2202 deref_array
->array_index
->accept(this);
2204 src_reg
tmp(this, glsl_type::uint_type
);
2205 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2206 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2208 offset
= location
->data
.atomic
.offset
;
2211 /* Emit the appropriate machine instruction */
2212 const char *callee
= ir
->callee
->function_name();
2213 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2215 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2216 emit_untyped_surface_read(surf_index
, dst
, offset
);
2218 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2219 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2220 src_reg(), src_reg());
2222 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2223 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2224 src_reg(), src_reg());
2229 vec4_visitor::visit(ir_call
*ir
)
2231 const char *callee
= ir
->callee
->function_name();
2233 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2234 !strcmp("__intrinsic_atomic_increment", callee
) ||
2235 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2236 visit_atomic_counter_intrinsic(ir
);
2238 assert(!"Unsupported intrinsic.");
2243 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, int sampler
)
2245 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_MCS
);
2248 inst
->sampler
= sampler
;
2249 inst
->dst
= dst_reg(this, glsl_type::uvec4_type
);
2250 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2252 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2253 int param_base
= inst
->base_mrf
;
2254 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2255 int zero_mask
= 0xf & ~coord_mask
;
2257 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2260 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2264 return src_reg(inst
->dst
);
2268 vec4_visitor::visit(ir_texture
*ir
)
2271 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2273 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2274 * emitting anything other than setting up the constant result.
2276 if (ir
->op
== ir_tg4
) {
2277 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2278 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2279 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2280 dst_reg
result(this, ir
->type
);
2281 this->result
= src_reg(result
);
2282 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2287 /* Should be lowered by do_lower_texture_projection */
2288 assert(!ir
->projector
);
2290 /* Should be lowered */
2291 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2293 /* Generate code to compute all the subexpression trees. This has to be
2294 * done before loading any values into MRFs for the sampler message since
2295 * generating these values may involve SEND messages that need the MRFs.
2298 if (ir
->coordinate
) {
2299 ir
->coordinate
->accept(this);
2300 coordinate
= this->result
;
2303 src_reg shadow_comparitor
;
2304 if (ir
->shadow_comparitor
) {
2305 ir
->shadow_comparitor
->accept(this);
2306 shadow_comparitor
= this->result
;
2309 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2310 src_reg offset_value
;
2311 if (has_nonconstant_offset
) {
2312 ir
->offset
->accept(this);
2313 offset_value
= src_reg(this->result
);
2316 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2317 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2320 lod
= src_reg(0.0f
);
2321 lod_type
= glsl_type::float_type
;
2326 ir
->lod_info
.lod
->accept(this);
2328 lod_type
= ir
->lod_info
.lod
->type
;
2330 case ir_query_levels
:
2332 lod_type
= glsl_type::int_type
;
2335 ir
->lod_info
.sample_index
->accept(this);
2336 sample_index
= this->result
;
2337 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2339 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2340 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler
);
2345 ir
->lod_info
.grad
.dPdx
->accept(this);
2346 dPdx
= this->result
;
2348 ir
->lod_info
.grad
.dPdy
->accept(this);
2349 dPdy
= this->result
;
2351 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2359 vec4_instruction
*inst
= NULL
;
2363 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXL
);
2366 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXD
);
2369 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF
);
2372 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_CMS
);
2375 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
2378 if (has_nonconstant_offset
)
2379 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TG4_OFFSET
);
2381 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TG4
);
2383 case ir_query_levels
:
2384 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
2387 assert(!"TXB is not valid for vertex shaders.");
2390 assert(!"LOD is not valid for vertex shaders.");
2393 assert(!"Unrecognized tex op");
2396 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
2397 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
2399 /* Stuff the channel select bits in the top of the texture offset */
2400 if (ir
->op
== ir_tg4
)
2401 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16;
2403 /* The message header is necessary for:
2406 * - Gather channel selection
2407 * - Sampler indices too large to fit in a 4-bit value.
2409 inst
->header_present
=
2410 brw
->gen
< 5 || inst
->texture_offset
!= 0 || ir
->op
== ir_tg4
||
2413 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2414 inst
->sampler
= sampler
;
2415 inst
->dst
= dst_reg(this, ir
->type
);
2416 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2417 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2419 /* MRF for the first parameter */
2420 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2422 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2423 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2424 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2426 /* Load the coordinate */
2427 /* FINISHME: gl_clamp_mask and saturate */
2428 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2429 int zero_mask
= 0xf & ~coord_mask
;
2431 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2434 if (zero_mask
!= 0) {
2435 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2438 /* Load the shadow comparitor */
2439 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2440 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2442 shadow_comparitor
));
2446 /* Load the LOD info */
2447 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2449 if (brw
->gen
>= 5) {
2450 mrf
= param_base
+ 1;
2451 if (ir
->shadow_comparitor
) {
2452 writemask
= WRITEMASK_Y
;
2453 /* mlen already incremented */
2455 writemask
= WRITEMASK_X
;
2458 } else /* brw->gen == 4 */ {
2460 writemask
= WRITEMASK_W
;
2462 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2463 } else if (ir
->op
== ir_txf
) {
2464 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2465 } else if (ir
->op
== ir_txf_ms
) {
2466 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2469 /* MCS data is in the first channel of `mcs`, but we need to get it into
2470 * the .y channel of the second vec4 of params, so replicate .x across
2471 * the whole vec4 and then mask off everything except .y
2473 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2474 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2477 } else if (ir
->op
== ir_txd
) {
2478 const glsl_type
*type
= lod_type
;
2480 if (brw
->gen
>= 5) {
2481 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2482 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2483 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2484 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2487 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2488 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2489 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2490 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2491 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2494 if (ir
->shadow_comparitor
) {
2495 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2496 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2497 shadow_comparitor
));
2500 } else /* brw->gen == 4 */ {
2501 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2502 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2505 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2506 if (ir
->shadow_comparitor
) {
2507 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2508 shadow_comparitor
));
2511 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2519 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2520 * spec requires layers.
2522 if (ir
->op
== ir_txs
) {
2523 glsl_type
const *type
= ir
->sampler
->type
;
2524 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2525 type
->sampler_array
) {
2526 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2527 writemask(inst
->dst
, WRITEMASK_Z
),
2528 src_reg(inst
->dst
), src_reg(6));
2532 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2533 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2536 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2540 * Apply workarounds for Gen6 gather with UINT/SINT
2543 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2548 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2549 dst_reg dst_f
= dst
;
2550 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2552 /* Convert from UNORM to UINT */
2553 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2554 emit(MOV(dst
, src_reg(dst_f
)));
2557 /* Reinterpret the UINT value as a signed INT value by
2558 * shifting the sign bit into place, then shifting back
2561 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2562 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2567 * Set up the gather channel based on the swizzle, for gather4.
2570 vec4_visitor::gather_channel(ir_texture
*ir
, int sampler
)
2572 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2573 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2575 case SWIZZLE_X
: return 0;
2577 /* gather4 sampler is broken for green channel on RG32F --
2578 * we must ask for blue instead.
2580 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2583 case SWIZZLE_Z
: return 2;
2584 case SWIZZLE_W
: return 3;
2586 assert(!"Not reached"); /* zero, one swizzles handled already */
2592 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
)
2594 int s
= key
->tex
.swizzles
[sampler
];
2596 this->result
= src_reg(this, ir
->type
);
2597 dst_reg
swizzled_result(this->result
);
2599 if (ir
->op
== ir_query_levels
) {
2600 /* # levels is in .w */
2601 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2602 emit(MOV(swizzled_result
, orig_val
));
2606 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2607 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2608 emit(MOV(swizzled_result
, orig_val
));
2613 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2614 int swizzle
[4] = {0};
2616 for (int i
= 0; i
< 4; i
++) {
2617 switch (GET_SWZ(s
, i
)) {
2619 zero_mask
|= (1 << i
);
2622 one_mask
|= (1 << i
);
2625 copy_mask
|= (1 << i
);
2626 swizzle
[i
] = GET_SWZ(s
, i
);
2632 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2633 swizzled_result
.writemask
= copy_mask
;
2634 emit(MOV(swizzled_result
, orig_val
));
2638 swizzled_result
.writemask
= zero_mask
;
2639 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2643 swizzled_result
.writemask
= one_mask
;
2644 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2649 vec4_visitor::visit(ir_return
*ir
)
2651 assert(!"not reached");
2655 vec4_visitor::visit(ir_discard
*ir
)
2657 assert(!"not reached");
2661 vec4_visitor::visit(ir_if
*ir
)
2663 /* Don't point the annotation at the if statement, because then it plus
2664 * the then and else blocks get printed.
2666 this->base_ir
= ir
->condition
;
2668 if (brw
->gen
== 6) {
2672 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2673 emit(IF(predicate
));
2676 visit_instructions(&ir
->then_instructions
);
2678 if (!ir
->else_instructions
.is_empty()) {
2679 this->base_ir
= ir
->condition
;
2680 emit(BRW_OPCODE_ELSE
);
2682 visit_instructions(&ir
->else_instructions
);
2685 this->base_ir
= ir
->condition
;
2686 emit(BRW_OPCODE_ENDIF
);
2690 vec4_visitor::visit(ir_emit_vertex
*)
2692 assert(!"not reached");
2696 vec4_visitor::visit(ir_end_primitive
*)
2698 assert(!"not reached");
2702 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2703 dst_reg dst
, src_reg offset
,
2704 src_reg src0
, src_reg src1
)
2708 /* Set the atomic operation offset. */
2709 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2712 /* Set the atomic operation arguments. */
2713 if (src0
.file
!= BAD_FILE
) {
2714 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2718 if (src1
.file
!= BAD_FILE
) {
2719 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2723 /* Emit the instruction. Note that this maps to the normal SIMD8
2724 * untyped atomic message on Ivy Bridge, but that's OK because
2725 * unused channels will be masked out.
2727 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2728 src_reg(atomic_op
), src_reg(surf_index
));
2734 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
2737 /* Set the surface read offset. */
2738 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
2740 /* Emit the instruction. Note that this maps to the normal SIMD8
2741 * untyped surface read message, but that's OK because unused
2742 * channels will be masked out.
2744 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
,
2745 dst
, src_reg(surf_index
));
2751 vec4_visitor::emit_ndc_computation()
2753 /* Get the position */
2754 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2756 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2757 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2758 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2760 current_annotation
= "NDC";
2761 dst_reg ndc_w
= ndc
;
2762 ndc_w
.writemask
= WRITEMASK_W
;
2763 src_reg pos_w
= pos
;
2764 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2765 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2767 dst_reg ndc_xyz
= ndc
;
2768 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2770 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2774 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
2777 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2778 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2779 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2780 dst_reg header1_w
= header1
;
2781 header1_w
.writemask
= WRITEMASK_W
;
2783 emit(MOV(header1
, 0u));
2785 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2786 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2788 current_annotation
= "Point size";
2789 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2790 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2793 if (key
->userclip_active
) {
2794 current_annotation
= "Clipping flags";
2795 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
2796 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
2798 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2799 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
2800 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
2802 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2803 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
2804 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
2805 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
2808 /* i965 clipping workaround:
2809 * 1) Test for -ve rhw
2811 * set ndc = (0,0,0,0)
2814 * Later, clipping will detect ucp[6] and ensure the primitive is
2815 * clipped against all fixed planes.
2817 if (brw
->has_negative_rhw_bug
) {
2818 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2819 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2820 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2821 vec4_instruction
*inst
;
2822 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2823 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2824 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
2825 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2828 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2829 } else if (brw
->gen
< 6) {
2830 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2832 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2833 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2834 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
2835 src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
2837 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
2838 emit(MOV(retype(brw_writemask(reg
, WRITEMASK_Y
), BRW_REGISTER_TYPE_D
),
2839 src_reg(output_reg
[VARYING_SLOT_LAYER
])));
2841 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
2842 emit(MOV(retype(brw_writemask(reg
, WRITEMASK_Z
), BRW_REGISTER_TYPE_D
),
2843 src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
2849 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
2851 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2853 * "If a linked set of shaders forming the vertex stage contains no
2854 * static write to gl_ClipVertex or gl_ClipDistance, but the
2855 * application has requested clipping against user clip planes through
2856 * the API, then the coordinate written to gl_Position is used for
2857 * comparison against the user clip planes."
2859 * This function is only called if the shader didn't write to
2860 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2861 * if the user wrote to it; otherwise we use gl_Position.
2863 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
2864 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
2865 clip_vertex
= VARYING_SLOT_POS
;
2868 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
2870 reg
.writemask
= 1 << i
;
2872 src_reg(output_reg
[clip_vertex
]),
2873 src_reg(this->userplane
[i
+ offset
])));
2878 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
2880 assert (varying
< VARYING_SLOT_MAX
);
2881 reg
.type
= output_reg
[varying
].type
;
2882 current_annotation
= output_reg_annotation
[varying
];
2883 /* Copy the register, saturating if necessary */
2884 vec4_instruction
*inst
= emit(MOV(reg
,
2885 src_reg(output_reg
[varying
])));
2886 if ((varying
== VARYING_SLOT_COL0
||
2887 varying
== VARYING_SLOT_COL1
||
2888 varying
== VARYING_SLOT_BFC0
||
2889 varying
== VARYING_SLOT_BFC1
) &&
2890 key
->clamp_vertex_color
) {
2891 inst
->saturate
= true;
2896 vec4_visitor::emit_urb_slot(int mrf
, int varying
)
2898 struct brw_reg hw_reg
= brw_message_reg(mrf
);
2899 dst_reg reg
= dst_reg(MRF
, mrf
);
2900 reg
.type
= BRW_REGISTER_TYPE_F
;
2903 case VARYING_SLOT_PSIZ
:
2904 /* PSIZ is always in slot 0, and is coupled with other flags. */
2905 current_annotation
= "indices, point width, clip flags";
2906 emit_psiz_and_flags(hw_reg
);
2908 case BRW_VARYING_SLOT_NDC
:
2909 current_annotation
= "NDC";
2910 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
2912 case VARYING_SLOT_POS
:
2913 current_annotation
= "gl_Position";
2914 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
2916 case VARYING_SLOT_EDGE
:
2917 /* This is present when doing unfilled polygons. We're supposed to copy
2918 * the edge flag from the user-provided vertex array
2919 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
2920 * of that attribute (starts as 1.0f). This is then used in clipping to
2921 * determine which edges should be drawn as wireframe.
2923 current_annotation
= "edge flag";
2924 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
2925 glsl_type::float_type
, WRITEMASK_XYZW
))));
2927 case BRW_VARYING_SLOT_PAD
:
2928 /* No need to write to this slot */
2931 emit_generic_urb_slot(reg
, varying
);
2937 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
2939 if (brw
->gen
>= 6) {
2940 /* URB data written (does not include the message header reg) must
2941 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
2942 * section 5.4.3.2.2: URB_INTERLEAVED.
2944 * URB entries are allocated on a multiple of 1024 bits, so an
2945 * extra 128 bits written here to make the end align to 256 is
2948 if ((mlen
% 2) != 1)
2957 * Generates the VUE payload plus the necessary URB write instructions to
2960 * The VUE layout is documented in Volume 2a.
2963 vec4_visitor::emit_vertex()
2965 /* MRF 0 is reserved for the debugger, so start with message header
2970 /* In the process of generating our URB write message contents, we
2971 * may need to unspill a register or load from an array. Those
2972 * reads would use MRFs 14-15.
2974 int max_usable_mrf
= 13;
2976 /* The following assertion verifies that max_usable_mrf causes an
2977 * even-numbered amount of URB write data, which will meet gen6's
2978 * requirements for length alignment.
2980 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
2982 /* First mrf is the g0-based message header containing URB handles and
2985 emit_urb_write_header(mrf
++);
2988 emit_ndc_computation();
2991 /* Lower legacy ff and ClipVertex clipping to clip distances */
2992 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
2993 current_annotation
= "user clip distances";
2995 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
2996 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
2998 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
2999 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3002 /* We may need to split this up into several URB writes, so do them in a
3006 bool complete
= false;
3008 /* URB offset is in URB row increments, and each of our MRFs is half of
3009 * one of those, since we're doing interleaved writes.
3011 int offset
= slot
/ 2;
3014 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3015 emit_urb_slot(mrf
++, prog_data
->vue_map
.slot_to_varying
[slot
]);
3017 /* If this was max_usable_mrf, we can't fit anything more into this
3020 if (mrf
> max_usable_mrf
) {
3026 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3027 current_annotation
= "URB write";
3028 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3029 inst
->base_mrf
= base_mrf
;
3030 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
3031 inst
->offset
+= offset
;
3037 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
3038 src_reg
*reladdr
, int reg_offset
)
3040 /* Because we store the values to scratch interleaved like our
3041 * vertex data, we need to scale the vec4 index by 2.
3043 int message_header_scale
= 2;
3045 /* Pre-gen6, the message header uses byte offsets instead of vec4
3046 * (16-byte) offset units.
3049 message_header_scale
*= 16;
3052 src_reg index
= src_reg(this, glsl_type::int_type
);
3054 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
3055 emit_before(inst
, MUL(dst_reg(index
),
3056 index
, src_reg(message_header_scale
)));
3060 return src_reg(reg_offset
* message_header_scale
);
3065 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
3066 src_reg
*reladdr
, int reg_offset
)
3069 src_reg index
= src_reg(this, glsl_type::int_type
);
3071 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
3073 /* Pre-gen6, the message header uses byte offsets instead of vec4
3074 * (16-byte) offset units.
3077 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3081 } else if (brw
->gen
>= 8) {
3082 /* Store the offset in a GRF so we can send-from-GRF. */
3083 src_reg offset
= src_reg(this, glsl_type::int_type
);
3084 emit_before(inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3087 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
3088 return src_reg(reg_offset
* message_header_scale
);
3093 * Emits an instruction before @inst to load the value named by @orig_src
3094 * from scratch space at @base_offset to @temp.
3096 * @base_offset is measured in 32-byte units (the size of a register).
3099 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
3100 dst_reg temp
, src_reg orig_src
,
3103 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3104 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
3106 emit_before(inst
, SCRATCH_READ(temp
, index
));
3110 * Emits an instruction after @inst to store the value to be written
3111 * to @orig_dst to scratch space at @base_offset, from @temp.
3113 * @base_offset is measured in 32-byte units (the size of a register).
3116 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
, int base_offset
)
3118 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3119 src_reg index
= get_scratch_offset(inst
, inst
->dst
.reladdr
, reg_offset
);
3121 /* Create a temporary register to store *inst's result in.
3123 * We have to be careful in MOVing from our temporary result register in
3124 * the scratch write. If we swizzle from channels of the temporary that
3125 * weren't initialized, it will confuse live interval analysis, which will
3126 * make spilling fail to make progress.
3128 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
3129 temp
.type
= inst
->dst
.type
;
3130 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
3132 for (int i
= 0; i
< 4; i
++)
3133 if (inst
->dst
.writemask
& (1 << i
))
3136 swizzles
[i
] = first_writemask_chan
;
3137 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3138 swizzles
[2], swizzles
[3]);
3140 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3141 inst
->dst
.writemask
));
3142 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3143 write
->predicate
= inst
->predicate
;
3144 write
->ir
= inst
->ir
;
3145 write
->annotation
= inst
->annotation
;
3146 inst
->insert_after(write
);
3148 inst
->dst
.file
= temp
.file
;
3149 inst
->dst
.reg
= temp
.reg
;
3150 inst
->dst
.reg_offset
= temp
.reg_offset
;
3151 inst
->dst
.reladdr
= NULL
;
3155 * We can't generally support array access in GRF space, because a
3156 * single instruction's destination can only span 2 contiguous
3157 * registers. So, we send all GRF arrays that get variable index
3158 * access to scratch space.
3161 vec4_visitor::move_grf_array_access_to_scratch()
3163 int scratch_loc
[this->virtual_grf_count
];
3165 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
3166 scratch_loc
[i
] = -1;
3169 /* First, calculate the set of virtual GRFs that need to be punted
3170 * to scratch due to having any array access on them, and where in
3173 foreach_list(node
, &this->instructions
) {
3174 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3176 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3177 scratch_loc
[inst
->dst
.reg
] == -1) {
3178 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3179 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
3182 for (int i
= 0 ; i
< 3; i
++) {
3183 src_reg
*src
= &inst
->src
[i
];
3185 if (src
->file
== GRF
&& src
->reladdr
&&
3186 scratch_loc
[src
->reg
] == -1) {
3187 scratch_loc
[src
->reg
] = c
->last_scratch
;
3188 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
3193 /* Now, for anything that will be accessed through scratch, rewrite
3194 * it to load/store. Note that this is a _safe list walk, because
3195 * we may generate a new scratch_write instruction after the one
3198 foreach_list_safe(node
, &this->instructions
) {
3199 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3201 /* Set up the annotation tracking for new generated instructions. */
3203 current_annotation
= inst
->annotation
;
3205 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3206 emit_scratch_write(inst
, scratch_loc
[inst
->dst
.reg
]);
3209 for (int i
= 0 ; i
< 3; i
++) {
3210 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3213 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3215 emit_scratch_read(inst
, temp
, inst
->src
[i
],
3216 scratch_loc
[inst
->src
[i
].reg
]);
3218 inst
->src
[i
].file
= temp
.file
;
3219 inst
->src
[i
].reg
= temp
.reg
;
3220 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3221 inst
->src
[i
].reladdr
= NULL
;
3227 * Emits an instruction before @inst to load the value named by @orig_src
3228 * from the pull constant buffer (surface) at @base_offset to @temp.
3231 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
3232 dst_reg temp
, src_reg orig_src
,
3235 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3236 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3237 src_reg offset
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
3238 vec4_instruction
*load
;
3240 if (brw
->gen
>= 7) {
3241 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3242 grf_offset
.type
= offset
.type
;
3243 emit_before(inst
, MOV(grf_offset
, offset
));
3245 load
= new(mem_ctx
) vec4_instruction(this,
3246 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3247 temp
, index
, src_reg(grf_offset
));
3249 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
3250 temp
, index
, offset
);
3251 load
->base_mrf
= 14;
3254 emit_before(inst
, load
);
3258 * Implements array access of uniforms by inserting a
3259 * PULL_CONSTANT_LOAD instruction.
3261 * Unlike temporary GRF array access (where we don't support it due to
3262 * the difficulty of doing relative addressing on instruction
3263 * destinations), we could potentially do array access of uniforms
3264 * that were loaded in GRF space as push constants. In real-world
3265 * usage we've seen, though, the arrays being used are always larger
3266 * than we could load as push constants, so just always move all
3267 * uniform array access out to a pull constant buffer.
3270 vec4_visitor::move_uniform_array_access_to_pull_constants()
3272 int pull_constant_loc
[this->uniforms
];
3274 for (int i
= 0; i
< this->uniforms
; i
++) {
3275 pull_constant_loc
[i
] = -1;
3278 /* Walk through and find array access of uniforms. Put a copy of that
3279 * uniform in the pull constant buffer.
3281 * Note that we don't move constant-indexed accesses to arrays. No
3282 * testing has been done of the performance impact of this choice.
3284 foreach_list_safe(node
, &this->instructions
) {
3285 vec4_instruction
*inst
= (vec4_instruction
*)node
;
3287 for (int i
= 0 ; i
< 3; i
++) {
3288 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3291 int uniform
= inst
->src
[i
].reg
;
3293 /* If this array isn't already present in the pull constant buffer,
3296 if (pull_constant_loc
[uniform
] == -1) {
3297 const float **values
= &stage_prog_data
->param
[uniform
* 4];
3299 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3301 assert(uniform
< uniform_array_size
);
3302 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3303 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3308 /* Set up the annotation tracking for new generated instructions. */
3310 current_annotation
= inst
->annotation
;
3312 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3314 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
3315 pull_constant_loc
[uniform
]);
3317 inst
->src
[i
].file
= temp
.file
;
3318 inst
->src
[i
].reg
= temp
.reg
;
3319 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3320 inst
->src
[i
].reladdr
= NULL
;
3324 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3325 * no need to track them as larger-than-vec4 objects. This will be
3326 * relied on in cutting out unused uniform vectors from push
3329 split_uniform_registers();
3333 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3335 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3339 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3340 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3344 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3345 struct brw_vec4_compile
*c
,
3346 struct gl_program
*prog
,
3347 const struct brw_vec4_prog_key
*key
,
3348 struct brw_vec4_prog_data
*prog_data
,
3349 struct gl_shader_program
*shader_prog
,
3350 gl_shader_stage stage
,
3354 shader_time_shader_type st_base
,
3355 shader_time_shader_type st_written
,
3356 shader_time_shader_type st_reset
)
3357 : backend_visitor(brw
, shader_prog
, prog
, &prog_data
->base
, stage
),
3360 prog_data(prog_data
),
3361 sanity_param_count(0),
3363 first_non_payload_grf(0),
3364 need_all_constants_in_pull_buffer(false),
3365 debug_flag(debug_flag
),
3366 no_spills(no_spills
),
3368 st_written(st_written
),
3371 this->mem_ctx
= mem_ctx
;
3372 this->failed
= false;
3374 this->base_ir
= NULL
;
3375 this->current_annotation
= NULL
;
3376 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3378 this->variable_ht
= hash_table_ctor(0,
3379 hash_table_pointer_hash
,
3380 hash_table_pointer_compare
);
3382 this->virtual_grf_start
= NULL
;
3383 this->virtual_grf_end
= NULL
;
3384 this->virtual_grf_sizes
= NULL
;
3385 this->virtual_grf_count
= 0;
3386 this->virtual_grf_reg_map
= NULL
;
3387 this->virtual_grf_reg_count
= 0;
3388 this->virtual_grf_array_size
= 0;
3389 this->live_intervals_valid
= false;
3391 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3395 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3396 * at least one. See setup_uniforms() in brw_vec4.cpp.
3398 this->uniform_array_size
= 1;
3400 this->uniform_array_size
= MAX2(stage_prog_data
->nr_params
, 1);
3403 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3404 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3407 vec4_visitor::~vec4_visitor()
3409 hash_table_dtor(this->variable_ht
);
3414 vec4_visitor::fail(const char *format
, ...)
3424 va_start(va
, format
);
3425 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3427 msg
= ralloc_asprintf(mem_ctx
, "vec4 compile failed: %s\n", msg
);
3429 this->fail_msg
= msg
;
3432 fprintf(stderr
, "%s", msg
);
3436 } /* namespace brw */