2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_uniform.h"
27 #include "main/context.h"
28 #include "main/macros.h"
29 #include "program/prog_parameter.h"
30 #include "program/sampler.h"
35 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
36 enum opcode opcode
, dst_reg dst
,
37 src_reg src0
, src_reg src1
, src_reg src2
)
39 this->opcode
= opcode
;
44 this->ir
= v
->base_ir
;
45 this->annotation
= v
->current_annotation
;
49 vec4_visitor::emit(vec4_instruction
*inst
)
51 this->instructions
.push_tail(inst
);
57 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
59 new_inst
->ir
= inst
->ir
;
60 new_inst
->annotation
= inst
->annotation
;
62 inst
->insert_before(new_inst
);
68 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
69 src_reg src0
, src_reg src1
, src_reg src2
)
71 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
77 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
79 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
83 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
85 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
89 vec4_visitor::emit(enum opcode opcode
)
91 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
96 vec4_visitor::op(dst_reg dst, src_reg src0) \
98 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
104 vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1) \
106 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
131 /** Gen4 predicated IF. */
133 vec4_visitor::IF(uint32_t predicate
)
135 vec4_instruction
*inst
;
137 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
138 inst
->predicate
= predicate
;
143 /** Gen6+ IF with embedded comparison. */
145 vec4_visitor::IF(src_reg src0
, src_reg src1
, uint32_t condition
)
147 assert(intel
->gen
>= 6);
149 vec4_instruction
*inst
;
151 resolve_ud_negate(&src0
);
152 resolve_ud_negate(&src1
);
154 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
156 inst
->conditional_mod
= condition
;
162 * CMP: Sets the low bit of the destination channels with the result
163 * of the comparison, while the upper bits are undefined, and updates
164 * the flag register with the packed 16 bits of the result.
167 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
, uint32_t condition
)
169 vec4_instruction
*inst
;
171 /* original gen4 does type conversion to the destination type
172 * before before comparison, producing garbage results for floating
175 if (intel
->gen
== 4) {
176 dst
.type
= src0
.type
;
177 if (dst
.file
== HW_REG
)
178 dst
.fixed_hw_reg
.type
= dst
.type
;
181 resolve_ud_negate(&src0
);
182 resolve_ud_negate(&src1
);
184 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
185 inst
->conditional_mod
= condition
;
191 vec4_visitor::SCRATCH_READ(dst_reg dst
, src_reg index
)
193 vec4_instruction
*inst
;
195 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_READ
,
204 vec4_visitor::SCRATCH_WRITE(dst_reg dst
, src_reg src
, src_reg index
)
206 vec4_instruction
*inst
;
208 inst
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_SCRATCH_WRITE
,
217 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
219 static enum opcode dot_opcodes
[] = {
220 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
223 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
227 vec4_visitor::fix_math_operand(src_reg src
)
229 /* The gen6 math instruction ignores the source modifiers --
230 * swizzle, abs, negate, and at least some parts of the register
231 * region description.
233 * Rather than trying to enumerate all these cases, *always* expand the
234 * operand to a temp GRF for gen6.
236 * For gen7, keep the operand as-is, except if immediate, which gen7 still
240 if (intel
->gen
== 7 && src
.file
!= IMM
)
243 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
244 expanded
.type
= src
.type
;
245 emit(MOV(expanded
, src
));
246 return src_reg(expanded
);
250 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
252 src
= fix_math_operand(src
);
254 if (dst
.writemask
!= WRITEMASK_XYZW
) {
255 /* The gen6 math instruction must be align1, so we can't do
258 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
260 emit(opcode
, temp_dst
, src
);
262 emit(MOV(dst
, src_reg(temp_dst
)));
264 emit(opcode
, dst
, src
);
269 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
271 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
277 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
280 case SHADER_OPCODE_RCP
:
281 case SHADER_OPCODE_RSQ
:
282 case SHADER_OPCODE_SQRT
:
283 case SHADER_OPCODE_EXP2
:
284 case SHADER_OPCODE_LOG2
:
285 case SHADER_OPCODE_SIN
:
286 case SHADER_OPCODE_COS
:
289 assert(!"not reached: bad math opcode");
293 if (intel
->gen
>= 6) {
294 return emit_math1_gen6(opcode
, dst
, src
);
296 return emit_math1_gen4(opcode
, dst
, src
);
301 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
302 dst_reg dst
, src_reg src0
, src_reg src1
)
304 src0
= fix_math_operand(src0
);
305 src1
= fix_math_operand(src1
);
307 if (dst
.writemask
!= WRITEMASK_XYZW
) {
308 /* The gen6 math instruction must be align1, so we can't do
311 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
312 temp_dst
.type
= dst
.type
;
314 emit(opcode
, temp_dst
, src0
, src1
);
316 emit(MOV(dst
, src_reg(temp_dst
)));
318 emit(opcode
, dst
, src0
, src1
);
323 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
324 dst_reg dst
, src_reg src0
, src_reg src1
)
326 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
332 vec4_visitor::emit_math(enum opcode opcode
,
333 dst_reg dst
, src_reg src0
, src_reg src1
)
336 case SHADER_OPCODE_POW
:
337 case SHADER_OPCODE_INT_QUOTIENT
:
338 case SHADER_OPCODE_INT_REMAINDER
:
341 assert(!"not reached: unsupported binary math opcode");
345 if (intel
->gen
>= 6) {
346 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
348 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
353 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
356 assert(!"ir_unop_pack_half_2x16 should be lowered");
358 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
359 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
361 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
363 * Because this instruction does not have a 16-bit floating-point type,
364 * the destination data type must be Word (W).
366 * The destination must be DWord-aligned and specify a horizontal stride
367 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
368 * each destination channel and the upper word is not modified.
370 * The above restriction implies that the f32to16 instruction must use
371 * align1 mode, because only in align1 mode is it possible to specify
372 * horizontal stride. We choose here to defy the hardware docs and emit
373 * align16 instructions.
375 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
376 * instructions. I was partially successful in that the code passed all
377 * tests. However, the code was dubiously correct and fragile, and the
378 * tests were not harsh enough to probe that frailty. Not trusting the
379 * code, I chose instead to remain in align16 mode in defiance of the hw
382 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
383 * simulator, emitting a f32to16 in align16 mode with UD as destination
384 * data type is safe. The behavior differs from that specified in the PRM
385 * in that the upper word of each destination channel is cleared to 0.
388 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
389 src_reg
tmp_src(tmp_dst
);
392 /* Verify the undocumented behavior on which the following instructions
393 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
394 * then the result of the bit-or instruction below will be incorrect.
396 * You should inspect the disasm output in order to verify that the MOV is
397 * not optimized away.
399 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
402 /* Give tmp the form below, where "." means untouched.
405 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
407 * That the upper word of each write-channel be 0 is required for the
408 * following bit-shift and bit-or instructions to work. Note that this
409 * relies on the undocumented hardware behavior mentioned above.
411 tmp_dst
.writemask
= WRITEMASK_XY
;
412 emit(F32TO16(tmp_dst
, src0
));
414 /* Give the write-channels of dst the form:
417 tmp_src
.swizzle
= SWIZZLE_Y
;
418 emit(SHL(dst
, tmp_src
, src_reg(16u)));
420 /* Finally, give the write-channels of dst the form of packHalf2x16's
424 tmp_src
.swizzle
= SWIZZLE_X
;
425 emit(OR(dst
, src_reg(dst
), tmp_src
));
429 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
432 assert(!"ir_unop_unpack_half_2x16 should be lowered");
434 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
435 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
437 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
439 * Because this instruction does not have a 16-bit floating-point type,
440 * the source data type must be Word (W). The destination type must be
443 * To use W as the source data type, we must adjust horizontal strides,
444 * which is only possible in align1 mode. All my [chadv] attempts at
445 * emitting align1 instructions for unpackHalf2x16 failed to pass the
446 * Piglit tests, so I gave up.
448 * I've verified that, on gen7 hardware and the simulator, it is safe to
449 * emit f16to32 in align16 mode with UD as source data type.
452 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
453 src_reg
tmp_src(tmp_dst
);
455 tmp_dst
.writemask
= WRITEMASK_X
;
456 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
458 tmp_dst
.writemask
= WRITEMASK_Y
;
459 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
461 dst
.writemask
= WRITEMASK_XY
;
462 emit(F16TO32(dst
, tmp_src
));
466 vec4_visitor::visit_instructions(const exec_list
*list
)
468 foreach_list(node
, list
) {
469 ir_instruction
*ir
= (ir_instruction
*)node
;
478 type_size(const struct glsl_type
*type
)
483 switch (type
->base_type
) {
486 case GLSL_TYPE_FLOAT
:
488 if (type
->is_matrix()) {
489 return type
->matrix_columns
;
491 /* Regardless of size of vector, it gets a vec4. This is bad
492 * packing for things like floats, but otherwise arrays become a
493 * mess. Hopefully a later pass over the code can pack scalars
494 * down if appropriate.
498 case GLSL_TYPE_ARRAY
:
499 assert(type
->length
> 0);
500 return type_size(type
->fields
.array
) * type
->length
;
501 case GLSL_TYPE_STRUCT
:
503 for (i
= 0; i
< type
->length
; i
++) {
504 size
+= type_size(type
->fields
.structure
[i
].type
);
507 case GLSL_TYPE_SAMPLER
:
508 /* Samplers take up one slot in UNIFORMS[], but they're baked in
513 case GLSL_TYPE_ERROR
:
514 case GLSL_TYPE_INTERFACE
:
523 vec4_visitor::virtual_grf_alloc(int size
)
525 if (virtual_grf_array_size
<= virtual_grf_count
) {
526 if (virtual_grf_array_size
== 0)
527 virtual_grf_array_size
= 16;
529 virtual_grf_array_size
*= 2;
530 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
531 virtual_grf_array_size
);
532 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
533 virtual_grf_array_size
);
535 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
536 virtual_grf_reg_count
+= size
;
537 virtual_grf_sizes
[virtual_grf_count
] = size
;
538 return virtual_grf_count
++;
541 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
546 this->reg
= v
->virtual_grf_alloc(type_size(type
));
548 if (type
->is_array() || type
->is_record()) {
549 this->swizzle
= BRW_SWIZZLE_NOOP
;
551 this->swizzle
= swizzle_for_size(type
->vector_elements
);
554 this->type
= brw_type_for_base_type(type
);
557 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
562 this->reg
= v
->virtual_grf_alloc(type_size(type
));
564 if (type
->is_array() || type
->is_record()) {
565 this->writemask
= WRITEMASK_XYZW
;
567 this->writemask
= (1 << type
->vector_elements
) - 1;
570 this->type
= brw_type_for_base_type(type
);
573 /* Our support for uniforms is piggy-backed on the struct
574 * gl_fragment_program, because that's where the values actually
575 * get stored, rather than in some global gl_shader_program uniform
579 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
581 int namelen
= strlen(ir
->name
);
583 /* The data for our (non-builtin) uniforms is stored in a series of
584 * gl_uniform_driver_storage structs for each subcomponent that
585 * glGetUniformLocation() could name. We know it's been set up in the same
586 * order we'd walk the type, so walk the list of storage and find anything
587 * with our name, or the prefix of a component that starts with our name.
589 for (unsigned u
= 0; u
< prog
->NumUserUniformStorage
; u
++) {
590 struct gl_uniform_storage
*storage
= &prog
->UniformStorage
[u
];
592 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
593 (storage
->name
[namelen
] != 0 &&
594 storage
->name
[namelen
] != '.' &&
595 storage
->name
[namelen
] != '[')) {
599 gl_constant_value
*components
= storage
->storage
;
600 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
601 storage
->type
->matrix_columns
);
603 for (unsigned s
= 0; s
< vector_count
; s
++) {
604 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
607 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
608 c
->prog_data
.param
[uniforms
* 4 + i
] = &components
->f
;
612 static float zero
= 0;
613 c
->prog_data
.param
[uniforms
* 4 + i
] = &zero
;
622 vec4_visitor::setup_uniform_clipplane_values()
624 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
626 if (intel
->gen
< 6) {
627 /* Pre-Gen6, we compact clip planes. For example, if the user
628 * enables just clip planes 0, 1, and 3, we will enable clip planes
629 * 0, 1, and 2 in the hardware, and we'll move clip plane 3 to clip
630 * plane 2. This simplifies the implementation of the Gen6 clip
633 int compacted_clipplane_index
= 0;
634 for (int i
= 0; i
< MAX_CLIP_PLANES
; ++i
) {
635 if (!(c
->key
.userclip_planes_enabled_gen_4_5
& (1 << i
)))
638 this->uniform_vector_size
[this->uniforms
] = 4;
639 this->userplane
[compacted_clipplane_index
] = dst_reg(UNIFORM
, this->uniforms
);
640 this->userplane
[compacted_clipplane_index
].type
= BRW_REGISTER_TYPE_F
;
641 for (int j
= 0; j
< 4; ++j
) {
642 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
644 ++compacted_clipplane_index
;
648 /* In Gen6 and later, we don't compact clip planes, because this
649 * simplifies the implementation of gl_ClipDistance.
651 for (int i
= 0; i
< c
->key
.nr_userclip_plane_consts
; ++i
) {
652 this->uniform_vector_size
[this->uniforms
] = 4;
653 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
654 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
655 for (int j
= 0; j
< 4; ++j
) {
656 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &clip_planes
[i
][j
];
663 /* Our support for builtin uniforms is even scarier than non-builtin.
664 * It sits on top of the PROG_STATE_VAR parameters that are
665 * automatically updated from GL context state.
668 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
670 const ir_state_slot
*const slots
= ir
->state_slots
;
671 assert(ir
->state_slots
!= NULL
);
673 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
674 /* This state reference has already been setup by ir_to_mesa,
675 * but we'll get the same index back here. We can reference
676 * ParameterValues directly, since unlike brw_fs.cpp, we never
677 * add new state references during compile.
679 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
680 (gl_state_index
*)slots
[i
].tokens
);
681 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
683 this->uniform_vector_size
[this->uniforms
] = 0;
684 /* Add each of the unique swizzled channels of the element.
685 * This will end up matching the size of the glsl_type of this field.
688 for (unsigned int j
= 0; j
< 4; j
++) {
689 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
692 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
693 if (swiz
<= last_swiz
)
694 this->uniform_vector_size
[this->uniforms
]++;
701 vec4_visitor::variable_storage(ir_variable
*var
)
703 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
707 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
, uint32_t *predicate
)
709 ir_expression
*expr
= ir
->as_expression();
711 *predicate
= BRW_PREDICATE_NORMAL
;
715 vec4_instruction
*inst
;
717 assert(expr
->get_num_operands() <= 2);
718 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
719 expr
->operands
[i
]->accept(this);
720 op
[i
] = this->result
;
722 resolve_ud_negate(&op
[i
]);
725 switch (expr
->operation
) {
726 case ir_unop_logic_not
:
727 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
728 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
731 case ir_binop_logic_xor
:
732 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
733 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
736 case ir_binop_logic_or
:
737 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
738 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
741 case ir_binop_logic_and
:
742 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
743 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
747 if (intel
->gen
>= 6) {
748 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
750 inst
= emit(MOV(dst_null_f(), op
[0]));
751 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
756 if (intel
->gen
>= 6) {
757 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
759 inst
= emit(MOV(dst_null_d(), op
[0]));
760 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
764 case ir_binop_all_equal
:
765 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
766 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
769 case ir_binop_any_nequal
:
770 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
771 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
775 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
776 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
779 case ir_binop_greater
:
780 case ir_binop_gequal
:
782 case ir_binop_lequal
:
784 case ir_binop_nequal
:
785 emit(CMP(dst_null_d(), op
[0], op
[1],
786 brw_conditional_for_comparison(expr
->operation
)));
790 assert(!"not reached");
798 resolve_ud_negate(&this->result
);
800 if (intel
->gen
>= 6) {
801 vec4_instruction
*inst
= emit(AND(dst_null_d(),
802 this->result
, src_reg(1)));
803 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
805 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
806 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
811 * Emit a gen6 IF statement with the comparison folded into the IF
815 vec4_visitor::emit_if_gen6(ir_if
*ir
)
817 ir_expression
*expr
= ir
->condition
->as_expression();
823 assert(expr
->get_num_operands() <= 2);
824 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
825 expr
->operands
[i
]->accept(this);
826 op
[i
] = this->result
;
829 switch (expr
->operation
) {
830 case ir_unop_logic_not
:
831 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
834 case ir_binop_logic_xor
:
835 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
838 case ir_binop_logic_or
:
839 temp
= dst_reg(this, glsl_type::bool_type
);
840 emit(OR(temp
, op
[0], op
[1]));
841 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
844 case ir_binop_logic_and
:
845 temp
= dst_reg(this, glsl_type::bool_type
);
846 emit(AND(temp
, op
[0], op
[1]));
847 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
851 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
855 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
858 case ir_binop_greater
:
859 case ir_binop_gequal
:
861 case ir_binop_lequal
:
863 case ir_binop_nequal
:
864 emit(IF(op
[0], op
[1],
865 brw_conditional_for_comparison(expr
->operation
)));
868 case ir_binop_all_equal
:
869 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
870 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
873 case ir_binop_any_nequal
:
874 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
875 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
879 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
880 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
884 assert(!"not reached");
885 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
891 ir
->condition
->accept(this);
893 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
897 with_writemask(dst_reg
const & r
, int mask
)
900 result
.writemask
= mask
;
905 vec4_visitor::emit_attribute_fixups()
907 dst_reg sign_recovery_shift
;
908 dst_reg normalize_factor
;
909 dst_reg es3_normalize_factor
;
911 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
912 if (prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
913 uint8_t wa_flags
= c
->key
.gl_attrib_wa_flags
[i
];
914 dst_reg
reg(ATTR
, i
);
916 reg_d
.type
= BRW_REGISTER_TYPE_D
;
917 dst_reg reg_ud
= reg
;
918 reg_ud
.type
= BRW_REGISTER_TYPE_UD
;
920 /* Do GL_FIXED rescaling for GLES2.0. Our GL_FIXED attributes
921 * come in as floating point conversions of the integer values.
923 if (wa_flags
& BRW_ATTRIB_WA_COMPONENT_MASK
) {
925 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
926 dst
.writemask
= (1 << (wa_flags
& BRW_ATTRIB_WA_COMPONENT_MASK
)) - 1;
927 emit(MUL(dst
, src_reg(dst
), src_reg(1.0f
/ 65536.0f
)));
930 /* Do sign recovery for 2101010 formats if required. */
931 if (wa_flags
& BRW_ATTRIB_WA_SIGN
) {
932 if (sign_recovery_shift
.file
== BAD_FILE
) {
933 /* shift constant: <22,22,22,30> */
934 sign_recovery_shift
= dst_reg(this, glsl_type::uvec4_type
);
935 emit(MOV(with_writemask(sign_recovery_shift
, WRITEMASK_XYZ
), src_reg(22u)));
936 emit(MOV(with_writemask(sign_recovery_shift
, WRITEMASK_W
), src_reg(30u)));
939 emit(SHL(reg_ud
, src_reg(reg_ud
), src_reg(sign_recovery_shift
)));
940 emit(ASR(reg_d
, src_reg(reg_d
), src_reg(sign_recovery_shift
)));
943 /* Apply BGRA swizzle if required. */
944 if (wa_flags
& BRW_ATTRIB_WA_BGRA
) {
945 src_reg temp
= src_reg(reg
);
946 temp
.swizzle
= BRW_SWIZZLE4(2,1,0,3);
947 emit(MOV(reg
, temp
));
950 if (wa_flags
& BRW_ATTRIB_WA_NORMALIZE
) {
951 /* ES 3.0 has different rules for converting signed normalized
952 * fixed-point numbers than desktop GL.
954 if (_mesa_is_gles3(ctx
) && (wa_flags
& BRW_ATTRIB_WA_SIGN
)) {
955 /* According to equation 2.2 of the ES 3.0 specification,
956 * signed normalization conversion is done by:
958 * f = c / (2^(b-1)-1)
960 if (es3_normalize_factor
.file
== BAD_FILE
) {
961 /* mul constant: 1 / (2^(b-1) - 1) */
962 es3_normalize_factor
= dst_reg(this, glsl_type::vec4_type
);
963 emit(MOV(with_writemask(es3_normalize_factor
, WRITEMASK_XYZ
),
964 src_reg(1.0f
/ ((1<<9) - 1))));
965 emit(MOV(with_writemask(es3_normalize_factor
, WRITEMASK_W
),
966 src_reg(1.0f
/ ((1<<1) - 1))));
970 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
971 emit(MOV(dst
, src_reg(reg_d
)));
972 emit(MUL(dst
, src_reg(dst
), src_reg(es3_normalize_factor
)));
973 emit_minmax(BRW_CONDITIONAL_G
, dst
, src_reg(dst
), src_reg(-1.0f
));
975 /* The following equations are from the OpenGL 3.2 specification:
977 * 2.1 unsigned normalization
980 * 2.2 signed normalization
983 * Both of these share a common divisor, which is represented by
984 * "normalize_factor" in the code below.
986 if (normalize_factor
.file
== BAD_FILE
) {
987 /* 1 / (2^b - 1) for b=<10,10,10,2> */
988 normalize_factor
= dst_reg(this, glsl_type::vec4_type
);
989 emit(MOV(with_writemask(normalize_factor
, WRITEMASK_XYZ
),
990 src_reg(1.0f
/ ((1<<10) - 1))));
991 emit(MOV(with_writemask(normalize_factor
, WRITEMASK_W
),
992 src_reg(1.0f
/ ((1<<2) - 1))));
996 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
997 emit(MOV(dst
, src_reg((wa_flags
& BRW_ATTRIB_WA_SIGN
) ? reg_d
: reg_ud
)));
999 /* For signed normalization, we want the numerator to be 2c+1. */
1000 if (wa_flags
& BRW_ATTRIB_WA_SIGN
) {
1001 emit(MUL(dst
, src_reg(dst
), src_reg(2.0f
)));
1002 emit(ADD(dst
, src_reg(dst
), src_reg(1.0f
)));
1005 emit(MUL(dst
, src_reg(dst
), src_reg(normalize_factor
)));
1009 if (wa_flags
& BRW_ATTRIB_WA_SCALE
) {
1011 dst
.type
= brw_type_for_base_type(glsl_type::vec4_type
);
1012 emit(MOV(dst
, src_reg((wa_flags
& BRW_ATTRIB_WA_SIGN
) ? reg_d
: reg_ud
)));
1019 vec4_visitor::visit(ir_variable
*ir
)
1021 dst_reg
*reg
= NULL
;
1023 if (variable_storage(ir
))
1027 case ir_var_shader_in
:
1028 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
1031 case ir_var_shader_out
:
1032 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1034 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1035 output_reg
[ir
->location
+ i
] = *reg
;
1036 output_reg
[ir
->location
+ i
].reg_offset
= i
;
1037 output_reg
[ir
->location
+ i
].type
=
1038 brw_type_for_base_type(ir
->type
->get_scalar_type());
1039 output_reg_annotation
[ir
->location
+ i
] = ir
->name
;
1044 case ir_var_temporary
:
1045 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1048 case ir_var_uniform
:
1049 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1051 /* Thanks to the lower_ubo_reference pass, we will see only
1052 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1053 * variables, so no need for them to be in variable_ht.
1055 if (ir
->is_in_uniform_block())
1058 /* Track how big the whole uniform variable is, in case we need to put a
1059 * copy of its data into pull constants for array access.
1061 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1063 if (!strncmp(ir
->name
, "gl_", 3)) {
1064 setup_builtin_uniform_values(ir
);
1066 setup_uniform_values(ir
);
1070 case ir_var_system_value
:
1071 /* VertexID is stored by the VF as the last vertex element, but
1072 * we don't represent it with a flag in inputs_read, so we call
1073 * it VERT_ATTRIB_MAX, which setup_attributes() picks up on.
1075 reg
= new(mem_ctx
) dst_reg(ATTR
, VERT_ATTRIB_MAX
);
1076 prog_data
->uses_vertexid
= true;
1078 switch (ir
->location
) {
1079 case SYSTEM_VALUE_VERTEX_ID
:
1080 reg
->writemask
= WRITEMASK_X
;
1082 case SYSTEM_VALUE_INSTANCE_ID
:
1083 reg
->writemask
= WRITEMASK_Y
;
1086 assert(!"not reached");
1092 assert(!"not reached");
1095 reg
->type
= brw_type_for_base_type(ir
->type
);
1096 hash_table_insert(this->variable_ht
, reg
, ir
);
1100 vec4_visitor::visit(ir_loop
*ir
)
1104 /* We don't want debugging output to print the whole body of the
1105 * loop as the annotation.
1107 this->base_ir
= NULL
;
1109 if (ir
->counter
!= NULL
) {
1110 this->base_ir
= ir
->counter
;
1111 ir
->counter
->accept(this);
1112 counter
= *(variable_storage(ir
->counter
));
1114 if (ir
->from
!= NULL
) {
1115 this->base_ir
= ir
->from
;
1116 ir
->from
->accept(this);
1118 emit(MOV(counter
, this->result
));
1122 emit(BRW_OPCODE_DO
);
1125 this->base_ir
= ir
->to
;
1126 ir
->to
->accept(this);
1128 emit(CMP(dst_null_d(), src_reg(counter
), this->result
,
1129 brw_conditional_for_comparison(ir
->cmp
)));
1131 vec4_instruction
*inst
= emit(BRW_OPCODE_BREAK
);
1132 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1135 visit_instructions(&ir
->body_instructions
);
1138 if (ir
->increment
) {
1139 this->base_ir
= ir
->increment
;
1140 ir
->increment
->accept(this);
1141 emit(ADD(counter
, src_reg(counter
), this->result
));
1144 emit(BRW_OPCODE_WHILE
);
1148 vec4_visitor::visit(ir_loop_jump
*ir
)
1151 case ir_loop_jump::jump_break
:
1152 emit(BRW_OPCODE_BREAK
);
1154 case ir_loop_jump::jump_continue
:
1155 emit(BRW_OPCODE_CONTINUE
);
1162 vec4_visitor::visit(ir_function_signature
*ir
)
1169 vec4_visitor::visit(ir_function
*ir
)
1171 /* Ignore function bodies other than main() -- we shouldn't see calls to
1172 * them since they should all be inlined.
1174 if (strcmp(ir
->name
, "main") == 0) {
1175 const ir_function_signature
*sig
;
1178 sig
= ir
->matching_signature(&empty
);
1182 visit_instructions(&sig
->body
);
1187 vec4_visitor::try_emit_sat(ir_expression
*ir
)
1189 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
1193 sat_src
->accept(this);
1194 src_reg src
= this->result
;
1196 this->result
= src_reg(this, ir
->type
);
1197 vec4_instruction
*inst
;
1198 inst
= emit(MOV(dst_reg(this->result
), src
));
1199 inst
->saturate
= true;
1205 vec4_visitor::emit_bool_comparison(unsigned int op
,
1206 dst_reg dst
, src_reg src0
, src_reg src1
)
1208 /* original gen4 does destination conversion before comparison. */
1210 dst
.type
= src0
.type
;
1212 emit(CMP(dst
, src0
, src1
, brw_conditional_for_comparison(op
)));
1214 dst
.type
= BRW_REGISTER_TYPE_D
;
1215 emit(AND(dst
, src_reg(dst
), src_reg(0x1)));
1219 vec4_visitor::emit_minmax(uint32_t conditionalmod
, dst_reg dst
,
1220 src_reg src0
, src_reg src1
)
1222 vec4_instruction
*inst
;
1224 if (intel
->gen
>= 6) {
1225 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1226 inst
->conditional_mod
= conditionalmod
;
1228 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1230 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1231 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1236 vec4_visitor::visit(ir_expression
*ir
)
1238 unsigned int operand
;
1239 src_reg op
[Elements(ir
->operands
)];
1242 vec4_instruction
*inst
;
1244 if (try_emit_sat(ir
))
1247 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1248 this->result
.file
= BAD_FILE
;
1249 ir
->operands
[operand
]->accept(this);
1250 if (this->result
.file
== BAD_FILE
) {
1251 printf("Failed to get tree for expression operand:\n");
1252 ir
->operands
[operand
]->print();
1255 op
[operand
] = this->result
;
1257 /* Matrix expression operands should have been broken down to vector
1258 * operations already.
1260 assert(!ir
->operands
[operand
]->type
->is_matrix());
1263 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1264 if (ir
->operands
[1]) {
1265 vector_elements
= MAX2(vector_elements
,
1266 ir
->operands
[1]->type
->vector_elements
);
1269 this->result
.file
= BAD_FILE
;
1271 /* Storage for our result. Ideally for an assignment we'd be using
1272 * the actual storage for the result here, instead.
1274 result_src
= src_reg(this, ir
->type
);
1275 /* convenience for the emit functions below. */
1276 result_dst
= dst_reg(result_src
);
1277 /* If nothing special happens, this is the result. */
1278 this->result
= result_src
;
1279 /* Limit writes to the channels that will be used by result_src later.
1280 * This does limit this temp's use as a temporary for multi-instruction
1283 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1285 switch (ir
->operation
) {
1286 case ir_unop_logic_not
:
1287 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1288 * ones complement of the whole register, not just bit 0.
1290 emit(XOR(result_dst
, op
[0], src_reg(1)));
1293 op
[0].negate
= !op
[0].negate
;
1294 this->result
= op
[0];
1298 op
[0].negate
= false;
1299 this->result
= op
[0];
1303 emit(MOV(result_dst
, src_reg(0.0f
)));
1305 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_G
));
1306 inst
= emit(MOV(result_dst
, src_reg(1.0f
)));
1307 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1309 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_L
));
1310 inst
= emit(MOV(result_dst
, src_reg(-1.0f
)));
1311 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1316 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1320 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1323 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1327 assert(!"not reached: should be handled by ir_explog_to_explog2");
1330 case ir_unop_sin_reduced
:
1331 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1334 case ir_unop_cos_reduced
:
1335 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1340 assert(!"derivatives not valid in vertex shader");
1344 assert(!"not reached: should be handled by lower_noise");
1348 emit(ADD(result_dst
, op
[0], op
[1]));
1351 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1355 if (ir
->type
->is_integer()) {
1356 /* For integer multiplication, the MUL uses the low 16 bits
1357 * of one of the operands (src0 on gen6, src1 on gen7). The
1358 * MACH accumulates in the contribution of the upper 16 bits
1361 * FINISHME: Emit just the MUL if we know an operand is small
1364 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
1366 emit(MUL(acc
, op
[0], op
[1]));
1367 emit(MACH(dst_null_d(), op
[0], op
[1]));
1368 emit(MOV(result_dst
, src_reg(acc
)));
1370 emit(MUL(result_dst
, op
[0], op
[1]));
1374 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1375 assert(ir
->type
->is_integer());
1376 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1379 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1380 assert(ir
->type
->is_integer());
1381 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1385 case ir_binop_greater
:
1386 case ir_binop_lequal
:
1387 case ir_binop_gequal
:
1388 case ir_binop_equal
:
1389 case ir_binop_nequal
: {
1390 emit(CMP(result_dst
, op
[0], op
[1],
1391 brw_conditional_for_comparison(ir
->operation
)));
1392 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1396 case ir_binop_all_equal
:
1397 /* "==" operator producing a scalar boolean. */
1398 if (ir
->operands
[0]->type
->is_vector() ||
1399 ir
->operands
[1]->type
->is_vector()) {
1400 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1401 emit(MOV(result_dst
, src_reg(0)));
1402 inst
= emit(MOV(result_dst
, src_reg(1)));
1403 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1405 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1406 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1409 case ir_binop_any_nequal
:
1410 /* "!=" operator producing a scalar boolean. */
1411 if (ir
->operands
[0]->type
->is_vector() ||
1412 ir
->operands
[1]->type
->is_vector()) {
1413 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1415 emit(MOV(result_dst
, src_reg(0)));
1416 inst
= emit(MOV(result_dst
, src_reg(1)));
1417 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1419 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1420 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1425 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1426 emit(MOV(result_dst
, src_reg(0)));
1428 inst
= emit(MOV(result_dst
, src_reg(1)));
1429 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1432 case ir_binop_logic_xor
:
1433 emit(XOR(result_dst
, op
[0], op
[1]));
1436 case ir_binop_logic_or
:
1437 emit(OR(result_dst
, op
[0], op
[1]));
1440 case ir_binop_logic_and
:
1441 emit(AND(result_dst
, op
[0], op
[1]));
1445 assert(ir
->operands
[0]->type
->is_vector());
1446 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1447 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1451 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1454 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1457 case ir_unop_bitcast_i2f
:
1458 case ir_unop_bitcast_u2f
:
1459 this->result
= op
[0];
1460 this->result
.type
= BRW_REGISTER_TYPE_F
;
1463 case ir_unop_bitcast_f2i
:
1464 this->result
= op
[0];
1465 this->result
.type
= BRW_REGISTER_TYPE_D
;
1468 case ir_unop_bitcast_f2u
:
1469 this->result
= op
[0];
1470 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1481 emit(MOV(result_dst
, op
[0]));
1485 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1486 emit(AND(result_dst
, result_src
, src_reg(1)));
1491 emit(RNDZ(result_dst
, op
[0]));
1494 op
[0].negate
= !op
[0].negate
;
1495 inst
= emit(RNDD(result_dst
, op
[0]));
1496 this->result
.negate
= true;
1499 inst
= emit(RNDD(result_dst
, op
[0]));
1502 inst
= emit(FRC(result_dst
, op
[0]));
1504 case ir_unop_round_even
:
1505 emit(RNDE(result_dst
, op
[0]));
1509 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1512 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1516 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1519 case ir_unop_bit_not
:
1520 inst
= emit(NOT(result_dst
, op
[0]));
1522 case ir_binop_bit_and
:
1523 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1525 case ir_binop_bit_xor
:
1526 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1528 case ir_binop_bit_or
:
1529 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1532 case ir_binop_lshift
:
1533 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1536 case ir_binop_rshift
:
1537 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1538 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1540 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1543 case ir_binop_ubo_load
: {
1544 ir_constant
*uniform_block
= ir
->operands
[0]->as_constant();
1545 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1546 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1547 src_reg offset
= op
[1];
1549 /* Now, load the vector from that offset. */
1550 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1552 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1553 packed_consts
.type
= result
.type
;
1554 src_reg surf_index
=
1555 src_reg(SURF_INDEX_VS_UBO(uniform_block
->value
.u
[0]));
1556 if (const_offset_ir
) {
1557 offset
= src_reg(const_offset
/ 16);
1559 emit(SHR(dst_reg(offset
), offset
, src_reg(4)));
1562 vec4_instruction
*pull
=
1563 emit(new(mem_ctx
) vec4_instruction(this,
1564 VS_OPCODE_PULL_CONSTANT_LOAD
,
1565 dst_reg(packed_consts
),
1568 pull
->base_mrf
= 14;
1571 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1572 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1573 const_offset
% 16 / 4,
1574 const_offset
% 16 / 4,
1575 const_offset
% 16 / 4);
1577 /* UBO bools are any nonzero int. We store bools as either 0 or 1. */
1578 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1579 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1580 BRW_CONDITIONAL_NZ
));
1581 emit(AND(result_dst
, result
, src_reg(0x1)));
1583 emit(MOV(result_dst
, packed_consts
));
1589 assert(!"not reached: should be handled by lrp_to_arith");
1592 case ir_quadop_vector
:
1593 assert(!"not reached: should be handled by lower_quadop_vector");
1596 case ir_unop_pack_half_2x16
:
1597 emit_pack_half_2x16(result_dst
, op
[0]);
1599 case ir_unop_unpack_half_2x16
:
1600 emit_unpack_half_2x16(result_dst
, op
[0]);
1602 case ir_unop_pack_snorm_2x16
:
1603 case ir_unop_pack_snorm_4x8
:
1604 case ir_unop_pack_unorm_2x16
:
1605 case ir_unop_pack_unorm_4x8
:
1606 case ir_unop_unpack_snorm_2x16
:
1607 case ir_unop_unpack_snorm_4x8
:
1608 case ir_unop_unpack_unorm_2x16
:
1609 case ir_unop_unpack_unorm_4x8
:
1610 assert(!"not reached: should be handled by lower_packing_builtins");
1612 case ir_unop_unpack_half_2x16_split_x
:
1613 case ir_unop_unpack_half_2x16_split_y
:
1614 case ir_binop_pack_half_2x16_split
:
1615 assert(!"not reached: should not occur in vertex shader");
1622 vec4_visitor::visit(ir_swizzle
*ir
)
1628 /* Note that this is only swizzles in expressions, not those on the left
1629 * hand side of an assignment, which do write masking. See ir_assignment
1633 ir
->val
->accept(this);
1635 assert(src
.file
!= BAD_FILE
);
1637 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1640 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1643 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1646 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1649 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1653 for (; i
< 4; i
++) {
1654 /* Replicate the last channel out. */
1655 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1658 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1664 vec4_visitor::visit(ir_dereference_variable
*ir
)
1666 const struct glsl_type
*type
= ir
->type
;
1667 dst_reg
*reg
= variable_storage(ir
->var
);
1670 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1671 this->result
= src_reg(brw_null_reg());
1675 this->result
= src_reg(*reg
);
1677 /* System values get their swizzle from the dst_reg writemask */
1678 if (ir
->var
->mode
== ir_var_system_value
)
1681 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1682 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1686 vec4_visitor::visit(ir_dereference_array
*ir
)
1688 ir_constant
*constant_index
;
1690 int element_size
= type_size(ir
->type
);
1692 constant_index
= ir
->array_index
->constant_expression_value();
1694 ir
->array
->accept(this);
1697 if (constant_index
) {
1698 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1700 /* Variable index array dereference. It eats the "vec4" of the
1701 * base of the array and an index that offsets the Mesa register
1704 ir
->array_index
->accept(this);
1708 if (element_size
== 1) {
1709 index_reg
= this->result
;
1711 index_reg
= src_reg(this, glsl_type::int_type
);
1713 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(element_size
)));
1717 src_reg temp
= src_reg(this, glsl_type::int_type
);
1719 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1724 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1725 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1728 /* If the type is smaller than a vec4, replicate the last channel out. */
1729 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1730 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1732 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1733 src
.type
= brw_type_for_base_type(ir
->type
);
1739 vec4_visitor::visit(ir_dereference_record
*ir
)
1742 const glsl_type
*struct_type
= ir
->record
->type
;
1745 ir
->record
->accept(this);
1747 for (i
= 0; i
< struct_type
->length
; i
++) {
1748 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1750 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1753 /* If the type is smaller than a vec4, replicate the last channel out. */
1754 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1755 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1757 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1758 this->result
.type
= brw_type_for_base_type(ir
->type
);
1760 this->result
.reg_offset
+= offset
;
1764 * We want to be careful in assignment setup to hit the actual storage
1765 * instead of potentially using a temporary like we might with the
1766 * ir_dereference handler.
1769 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1771 /* The LHS must be a dereference. If the LHS is a variable indexed array
1772 * access of a vector, it must be separated into a series conditional moves
1773 * before reaching this point (see ir_vec_index_to_cond_assign).
1775 assert(ir
->as_dereference());
1776 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1778 assert(!deref_array
->array
->type
->is_vector());
1781 /* Use the rvalue deref handler for the most part. We'll ignore
1782 * swizzles in it and write swizzles using writemask, though.
1785 return dst_reg(v
->result
);
1789 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1790 const struct glsl_type
*type
, uint32_t predicate
)
1792 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1793 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1794 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1799 if (type
->is_array()) {
1800 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1801 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1806 if (type
->is_matrix()) {
1807 const struct glsl_type
*vec_type
;
1809 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1810 type
->vector_elements
, 1);
1812 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1813 emit_block_move(dst
, src
, vec_type
, predicate
);
1818 assert(type
->is_scalar() || type
->is_vector());
1820 dst
->type
= brw_type_for_base_type(type
);
1821 src
->type
= dst
->type
;
1823 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1825 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1827 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1828 inst
->predicate
= predicate
;
1835 /* If the RHS processing resulted in an instruction generating a
1836 * temporary value, and it would be easy to rewrite the instruction to
1837 * generate its result right into the LHS instead, do so. This ends
1838 * up reliably removing instructions where it can be tricky to do so
1839 * later without real UD chain information.
1842 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1845 vec4_instruction
*pre_rhs_inst
,
1846 vec4_instruction
*last_rhs_inst
)
1848 /* This could be supported, but it would take more smarts. */
1852 if (pre_rhs_inst
== last_rhs_inst
)
1853 return false; /* No instructions generated to work with. */
1855 /* Make sure the last instruction generated our source reg. */
1856 if (src
.file
!= GRF
||
1857 src
.file
!= last_rhs_inst
->dst
.file
||
1858 src
.reg
!= last_rhs_inst
->dst
.reg
||
1859 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1863 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1866 /* Check that that last instruction fully initialized the channels
1867 * we want to use, in the order we want to use them. We could
1868 * potentially reswizzle the operands of many instructions so that
1869 * we could handle out of order channels, but don't yet.
1872 for (unsigned i
= 0; i
< 4; i
++) {
1873 if (dst
.writemask
& (1 << i
)) {
1874 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1877 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1882 /* Success! Rewrite the instruction. */
1883 last_rhs_inst
->dst
.file
= dst
.file
;
1884 last_rhs_inst
->dst
.reg
= dst
.reg
;
1885 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1886 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1887 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1893 vec4_visitor::visit(ir_assignment
*ir
)
1895 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1896 uint32_t predicate
= BRW_PREDICATE_NONE
;
1898 if (!ir
->lhs
->type
->is_scalar() &&
1899 !ir
->lhs
->type
->is_vector()) {
1900 ir
->rhs
->accept(this);
1901 src_reg src
= this->result
;
1903 if (ir
->condition
) {
1904 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1907 /* emit_block_move doesn't account for swizzles in the source register.
1908 * This should be ok, since the source register is a structure or an
1909 * array, and those can't be swizzled. But double-check to be sure.
1911 assert(src
.swizzle
==
1912 (ir
->rhs
->type
->is_matrix()
1913 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
1914 : BRW_SWIZZLE_NOOP
));
1916 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
1920 /* Now we're down to just a scalar/vector with writemasks. */
1923 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1924 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1926 ir
->rhs
->accept(this);
1928 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1930 src_reg src
= this->result
;
1933 int first_enabled_chan
= 0;
1936 assert(ir
->lhs
->type
->is_vector() ||
1937 ir
->lhs
->type
->is_scalar());
1938 dst
.writemask
= ir
->write_mask
;
1940 for (int i
= 0; i
< 4; i
++) {
1941 if (dst
.writemask
& (1 << i
)) {
1942 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1947 /* Swizzle a small RHS vector into the channels being written.
1949 * glsl ir treats write_mask as dictating how many channels are
1950 * present on the RHS while in our instructions we need to make
1951 * those channels appear in the slots of the vec4 they're written to.
1953 for (int i
= 0; i
< 4; i
++) {
1954 if (dst
.writemask
& (1 << i
))
1955 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1957 swizzles
[i
] = first_enabled_chan
;
1959 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1960 swizzles
[2], swizzles
[3]);
1962 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
1966 if (ir
->condition
) {
1967 emit_bool_to_cond_code(ir
->condition
, &predicate
);
1970 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1971 vec4_instruction
*inst
= emit(MOV(dst
, src
));
1972 inst
->predicate
= predicate
;
1980 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
1982 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1983 foreach_list(node
, &ir
->components
) {
1984 ir_constant
*field_value
= (ir_constant
*)node
;
1986 emit_constant_values(dst
, field_value
);
1991 if (ir
->type
->is_array()) {
1992 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1993 emit_constant_values(dst
, ir
->array_elements
[i
]);
1998 if (ir
->type
->is_matrix()) {
1999 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2000 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2002 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2003 dst
->writemask
= 1 << j
;
2004 dst
->type
= BRW_REGISTER_TYPE_F
;
2006 emit(MOV(*dst
, src_reg(vec
[j
])));
2013 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2015 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2016 if (!(remaining_writemask
& (1 << i
)))
2019 dst
->writemask
= 1 << i
;
2020 dst
->type
= brw_type_for_base_type(ir
->type
);
2022 /* Find other components that match the one we're about to
2023 * write. Emits fewer instructions for things like vec4(0.5,
2026 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2027 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2028 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2029 dst
->writemask
|= (1 << j
);
2031 /* u, i, and f storage all line up, so no need for a
2032 * switch case for comparing each type.
2034 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2035 dst
->writemask
|= (1 << j
);
2039 switch (ir
->type
->base_type
) {
2040 case GLSL_TYPE_FLOAT
:
2041 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2044 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2046 case GLSL_TYPE_UINT
:
2047 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2049 case GLSL_TYPE_BOOL
:
2050 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
2053 assert(!"Non-float/uint/int/bool constant");
2057 remaining_writemask
&= ~dst
->writemask
;
2063 vec4_visitor::visit(ir_constant
*ir
)
2065 dst_reg dst
= dst_reg(this, ir
->type
);
2066 this->result
= src_reg(dst
);
2068 emit_constant_values(&dst
, ir
);
2072 vec4_visitor::visit(ir_call
*ir
)
2074 assert(!"not reached");
2078 vec4_visitor::visit(ir_texture
*ir
)
2080 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &vp
->Base
);
2082 /* Should be lowered by do_lower_texture_projection */
2083 assert(!ir
->projector
);
2085 /* Generate code to compute all the subexpression trees. This has to be
2086 * done before loading any values into MRFs for the sampler message since
2087 * generating these values may involve SEND messages that need the MRFs.
2090 if (ir
->coordinate
) {
2091 ir
->coordinate
->accept(this);
2092 coordinate
= this->result
;
2095 src_reg shadow_comparitor
;
2096 if (ir
->shadow_comparitor
) {
2097 ir
->shadow_comparitor
->accept(this);
2098 shadow_comparitor
= this->result
;
2101 const glsl_type
*lod_type
;
2102 src_reg lod
, dPdx
, dPdy
;
2105 lod
= src_reg(0.0f
);
2106 lod_type
= glsl_type::float_type
;
2111 ir
->lod_info
.lod
->accept(this);
2113 lod_type
= ir
->lod_info
.lod
->type
;
2116 ir
->lod_info
.grad
.dPdx
->accept(this);
2117 dPdx
= this->result
;
2119 ir
->lod_info
.grad
.dPdy
->accept(this);
2120 dPdy
= this->result
;
2122 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2128 vec4_instruction
*inst
= NULL
;
2132 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXL
);
2135 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXD
);
2138 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF
);
2141 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXS
);
2144 assert(!"TXB is not valid for vertex shaders.");
2147 bool use_texture_offset
= ir
->offset
!= NULL
&& ir
->op
!= ir_txf
;
2149 /* Texel offsets go in the message header; Gen4 also requires headers. */
2150 inst
->header_present
= use_texture_offset
|| intel
->gen
< 5;
2152 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2153 inst
->sampler
= sampler
;
2154 inst
->dst
= dst_reg(this, ir
->type
);
2155 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2156 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2158 if (use_texture_offset
)
2159 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
2161 /* MRF for the first parameter */
2162 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2164 if (ir
->op
== ir_txs
) {
2165 int writemask
= intel
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2166 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2168 int i
, coord_mask
= 0, zero_mask
= 0;
2169 /* Load the coordinate */
2170 /* FINISHME: gl_clamp_mask and saturate */
2171 for (i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++)
2172 coord_mask
|= (1 << i
);
2174 zero_mask
|= (1 << i
);
2176 if (ir
->offset
&& ir
->op
== ir_txf
) {
2177 /* It appears that the ld instruction used for txf does its
2178 * address bounds check before adding in the offset. To work
2179 * around this, just add the integer offset to the integer
2180 * texel coordinate, and don't put the offset in the header.
2182 ir_constant
*offset
= ir
->offset
->as_constant();
2185 for (int j
= 0; j
< ir
->coordinate
->type
->vector_elements
; j
++) {
2186 src_reg src
= coordinate
;
2187 src
.swizzle
= BRW_SWIZZLE4(BRW_GET_SWZ(src
.swizzle
, j
),
2188 BRW_GET_SWZ(src
.swizzle
, j
),
2189 BRW_GET_SWZ(src
.swizzle
, j
),
2190 BRW_GET_SWZ(src
.swizzle
, j
));
2191 emit(ADD(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, 1 << j
),
2192 src
, offset
->value
.i
[j
]));
2195 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2198 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2200 /* Load the shadow comparitor */
2201 if (ir
->shadow_comparitor
) {
2202 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2204 shadow_comparitor
));
2208 /* Load the LOD info */
2209 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2211 if (intel
->gen
>= 5) {
2212 mrf
= param_base
+ 1;
2213 if (ir
->shadow_comparitor
) {
2214 writemask
= WRITEMASK_Y
;
2215 /* mlen already incremented */
2217 writemask
= WRITEMASK_X
;
2220 } else /* intel->gen == 4 */ {
2222 writemask
= WRITEMASK_Z
;
2224 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2225 } else if (ir
->op
== ir_txf
) {
2226 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
),
2228 } else if (ir
->op
== ir_txd
) {
2229 const glsl_type
*type
= lod_type
;
2231 if (intel
->gen
>= 5) {
2232 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2233 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2234 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2235 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2238 if (ir
->type
->vector_elements
== 3) {
2239 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2240 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2241 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2242 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2245 } else /* intel->gen == 4 */ {
2246 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2247 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2255 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2256 * spec requires layers.
2258 if (ir
->op
== ir_txs
) {
2259 glsl_type
const *type
= ir
->sampler
->type
;
2260 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2261 type
->sampler_array
) {
2262 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2263 with_writemask(inst
->dst
, WRITEMASK_Z
),
2264 src_reg(inst
->dst
), src_reg(6));
2268 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2272 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, int sampler
)
2274 int s
= c
->key
.tex
.swizzles
[sampler
];
2276 this->result
= src_reg(this, ir
->type
);
2277 dst_reg
swizzled_result(this->result
);
2279 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2280 || s
== SWIZZLE_NOOP
) {
2281 emit(MOV(swizzled_result
, orig_val
));
2285 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2288 for (int i
= 0; i
< 4; i
++) {
2289 switch (GET_SWZ(s
, i
)) {
2291 zero_mask
|= (1 << i
);
2294 one_mask
|= (1 << i
);
2297 copy_mask
|= (1 << i
);
2298 swizzle
[i
] = GET_SWZ(s
, i
);
2304 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2305 swizzled_result
.writemask
= copy_mask
;
2306 emit(MOV(swizzled_result
, orig_val
));
2310 swizzled_result
.writemask
= zero_mask
;
2311 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2315 swizzled_result
.writemask
= one_mask
;
2316 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2321 vec4_visitor::visit(ir_return
*ir
)
2323 assert(!"not reached");
2327 vec4_visitor::visit(ir_discard
*ir
)
2329 assert(!"not reached");
2333 vec4_visitor::visit(ir_if
*ir
)
2335 /* Don't point the annotation at the if statement, because then it plus
2336 * the then and else blocks get printed.
2338 this->base_ir
= ir
->condition
;
2340 if (intel
->gen
== 6) {
2344 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2345 emit(IF(predicate
));
2348 visit_instructions(&ir
->then_instructions
);
2350 if (!ir
->else_instructions
.is_empty()) {
2351 this->base_ir
= ir
->condition
;
2352 emit(BRW_OPCODE_ELSE
);
2354 visit_instructions(&ir
->else_instructions
);
2357 this->base_ir
= ir
->condition
;
2358 emit(BRW_OPCODE_ENDIF
);
2362 vec4_visitor::emit_ndc_computation()
2364 /* Get the position */
2365 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
2367 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2368 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2369 output_reg
[BRW_VERT_RESULT_NDC
] = ndc
;
2371 current_annotation
= "NDC";
2372 dst_reg ndc_w
= ndc
;
2373 ndc_w
.writemask
= WRITEMASK_W
;
2374 src_reg pos_w
= pos
;
2375 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2376 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2378 dst_reg ndc_xyz
= ndc
;
2379 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2381 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2385 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
2387 if (intel
->gen
< 6 &&
2388 ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
2389 c
->key
.userclip_active
|| brw
->has_negative_rhw_bug
)) {
2390 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2391 dst_reg header1_w
= header1
;
2392 header1_w
.writemask
= WRITEMASK_W
;
2395 emit(MOV(header1
, 0u));
2397 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
2398 src_reg psiz
= src_reg(output_reg
[VERT_RESULT_PSIZ
]);
2400 current_annotation
= "Point size";
2401 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2402 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2405 current_annotation
= "Clipping flags";
2406 for (i
= 0; i
< c
->key
.nr_userclip_plane_consts
; i
++) {
2407 vec4_instruction
*inst
;
2409 inst
= emit(DP4(dst_null_f(), src_reg(output_reg
[VERT_RESULT_HPOS
]),
2410 src_reg(this->userplane
[i
])));
2411 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
2413 inst
= emit(OR(header1_w
, src_reg(header1_w
), 1u << i
));
2414 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2417 /* i965 clipping workaround:
2418 * 1) Test for -ve rhw
2420 * set ndc = (0,0,0,0)
2423 * Later, clipping will detect ucp[6] and ensure the primitive is
2424 * clipped against all fixed planes.
2426 if (brw
->has_negative_rhw_bug
) {
2427 src_reg ndc_w
= src_reg(output_reg
[BRW_VERT_RESULT_NDC
]);
2428 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2429 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2430 vec4_instruction
*inst
;
2431 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2432 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2433 inst
= emit(MOV(output_reg
[BRW_VERT_RESULT_NDC
], src_reg(0.0f
)));
2434 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2437 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2438 } else if (intel
->gen
< 6) {
2439 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2441 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2442 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
2443 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
2444 src_reg(output_reg
[VERT_RESULT_PSIZ
])));
2450 vec4_visitor::emit_clip_distances(struct brw_reg reg
, int offset
)
2452 if (intel
->gen
< 6) {
2453 /* Clip distance slots are set aside in gen5, but they are not used. It
2454 * is not clear whether we actually need to set aside space for them,
2455 * but the performance cost is negligible.
2460 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2462 * "If a linked set of shaders forming the vertex stage contains no
2463 * static write to gl_ClipVertex or gl_ClipDistance, but the
2464 * application has requested clipping against user clip planes through
2465 * the API, then the coordinate written to gl_Position is used for
2466 * comparison against the user clip planes."
2468 * This function is only called if the shader didn't write to
2469 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2470 * if the user wrote to it; otherwise we use gl_Position.
2472 gl_vert_result clip_vertex
= VERT_RESULT_CLIP_VERTEX
;
2473 if (!(c
->prog_data
.outputs_written
2474 & BITFIELD64_BIT(VERT_RESULT_CLIP_VERTEX
))) {
2475 clip_vertex
= VERT_RESULT_HPOS
;
2478 for (int i
= 0; i
+ offset
< c
->key
.nr_userclip_plane_consts
&& i
< 4;
2480 emit(DP4(dst_reg(brw_writemask(reg
, 1 << i
)),
2481 src_reg(output_reg
[clip_vertex
]),
2482 src_reg(this->userplane
[i
+ offset
])));
2487 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int vert_result
)
2489 assert (vert_result
< VERT_RESULT_MAX
);
2490 reg
.type
= output_reg
[vert_result
].type
;
2491 current_annotation
= output_reg_annotation
[vert_result
];
2492 /* Copy the register, saturating if necessary */
2493 vec4_instruction
*inst
= emit(MOV(reg
,
2494 src_reg(output_reg
[vert_result
])));
2495 if ((vert_result
== VERT_RESULT_COL0
||
2496 vert_result
== VERT_RESULT_COL1
||
2497 vert_result
== VERT_RESULT_BFC0
||
2498 vert_result
== VERT_RESULT_BFC1
) &&
2499 c
->key
.clamp_vertex_color
) {
2500 inst
->saturate
= true;
2505 vec4_visitor::emit_urb_slot(int mrf
, int vert_result
)
2507 struct brw_reg hw_reg
= brw_message_reg(mrf
);
2508 dst_reg reg
= dst_reg(MRF
, mrf
);
2509 reg
.type
= BRW_REGISTER_TYPE_F
;
2511 switch (vert_result
) {
2512 case VERT_RESULT_PSIZ
:
2513 /* PSIZ is always in slot 0, and is coupled with other flags. */
2514 current_annotation
= "indices, point width, clip flags";
2515 emit_psiz_and_flags(hw_reg
);
2517 case BRW_VERT_RESULT_NDC
:
2518 current_annotation
= "NDC";
2519 emit(MOV(reg
, src_reg(output_reg
[BRW_VERT_RESULT_NDC
])));
2521 case BRW_VERT_RESULT_HPOS_DUPLICATE
:
2522 case VERT_RESULT_HPOS
:
2523 current_annotation
= "gl_Position";
2524 emit(MOV(reg
, src_reg(output_reg
[VERT_RESULT_HPOS
])));
2526 case VERT_RESULT_CLIP_DIST0
:
2527 case VERT_RESULT_CLIP_DIST1
:
2528 if (this->c
->key
.uses_clip_distance
) {
2529 emit_generic_urb_slot(reg
, vert_result
);
2531 current_annotation
= "user clip distances";
2532 emit_clip_distances(hw_reg
, (vert_result
- VERT_RESULT_CLIP_DIST0
) * 4);
2535 case VERT_RESULT_EDGE
:
2536 /* This is present when doing unfilled polygons. We're supposed to copy
2537 * the edge flag from the user-provided vertex array
2538 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
2539 * of that attribute (starts as 1.0f). This is then used in clipping to
2540 * determine which edges should be drawn as wireframe.
2542 current_annotation
= "edge flag";
2543 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
2544 glsl_type::float_type
, WRITEMASK_XYZW
))));
2546 case BRW_VERT_RESULT_PAD
:
2547 /* No need to write to this slot */
2550 emit_generic_urb_slot(reg
, vert_result
);
2556 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
2558 struct intel_context
*intel
= &brw
->intel
;
2560 if (intel
->gen
>= 6) {
2561 /* URB data written (does not include the message header reg) must
2562 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
2563 * section 5.4.3.2.2: URB_INTERLEAVED.
2565 * URB entries are allocated on a multiple of 1024 bits, so an
2566 * extra 128 bits written here to make the end align to 256 is
2569 if ((mlen
% 2) != 1)
2577 * Generates the VUE payload plus the 1 or 2 URB write instructions to
2578 * complete the VS thread.
2580 * The VUE layout is documented in Volume 2a.
2583 vec4_visitor::emit_urb_writes()
2585 /* MRF 0 is reserved for the debugger, so start with message header
2590 /* In the process of generating our URB write message contents, we
2591 * may need to unspill a register or load from an array. Those
2592 * reads would use MRFs 14-15.
2594 int max_usable_mrf
= 13;
2596 /* The following assertion verifies that max_usable_mrf causes an
2597 * even-numbered amount of URB write data, which will meet gen6's
2598 * requirements for length alignment.
2600 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
2602 /* First mrf is the g0-based message header containing URB handles and such,
2603 * which is implied in VS_OPCODE_URB_WRITE.
2607 if (intel
->gen
< 6) {
2608 emit_ndc_computation();
2611 /* Set up the VUE data for the first URB write */
2613 for (slot
= 0; slot
< c
->prog_data
.vue_map
.num_slots
; ++slot
) {
2614 emit_urb_slot(mrf
++, c
->prog_data
.vue_map
.slot_to_vert_result
[slot
]);
2616 /* If this was max_usable_mrf, we can't fit anything more into this URB
2619 if (mrf
> max_usable_mrf
) {
2625 current_annotation
= "URB write";
2626 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
2627 inst
->base_mrf
= base_mrf
;
2628 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2629 inst
->eot
= (slot
>= c
->prog_data
.vue_map
.num_slots
);
2631 /* Optional second URB write */
2635 for (; slot
< c
->prog_data
.vue_map
.num_slots
; ++slot
) {
2636 assert(mrf
< max_usable_mrf
);
2638 emit_urb_slot(mrf
++, c
->prog_data
.vue_map
.slot_to_vert_result
[slot
]);
2641 current_annotation
= "URB write";
2642 inst
= emit(VS_OPCODE_URB_WRITE
);
2643 inst
->base_mrf
= base_mrf
;
2644 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
2646 /* URB destination offset. In the previous write, we got MRFs
2647 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
2648 * URB row increments, and each of our MRFs is half of one of
2649 * those, since we're doing interleaved writes.
2651 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
2656 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
2657 src_reg
*reladdr
, int reg_offset
)
2659 /* Because we store the values to scratch interleaved like our
2660 * vertex data, we need to scale the vec4 index by 2.
2662 int message_header_scale
= 2;
2664 /* Pre-gen6, the message header uses byte offsets instead of vec4
2665 * (16-byte) offset units.
2668 message_header_scale
*= 16;
2671 src_reg index
= src_reg(this, glsl_type::int_type
);
2673 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2674 emit_before(inst
, MUL(dst_reg(index
),
2675 index
, src_reg(message_header_scale
)));
2679 return src_reg(reg_offset
* message_header_scale
);
2684 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
2685 src_reg
*reladdr
, int reg_offset
)
2688 src_reg index
= src_reg(this, glsl_type::int_type
);
2690 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
2692 /* Pre-gen6, the message header uses byte offsets instead of vec4
2693 * (16-byte) offset units.
2695 if (intel
->gen
< 6) {
2696 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
2701 int message_header_scale
= intel
->gen
< 6 ? 16 : 1;
2702 return src_reg(reg_offset
* message_header_scale
);
2707 * Emits an instruction before @inst to load the value named by @orig_src
2708 * from scratch space at @base_offset to @temp.
2710 * @base_offset is measured in 32-byte units (the size of a register).
2713 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2714 dst_reg temp
, src_reg orig_src
,
2717 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2718 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2720 emit_before(inst
, SCRATCH_READ(temp
, index
));
2724 * Emits an instruction after @inst to store the value to be written
2725 * to @orig_dst to scratch space at @base_offset, from @temp.
2727 * @base_offset is measured in 32-byte units (the size of a register).
2730 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
, int base_offset
)
2732 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
2733 src_reg index
= get_scratch_offset(inst
, inst
->dst
.reladdr
, reg_offset
);
2735 /* Create a temporary register to store *inst's result in.
2737 * We have to be careful in MOVing from our temporary result register in
2738 * the scratch write. If we swizzle from channels of the temporary that
2739 * weren't initialized, it will confuse live interval analysis, which will
2740 * make spilling fail to make progress.
2742 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2743 temp
.type
= inst
->dst
.type
;
2744 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
2746 for (int i
= 0; i
< 4; i
++)
2747 if (inst
->dst
.writemask
& (1 << i
))
2750 swizzles
[i
] = first_writemask_chan
;
2751 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2752 swizzles
[2], swizzles
[3]);
2754 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
2755 inst
->dst
.writemask
));
2756 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
2757 write
->predicate
= inst
->predicate
;
2758 write
->ir
= inst
->ir
;
2759 write
->annotation
= inst
->annotation
;
2760 inst
->insert_after(write
);
2762 inst
->dst
.file
= temp
.file
;
2763 inst
->dst
.reg
= temp
.reg
;
2764 inst
->dst
.reg_offset
= temp
.reg_offset
;
2765 inst
->dst
.reladdr
= NULL
;
2769 * We can't generally support array access in GRF space, because a
2770 * single instruction's destination can only span 2 contiguous
2771 * registers. So, we send all GRF arrays that get variable index
2772 * access to scratch space.
2775 vec4_visitor::move_grf_array_access_to_scratch()
2777 int scratch_loc
[this->virtual_grf_count
];
2779 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2780 scratch_loc
[i
] = -1;
2783 /* First, calculate the set of virtual GRFs that need to be punted
2784 * to scratch due to having any array access on them, and where in
2787 foreach_list(node
, &this->instructions
) {
2788 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2790 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2791 scratch_loc
[inst
->dst
.reg
] == -1) {
2792 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2793 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
2796 for (int i
= 0 ; i
< 3; i
++) {
2797 src_reg
*src
= &inst
->src
[i
];
2799 if (src
->file
== GRF
&& src
->reladdr
&&
2800 scratch_loc
[src
->reg
] == -1) {
2801 scratch_loc
[src
->reg
] = c
->last_scratch
;
2802 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
2807 /* Now, for anything that will be accessed through scratch, rewrite
2808 * it to load/store. Note that this is a _safe list walk, because
2809 * we may generate a new scratch_write instruction after the one
2812 foreach_list_safe(node
, &this->instructions
) {
2813 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2815 /* Set up the annotation tracking for new generated instructions. */
2817 current_annotation
= inst
->annotation
;
2819 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2820 emit_scratch_write(inst
, scratch_loc
[inst
->dst
.reg
]);
2823 for (int i
= 0 ; i
< 3; i
++) {
2824 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2827 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2829 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2830 scratch_loc
[inst
->src
[i
].reg
]);
2832 inst
->src
[i
].file
= temp
.file
;
2833 inst
->src
[i
].reg
= temp
.reg
;
2834 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2835 inst
->src
[i
].reladdr
= NULL
;
2841 * Emits an instruction before @inst to load the value named by @orig_src
2842 * from the pull constant buffer (surface) at @base_offset to @temp.
2845 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
2846 dst_reg temp
, src_reg orig_src
,
2849 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2850 src_reg index
= src_reg((unsigned)SURF_INDEX_VERT_CONST_BUFFER
);
2851 src_reg offset
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
2852 vec4_instruction
*load
;
2854 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
2855 temp
, index
, offset
);
2856 load
->base_mrf
= 14;
2858 emit_before(inst
, load
);
2862 * Implements array access of uniforms by inserting a
2863 * PULL_CONSTANT_LOAD instruction.
2865 * Unlike temporary GRF array access (where we don't support it due to
2866 * the difficulty of doing relative addressing on instruction
2867 * destinations), we could potentially do array access of uniforms
2868 * that were loaded in GRF space as push constants. In real-world
2869 * usage we've seen, though, the arrays being used are always larger
2870 * than we could load as push constants, so just always move all
2871 * uniform array access out to a pull constant buffer.
2874 vec4_visitor::move_uniform_array_access_to_pull_constants()
2876 int pull_constant_loc
[this->uniforms
];
2878 for (int i
= 0; i
< this->uniforms
; i
++) {
2879 pull_constant_loc
[i
] = -1;
2882 /* Walk through and find array access of uniforms. Put a copy of that
2883 * uniform in the pull constant buffer.
2885 * Note that we don't move constant-indexed accesses to arrays. No
2886 * testing has been done of the performance impact of this choice.
2888 foreach_list_safe(node
, &this->instructions
) {
2889 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2891 for (int i
= 0 ; i
< 3; i
++) {
2892 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2895 int uniform
= inst
->src
[i
].reg
;
2897 /* If this array isn't already present in the pull constant buffer,
2900 if (pull_constant_loc
[uniform
] == -1) {
2901 const float **values
= &prog_data
->param
[uniform
* 4];
2903 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
/ 4;
2905 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
2906 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
2910 /* Set up the annotation tracking for new generated instructions. */
2912 current_annotation
= inst
->annotation
;
2914 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2916 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
2917 pull_constant_loc
[uniform
]);
2919 inst
->src
[i
].file
= temp
.file
;
2920 inst
->src
[i
].reg
= temp
.reg
;
2921 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2922 inst
->src
[i
].reladdr
= NULL
;
2926 /* Now there are no accesses of the UNIFORM file with a reladdr, so
2927 * no need to track them as larger-than-vec4 objects. This will be
2928 * relied on in cutting out unused uniform vectors from push
2931 split_uniform_registers();
2935 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
2937 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2941 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
2942 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
2946 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
2947 struct brw_vs_compile
*c
,
2948 struct gl_shader_program
*prog
,
2949 struct brw_shader
*shader
,
2954 this->intel
= &brw
->intel
;
2955 this->ctx
= &intel
->ctx
;
2957 this->shader
= shader
;
2959 this->mem_ctx
= mem_ctx
;
2960 this->failed
= false;
2962 this->base_ir
= NULL
;
2963 this->current_annotation
= NULL
;
2964 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
2967 this->vp
= &c
->vp
->program
;
2968 this->prog_data
= &c
->prog_data
;
2970 this->variable_ht
= hash_table_ctor(0,
2971 hash_table_pointer_hash
,
2972 hash_table_pointer_compare
);
2974 this->virtual_grf_def
= NULL
;
2975 this->virtual_grf_use
= NULL
;
2976 this->virtual_grf_sizes
= NULL
;
2977 this->virtual_grf_count
= 0;
2978 this->virtual_grf_reg_map
= NULL
;
2979 this->virtual_grf_reg_count
= 0;
2980 this->virtual_grf_array_size
= 0;
2981 this->live_intervals_valid
= false;
2983 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2988 vec4_visitor::~vec4_visitor()
2990 hash_table_dtor(this->variable_ht
);
2995 vec4_visitor::fail(const char *format
, ...)
3005 va_start(va
, format
);
3006 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3008 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
3010 this->fail_msg
= msg
;
3012 if (INTEL_DEBUG
& DEBUG_VS
) {
3013 fprintf(stderr
, "%s", msg
);
3017 } /* namespace brw */