2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
32 src_reg::src_reg(dst_reg reg
)
36 this->file
= reg
.file
;
38 this->reg_offset
= reg
.reg_offset
;
39 this->type
= reg
.type
;
40 this->reladdr
= reg
.reladdr
;
41 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
47 for (int i
= 0; i
< 4; i
++) {
48 if (!(reg
.writemask
& (1 << i
)))
51 swizzles
[next_chan
++] = last
= i
;
54 for (; next_chan
< 4; next_chan
++) {
55 swizzles
[next_chan
] = last
;
58 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
59 swizzles
[2], swizzles
[3]);
62 dst_reg::dst_reg(src_reg reg
)
66 this->file
= reg
.file
;
68 this->reg_offset
= reg
.reg_offset
;
69 this->type
= reg
.type
;
70 this->writemask
= WRITEMASK_XYZW
;
71 this->reladdr
= reg
.reladdr
;
72 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
75 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
76 enum opcode opcode
, dst_reg dst
,
77 src_reg src0
, src_reg src1
, src_reg src2
)
79 this->opcode
= opcode
;
84 this->ir
= v
->base_ir
;
85 this->annotation
= v
->current_annotation
;
89 vec4_visitor::emit(vec4_instruction
*inst
)
91 this->instructions
.push_tail(inst
);
97 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
98 src_reg src0
, src_reg src1
, src_reg src2
)
100 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
106 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
108 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
112 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
114 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
118 vec4_visitor::emit(enum opcode opcode
)
120 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
124 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
126 static enum opcode dot_opcodes
[] = {
127 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
130 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
134 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
136 /* The gen6 math instruction ignores the source modifiers --
137 * swizzle, abs, negate, and at least some parts of the register
138 * region description.
140 src_reg temp_src
= src_reg(this, glsl_type::vec4_type
);
141 emit(BRW_OPCODE_MOV
, dst_reg(temp_src
), src
);
143 if (dst
.writemask
!= WRITEMASK_XYZW
) {
144 /* The gen6 math instruction must be align1, so we can't do
147 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
149 emit(opcode
, temp_dst
, temp_src
);
151 emit(BRW_OPCODE_MOV
, dst
, src_reg(temp_dst
));
153 emit(opcode
, dst
, temp_src
);
158 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
160 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
166 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
169 case SHADER_OPCODE_RCP
:
170 case SHADER_OPCODE_RSQ
:
171 case SHADER_OPCODE_SQRT
:
172 case SHADER_OPCODE_EXP2
:
173 case SHADER_OPCODE_LOG2
:
174 case SHADER_OPCODE_SIN
:
175 case SHADER_OPCODE_COS
:
178 assert(!"not reached: bad math opcode");
182 if (intel
->gen
>= 6) {
183 return emit_math1_gen6(opcode
, dst
, src
);
185 return emit_math1_gen4(opcode
, dst
, src
);
190 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
191 dst_reg dst
, src_reg src0
, src_reg src1
)
195 /* The gen6 math instruction ignores the source modifiers --
196 * swizzle, abs, negate, and at least some parts of the register
197 * region description. Move the sources to temporaries to make it
201 expanded
= src_reg(this, glsl_type::vec4_type
);
202 emit(BRW_OPCODE_MOV
, dst_reg(expanded
), src0
);
205 expanded
= src_reg(this, glsl_type::vec4_type
);
206 emit(BRW_OPCODE_MOV
, dst_reg(expanded
), src1
);
209 if (dst
.writemask
!= WRITEMASK_XYZW
) {
210 /* The gen6 math instruction must be align1, so we can't do
213 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
215 emit(opcode
, temp_dst
, src0
, src1
);
217 emit(BRW_OPCODE_MOV
, dst
, src_reg(temp_dst
));
219 emit(opcode
, dst
, src0
, src1
);
224 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
225 dst_reg dst
, src_reg src0
, src_reg src1
)
227 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
233 vec4_visitor::emit_math(enum opcode opcode
,
234 dst_reg dst
, src_reg src0
, src_reg src1
)
236 assert(opcode
== SHADER_OPCODE_POW
);
238 if (intel
->gen
>= 6) {
239 return emit_math2_gen6(opcode
, dst
, src0
, src1
);
241 return emit_math2_gen4(opcode
, dst
, src0
, src1
);
246 vec4_visitor::visit_instructions(const exec_list
*list
)
248 foreach_list(node
, list
) {
249 ir_instruction
*ir
= (ir_instruction
*)node
;
258 type_size(const struct glsl_type
*type
)
263 switch (type
->base_type
) {
266 case GLSL_TYPE_FLOAT
:
268 if (type
->is_matrix()) {
269 return type
->matrix_columns
;
271 /* Regardless of size of vector, it gets a vec4. This is bad
272 * packing for things like floats, but otherwise arrays become a
273 * mess. Hopefully a later pass over the code can pack scalars
274 * down if appropriate.
278 case GLSL_TYPE_ARRAY
:
279 assert(type
->length
> 0);
280 return type_size(type
->fields
.array
) * type
->length
;
281 case GLSL_TYPE_STRUCT
:
283 for (i
= 0; i
< type
->length
; i
++) {
284 size
+= type_size(type
->fields
.structure
[i
].type
);
287 case GLSL_TYPE_SAMPLER
:
288 /* Samplers take up one slot in UNIFORMS[], but they're baked in
299 vec4_visitor::virtual_grf_alloc(int size
)
301 if (virtual_grf_array_size
<= virtual_grf_count
) {
302 if (virtual_grf_array_size
== 0)
303 virtual_grf_array_size
= 16;
305 virtual_grf_array_size
*= 2;
306 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
307 virtual_grf_array_size
);
309 virtual_grf_sizes
[virtual_grf_count
] = size
;
310 return virtual_grf_count
++;
313 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
318 this->reg
= v
->virtual_grf_alloc(type_size(type
));
320 if (type
->is_array() || type
->is_record()) {
321 this->swizzle
= BRW_SWIZZLE_NOOP
;
323 this->swizzle
= swizzle_for_size(type
->vector_elements
);
326 this->type
= brw_type_for_base_type(type
);
329 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
334 this->reg
= v
->virtual_grf_alloc(type_size(type
));
336 if (type
->is_array() || type
->is_record()) {
337 this->writemask
= WRITEMASK_XYZW
;
339 this->writemask
= (1 << type
->vector_elements
) - 1;
342 this->type
= brw_type_for_base_type(type
);
345 /* Our support for uniforms is piggy-backed on the struct
346 * gl_fragment_program, because that's where the values actually
347 * get stored, rather than in some global gl_shader_program uniform
351 vec4_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
353 unsigned int offset
= 0;
354 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[loc
][0].f
;
356 if (type
->is_matrix()) {
357 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
358 type
->vector_elements
,
361 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
362 offset
+= setup_uniform_values(loc
+ offset
, column
);
368 switch (type
->base_type
) {
369 case GLSL_TYPE_FLOAT
:
373 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
374 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &values
[i
];
377 /* Set up pad elements to get things aligned to a vec4 boundary. */
378 for (unsigned int i
= type
->vector_elements
; i
< 4; i
++) {
379 static float zero
= 0;
381 c
->prog_data
.param
[this->uniforms
* 4 + i
] = &zero
;
384 /* Track the size of this uniform vector, for future packing of
387 this->uniform_vector_size
[this->uniforms
] = type
->vector_elements
;
392 case GLSL_TYPE_STRUCT
:
393 for (unsigned int i
= 0; i
< type
->length
; i
++) {
394 offset
+= setup_uniform_values(loc
+ offset
,
395 type
->fields
.structure
[i
].type
);
399 case GLSL_TYPE_ARRAY
:
400 for (unsigned int i
= 0; i
< type
->length
; i
++) {
401 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
405 case GLSL_TYPE_SAMPLER
:
406 /* The sampler takes up a slot, but we don't use any values from it. */
410 assert(!"not reached");
415 /* Our support for builtin uniforms is even scarier than non-builtin.
416 * It sits on top of the PROG_STATE_VAR parameters that are
417 * automatically updated from GL context state.
420 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
422 const ir_state_slot
*const slots
= ir
->state_slots
;
423 assert(ir
->state_slots
!= NULL
);
425 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
426 /* This state reference has already been setup by ir_to_mesa,
427 * but we'll get the same index back here. We can reference
428 * ParameterValues directly, since unlike brw_fs.cpp, we never
429 * add new state references during compile.
431 int index
= _mesa_add_state_reference(this->vp
->Base
.Parameters
,
432 (gl_state_index
*)slots
[i
].tokens
);
433 float *values
= &this->vp
->Base
.Parameters
->ParameterValues
[index
][0].f
;
435 this->uniform_vector_size
[this->uniforms
] = 0;
436 /* Add each of the unique swizzled channels of the element.
437 * This will end up matching the size of the glsl_type of this field.
440 for (unsigned int j
= 0; j
< 4; j
++) {
441 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
444 c
->prog_data
.param
[this->uniforms
* 4 + j
] = &values
[swiz
];
445 if (swiz
<= last_swiz
)
446 this->uniform_vector_size
[this->uniforms
]++;
453 vec4_visitor::variable_storage(ir_variable
*var
)
455 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
459 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
461 ir_expression
*expr
= ir
->as_expression();
465 vec4_instruction
*inst
;
467 assert(expr
->get_num_operands() <= 2);
468 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
469 assert(expr
->operands
[i
]->type
->is_scalar());
471 expr
->operands
[i
]->accept(this);
472 op
[i
] = this->result
;
475 switch (expr
->operation
) {
476 case ir_unop_logic_not
:
477 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], src_reg(1));
478 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
481 case ir_binop_logic_xor
:
482 inst
= emit(BRW_OPCODE_XOR
, dst_null_d(), op
[0], op
[1]);
483 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
486 case ir_binop_logic_or
:
487 inst
= emit(BRW_OPCODE_OR
, dst_null_d(), op
[0], op
[1]);
488 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
491 case ir_binop_logic_and
:
492 inst
= emit(BRW_OPCODE_AND
, dst_null_d(), op
[0], op
[1]);
493 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
497 if (intel
->gen
>= 6) {
498 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0.0f
));
500 inst
= emit(BRW_OPCODE_MOV
, dst_null_f(), op
[0]);
502 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
506 if (intel
->gen
>= 6) {
507 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
509 inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), op
[0]);
511 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
514 case ir_binop_greater
:
515 case ir_binop_gequal
:
517 case ir_binop_lequal
:
519 case ir_binop_all_equal
:
520 case ir_binop_nequal
:
521 case ir_binop_any_nequal
:
522 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
523 inst
->conditional_mod
=
524 brw_conditional_for_comparison(expr
->operation
);
528 assert(!"not reached");
536 if (intel
->gen
>= 6) {
537 vec4_instruction
*inst
= emit(BRW_OPCODE_AND
, dst_null_d(),
538 this->result
, src_reg(1));
539 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
541 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst_null_d(), this->result
);
542 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
547 * Emit a gen6 IF statement with the comparison folded into the IF
551 vec4_visitor::emit_if_gen6(ir_if
*ir
)
553 ir_expression
*expr
= ir
->condition
->as_expression();
557 vec4_instruction
*inst
;
560 assert(expr
->get_num_operands() <= 2);
561 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
562 expr
->operands
[i
]->accept(this);
563 op
[i
] = this->result
;
566 switch (expr
->operation
) {
567 case ir_unop_logic_not
:
568 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
569 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
572 case ir_binop_logic_xor
:
573 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
574 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
577 case ir_binop_logic_or
:
578 temp
= dst_reg(this, glsl_type::bool_type
);
579 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
580 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
581 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
584 case ir_binop_logic_and
:
585 temp
= dst_reg(this, glsl_type::bool_type
);
586 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
587 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), src_reg(temp
), src_reg(0));
588 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
592 inst
= emit(BRW_OPCODE_IF
, dst_null_f(), op
[0], src_reg(0));
593 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
597 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
598 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
601 case ir_binop_greater
:
602 case ir_binop_gequal
:
604 case ir_binop_lequal
:
606 case ir_binop_nequal
:
607 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], op
[1]);
608 inst
->conditional_mod
=
609 brw_conditional_for_comparison(expr
->operation
);
612 case ir_binop_all_equal
:
613 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
614 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
616 inst
= emit(BRW_OPCODE_IF
);
617 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
620 case ir_binop_any_nequal
:
621 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], op
[1]);
622 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
624 inst
= emit(BRW_OPCODE_IF
);
625 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
629 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
630 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
632 inst
= emit(BRW_OPCODE_IF
);
633 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
637 assert(!"not reached");
638 inst
= emit(BRW_OPCODE_IF
, dst_null_d(), op
[0], src_reg(0));
639 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
645 ir
->condition
->accept(this);
647 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
, dst_null_d(),
648 this->result
, src_reg(0));
649 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
653 vec4_visitor::visit(ir_variable
*ir
)
657 if (variable_storage(ir
))
662 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->location
);
666 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
668 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
669 output_reg
[ir
->location
+ i
] = *reg
;
670 output_reg
[ir
->location
+ i
].reg_offset
= i
;
671 output_reg
[ir
->location
+ i
].type
= BRW_REGISTER_TYPE_F
;
676 case ir_var_temporary
:
677 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
681 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
683 /* Track how big the whole uniform variable is, in case we need to put a
684 * copy of its data into pull constants for array access.
686 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
688 if (!strncmp(ir
->name
, "gl_", 3)) {
689 setup_builtin_uniform_values(ir
);
691 setup_uniform_values(ir
->location
, ir
->type
);
696 assert(!"not reached");
699 reg
->type
= brw_type_for_base_type(ir
->type
);
700 hash_table_insert(this->variable_ht
, reg
, ir
);
704 vec4_visitor::visit(ir_loop
*ir
)
708 /* We don't want debugging output to print the whole body of the
709 * loop as the annotation.
711 this->base_ir
= NULL
;
713 if (ir
->counter
!= NULL
) {
714 this->base_ir
= ir
->counter
;
715 ir
->counter
->accept(this);
716 counter
= *(variable_storage(ir
->counter
));
718 if (ir
->from
!= NULL
) {
719 this->base_ir
= ir
->from
;
720 ir
->from
->accept(this);
722 emit(BRW_OPCODE_MOV
, counter
, this->result
);
729 this->base_ir
= ir
->to
;
730 ir
->to
->accept(this);
732 vec4_instruction
*inst
= emit(BRW_OPCODE_CMP
, dst_null_d(),
733 src_reg(counter
), this->result
);
734 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
736 inst
= emit(BRW_OPCODE_BREAK
);
737 inst
->predicate
= BRW_PREDICATE_NORMAL
;
740 visit_instructions(&ir
->body_instructions
);
744 this->base_ir
= ir
->increment
;
745 ir
->increment
->accept(this);
746 emit(BRW_OPCODE_ADD
, counter
, src_reg(counter
), this->result
);
749 emit(BRW_OPCODE_WHILE
);
753 vec4_visitor::visit(ir_loop_jump
*ir
)
756 case ir_loop_jump::jump_break
:
757 emit(BRW_OPCODE_BREAK
);
759 case ir_loop_jump::jump_continue
:
760 emit(BRW_OPCODE_CONTINUE
);
767 vec4_visitor::visit(ir_function_signature
*ir
)
774 vec4_visitor::visit(ir_function
*ir
)
776 /* Ignore function bodies other than main() -- we shouldn't see calls to
777 * them since they should all be inlined.
779 if (strcmp(ir
->name
, "main") == 0) {
780 const ir_function_signature
*sig
;
783 sig
= ir
->matching_signature(&empty
);
787 visit_instructions(&sig
->body
);
792 vec4_visitor::try_emit_sat(ir_expression
*ir
)
794 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
798 sat_src
->accept(this);
799 src_reg src
= this->result
;
801 this->result
= src_reg(this, ir
->type
);
802 vec4_instruction
*inst
;
803 inst
= emit(BRW_OPCODE_MOV
, dst_reg(this->result
), src
);
804 inst
->saturate
= true;
810 vec4_visitor::emit_bool_comparison(unsigned int op
,
811 dst_reg dst
, src_reg src0
, src_reg src1
)
813 /* original gen4 does destination conversion before comparison. */
815 dst
.type
= src0
.type
;
817 vec4_instruction
*inst
= emit(BRW_OPCODE_CMP
, dst
, src0
, src1
);
818 inst
->conditional_mod
= brw_conditional_for_comparison(op
);
820 dst
.type
= BRW_REGISTER_TYPE_D
;
821 emit(BRW_OPCODE_AND
, dst
, src_reg(dst
), src_reg(0x1));
825 vec4_visitor::visit(ir_expression
*ir
)
827 unsigned int operand
;
828 src_reg op
[Elements(ir
->operands
)];
831 vec4_instruction
*inst
;
833 if (try_emit_sat(ir
))
836 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
837 this->result
.file
= BAD_FILE
;
838 ir
->operands
[operand
]->accept(this);
839 if (this->result
.file
== BAD_FILE
) {
840 printf("Failed to get tree for expression operand:\n");
841 ir
->operands
[operand
]->print();
844 op
[operand
] = this->result
;
846 /* Matrix expression operands should have been broken down to vector
847 * operations already.
849 assert(!ir
->operands
[operand
]->type
->is_matrix());
852 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
853 if (ir
->operands
[1]) {
854 vector_elements
= MAX2(vector_elements
,
855 ir
->operands
[1]->type
->vector_elements
);
858 this->result
.file
= BAD_FILE
;
860 /* Storage for our result. Ideally for an assignment we'd be using
861 * the actual storage for the result here, instead.
863 result_src
= src_reg(this, ir
->type
);
864 /* convenience for the emit functions below. */
865 result_dst
= dst_reg(result_src
);
866 /* If nothing special happens, this is the result. */
867 this->result
= result_src
;
868 /* Limit writes to the channels that will be used by result_src later.
869 * This does limit this temp's use as a temporary for multi-instruction
872 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
874 switch (ir
->operation
) {
875 case ir_unop_logic_not
:
876 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
877 * ones complement of the whole register, not just bit 0.
879 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], src_reg(1));
882 op
[0].negate
= !op
[0].negate
;
883 this->result
= op
[0];
887 op
[0].negate
= false;
888 this->result
= op
[0];
892 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0.0f
));
894 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
895 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
896 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1.0f
));
897 inst
->predicate
= BRW_PREDICATE_NORMAL
;
899 inst
= emit(BRW_OPCODE_CMP
, dst_null_f(), op
[0], src_reg(0.0f
));
900 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
901 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(-1.0f
));
902 inst
->predicate
= BRW_PREDICATE_NORMAL
;
907 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
911 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
914 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
918 assert(!"not reached: should be handled by ir_explog_to_explog2");
921 case ir_unop_sin_reduced
:
922 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
925 case ir_unop_cos_reduced
:
926 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
931 assert(!"derivatives not valid in vertex shader");
935 assert(!"not reached: should be handled by lower_noise");
939 emit(BRW_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
942 assert(!"not reached: should be handled by ir_sub_to_add_neg");
946 if (ir
->type
->is_integer()) {
947 /* For integer multiplication, the MUL uses the low 16 bits
948 * of one of the operands (src0 on gen6, src1 on gen7). The
949 * MACH accumulates in the contribution of the upper 16 bits
952 * FINISHME: Emit just the MUL if we know an operand is small
955 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
957 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
958 emit(BRW_OPCODE_MACH
, dst_null_d(), op
[0], op
[1]);
959 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(acc
));
961 emit(BRW_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
965 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
967 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
971 case ir_binop_greater
:
972 case ir_binop_lequal
:
973 case ir_binop_gequal
:
975 case ir_binop_nequal
: {
976 dst_reg temp
= result_dst
;
977 /* original gen4 does implicit conversion before comparison. */
979 temp
.type
= op
[0].type
;
981 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
982 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
983 emit(BRW_OPCODE_AND
, result_dst
, this->result
, src_reg(0x1));
987 case ir_binop_all_equal
:
988 /* "==" operator producing a scalar boolean. */
989 if (ir
->operands
[0]->type
->is_vector() ||
990 ir
->operands
[1]->type
->is_vector()) {
991 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
992 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
994 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
995 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
996 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
998 dst_reg temp
= result_dst
;
999 /* original gen4 does implicit conversion before comparison. */
1001 temp
.type
= op
[0].type
;
1003 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
1004 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1005 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
1008 case ir_binop_any_nequal
:
1009 /* "!=" operator producing a scalar boolean. */
1010 if (ir
->operands
[0]->type
->is_vector() ||
1011 ir
->operands
[1]->type
->is_vector()) {
1012 inst
= emit(BRW_OPCODE_CMP
, dst_null_cmp(), op
[0], op
[1]);
1013 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1015 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1016 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1017 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1019 dst_reg temp
= result_dst
;
1020 /* original gen4 does implicit conversion before comparison. */
1022 temp
.type
= op
[0].type
;
1024 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
1025 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1026 emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(0x1));
1031 inst
= emit(BRW_OPCODE_CMP
, dst_null_d(), op
[0], src_reg(0));
1032 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1034 emit(BRW_OPCODE_MOV
, result_dst
, src_reg(0));
1036 inst
= emit(BRW_OPCODE_MOV
, result_dst
, src_reg(1));
1037 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1040 case ir_binop_logic_xor
:
1041 emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1044 case ir_binop_logic_or
:
1045 emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1048 case ir_binop_logic_and
:
1049 emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1053 assert(ir
->operands
[0]->type
->is_vector());
1054 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1055 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1059 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1062 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1071 emit(BRW_OPCODE_MOV
, result_dst
, op
[0]);
1075 dst_reg temp
= result_dst
;
1076 /* original gen4 does implicit conversion before comparison. */
1078 temp
.type
= op
[0].type
;
1080 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], src_reg(0.0f
));
1081 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1082 inst
= emit(BRW_OPCODE_AND
, result_dst
, result_src
, src_reg(1));
1087 emit(BRW_OPCODE_RNDZ
, result_dst
, op
[0]);
1090 op
[0].negate
= !op
[0].negate
;
1091 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1092 this->result
.negate
= true;
1095 inst
= emit(BRW_OPCODE_RNDD
, result_dst
, op
[0]);
1098 inst
= emit(BRW_OPCODE_FRC
, result_dst
, op
[0]);
1100 case ir_unop_round_even
:
1101 emit(BRW_OPCODE_RNDE
, result_dst
, op
[0]);
1105 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1106 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1108 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1109 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1112 inst
= emit(BRW_OPCODE_CMP
, result_dst
, op
[0], op
[1]);
1113 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1115 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[0], op
[1]);
1116 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1120 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1123 case ir_unop_bit_not
:
1124 inst
= emit(BRW_OPCODE_NOT
, result_dst
, op
[0]);
1126 case ir_binop_bit_and
:
1127 inst
= emit(BRW_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1129 case ir_binop_bit_xor
:
1130 inst
= emit(BRW_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1132 case ir_binop_bit_or
:
1133 inst
= emit(BRW_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1136 case ir_binop_lshift
:
1137 case ir_binop_rshift
:
1138 assert(!"GLSL 1.30 features unsupported");
1141 case ir_quadop_vector
:
1142 assert(!"not reached: should be handled by lower_quadop_vector");
1149 vec4_visitor::visit(ir_swizzle
*ir
)
1155 /* Note that this is only swizzles in expressions, not those on the left
1156 * hand side of an assignment, which do write masking. See ir_assignment
1160 ir
->val
->accept(this);
1162 assert(src
.file
!= BAD_FILE
);
1164 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1167 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1170 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1173 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1176 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1180 for (; i
< 4; i
++) {
1181 /* Replicate the last channel out. */
1182 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1185 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1191 vec4_visitor::visit(ir_dereference_variable
*ir
)
1193 const struct glsl_type
*type
= ir
->type
;
1194 dst_reg
*reg
= variable_storage(ir
->var
);
1197 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1198 this->result
= src_reg(brw_null_reg());
1202 this->result
= src_reg(*reg
);
1204 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1205 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1209 vec4_visitor::visit(ir_dereference_array
*ir
)
1211 ir_constant
*constant_index
;
1213 int element_size
= type_size(ir
->type
);
1215 constant_index
= ir
->array_index
->constant_expression_value();
1217 ir
->array
->accept(this);
1220 if (constant_index
) {
1221 src
.reg_offset
+= constant_index
->value
.i
[0] * element_size
;
1223 /* Variable index array dereference. It eats the "vec4" of the
1224 * base of the array and an index that offsets the Mesa register
1227 ir
->array_index
->accept(this);
1231 if (element_size
== 1) {
1232 index_reg
= this->result
;
1234 index_reg
= src_reg(this, glsl_type::int_type
);
1236 emit(BRW_OPCODE_MUL
, dst_reg(index_reg
),
1237 this->result
, src_reg(element_size
));
1241 src_reg temp
= src_reg(this, glsl_type::int_type
);
1243 emit(BRW_OPCODE_ADD
, dst_reg(temp
), *src
.reladdr
, index_reg
);
1248 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1249 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1252 /* If the type is smaller than a vec4, replicate the last channel out. */
1253 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1254 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1256 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1257 src
.type
= brw_type_for_base_type(ir
->type
);
1263 vec4_visitor::visit(ir_dereference_record
*ir
)
1266 const glsl_type
*struct_type
= ir
->record
->type
;
1269 ir
->record
->accept(this);
1271 for (i
= 0; i
< struct_type
->length
; i
++) {
1272 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1274 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1277 /* If the type is smaller than a vec4, replicate the last channel out. */
1278 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
1279 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1281 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1282 this->result
.type
= brw_type_for_base_type(ir
->type
);
1284 this->result
.reg_offset
+= offset
;
1288 * We want to be careful in assignment setup to hit the actual storage
1289 * instead of potentially using a temporary like we might with the
1290 * ir_dereference handler.
1293 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1295 /* The LHS must be a dereference. If the LHS is a variable indexed array
1296 * access of a vector, it must be separated into a series conditional moves
1297 * before reaching this point (see ir_vec_index_to_cond_assign).
1299 assert(ir
->as_dereference());
1300 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1302 assert(!deref_array
->array
->type
->is_vector());
1305 /* Use the rvalue deref handler for the most part. We'll ignore
1306 * swizzles in it and write swizzles using writemask, though.
1309 return dst_reg(v
->result
);
1313 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1314 const struct glsl_type
*type
, bool predicated
)
1316 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1317 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1318 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicated
);
1323 if (type
->is_array()) {
1324 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1325 emit_block_move(dst
, src
, type
->fields
.array
, predicated
);
1330 if (type
->is_matrix()) {
1331 const struct glsl_type
*vec_type
;
1333 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1334 type
->vector_elements
, 1);
1336 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1337 emit_block_move(dst
, src
, vec_type
, predicated
);
1342 assert(type
->is_scalar() || type
->is_vector());
1344 dst
->type
= brw_type_for_base_type(type
);
1345 src
->type
= dst
->type
;
1347 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1349 /* Do we need to worry about swizzling a swizzle? */
1350 assert(src
->swizzle
= BRW_SWIZZLE_NOOP
);
1351 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1353 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, *dst
, *src
);
1355 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1362 /* If the RHS processing resulted in an instruction generating a
1363 * temporary value, and it would be easy to rewrite the instruction to
1364 * generate its result right into the LHS instead, do so. This ends
1365 * up reliably removing instructions where it can be tricky to do so
1366 * later without real UD chain information.
1369 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1372 vec4_instruction
*pre_rhs_inst
,
1373 vec4_instruction
*last_rhs_inst
)
1375 /* This could be supported, but it would take more smarts. */
1379 if (pre_rhs_inst
== last_rhs_inst
)
1380 return false; /* No instructions generated to work with. */
1382 /* Make sure the last instruction generated our source reg. */
1383 if (src
.file
!= GRF
||
1384 src
.file
!= last_rhs_inst
->dst
.file
||
1385 src
.reg
!= last_rhs_inst
->dst
.reg
||
1386 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
1390 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
1393 /* Check that that last instruction fully initialized the channels
1394 * we want to use, in the order we want to use them. We could
1395 * potentially reswizzle the operands of many instructions so that
1396 * we could handle out of order channels, but don't yet.
1398 for (int i
= 0; i
< 4; i
++) {
1399 if (dst
.writemask
& (1 << i
)) {
1400 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
1403 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
1408 /* Success! Rewrite the instruction. */
1409 last_rhs_inst
->dst
.file
= dst
.file
;
1410 last_rhs_inst
->dst
.reg
= dst
.reg
;
1411 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
1412 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
1413 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
1419 vec4_visitor::visit(ir_assignment
*ir
)
1421 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
1423 if (!ir
->lhs
->type
->is_scalar() &&
1424 !ir
->lhs
->type
->is_vector()) {
1425 ir
->rhs
->accept(this);
1426 src_reg src
= this->result
;
1428 if (ir
->condition
) {
1429 emit_bool_to_cond_code(ir
->condition
);
1432 emit_block_move(&dst
, &src
, ir
->rhs
->type
, ir
->condition
!= NULL
);
1436 /* Now we're down to just a scalar/vector with writemasks. */
1439 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
1440 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1442 ir
->rhs
->accept(this);
1444 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
1446 src_reg src
= this->result
;
1449 int first_enabled_chan
= 0;
1452 assert(ir
->lhs
->type
->is_vector() ||
1453 ir
->lhs
->type
->is_scalar());
1454 dst
.writemask
= ir
->write_mask
;
1456 for (int i
= 0; i
< 4; i
++) {
1457 if (dst
.writemask
& (1 << i
)) {
1458 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
1463 /* Swizzle a small RHS vector into the channels being written.
1465 * glsl ir treats write_mask as dictating how many channels are
1466 * present on the RHS while in our instructions we need to make
1467 * those channels appear in the slots of the vec4 they're written to.
1469 for (int i
= 0; i
< 4; i
++) {
1470 if (dst
.writemask
& (1 << i
))
1471 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
1473 swizzles
[i
] = first_enabled_chan
;
1475 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
1476 swizzles
[2], swizzles
[3]);
1478 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
1482 if (ir
->condition
) {
1483 emit_bool_to_cond_code(ir
->condition
);
1486 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
1487 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, dst
, src
);
1490 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1498 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
1500 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
1501 foreach_list(node
, &ir
->components
) {
1502 ir_constant
*field_value
= (ir_constant
*)node
;
1504 emit_constant_values(dst
, field_value
);
1509 if (ir
->type
->is_array()) {
1510 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
1511 emit_constant_values(dst
, ir
->array_elements
[i
]);
1516 if (ir
->type
->is_matrix()) {
1517 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
1518 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
1519 dst
->writemask
= 1 << j
;
1520 dst
->type
= BRW_REGISTER_TYPE_F
;
1522 emit(BRW_OPCODE_MOV
, *dst
,
1523 src_reg(ir
->value
.f
[i
* ir
->type
->vector_elements
+ j
]));
1530 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1531 dst
->writemask
= 1 << i
;
1532 dst
->type
= brw_type_for_base_type(ir
->type
);
1534 switch (ir
->type
->base_type
) {
1535 case GLSL_TYPE_FLOAT
:
1536 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.f
[i
]));
1539 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.i
[i
]));
1541 case GLSL_TYPE_UINT
:
1542 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.u
[i
]));
1544 case GLSL_TYPE_BOOL
:
1545 emit(BRW_OPCODE_MOV
, *dst
, src_reg(ir
->value
.b
[i
]));
1548 assert(!"Non-float/uint/int/bool constant");
1556 vec4_visitor::visit(ir_constant
*ir
)
1558 dst_reg dst
= dst_reg(this, ir
->type
);
1559 this->result
= src_reg(dst
);
1561 emit_constant_values(&dst
, ir
);
1565 vec4_visitor::visit(ir_call
*ir
)
1567 assert(!"not reached");
1571 vec4_visitor::visit(ir_texture
*ir
)
1573 /* FINISHME: Implement vertex texturing.
1575 * With 0 vertex samplers available, the linker will reject
1576 * programs that do vertex texturing, but after our visitor has
1582 vec4_visitor::visit(ir_return
*ir
)
1584 assert(!"not reached");
1588 vec4_visitor::visit(ir_discard
*ir
)
1590 assert(!"not reached");
1594 vec4_visitor::visit(ir_if
*ir
)
1596 /* Don't point the annotation at the if statement, because then it plus
1597 * the then and else blocks get printed.
1599 this->base_ir
= ir
->condition
;
1601 if (intel
->gen
== 6) {
1604 emit_bool_to_cond_code(ir
->condition
);
1605 vec4_instruction
*inst
= emit(BRW_OPCODE_IF
);
1606 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1609 visit_instructions(&ir
->then_instructions
);
1611 if (!ir
->else_instructions
.is_empty()) {
1612 this->base_ir
= ir
->condition
;
1613 emit(BRW_OPCODE_ELSE
);
1615 visit_instructions(&ir
->else_instructions
);
1618 this->base_ir
= ir
->condition
;
1619 emit(BRW_OPCODE_ENDIF
);
1623 vec4_visitor::emit_vue_header_gen4(int header_mrf
)
1625 /* Get the position */
1626 src_reg pos
= src_reg(output_reg
[VERT_RESULT_HPOS
]);
1628 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1629 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1631 current_annotation
= "NDC";
1632 dst_reg ndc_w
= ndc
;
1633 ndc_w
.writemask
= WRITEMASK_W
;
1634 src_reg pos_w
= pos
;
1635 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1636 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1638 dst_reg ndc_xyz
= ndc
;
1639 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1641 emit(BRW_OPCODE_MUL
, ndc_xyz
, pos
, src_reg(ndc_w
));
1643 if ((c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) ||
1644 c
->key
.nr_userclip
|| brw
->has_negative_rhw_bug
) {
1645 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1648 emit(BRW_OPCODE_MOV
, header1
, 0u);
1650 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1651 assert(!"finishme: psiz");
1654 header1
.writemask
= WRITEMASK_W
;
1655 emit(BRW_OPCODE_MUL
, header1
, psiz
, 1u << 11);
1656 emit(BRW_OPCODE_AND
, header1
, src_reg(header1
), 0x7ff << 8);
1659 for (i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1660 vec4_instruction
*inst
;
1662 inst
= emit(BRW_OPCODE_DP4
, dst_reg(brw_null_reg()),
1663 pos
, src_reg(c
->userplane
[i
]));
1664 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1666 emit(BRW_OPCODE_OR
, header1
, src_reg(header1
), 1u << i
);
1667 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1670 /* i965 clipping workaround:
1671 * 1) Test for -ve rhw
1673 * set ndc = (0,0,0,0)
1676 * Later, clipping will detect ucp[6] and ensure the primitive is
1677 * clipped against all fixed planes.
1679 if (brw
->has_negative_rhw_bug
) {
1683 vec8(brw_null_reg()),
1685 brw_swizzle1(ndc
, 3),
1688 brw_OR(p
, brw_writemask(header1
, WRITEMASK_W
), header1
, brw_imm_ud(1<<6));
1689 brw_MOV(p
, ndc
, brw_imm_f(0));
1690 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1694 header1
.writemask
= WRITEMASK_XYZW
;
1695 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(header1
));
1697 emit(BRW_OPCODE_MOV
, retype(brw_message_reg(header_mrf
++),
1698 BRW_REGISTER_TYPE_UD
), 0u);
1701 if (intel
->gen
== 5) {
1702 /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
1703 * dword 0-3 (m1) of the header is indices, point width, clip flags.
1704 * dword 4-7 (m2) is the ndc position (set above)
1705 * dword 8-11 (m3) of the vertex header is the 4D space position
1706 * dword 12-19 (m4,m5) of the vertex header is the user clip distance.
1707 * m6 is a pad so that the vertex element data is aligned
1708 * m7 is the first vertex data we fill.
1710 current_annotation
= "NDC";
1711 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1713 current_annotation
= "gl_Position";
1714 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1716 /* user clip distance. */
1719 /* Pad so that vertex element data is aligned. */
1722 /* There are 8 dwords in VUE header pre-Ironlake:
1723 * dword 0-3 (m1) is indices, point width, clip flags.
1724 * dword 4-7 (m2) is ndc position (set above)
1726 * dword 8-11 (m3) is the first vertex data.
1728 current_annotation
= "NDC";
1729 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), src_reg(ndc
));
1731 current_annotation
= "gl_Position";
1732 emit(BRW_OPCODE_MOV
, brw_message_reg(header_mrf
++), pos
);
1739 vec4_visitor::emit_vue_header_gen6(int header_mrf
)
1743 /* There are 8 or 16 DWs (D0-D15) in VUE header on Sandybridge:
1744 * dword 0-3 (m2) of the header is indices, point width, clip flags.
1745 * dword 4-7 (m3) is the 4D space position
1746 * dword 8-15 (m4,m5) of the vertex header is the user clip distance if
1749 * m4 or 6 is the first vertex element data we fill.
1752 current_annotation
= "indices, point width, clip flags";
1753 reg
= brw_message_reg(header_mrf
++);
1754 emit(BRW_OPCODE_MOV
, retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0));
1755 if (c
->prog_data
.outputs_written
& BITFIELD64_BIT(VERT_RESULT_PSIZ
)) {
1756 emit(BRW_OPCODE_MOV
, brw_writemask(reg
, WRITEMASK_W
),
1757 src_reg(output_reg
[VERT_RESULT_PSIZ
]));
1760 current_annotation
= "gl_Position";
1761 emit(BRW_OPCODE_MOV
,
1762 brw_message_reg(header_mrf
++), src_reg(output_reg
[VERT_RESULT_HPOS
]));
1764 current_annotation
= "user clip distances";
1765 if (c
->key
.nr_userclip
) {
1766 for (int i
= 0; i
< c
->key
.nr_userclip
; i
++) {
1769 m
= brw_message_reg(header_mrf
);
1771 m
= brw_message_reg(header_mrf
+ 1);
1773 emit(BRW_OPCODE_DP4
,
1774 dst_reg(brw_writemask(m
, 1 << (i
& 3))),
1775 src_reg(c
->userplane
[i
]));
1780 current_annotation
= NULL
;
1786 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
1788 struct intel_context
*intel
= &brw
->intel
;
1790 if (intel
->gen
>= 6) {
1791 /* URB data written (does not include the message header reg) must
1792 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1793 * section 5.4.3.2.2: URB_INTERLEAVED.
1795 * URB entries are allocated on a multiple of 1024 bits, so an
1796 * extra 128 bits written here to make the end align to 256 is
1799 if ((mlen
% 2) != 1)
1807 * Generates the VUE payload plus the 1 or 2 URB write instructions to
1808 * complete the VS thread.
1810 * The VUE layout is documented in Volume 2a.
1813 vec4_visitor::emit_urb_writes()
1815 /* MRF 0 is reserved for the debugger, so start with message header
1821 uint64_t outputs_remaining
= c
->prog_data
.outputs_written
;
1822 /* In the process of generating our URB write message contents, we
1823 * may need to unspill a register or load from an array. Those
1824 * reads would use MRFs 14-15.
1826 int max_usable_mrf
= 13;
1828 /* FINISHME: edgeflag */
1830 /* First mrf is the g0-based message header containing URB handles and such,
1831 * which is implied in VS_OPCODE_URB_WRITE.
1835 if (intel
->gen
>= 6) {
1836 mrf
= emit_vue_header_gen6(mrf
);
1838 mrf
= emit_vue_header_gen4(mrf
);
1841 /* Set up the VUE data for the first URB write */
1843 for (attr
= 0; attr
< VERT_RESULT_MAX
; attr
++) {
1844 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1847 outputs_remaining
&= ~BITFIELD64_BIT(attr
);
1849 /* This is set up in the VUE header. */
1850 if (attr
== VERT_RESULT_HPOS
)
1853 /* This is loaded into the VUE header, and thus doesn't occupy
1854 * an attribute slot.
1856 if (attr
== VERT_RESULT_PSIZ
)
1859 vec4_instruction
*inst
= emit(BRW_OPCODE_MOV
, brw_message_reg(mrf
++),
1860 src_reg(output_reg
[attr
]));
1862 if ((attr
== VERT_RESULT_COL0
||
1863 attr
== VERT_RESULT_COL1
||
1864 attr
== VERT_RESULT_BFC0
||
1865 attr
== VERT_RESULT_BFC1
) &&
1866 c
->key
.clamp_vertex_color
) {
1867 inst
->saturate
= true;
1870 /* If this was MRF 15, we can't fit anything more into this URB
1871 * WRITE. Note that base_mrf of 1 means that MRF 15 is an
1872 * even-numbered amount of URB write data, which will meet
1873 * gen6's requirements for length alignment.
1875 if (mrf
> max_usable_mrf
) {
1881 vec4_instruction
*inst
= emit(VS_OPCODE_URB_WRITE
);
1882 inst
->base_mrf
= base_mrf
;
1883 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1884 inst
->eot
= !outputs_remaining
;
1886 urb_entry_size
= mrf
- base_mrf
;
1888 /* Optional second URB write */
1889 if (outputs_remaining
) {
1892 for (; attr
< VERT_RESULT_MAX
; attr
++) {
1893 if (!(c
->prog_data
.outputs_written
& BITFIELD64_BIT(attr
)))
1896 assert(mrf
< max_usable_mrf
);
1898 emit(BRW_OPCODE_MOV
, brw_message_reg(mrf
++), src_reg(output_reg
[attr
]));
1901 inst
= emit(VS_OPCODE_URB_WRITE
);
1902 inst
->base_mrf
= base_mrf
;
1903 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
1905 /* URB destination offset. In the previous write, we got MRFs
1906 * 2-13 minus the one header MRF, so 12 regs. URB offset is in
1907 * URB row increments, and each of our MRFs is half of one of
1908 * those, since we're doing interleaved writes.
1910 inst
->offset
= (max_usable_mrf
- base_mrf
) / 2;
1912 urb_entry_size
+= mrf
- base_mrf
;
1915 if (intel
->gen
== 6)
1916 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 8) / 8;
1918 c
->prog_data
.urb_entry_size
= ALIGN(urb_entry_size
, 4) / 4;
1922 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
1923 src_reg
*reladdr
, int reg_offset
)
1925 /* Because we store the values to scratch interleaved like our
1926 * vertex data, we need to scale the vec4 index by 2.
1928 int message_header_scale
= 2;
1930 /* Pre-gen6, the message header uses byte offsets instead of vec4
1931 * (16-byte) offset units.
1934 message_header_scale
*= 16;
1937 src_reg index
= src_reg(this, glsl_type::int_type
);
1939 vec4_instruction
*add
= emit(BRW_OPCODE_ADD
,
1942 src_reg(reg_offset
));
1943 /* Move our new instruction from the tail to its correct place. */
1945 inst
->insert_before(add
);
1947 vec4_instruction
*mul
= emit(BRW_OPCODE_MUL
, dst_reg(index
),
1948 index
, src_reg(message_header_scale
));
1950 inst
->insert_before(mul
);
1954 return src_reg(reg_offset
* message_header_scale
);
1959 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
1960 src_reg
*reladdr
, int reg_offset
)
1963 src_reg index
= src_reg(this, glsl_type::int_type
);
1965 vec4_instruction
*add
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_ADD
,
1968 src_reg(reg_offset
));
1970 add
->annotation
= inst
->annotation
;
1971 inst
->insert_before(add
);
1973 /* Pre-gen6, the message header uses byte offsets instead of vec4
1974 * (16-byte) offset units.
1976 if (intel
->gen
< 6) {
1977 vec4_instruction
*mul
= new(mem_ctx
) vec4_instruction(this,
1983 mul
->annotation
= inst
->annotation
;
1984 inst
->insert_before(mul
);
1989 int message_header_scale
= intel
->gen
< 6 ? 16 : 1;
1990 return src_reg(reg_offset
* message_header_scale
);
1995 * Emits an instruction before @inst to load the value named by @orig_src
1996 * from scratch space at @base_offset to @temp.
1999 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
2000 dst_reg temp
, src_reg orig_src
,
2003 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2004 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
2006 vec4_instruction
*scratch_read_inst
= emit(VS_OPCODE_SCRATCH_READ
,
2009 scratch_read_inst
->base_mrf
= 14;
2010 scratch_read_inst
->mlen
= 1;
2011 /* Move our instruction from the tail to its correct place. */
2012 scratch_read_inst
->remove();
2013 inst
->insert_before(scratch_read_inst
);
2017 * Emits an instruction after @inst to store the value to be written
2018 * to @orig_dst to scratch space at @base_offset, from @temp.
2021 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
,
2022 src_reg temp
, dst_reg orig_dst
,
2025 int reg_offset
= base_offset
+ orig_dst
.reg_offset
;
2026 src_reg index
= get_scratch_offset(inst
, orig_dst
.reladdr
, reg_offset
);
2028 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
2029 orig_dst
.writemask
));
2030 vec4_instruction
*scratch_write_inst
= emit(VS_OPCODE_SCRATCH_WRITE
,
2032 scratch_write_inst
->base_mrf
= 13;
2033 scratch_write_inst
->mlen
= 2;
2034 scratch_write_inst
->predicate
= inst
->predicate
;
2035 /* Move our instruction from the tail to its correct place. */
2036 scratch_write_inst
->remove();
2037 inst
->insert_after(scratch_write_inst
);
2041 * We can't generally support array access in GRF space, because a
2042 * single instruction's destination can only span 2 contiguous
2043 * registers. So, we send all GRF arrays that get variable index
2044 * access to scratch space.
2047 vec4_visitor::move_grf_array_access_to_scratch()
2049 int scratch_loc
[this->virtual_grf_count
];
2051 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
2052 scratch_loc
[i
] = -1;
2055 /* First, calculate the set of virtual GRFs that need to be punted
2056 * to scratch due to having any array access on them, and where in
2059 foreach_list(node
, &this->instructions
) {
2060 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2062 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
2063 scratch_loc
[inst
->dst
.reg
] == -1) {
2064 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
2065 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
] * 8 * 4;
2068 for (int i
= 0 ; i
< 3; i
++) {
2069 src_reg
*src
= &inst
->src
[i
];
2071 if (src
->file
== GRF
&& src
->reladdr
&&
2072 scratch_loc
[src
->reg
] == -1) {
2073 scratch_loc
[src
->reg
] = c
->last_scratch
;
2074 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
] * 8 * 4;
2079 /* Now, for anything that will be accessed through scratch, rewrite
2080 * it to load/store. Note that this is a _safe list walk, because
2081 * we may generate a new scratch_write instruction after the one
2084 foreach_list_safe(node
, &this->instructions
) {
2085 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2087 /* Set up the annotation tracking for new generated instructions. */
2089 current_annotation
= inst
->annotation
;
2091 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
2092 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
2094 emit_scratch_write(inst
, temp
, inst
->dst
, scratch_loc
[inst
->dst
.reg
]);
2096 inst
->dst
.file
= temp
.file
;
2097 inst
->dst
.reg
= temp
.reg
;
2098 inst
->dst
.reg_offset
= temp
.reg_offset
;
2099 inst
->dst
.reladdr
= NULL
;
2102 for (int i
= 0 ; i
< 3; i
++) {
2103 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
2106 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2108 emit_scratch_read(inst
, temp
, inst
->src
[i
],
2109 scratch_loc
[inst
->src
[i
].reg
]);
2111 inst
->src
[i
].file
= temp
.file
;
2112 inst
->src
[i
].reg
= temp
.reg
;
2113 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2114 inst
->src
[i
].reladdr
= NULL
;
2120 * Emits an instruction before @inst to load the value named by @orig_src
2121 * from the pull constant buffer (surface) at @base_offset to @temp.
2124 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
2125 dst_reg temp
, src_reg orig_src
,
2128 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
2129 src_reg index
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
2130 vec4_instruction
*load
;
2132 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
2134 load
->annotation
= inst
->annotation
;
2135 load
->ir
= inst
->ir
;
2136 load
->base_mrf
= 14;
2138 inst
->insert_before(load
);
2142 * Implements array access of uniforms by inserting a
2143 * PULL_CONSTANT_LOAD instruction.
2145 * Unlike temporary GRF array access (where we don't support it due to
2146 * the difficulty of doing relative addressing on instruction
2147 * destinations), we could potentially do array access of uniforms
2148 * that were loaded in GRF space as push constants. In real-world
2149 * usage we've seen, though, the arrays being used are always larger
2150 * than we could load as push constants, so just always move all
2151 * uniform array access out to a pull constant buffer.
2154 vec4_visitor::move_uniform_array_access_to_pull_constants()
2156 int pull_constant_loc
[this->uniforms
];
2158 for (int i
= 0; i
< this->uniforms
; i
++) {
2159 pull_constant_loc
[i
] = -1;
2162 /* Walk through and find array access of uniforms. Put a copy of that
2163 * uniform in the pull constant buffer.
2165 * Note that we don't move constant-indexed accesses to arrays. No
2166 * testing has been done of the performance impact of this choice.
2168 foreach_list_safe(node
, &this->instructions
) {
2169 vec4_instruction
*inst
= (vec4_instruction
*)node
;
2171 for (int i
= 0 ; i
< 3; i
++) {
2172 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2175 int uniform
= inst
->src
[i
].reg
;
2177 /* If this array isn't already present in the pull constant buffer,
2180 if (pull_constant_loc
[uniform
] == -1) {
2181 const float **values
= &prog_data
->param
[uniform
* 4];
2183 pull_constant_loc
[uniform
] = prog_data
->nr_pull_params
;
2185 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
2186 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
2190 /* Set up the annotation tracking for new generated instructions. */
2192 current_annotation
= inst
->annotation
;
2194 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
2196 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
2197 pull_constant_loc
[uniform
]);
2199 inst
->src
[i
].file
= temp
.file
;
2200 inst
->src
[i
].reg
= temp
.reg
;
2201 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
2202 inst
->src
[i
].reladdr
= NULL
;
2207 vec4_visitor::vec4_visitor(struct brw_vs_compile
*c
,
2208 struct gl_shader_program
*prog
,
2209 struct brw_shader
*shader
)
2214 this->intel
= &brw
->intel
;
2215 this->ctx
= &intel
->ctx
;
2217 this->shader
= shader
;
2219 this->mem_ctx
= ralloc_context(NULL
);
2220 this->failed
= false;
2222 this->base_ir
= NULL
;
2223 this->current_annotation
= NULL
;
2226 this->vp
= prog
->VertexProgram
;
2227 this->prog_data
= &c
->prog_data
;
2229 this->variable_ht
= hash_table_ctor(0,
2230 hash_table_pointer_hash
,
2231 hash_table_pointer_compare
);
2233 this->virtual_grf_def
= NULL
;
2234 this->virtual_grf_use
= NULL
;
2235 this->virtual_grf_sizes
= NULL
;
2236 this->virtual_grf_count
= 0;
2237 this->virtual_grf_array_size
= 0;
2238 this->live_intervals_valid
= false;
2242 this->variable_ht
= hash_table_ctor(0,
2243 hash_table_pointer_hash
,
2244 hash_table_pointer_compare
);
2247 vec4_visitor::~vec4_visitor()
2249 ralloc_free(this->mem_ctx
);
2250 hash_table_dtor(this->variable_ht
);
2255 vec4_visitor::fail(const char *format
, ...)
2265 va_start(va
, format
);
2266 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
2268 msg
= ralloc_asprintf(mem_ctx
, "VS compile failed: %s\n", msg
);
2270 this->fail_msg
= msg
;
2272 if (INTEL_DEBUG
& DEBUG_VS
) {
2273 fprintf(stderr
, "%s", msg
);
2277 } /* namespace brw */