2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
29 #define FIRST_SPILL_MRF(gen) (gen == 6 ? 21 : 13)
33 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
34 const src_reg
&src0
, const src_reg
&src1
,
37 this->opcode
= opcode
;
42 this->saturate
= false;
43 this->force_writemask_all
= false;
44 this->no_dd_clear
= false;
45 this->no_dd_check
= false;
46 this->writes_accumulator
= false;
47 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
48 this->predicate
= BRW_PREDICATE_NONE
;
49 this->predicate_inverse
= false;
51 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
52 this->shadow_compare
= false;
54 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
55 this->header_size
= 0;
56 this->flag_subreg
= 0;
60 this->annotation
= NULL
;
64 vec4_visitor::emit(vec4_instruction
*inst
)
66 inst
->ir
= this->base_ir
;
67 inst
->annotation
= this->current_annotation
;
69 this->instructions
.push_tail(inst
);
75 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
76 vec4_instruction
*new_inst
)
78 new_inst
->ir
= inst
->ir
;
79 new_inst
->annotation
= inst
->annotation
;
81 inst
->insert_before(block
, new_inst
);
87 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
88 const src_reg
&src1
, const src_reg
&src2
)
90 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
95 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
98 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
102 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
104 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
108 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
110 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
114 vec4_visitor::emit(enum opcode opcode
)
116 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
121 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
123 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
128 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
129 const src_reg &src1) \
131 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
135 #define ALU2_ACC(op) \
137 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
138 const src_reg &src1) \
140 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
141 BRW_OPCODE_##op, dst, src0, src1); \
142 inst->writes_accumulator = true; \
148 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
149 const src_reg &src1, const src_reg &src2) \
151 assert(devinfo->gen >= 6); \
152 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
189 /** Gen4 predicated IF. */
191 vec4_visitor::IF(enum brw_predicate predicate
)
193 vec4_instruction
*inst
;
195 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
196 inst
->predicate
= predicate
;
201 /** Gen6 IF with embedded comparison. */
203 vec4_visitor::IF(src_reg src0
, src_reg src1
,
204 enum brw_conditional_mod condition
)
206 assert(devinfo
->gen
== 6);
208 vec4_instruction
*inst
;
210 resolve_ud_negate(&src0
);
211 resolve_ud_negate(&src1
);
213 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
215 inst
->conditional_mod
= condition
;
221 * CMP: Sets the low bit of the destination channels with the result
222 * of the comparison, while the upper bits are undefined, and updates
223 * the flag register with the packed 16 bits of the result.
226 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
227 enum brw_conditional_mod condition
)
229 vec4_instruction
*inst
;
231 /* Take the instruction:
233 * CMP null<d> src0<f> src1<f>
235 * Original gen4 does type conversion to the destination type before
236 * comparison, producing garbage results for floating point comparisons.
238 * The destination type doesn't matter on newer generations, so we set the
239 * type to match src0 so we can compact the instruction.
241 dst
.type
= src0
.type
;
242 if (dst
.file
== HW_REG
)
243 dst
.fixed_hw_reg
.type
= dst
.type
;
245 resolve_ud_negate(&src0
);
246 resolve_ud_negate(&src1
);
248 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
249 inst
->conditional_mod
= condition
;
255 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
257 vec4_instruction
*inst
;
259 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
261 inst
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
) + 1;
268 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
269 const src_reg
&index
)
271 vec4_instruction
*inst
;
273 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
275 inst
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
);
282 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
284 static enum opcode dot_opcodes
[] = {
285 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
288 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
292 vec4_visitor::fix_3src_operand(const src_reg
&src
)
294 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
295 * able to use vertical stride of zero to replicate the vec4 uniform, like
297 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
299 * But you can't, since vertical stride is always four in three-source
300 * instructions. Instead, insert a MOV instruction to do the replication so
301 * that the three-source instruction can consume it.
304 /* The MOV is only needed if the source is a uniform or immediate. */
305 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
308 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
311 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
312 expanded
.type
= src
.type
;
313 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
314 return src_reg(expanded
);
318 vec4_visitor::resolve_source_modifiers(const src_reg
&src
)
320 if (!src
.abs
&& !src
.negate
)
323 dst_reg resolved
= dst_reg(this, glsl_type::ivec4_type
);
324 resolved
.type
= src
.type
;
325 emit(MOV(resolved
, src
));
327 return src_reg(resolved
);
331 vec4_visitor::fix_math_operand(const src_reg
&src
)
333 if (devinfo
->gen
< 6 || devinfo
->gen
>= 8 || src
.file
== BAD_FILE
)
336 /* The gen6 math instruction ignores the source modifiers --
337 * swizzle, abs, negate, and at least some parts of the register
338 * region description.
340 * Rather than trying to enumerate all these cases, *always* expand the
341 * operand to a temp GRF for gen6.
343 * For gen7, keep the operand as-is, except if immediate, which gen7 still
347 if (devinfo
->gen
== 7 && src
.file
!= IMM
)
350 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
351 expanded
.type
= src
.type
;
352 emit(MOV(expanded
, src
));
353 return src_reg(expanded
);
357 vec4_visitor::emit_math(enum opcode opcode
,
359 const src_reg
&src0
, const src_reg
&src1
)
361 vec4_instruction
*math
=
362 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
364 if (devinfo
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
365 /* MATH on Gen6 must be align1, so we can't do writemasks. */
366 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
367 math
->dst
.type
= dst
.type
;
368 math
= emit(MOV(dst
, src_reg(math
->dst
)));
369 } else if (devinfo
->gen
< 6) {
371 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
378 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
380 if (devinfo
->gen
< 7) {
381 unreachable("ir_unop_pack_half_2x16 should be lowered");
384 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
385 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
387 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
389 * Because this instruction does not have a 16-bit floating-point type,
390 * the destination data type must be Word (W).
392 * The destination must be DWord-aligned and specify a horizontal stride
393 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
394 * each destination channel and the upper word is not modified.
396 * The above restriction implies that the f32to16 instruction must use
397 * align1 mode, because only in align1 mode is it possible to specify
398 * horizontal stride. We choose here to defy the hardware docs and emit
399 * align16 instructions.
401 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
402 * instructions. I was partially successful in that the code passed all
403 * tests. However, the code was dubiously correct and fragile, and the
404 * tests were not harsh enough to probe that frailty. Not trusting the
405 * code, I chose instead to remain in align16 mode in defiance of the hw
408 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
409 * simulator, emitting a f32to16 in align16 mode with UD as destination
410 * data type is safe. The behavior differs from that specified in the PRM
411 * in that the upper word of each destination channel is cleared to 0.
414 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
415 src_reg
tmp_src(tmp_dst
);
418 /* Verify the undocumented behavior on which the following instructions
419 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
420 * then the result of the bit-or instruction below will be incorrect.
422 * You should inspect the disasm output in order to verify that the MOV is
423 * not optimized away.
425 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
428 /* Give tmp the form below, where "." means untouched.
431 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
433 * That the upper word of each write-channel be 0 is required for the
434 * following bit-shift and bit-or instructions to work. Note that this
435 * relies on the undocumented hardware behavior mentioned above.
437 tmp_dst
.writemask
= WRITEMASK_XY
;
438 emit(F32TO16(tmp_dst
, src0
));
440 /* Give the write-channels of dst the form:
443 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
444 emit(SHL(dst
, tmp_src
, src_reg(16u)));
446 /* Finally, give the write-channels of dst the form of packHalf2x16's
450 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
451 emit(OR(dst
, src_reg(dst
), tmp_src
));
455 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
457 if (devinfo
->gen
< 7) {
458 unreachable("ir_unop_unpack_half_2x16 should be lowered");
461 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
462 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
464 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
466 * Because this instruction does not have a 16-bit floating-point type,
467 * the source data type must be Word (W). The destination type must be
470 * To use W as the source data type, we must adjust horizontal strides,
471 * which is only possible in align1 mode. All my [chadv] attempts at
472 * emitting align1 instructions for unpackHalf2x16 failed to pass the
473 * Piglit tests, so I gave up.
475 * I've verified that, on gen7 hardware and the simulator, it is safe to
476 * emit f16to32 in align16 mode with UD as source data type.
479 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
480 src_reg
tmp_src(tmp_dst
);
482 tmp_dst
.writemask
= WRITEMASK_X
;
483 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
485 tmp_dst
.writemask
= WRITEMASK_Y
;
486 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
488 dst
.writemask
= WRITEMASK_XY
;
489 emit(F16TO32(dst
, tmp_src
));
493 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
495 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
496 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
497 * is not suitable to generate the shift values, but we can use the packed
498 * vector float and a type-converting MOV.
500 dst_reg
shift(this, glsl_type::uvec4_type
);
501 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
503 dst_reg
shifted(this, glsl_type::uvec4_type
);
504 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
505 emit(SHR(shifted
, src0
, src_reg(shift
)));
507 shifted
.type
= BRW_REGISTER_TYPE_UB
;
508 dst_reg
f(this, glsl_type::vec4_type
);
509 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
511 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
515 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
517 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
518 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
519 * is not suitable to generate the shift values, but we can use the packed
520 * vector float and a type-converting MOV.
522 dst_reg
shift(this, glsl_type::uvec4_type
);
523 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
525 dst_reg
shifted(this, glsl_type::uvec4_type
);
526 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
527 emit(SHR(shifted
, src0
, src_reg(shift
)));
529 shifted
.type
= BRW_REGISTER_TYPE_B
;
530 dst_reg
f(this, glsl_type::vec4_type
);
531 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
533 dst_reg
scaled(this, glsl_type::vec4_type
);
534 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
536 dst_reg
max(this, glsl_type::vec4_type
);
537 emit_minmax(BRW_CONDITIONAL_GE
, max
, src_reg(scaled
), src_reg(-1.0f
));
538 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
542 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
544 dst_reg
saturated(this, glsl_type::vec4_type
);
545 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
546 inst
->saturate
= true;
548 dst_reg
scaled(this, glsl_type::vec4_type
);
549 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
551 dst_reg
rounded(this, glsl_type::vec4_type
);
552 emit(RNDE(rounded
, src_reg(scaled
)));
554 dst_reg
u(this, glsl_type::uvec4_type
);
555 emit(MOV(u
, src_reg(rounded
)));
558 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
562 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
564 dst_reg
max(this, glsl_type::vec4_type
);
565 emit_minmax(BRW_CONDITIONAL_GE
, max
, src0
, src_reg(-1.0f
));
567 dst_reg
min(this, glsl_type::vec4_type
);
568 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
570 dst_reg
scaled(this, glsl_type::vec4_type
);
571 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
573 dst_reg
rounded(this, glsl_type::vec4_type
);
574 emit(RNDE(rounded
, src_reg(scaled
)));
576 dst_reg
i(this, glsl_type::ivec4_type
);
577 emit(MOV(i
, src_reg(rounded
)));
580 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
584 vec4_visitor::visit_instructions(const exec_list
*list
)
586 foreach_in_list(ir_instruction
, ir
, list
) {
593 * Returns the minimum number of vec4 elements needed to pack a type.
595 * For simple types, it will return 1 (a single vec4); for matrices, the
596 * number of columns; for array and struct, the sum of the vec4_size of
597 * each of its elements; and for sampler and atomic, zero.
599 * This method is useful to calculate how much register space is needed to
600 * store a particular type.
603 type_size_vec4(const struct glsl_type
*type
)
608 switch (type
->base_type
) {
611 case GLSL_TYPE_FLOAT
:
613 if (type
->is_matrix()) {
614 return type
->matrix_columns
;
616 /* Regardless of size of vector, it gets a vec4. This is bad
617 * packing for things like floats, but otherwise arrays become a
618 * mess. Hopefully a later pass over the code can pack scalars
619 * down if appropriate.
623 case GLSL_TYPE_ARRAY
:
624 assert(type
->length
> 0);
625 return type_size_vec4(type
->fields
.array
) * type
->length
;
626 case GLSL_TYPE_STRUCT
:
628 for (i
= 0; i
< type
->length
; i
++) {
629 size
+= type_size_vec4(type
->fields
.structure
[i
].type
);
632 case GLSL_TYPE_SUBROUTINE
:
635 case GLSL_TYPE_SAMPLER
:
636 /* Samplers take up no register space, since they're baked in at
640 case GLSL_TYPE_ATOMIC_UINT
:
642 case GLSL_TYPE_IMAGE
:
643 return DIV_ROUND_UP(BRW_IMAGE_PARAM_SIZE
, 4);
645 case GLSL_TYPE_DOUBLE
:
646 case GLSL_TYPE_ERROR
:
647 case GLSL_TYPE_INTERFACE
:
648 unreachable("not reached");
654 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
659 this->reg
= v
->alloc
.allocate(type_size_vec4(type
));
661 if (type
->is_array() || type
->is_record()) {
662 this->swizzle
= BRW_SWIZZLE_NOOP
;
664 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
667 this->type
= brw_type_for_base_type(type
);
670 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
677 this->reg
= v
->alloc
.allocate(type_size_vec4(type
) * size
);
679 this->swizzle
= BRW_SWIZZLE_NOOP
;
681 this->type
= brw_type_for_base_type(type
);
684 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
689 this->reg
= v
->alloc
.allocate(type_size_vec4(type
));
691 if (type
->is_array() || type
->is_record()) {
692 this->writemask
= WRITEMASK_XYZW
;
694 this->writemask
= (1 << type
->vector_elements
) - 1;
697 this->type
= brw_type_for_base_type(type
);
701 vec4_visitor::setup_vec4_uniform_value(unsigned param_offset
,
702 const gl_constant_value
*values
,
705 static const gl_constant_value zero
= { 0 };
707 assert(param_offset
% 4 == 0);
709 for (unsigned i
= 0; i
< n
; ++i
)
710 stage_prog_data
->param
[param_offset
+ i
] = &values
[i
];
712 for (unsigned i
= n
; i
< 4; ++i
)
713 stage_prog_data
->param
[param_offset
+ i
] = &zero
;
715 uniform_vector_size
[param_offset
/ 4] = n
;
718 /* Our support for uniforms is piggy-backed on the struct
719 * gl_fragment_program, because that's where the values actually
720 * get stored, rather than in some global gl_shader_program uniform
724 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
726 int namelen
= strlen(ir
->name
);
728 /* The data for our (non-builtin) uniforms is stored in a series of
729 * gl_uniform_driver_storage structs for each subcomponent that
730 * glGetUniformLocation() could name. We know it's been set up in the same
731 * order we'd walk the type, so walk the list of storage and find anything
732 * with our name, or the prefix of a component that starts with our name.
734 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
735 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
737 if (storage
->builtin
)
740 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
741 (storage
->name
[namelen
] != 0 &&
742 storage
->name
[namelen
] != '.' &&
743 storage
->name
[namelen
] != '[')) {
747 const unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
748 storage
->type
->matrix_columns
);
749 const unsigned vector_size
= storage
->type
->vector_elements
;
751 for (unsigned s
= 0; s
< vector_count
; s
++) {
752 setup_vec4_uniform_value(uniforms
* 4,
753 &storage
->storage
[s
* vector_size
],
760 /* Our support for builtin uniforms is even scarier than non-builtin.
761 * It sits on top of the PROG_STATE_VAR parameters that are
762 * automatically updated from GL context state.
765 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
767 const ir_state_slot
*const slots
= ir
->get_state_slots();
768 assert(slots
!= NULL
);
770 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
771 /* This state reference has already been setup by ir_to_mesa,
772 * but we'll get the same index back here. We can reference
773 * ParameterValues directly, since unlike brw_fs.cpp, we never
774 * add new state references during compile.
776 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
777 (gl_state_index
*)slots
[i
].tokens
);
778 gl_constant_value
*values
=
779 &this->prog
->Parameters
->ParameterValues
[index
][0];
781 assert(this->uniforms
< uniform_array_size
);
783 for (unsigned j
= 0; j
< 4; j
++)
784 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
785 &values
[GET_SWZ(slots
[i
].swizzle
, j
)];
787 this->uniform_vector_size
[this->uniforms
] =
788 (ir
->type
->is_scalar() || ir
->type
->is_vector() ||
789 ir
->type
->is_matrix() ? ir
->type
->vector_elements
: 4);
796 vec4_visitor::variable_storage(ir_variable
*var
)
798 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
802 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
803 enum brw_predicate
*predicate
)
805 ir_expression
*expr
= ir
->as_expression();
807 *predicate
= BRW_PREDICATE_NORMAL
;
809 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
811 vec4_instruction
*inst
;
813 assert(expr
->get_num_operands() <= 3);
814 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
815 expr
->operands
[i
]->accept(this);
816 op
[i
] = this->result
;
818 resolve_ud_negate(&op
[i
]);
821 switch (expr
->operation
) {
822 case ir_unop_logic_not
:
823 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
824 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
827 case ir_binop_logic_xor
:
828 if (devinfo
->gen
<= 5) {
829 src_reg temp
= src_reg(this, ir
->type
);
830 emit(XOR(dst_reg(temp
), op
[0], op
[1]));
831 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
833 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
835 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
838 case ir_binop_logic_or
:
839 if (devinfo
->gen
<= 5) {
840 src_reg temp
= src_reg(this, ir
->type
);
841 emit(OR(dst_reg(temp
), op
[0], op
[1]));
842 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
844 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
846 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
849 case ir_binop_logic_and
:
850 if (devinfo
->gen
<= 5) {
851 src_reg temp
= src_reg(this, ir
->type
);
852 emit(AND(dst_reg(temp
), op
[0], op
[1]));
853 inst
= emit(AND(dst_null_d(), temp
, src_reg(1)));
855 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
857 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
861 if (devinfo
->gen
>= 6) {
862 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
864 inst
= emit(MOV(dst_null_f(), op
[0]));
865 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
870 if (devinfo
->gen
>= 6) {
871 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
873 inst
= emit(MOV(dst_null_d(), op
[0]));
874 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
878 case ir_binop_all_equal
:
879 if (devinfo
->gen
<= 5) {
880 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
881 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
883 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
884 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
887 case ir_binop_any_nequal
:
888 if (devinfo
->gen
<= 5) {
889 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
890 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
892 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
893 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
897 if (devinfo
->gen
<= 5) {
898 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
900 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
901 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
904 case ir_binop_greater
:
905 case ir_binop_gequal
:
907 case ir_binop_lequal
:
909 case ir_binop_nequal
:
910 if (devinfo
->gen
<= 5) {
911 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
912 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
914 emit(CMP(dst_null_d(), op
[0], op
[1],
915 brw_conditional_for_comparison(expr
->operation
)));
918 case ir_triop_csel
: {
919 /* Expand the boolean condition into the flag register. */
920 inst
= emit(MOV(dst_null_d(), op
[0]));
921 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
923 /* Select which boolean to return. */
924 dst_reg
temp(this, expr
->operands
[1]->type
);
925 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
926 inst
->predicate
= BRW_PREDICATE_NORMAL
;
928 /* Expand the result to a condition code. */
929 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
930 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
935 unreachable("not reached");
942 resolve_ud_negate(&this->result
);
944 vec4_instruction
*inst
= emit(AND(dst_null_d(), this->result
, src_reg(1)));
945 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
949 * Emit a gen6 IF statement with the comparison folded into the IF
953 vec4_visitor::emit_if_gen6(ir_if
*ir
)
955 ir_expression
*expr
= ir
->condition
->as_expression();
957 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
961 assert(expr
->get_num_operands() <= 3);
962 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
963 expr
->operands
[i
]->accept(this);
964 op
[i
] = this->result
;
967 switch (expr
->operation
) {
968 case ir_unop_logic_not
:
969 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
972 case ir_binop_logic_xor
:
973 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
976 case ir_binop_logic_or
:
977 temp
= dst_reg(this, glsl_type::bool_type
);
978 emit(OR(temp
, op
[0], op
[1]));
979 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
982 case ir_binop_logic_and
:
983 temp
= dst_reg(this, glsl_type::bool_type
);
984 emit(AND(temp
, op
[0], op
[1]));
985 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
989 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
993 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
996 case ir_binop_greater
:
997 case ir_binop_gequal
:
999 case ir_binop_lequal
:
1000 case ir_binop_equal
:
1001 case ir_binop_nequal
:
1002 emit(IF(op
[0], op
[1],
1003 brw_conditional_for_comparison(expr
->operation
)));
1006 case ir_binop_all_equal
:
1007 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1008 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
1011 case ir_binop_any_nequal
:
1012 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1013 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1017 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1018 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
1021 case ir_triop_csel
: {
1022 /* Expand the boolean condition into the flag register. */
1023 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
1024 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1026 /* Select which boolean to return. */
1027 dst_reg
temp(this, expr
->operands
[1]->type
);
1028 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
1029 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1031 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
1036 unreachable("not reached");
1041 ir
->condition
->accept(this);
1043 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
1047 vec4_visitor::visit(ir_variable
*ir
)
1049 dst_reg
*reg
= NULL
;
1051 if (variable_storage(ir
))
1054 switch (ir
->data
.mode
) {
1055 case ir_var_shader_in
:
1056 assert(ir
->data
.location
!= -1);
1057 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
1060 case ir_var_shader_out
:
1061 assert(ir
->data
.location
!= -1);
1062 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1064 for (int i
= 0; i
< type_size_vec4(ir
->type
); i
++) {
1065 output_reg
[ir
->data
.location
+ i
] = *reg
;
1066 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
1067 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
1072 case ir_var_temporary
:
1073 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1076 case ir_var_uniform
:
1077 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1079 /* Thanks to the lower_ubo_reference pass, we will see only
1080 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1081 * variables, so no need for them to be in variable_ht.
1083 * Some uniforms, such as samplers and atomic counters, have no actual
1084 * storage, so we should ignore them.
1086 if (ir
->is_in_buffer_block() || type_size_vec4(ir
->type
) == 0)
1089 /* Track how big the whole uniform variable is, in case we need to put a
1090 * copy of its data into pull constants for array access.
1092 assert(this->uniforms
< uniform_array_size
);
1093 this->uniform_size
[this->uniforms
] = type_size_vec4(ir
->type
);
1095 if (!strncmp(ir
->name
, "gl_", 3)) {
1096 setup_builtin_uniform_values(ir
);
1098 setup_uniform_values(ir
);
1102 case ir_var_system_value
:
1103 reg
= make_reg_for_system_value(ir
->data
.location
, ir
->type
);
1107 unreachable("not reached");
1110 reg
->type
= brw_type_for_base_type(ir
->type
);
1111 hash_table_insert(this->variable_ht
, reg
, ir
);
1115 vec4_visitor::visit(ir_loop
*ir
)
1117 /* We don't want debugging output to print the whole body of the
1118 * loop as the annotation.
1120 this->base_ir
= NULL
;
1122 emit(BRW_OPCODE_DO
);
1124 visit_instructions(&ir
->body_instructions
);
1126 emit(BRW_OPCODE_WHILE
);
1130 vec4_visitor::visit(ir_loop_jump
*ir
)
1133 case ir_loop_jump::jump_break
:
1134 emit(BRW_OPCODE_BREAK
);
1136 case ir_loop_jump::jump_continue
:
1137 emit(BRW_OPCODE_CONTINUE
);
1144 vec4_visitor::visit(ir_function_signature
*)
1146 unreachable("not reached");
1150 vec4_visitor::visit(ir_function
*ir
)
1152 /* Ignore function bodies other than main() -- we shouldn't see calls to
1153 * them since they should all be inlined.
1155 if (strcmp(ir
->name
, "main") == 0) {
1156 const ir_function_signature
*sig
;
1159 sig
= ir
->matching_signature(NULL
, &empty
, false);
1163 visit_instructions(&sig
->body
);
1168 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1170 /* 3-src instructions were introduced in gen6. */
1171 if (devinfo
->gen
< 6)
1174 /* MAD can only handle floating-point data. */
1175 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1180 bool mul_negate
, mul_abs
;
1182 for (int i
= 0; i
< 2; i
++) {
1186 mul
= ir
->operands
[i
]->as_expression();
1187 nonmul
= ir
->operands
[1 - i
];
1189 if (mul
&& mul
->operation
== ir_unop_abs
) {
1190 mul
= mul
->operands
[0]->as_expression();
1192 } else if (mul
&& mul
->operation
== ir_unop_neg
) {
1193 mul
= mul
->operands
[0]->as_expression();
1197 if (mul
&& mul
->operation
== ir_binop_mul
)
1201 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1204 nonmul
->accept(this);
1205 src_reg src0
= fix_3src_operand(this->result
);
1207 mul
->operands
[0]->accept(this);
1208 src_reg src1
= fix_3src_operand(this->result
);
1209 src1
.negate
^= mul_negate
;
1212 src1
.negate
= false;
1214 mul
->operands
[1]->accept(this);
1215 src_reg src2
= fix_3src_operand(this->result
);
1218 src2
.negate
= false;
1220 this->result
= src_reg(this, ir
->type
);
1221 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1227 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1229 /* This optimization relies on CMP setting the destination to 0 when
1230 * false. Early hardware only sets the least significant bit, and
1231 * leaves the other bits undefined. So we can't use it.
1233 if (devinfo
->gen
< 6)
1236 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1241 switch (cmp
->operation
) {
1243 case ir_binop_greater
:
1244 case ir_binop_lequal
:
1245 case ir_binop_gequal
:
1246 case ir_binop_equal
:
1247 case ir_binop_nequal
:
1254 cmp
->operands
[0]->accept(this);
1255 const src_reg cmp_src0
= this->result
;
1257 cmp
->operands
[1]->accept(this);
1258 const src_reg cmp_src1
= this->result
;
1260 this->result
= src_reg(this, ir
->type
);
1262 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1263 brw_conditional_for_comparison(cmp
->operation
)));
1265 /* If the comparison is false, this->result will just happen to be zero.
1267 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1268 this->result
, src_reg(1.0f
));
1269 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1270 inst
->predicate_inverse
= true;
1276 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1277 src_reg src0
, src_reg src1
)
1279 vec4_instruction
*inst
;
1281 if (devinfo
->gen
>= 6) {
1282 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1283 inst
->conditional_mod
= conditionalmod
;
1285 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1287 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1288 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1295 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1296 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1298 if (devinfo
->gen
>= 6) {
1299 /* Note that the instruction's argument order is reversed from GLSL
1302 return emit(LRP(dst
, fix_3src_operand(a
), fix_3src_operand(y
),
1303 fix_3src_operand(x
)));
1305 /* Earlier generations don't support three source operations, so we
1306 * need to emit x*(1-a) + y*a.
1308 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1309 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1310 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1311 y_times_a
.writemask
= dst
.writemask
;
1312 one_minus_a
.writemask
= dst
.writemask
;
1313 x_times_one_minus_a
.writemask
= dst
.writemask
;
1315 emit(MUL(y_times_a
, y
, a
));
1316 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1317 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1318 return emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1323 * Emits the instructions needed to perform a pull constant load. before_block
1324 * and before_inst can be NULL in which case the instruction will be appended
1325 * to the end of the instruction list.
1328 vec4_visitor::emit_pull_constant_load_reg(dst_reg dst
,
1331 bblock_t
*before_block
,
1332 vec4_instruction
*before_inst
)
1334 assert((before_inst
== NULL
&& before_block
== NULL
) ||
1335 (before_inst
&& before_block
));
1337 vec4_instruction
*pull
;
1339 if (devinfo
->gen
>= 9) {
1340 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
1341 src_reg
header(this, glsl_type::uvec4_type
, 2);
1344 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
1348 emit_before(before_block
, before_inst
, pull
);
1352 dst_reg index_reg
= retype(offset(dst_reg(header
), 1),
1354 pull
= MOV(writemask(index_reg
, WRITEMASK_X
), offset_reg
);
1357 emit_before(before_block
, before_inst
, pull
);
1361 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1366 pull
->header_size
= 1;
1367 } else if (devinfo
->gen
>= 7) {
1368 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1370 grf_offset
.type
= offset_reg
.type
;
1372 pull
= MOV(grf_offset
, offset_reg
);
1375 emit_before(before_block
, before_inst
, pull
);
1379 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1382 src_reg(grf_offset
));
1385 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
1389 pull
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
) + 1;
1394 emit_before(before_block
, before_inst
, pull
);
1400 vec4_visitor::emit_uniformize(const src_reg
&src
)
1402 const src_reg
chan_index(this, glsl_type::uint_type
);
1403 const dst_reg dst
= retype(dst_reg(this, glsl_type::uint_type
),
1406 emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, dst_reg(chan_index
))
1407 ->force_writemask_all
= true;
1408 emit(SHADER_OPCODE_BROADCAST
, dst
, src
, chan_index
)
1409 ->force_writemask_all
= true;
1411 return src_reg(dst
);
1415 vec4_visitor::visit(ir_expression
*ir
)
1417 unsigned int operand
;
1418 src_reg op
[ARRAY_SIZE(ir
->operands
)];
1419 vec4_instruction
*inst
;
1421 if (ir
->operation
== ir_binop_add
) {
1422 if (try_emit_mad(ir
))
1426 if (ir
->operation
== ir_unop_b2f
) {
1427 if (try_emit_b2f_of_compare(ir
))
1431 /* Storage for our result. Ideally for an assignment we'd be using
1432 * the actual storage for the result here, instead.
1434 dst_reg
result_dst(this, ir
->type
);
1435 src_reg
result_src(result_dst
);
1437 if (ir
->operation
== ir_triop_csel
) {
1438 ir
->operands
[1]->accept(this);
1439 op
[1] = this->result
;
1440 ir
->operands
[2]->accept(this);
1441 op
[2] = this->result
;
1443 enum brw_predicate predicate
;
1444 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1445 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1446 inst
->predicate
= predicate
;
1447 this->result
= result_src
;
1451 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1452 this->result
.file
= BAD_FILE
;
1453 ir
->operands
[operand
]->accept(this);
1454 if (this->result
.file
== BAD_FILE
) {
1455 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1456 ir
->operands
[operand
]->fprint(stderr
);
1459 op
[operand
] = this->result
;
1461 /* Matrix expression operands should have been broken down to vector
1462 * operations already.
1464 assert(!ir
->operands
[operand
]->type
->is_matrix());
1467 /* If nothing special happens, this is the result. */
1468 this->result
= result_src
;
1470 switch (ir
->operation
) {
1471 case ir_unop_logic_not
:
1472 emit(NOT(result_dst
, op
[0]));
1475 op
[0].negate
= !op
[0].negate
;
1476 emit(MOV(result_dst
, op
[0]));
1480 op
[0].negate
= false;
1481 emit(MOV(result_dst
, op
[0]));
1485 if (ir
->type
->is_float()) {
1486 /* AND(val, 0x80000000) gives the sign bit.
1488 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1491 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1493 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1494 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1495 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1497 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1498 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1500 this->result
.type
= BRW_REGISTER_TYPE_F
;
1502 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1503 * -> non-negative val generates 0x00000000.
1504 * Predicated OR sets 1 if val is positive.
1506 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1508 emit(ASR(result_dst
, op
[0], src_reg(31)));
1510 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1511 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1516 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1520 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1523 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1527 unreachable("not reached: should be handled by ir_explog_to_explog2");
1529 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1532 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1536 case ir_unop_dFdx_coarse
:
1537 case ir_unop_dFdx_fine
:
1539 case ir_unop_dFdy_coarse
:
1540 case ir_unop_dFdy_fine
:
1541 unreachable("derivatives not valid in vertex shader");
1543 case ir_unop_bitfield_reverse
:
1544 emit(BFREV(result_dst
, op
[0]));
1546 case ir_unop_bit_count
:
1547 emit(CBIT(result_dst
, op
[0]));
1549 case ir_unop_find_msb
: {
1550 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1552 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1553 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1555 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1556 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1557 * subtract the result from 31 to convert the MSB count into an LSB count.
1560 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1561 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1562 emit(MOV(result_dst
, temp
));
1564 src_reg src_tmp
= src_reg(result_dst
);
1565 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1567 src_tmp
.negate
= true;
1568 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1569 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1572 case ir_unop_find_lsb
:
1573 emit(FBL(result_dst
, op
[0]));
1575 case ir_unop_saturate
:
1576 inst
= emit(MOV(result_dst
, op
[0]));
1577 inst
->saturate
= true;
1581 unreachable("not reached: should be handled by lower_noise");
1583 case ir_unop_subroutine_to_int
:
1584 emit(MOV(result_dst
, op
[0]));
1588 emit(ADD(result_dst
, op
[0], op
[1]));
1591 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1594 if (devinfo
->gen
< 8 && ir
->type
->is_integer()) {
1595 /* For integer multiplication, the MUL uses the low 16 bits of one of
1596 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1597 * accumulates in the contribution of the upper 16 bits of that
1598 * operand. If we can determine that one of the args is in the low
1599 * 16 bits, though, we can just emit a single MUL.
1601 if (ir
->operands
[0]->is_uint16_constant()) {
1602 if (devinfo
->gen
< 7)
1603 emit(MUL(result_dst
, op
[0], op
[1]));
1605 emit(MUL(result_dst
, op
[1], op
[0]));
1606 } else if (ir
->operands
[1]->is_uint16_constant()) {
1607 if (devinfo
->gen
< 7)
1608 emit(MUL(result_dst
, op
[1], op
[0]));
1610 emit(MUL(result_dst
, op
[0], op
[1]));
1612 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1614 emit(MUL(acc
, op
[0], op
[1]));
1615 emit(MACH(dst_null_d(), op
[0], op
[1]));
1616 emit(MOV(result_dst
, src_reg(acc
)));
1619 emit(MUL(result_dst
, op
[0], op
[1]));
1622 case ir_binop_imul_high
: {
1623 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1625 emit(MUL(acc
, op
[0], op
[1]));
1626 emit(MACH(result_dst
, op
[0], op
[1]));
1630 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1631 assert(ir
->type
->is_integer());
1632 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1635 case ir_binop_carry
:
1636 unreachable("Should have been lowered by carry_to_arith().");
1638 case ir_binop_borrow
:
1639 unreachable("Should have been lowered by borrow_to_arith().");
1642 /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
1643 assert(ir
->type
->is_integer());
1644 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1648 case ir_binop_greater
:
1649 case ir_binop_lequal
:
1650 case ir_binop_gequal
:
1651 case ir_binop_equal
:
1652 case ir_binop_nequal
: {
1653 if (devinfo
->gen
<= 5) {
1654 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1655 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1657 emit(CMP(result_dst
, op
[0], op
[1],
1658 brw_conditional_for_comparison(ir
->operation
)));
1662 case ir_binop_all_equal
:
1663 if (devinfo
->gen
<= 5) {
1664 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1665 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1668 /* "==" operator producing a scalar boolean. */
1669 if (ir
->operands
[0]->type
->is_vector() ||
1670 ir
->operands
[1]->type
->is_vector()) {
1671 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1672 emit(MOV(result_dst
, src_reg(0)));
1673 inst
= emit(MOV(result_dst
, src_reg(~0)));
1674 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1676 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1679 case ir_binop_any_nequal
:
1680 if (devinfo
->gen
<= 5) {
1681 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1682 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
1685 /* "!=" operator producing a scalar boolean. */
1686 if (ir
->operands
[0]->type
->is_vector() ||
1687 ir
->operands
[1]->type
->is_vector()) {
1688 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1690 emit(MOV(result_dst
, src_reg(0)));
1691 inst
= emit(MOV(result_dst
, src_reg(~0)));
1692 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1694 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1699 if (devinfo
->gen
<= 5) {
1700 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1702 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1703 emit(MOV(result_dst
, src_reg(0)));
1705 inst
= emit(MOV(result_dst
, src_reg(~0)));
1706 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1709 case ir_binop_logic_xor
:
1710 emit(XOR(result_dst
, op
[0], op
[1]));
1713 case ir_binop_logic_or
:
1714 emit(OR(result_dst
, op
[0], op
[1]));
1717 case ir_binop_logic_and
:
1718 emit(AND(result_dst
, op
[0], op
[1]));
1722 assert(ir
->operands
[0]->type
->is_vector());
1723 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1724 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1728 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1731 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1734 case ir_unop_bitcast_i2f
:
1735 case ir_unop_bitcast_u2f
:
1736 this->result
= op
[0];
1737 this->result
.type
= BRW_REGISTER_TYPE_F
;
1740 case ir_unop_bitcast_f2i
:
1741 this->result
= op
[0];
1742 this->result
.type
= BRW_REGISTER_TYPE_D
;
1745 case ir_unop_bitcast_f2u
:
1746 this->result
= op
[0];
1747 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1756 emit(MOV(result_dst
, op
[0]));
1760 if (devinfo
->gen
<= 5) {
1761 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
1763 emit(MOV(result_dst
, negate(op
[0])));
1766 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1769 emit(CMP(result_dst
, op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1773 emit(RNDZ(result_dst
, op
[0]));
1775 case ir_unop_ceil
: {
1776 src_reg tmp
= src_reg(this, ir
->type
);
1777 op
[0].negate
= !op
[0].negate
;
1778 emit(RNDD(dst_reg(tmp
), op
[0]));
1780 emit(MOV(result_dst
, tmp
));
1784 inst
= emit(RNDD(result_dst
, op
[0]));
1787 inst
= emit(FRC(result_dst
, op
[0]));
1789 case ir_unop_round_even
:
1790 emit(RNDE(result_dst
, op
[0]));
1794 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1797 emit_minmax(BRW_CONDITIONAL_GE
, result_dst
, op
[0], op
[1]);
1801 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1804 case ir_unop_bit_not
:
1805 inst
= emit(NOT(result_dst
, op
[0]));
1807 case ir_binop_bit_and
:
1808 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1810 case ir_binop_bit_xor
:
1811 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1813 case ir_binop_bit_or
:
1814 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1817 case ir_binop_lshift
:
1818 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1821 case ir_binop_rshift
:
1822 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1823 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1825 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1829 emit(BFI1(result_dst
, op
[0], op
[1]));
1832 case ir_binop_ubo_load
: {
1833 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1834 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1835 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1838 /* Now, load the vector from that offset. */
1839 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1841 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1842 packed_consts
.type
= result
.type
;
1845 if (const_uniform_block
) {
1846 /* The block index is a constant, so just emit the binding table entry
1849 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1850 const_uniform_block
->value
.u
[0]);
1852 /* The block index is not a constant. Evaluate the index expression
1853 * per-channel and add the base UBO index; we have to select a value
1854 * from any live channel.
1856 surf_index
= src_reg(this, glsl_type::uint_type
);
1857 emit(ADD(dst_reg(surf_index
), op
[0],
1858 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1859 surf_index
= emit_uniformize(surf_index
);
1861 /* Assume this may touch any UBO. It would be nice to provide
1862 * a tighter bound, but the array information is already lowered away.
1864 brw_mark_surface_used(&prog_data
->base
,
1865 prog_data
->base
.binding_table
.ubo_start
+
1866 shader_prog
->NumUniformBlocks
- 1);
1869 if (const_offset_ir
) {
1870 if (devinfo
->gen
>= 8) {
1871 /* Store the offset in a GRF so we can send-from-GRF. */
1872 offset
= src_reg(this, glsl_type::int_type
);
1873 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1875 /* Immediates are fine on older generations since they'll be moved
1876 * to a (potentially fake) MRF at the generator level.
1878 offset
= src_reg(const_offset
/ 16);
1881 offset
= src_reg(this, glsl_type::uint_type
);
1882 emit(SHR(dst_reg(offset
), op
[1], src_reg(4u)));
1885 emit_pull_constant_load_reg(dst_reg(packed_consts
),
1888 NULL
, NULL
/* before_block/inst */);
1890 packed_consts
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
1891 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1892 const_offset
% 16 / 4,
1893 const_offset
% 16 / 4,
1894 const_offset
% 16 / 4);
1896 /* UBO bools are any nonzero int. We need to convert them to 0/~0. */
1897 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1898 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1899 BRW_CONDITIONAL_NZ
));
1901 emit(MOV(result_dst
, packed_consts
));
1906 case ir_binop_vector_extract
:
1907 unreachable("should have been lowered by vec_index_to_cond_assign");
1910 op
[0] = fix_3src_operand(op
[0]);
1911 op
[1] = fix_3src_operand(op
[1]);
1912 op
[2] = fix_3src_operand(op
[2]);
1913 /* Note that the instruction's argument order is reversed from GLSL
1916 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1920 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1924 unreachable("already handled above");
1928 op
[0] = fix_3src_operand(op
[0]);
1929 op
[1] = fix_3src_operand(op
[1]);
1930 op
[2] = fix_3src_operand(op
[2]);
1931 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1934 case ir_triop_bitfield_extract
:
1935 op
[0] = fix_3src_operand(op
[0]);
1936 op
[1] = fix_3src_operand(op
[1]);
1937 op
[2] = fix_3src_operand(op
[2]);
1938 /* Note that the instruction's argument order is reversed from GLSL
1941 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1944 case ir_triop_vector_insert
:
1945 unreachable("should have been lowered by lower_vector_insert");
1947 case ir_quadop_bitfield_insert
:
1948 unreachable("not reached: should be handled by "
1949 "bitfield_insert_to_bfm_bfi\n");
1951 case ir_quadop_vector
:
1952 unreachable("not reached: should be handled by lower_quadop_vector");
1954 case ir_unop_pack_half_2x16
:
1955 emit_pack_half_2x16(result_dst
, op
[0]);
1957 case ir_unop_unpack_half_2x16
:
1958 emit_unpack_half_2x16(result_dst
, op
[0]);
1960 case ir_unop_unpack_unorm_4x8
:
1961 emit_unpack_unorm_4x8(result_dst
, op
[0]);
1963 case ir_unop_unpack_snorm_4x8
:
1964 emit_unpack_snorm_4x8(result_dst
, op
[0]);
1966 case ir_unop_pack_unorm_4x8
:
1967 emit_pack_unorm_4x8(result_dst
, op
[0]);
1969 case ir_unop_pack_snorm_4x8
:
1970 emit_pack_snorm_4x8(result_dst
, op
[0]);
1972 case ir_unop_pack_snorm_2x16
:
1973 case ir_unop_pack_unorm_2x16
:
1974 case ir_unop_unpack_snorm_2x16
:
1975 case ir_unop_unpack_unorm_2x16
:
1976 unreachable("not reached: should be handled by lower_packing_builtins");
1977 case ir_unop_unpack_half_2x16_split_x
:
1978 case ir_unop_unpack_half_2x16_split_y
:
1979 case ir_binop_pack_half_2x16_split
:
1980 case ir_unop_interpolate_at_centroid
:
1981 case ir_binop_interpolate_at_sample
:
1982 case ir_binop_interpolate_at_offset
:
1983 unreachable("not reached: should not occur in vertex shader");
1984 case ir_binop_ldexp
:
1985 unreachable("not reached: should be handled by ldexp_to_arith()");
1993 case ir_unop_pack_double_2x32
:
1994 case ir_unop_unpack_double_2x32
:
1995 case ir_unop_frexp_sig
:
1996 case ir_unop_frexp_exp
:
1997 unreachable("fp64 todo");
2003 vec4_visitor::visit(ir_swizzle
*ir
)
2005 /* Note that this is only swizzles in expressions, not those on the left
2006 * hand side of an assignment, which do write masking. See ir_assignment
2009 const unsigned swz
= brw_compose_swizzle(
2010 brw_swizzle_for_size(ir
->type
->vector_elements
),
2011 BRW_SWIZZLE4(ir
->mask
.x
, ir
->mask
.y
, ir
->mask
.z
, ir
->mask
.w
));
2013 ir
->val
->accept(this);
2014 this->result
= swizzle(this->result
, swz
);
2018 vec4_visitor::visit(ir_dereference_variable
*ir
)
2020 const struct glsl_type
*type
= ir
->type
;
2021 dst_reg
*reg
= variable_storage(ir
->var
);
2024 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
2025 this->result
= src_reg(brw_null_reg());
2029 this->result
= src_reg(*reg
);
2031 /* System values get their swizzle from the dst_reg writemask */
2032 if (ir
->var
->data
.mode
== ir_var_system_value
)
2035 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
2036 this->result
.swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2041 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
2043 /* Under normal circumstances array elements are stored consecutively, so
2044 * the stride is equal to the size of the array element.
2046 return type_size_vec4(ir
->type
);
2051 vec4_visitor::visit(ir_dereference_array
*ir
)
2053 ir_constant
*constant_index
;
2055 int array_stride
= compute_array_stride(ir
);
2057 constant_index
= ir
->array_index
->constant_expression_value();
2059 ir
->array
->accept(this);
2062 if (constant_index
) {
2063 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
2065 /* Variable index array dereference. It eats the "vec4" of the
2066 * base of the array and an index that offsets the Mesa register
2069 ir
->array_index
->accept(this);
2073 if (array_stride
== 1) {
2074 index_reg
= this->result
;
2076 index_reg
= src_reg(this, glsl_type::int_type
);
2078 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
2082 src_reg temp
= src_reg(this, glsl_type::int_type
);
2084 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
2089 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
2090 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2093 /* If the type is smaller than a vec4, replicate the last channel out. */
2094 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2095 src
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2097 src
.swizzle
= BRW_SWIZZLE_NOOP
;
2098 src
.type
= brw_type_for_base_type(ir
->type
);
2104 vec4_visitor::visit(ir_dereference_record
*ir
)
2107 const glsl_type
*struct_type
= ir
->record
->type
;
2110 ir
->record
->accept(this);
2112 for (i
= 0; i
< struct_type
->length
; i
++) {
2113 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2115 offset
+= type_size_vec4(struct_type
->fields
.structure
[i
].type
);
2118 /* If the type is smaller than a vec4, replicate the last channel out. */
2119 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2120 this->result
.swizzle
= brw_swizzle_for_size(ir
->type
->vector_elements
);
2122 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
2123 this->result
.type
= brw_type_for_base_type(ir
->type
);
2125 this->result
.reg_offset
+= offset
;
2129 * We want to be careful in assignment setup to hit the actual storage
2130 * instead of potentially using a temporary like we might with the
2131 * ir_dereference handler.
2134 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
2136 /* The LHS must be a dereference. If the LHS is a variable indexed array
2137 * access of a vector, it must be separated into a series conditional moves
2138 * before reaching this point (see ir_vec_index_to_cond_assign).
2140 assert(ir
->as_dereference());
2141 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2143 assert(!deref_array
->array
->type
->is_vector());
2146 /* Use the rvalue deref handler for the most part. We'll ignore
2147 * swizzles in it and write swizzles using writemask, though.
2150 return dst_reg(v
->result
);
2154 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
2155 const struct glsl_type
*type
,
2156 enum brw_predicate predicate
)
2158 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2159 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2160 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
2165 if (type
->is_array()) {
2166 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2167 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
2172 if (type
->is_matrix()) {
2173 const struct glsl_type
*vec_type
;
2175 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2176 type
->vector_elements
, 1);
2178 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2179 emit_block_move(dst
, src
, vec_type
, predicate
);
2184 assert(type
->is_scalar() || type
->is_vector());
2186 dst
->type
= brw_type_for_base_type(type
);
2187 src
->type
= dst
->type
;
2189 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2191 src
->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
2193 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2194 inst
->predicate
= predicate
;
2201 /* If the RHS processing resulted in an instruction generating a
2202 * temporary value, and it would be easy to rewrite the instruction to
2203 * generate its result right into the LHS instead, do so. This ends
2204 * up reliably removing instructions where it can be tricky to do so
2205 * later without real UD chain information.
2208 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2211 vec4_instruction
*pre_rhs_inst
,
2212 vec4_instruction
*last_rhs_inst
)
2214 /* This could be supported, but it would take more smarts. */
2218 if (pre_rhs_inst
== last_rhs_inst
)
2219 return false; /* No instructions generated to work with. */
2221 /* Make sure the last instruction generated our source reg. */
2222 if (src
.file
!= GRF
||
2223 src
.file
!= last_rhs_inst
->dst
.file
||
2224 src
.reg
!= last_rhs_inst
->dst
.reg
||
2225 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2229 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2232 /* Check that that last instruction fully initialized the channels
2233 * we want to use, in the order we want to use them. We could
2234 * potentially reswizzle the operands of many instructions so that
2235 * we could handle out of order channels, but don't yet.
2238 for (unsigned i
= 0; i
< 4; i
++) {
2239 if (dst
.writemask
& (1 << i
)) {
2240 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2243 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2248 /* Success! Rewrite the instruction. */
2249 last_rhs_inst
->dst
.file
= dst
.file
;
2250 last_rhs_inst
->dst
.reg
= dst
.reg
;
2251 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2252 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2253 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2259 vec4_visitor::visit(ir_assignment
*ir
)
2261 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2262 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2264 if (!ir
->lhs
->type
->is_scalar() &&
2265 !ir
->lhs
->type
->is_vector()) {
2266 ir
->rhs
->accept(this);
2267 src_reg src
= this->result
;
2269 if (ir
->condition
) {
2270 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2273 /* emit_block_move doesn't account for swizzles in the source register.
2274 * This should be ok, since the source register is a structure or an
2275 * array, and those can't be swizzled. But double-check to be sure.
2277 assert(src
.swizzle
==
2278 (ir
->rhs
->type
->is_matrix()
2279 ? brw_swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2280 : BRW_SWIZZLE_NOOP
));
2282 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2286 /* Now we're down to just a scalar/vector with writemasks. */
2289 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2290 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2292 ir
->rhs
->accept(this);
2294 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2299 assert(ir
->lhs
->type
->is_vector() ||
2300 ir
->lhs
->type
->is_scalar());
2301 dst
.writemask
= ir
->write_mask
;
2303 /* Swizzle a small RHS vector into the channels being written.
2305 * glsl ir treats write_mask as dictating how many channels are
2306 * present on the RHS while in our instructions we need to make
2307 * those channels appear in the slots of the vec4 they're written to.
2309 for (int i
= 0; i
< 4; i
++)
2310 swizzles
[i
] = (ir
->write_mask
& (1 << i
) ? src_chan
++ : 0);
2312 src_reg src
= swizzle(this->result
,
2313 BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2314 swizzles
[2], swizzles
[3]));
2316 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2320 if (ir
->condition
) {
2321 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2324 for (i
= 0; i
< type_size_vec4(ir
->lhs
->type
); i
++) {
2325 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2326 inst
->predicate
= predicate
;
2334 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2336 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2337 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2338 emit_constant_values(dst
, field_value
);
2343 if (ir
->type
->is_array()) {
2344 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2345 emit_constant_values(dst
, ir
->array_elements
[i
]);
2350 if (ir
->type
->is_matrix()) {
2351 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2352 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2354 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2355 dst
->writemask
= 1 << j
;
2356 dst
->type
= BRW_REGISTER_TYPE_F
;
2358 emit(MOV(*dst
, src_reg(vec
[j
])));
2365 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2367 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2368 if (!(remaining_writemask
& (1 << i
)))
2371 dst
->writemask
= 1 << i
;
2372 dst
->type
= brw_type_for_base_type(ir
->type
);
2374 /* Find other components that match the one we're about to
2375 * write. Emits fewer instructions for things like vec4(0.5,
2378 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2379 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2380 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2381 dst
->writemask
|= (1 << j
);
2383 /* u, i, and f storage all line up, so no need for a
2384 * switch case for comparing each type.
2386 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2387 dst
->writemask
|= (1 << j
);
2391 switch (ir
->type
->base_type
) {
2392 case GLSL_TYPE_FLOAT
:
2393 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2396 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2398 case GLSL_TYPE_UINT
:
2399 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2401 case GLSL_TYPE_BOOL
:
2402 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
] != 0 ? ~0 : 0)));
2405 unreachable("Non-float/uint/int/bool constant");
2408 remaining_writemask
&= ~dst
->writemask
;
2414 vec4_visitor::visit(ir_constant
*ir
)
2416 dst_reg dst
= dst_reg(this, ir
->type
);
2417 this->result
= src_reg(dst
);
2419 emit_constant_values(&dst
, ir
);
2423 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2425 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2426 ir
->actual_parameters
.get_head());
2427 ir_variable
*location
= deref
->variable_referenced();
2428 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2429 location
->data
.binding
);
2431 /* Calculate the surface offset */
2432 src_reg
offset(this, glsl_type::uint_type
);
2433 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2435 deref_array
->array_index
->accept(this);
2437 src_reg
tmp(this, glsl_type::uint_type
);
2438 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2439 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2441 offset
= location
->data
.atomic
.offset
;
2444 /* Emit the appropriate machine instruction */
2445 const char *callee
= ir
->callee
->function_name();
2446 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2448 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2449 emit_untyped_surface_read(surf_index
, dst
, offset
);
2451 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2452 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2453 src_reg(), src_reg());
2455 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2456 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2457 src_reg(), src_reg());
2460 brw_mark_surface_used(stage_prog_data
, surf_index
);
2464 vec4_visitor::visit(ir_call
*ir
)
2466 const char *callee
= ir
->callee
->function_name();
2468 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2469 !strcmp("__intrinsic_atomic_increment", callee
) ||
2470 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2471 visit_atomic_counter_intrinsic(ir
);
2473 unreachable("Unsupported intrinsic.");
2478 vec4_visitor::emit_mcs_fetch(const glsl_type
*coordinate_type
,
2479 src_reg coordinate
, src_reg sampler
)
2481 vec4_instruction
*inst
=
2482 new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
,
2483 dst_reg(this, glsl_type::uvec4_type
));
2485 inst
->src
[1] = sampler
;
2489 if (devinfo
->gen
>= 9) {
2490 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
2491 vec4_instruction
*header_inst
= new(mem_ctx
)
2492 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
2493 dst_reg(MRF
, inst
->base_mrf
));
2498 inst
->header_size
= 1;
2499 param_base
= inst
->base_mrf
+ 1;
2502 param_base
= inst
->base_mrf
;
2505 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2506 int coord_mask
= (1 << coordinate_type
->vector_elements
) - 1;
2507 int zero_mask
= 0xf & ~coord_mask
;
2509 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, coord_mask
),
2512 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, zero_mask
),
2516 return src_reg(inst
->dst
);
2520 vec4_visitor::is_high_sampler(src_reg sampler
)
2522 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
2525 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2529 vec4_visitor::emit_texture(ir_texture_opcode op
,
2531 const glsl_type
*dest_type
,
2533 int coord_components
,
2534 src_reg shadow_comparitor
,
2535 src_reg lod
, src_reg lod2
,
2536 src_reg sample_index
,
2537 uint32_t constant_offset
,
2538 src_reg offset_value
,
2542 src_reg sampler_reg
)
2546 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2547 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2548 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2549 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2550 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2551 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2552 case ir_tg4
: opcode
= offset_value
.file
!= BAD_FILE
2553 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2554 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2555 case ir_texture_samples
: opcode
= SHADER_OPCODE_SAMPLEINFO
; break;
2557 unreachable("TXB is not valid for vertex shaders.");
2559 unreachable("LOD is not valid for vertex shaders.");
2561 unreachable("Unrecognized tex op");
2564 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(
2565 opcode
, dst_reg(this, dest_type
));
2567 inst
->offset
= constant_offset
;
2569 /* The message header is necessary for:
2571 * - Gen9+ for selecting SIMD4x2
2573 * - Gather channel selection
2574 * - Sampler indices too large to fit in a 4-bit value.
2575 * - Sampleinfo message - takes no parameters, but mlen = 0 is illegal
2578 (devinfo
->gen
< 5 || devinfo
->gen
>= 9 ||
2579 inst
->offset
!= 0 || op
== ir_tg4
||
2580 op
== ir_texture_samples
||
2581 is_high_sampler(sampler_reg
)) ? 1 : 0;
2583 inst
->mlen
= inst
->header_size
;
2584 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2585 inst
->shadow_compare
= shadow_comparitor
.file
!= BAD_FILE
;
2587 inst
->src
[1] = sampler_reg
;
2589 /* MRF for the first parameter */
2590 int param_base
= inst
->base_mrf
+ inst
->header_size
;
2592 if (op
== ir_txs
|| op
== ir_query_levels
) {
2593 int writemask
= devinfo
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2594 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, writemask
), lod
));
2596 } else if (op
== ir_texture_samples
) {
2597 inst
->dst
.writemask
= WRITEMASK_X
;
2599 /* Load the coordinate */
2600 /* FINISHME: gl_clamp_mask and saturate */
2601 int coord_mask
= (1 << coord_components
) - 1;
2602 int zero_mask
= 0xf & ~coord_mask
;
2604 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, coord_mask
),
2608 if (zero_mask
!= 0) {
2609 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, zero_mask
),
2612 /* Load the shadow comparitor */
2613 if (shadow_comparitor
.file
!= BAD_FILE
&& op
!= ir_txd
&& (op
!= ir_tg4
|| offset_value
.file
== BAD_FILE
)) {
2614 emit(MOV(dst_reg(MRF
, param_base
+ 1, shadow_comparitor
.type
,
2616 shadow_comparitor
));
2620 /* Load the LOD info */
2621 if (op
== ir_tex
|| op
== ir_txl
) {
2623 if (devinfo
->gen
>= 5) {
2624 mrf
= param_base
+ 1;
2625 if (shadow_comparitor
.file
!= BAD_FILE
) {
2626 writemask
= WRITEMASK_Y
;
2627 /* mlen already incremented */
2629 writemask
= WRITEMASK_X
;
2632 } else /* devinfo->gen == 4 */ {
2634 writemask
= WRITEMASK_W
;
2636 emit(MOV(dst_reg(MRF
, mrf
, lod
.type
, writemask
), lod
));
2637 } else if (op
== ir_txf
) {
2638 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, WRITEMASK_W
), lod
));
2639 } else if (op
== ir_txf_ms
) {
2640 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index
.type
, WRITEMASK_X
),
2642 if (devinfo
->gen
>= 7) {
2643 /* MCS data is in the first channel of `mcs`, but we need to get it into
2644 * the .y channel of the second vec4 of params, so replicate .x across
2645 * the whole vec4 and then mask off everything except .y
2647 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2648 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2652 } else if (op
== ir_txd
) {
2653 const brw_reg_type type
= lod
.type
;
2655 if (devinfo
->gen
>= 5) {
2656 lod
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2657 lod2
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2658 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), lod
));
2659 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), lod2
));
2662 if (dest_type
->vector_elements
== 3 || shadow_comparitor
.file
!= BAD_FILE
) {
2663 lod
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2664 lod2
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2665 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), lod
));
2666 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), lod2
));
2669 if (shadow_comparitor
.file
!= BAD_FILE
) {
2670 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2671 shadow_comparitor
.type
, WRITEMASK_Z
),
2672 shadow_comparitor
));
2675 } else /* devinfo->gen == 4 */ {
2676 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), lod
));
2677 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), lod2
));
2680 } else if (op
== ir_tg4
&& offset_value
.file
!= BAD_FILE
) {
2681 if (shadow_comparitor
.file
!= BAD_FILE
) {
2682 emit(MOV(dst_reg(MRF
, param_base
, shadow_comparitor
.type
, WRITEMASK_W
),
2683 shadow_comparitor
));
2686 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2694 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2695 * spec requires layers.
2697 if (op
== ir_txs
&& is_cube_array
) {
2698 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2699 writemask(inst
->dst
, WRITEMASK_Z
),
2700 src_reg(inst
->dst
), src_reg(6));
2703 if (devinfo
->gen
== 6 && op
== ir_tg4
) {
2704 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], inst
->dst
);
2707 swizzle_result(op
, dest
,
2708 src_reg(inst
->dst
), sampler
, dest_type
);
2712 vec4_visitor::visit(ir_texture
*ir
)
2715 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2717 ir_rvalue
*nonconst_sampler_index
=
2718 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2720 /* Handle non-constant sampler array indexing */
2721 src_reg sampler_reg
;
2722 if (nonconst_sampler_index
) {
2723 /* The highest sampler which may be used by this operation is
2724 * the last element of the array. Mark it here, because the generator
2725 * doesn't have enough information to determine the bound.
2727 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2728 ->array
->type
->array_size();
2730 uint32_t max_used
= sampler
+ array_size
- 1;
2731 if (ir
->op
== ir_tg4
&& devinfo
->gen
< 8) {
2732 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2734 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2737 brw_mark_surface_used(&prog_data
->base
, max_used
);
2739 /* Emit code to evaluate the actual indexing expression */
2740 nonconst_sampler_index
->accept(this);
2741 src_reg
temp(this, glsl_type::uint_type
);
2742 emit(ADD(dst_reg(temp
), this->result
, src_reg(sampler
)));
2743 sampler_reg
= emit_uniformize(temp
);
2745 /* Single sampler, or constant array index; the indexing expression
2746 * is just an immediate.
2748 sampler_reg
= src_reg(sampler
);
2751 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2752 * emitting anything other than setting up the constant result.
2754 if (ir
->op
== ir_tg4
) {
2755 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2756 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], chan
->value
.i
[0]);
2757 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2758 dst_reg
result(this, ir
->type
);
2759 this->result
= src_reg(result
);
2760 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2765 /* Should be lowered by do_lower_texture_projection */
2766 assert(!ir
->projector
);
2768 /* Should be lowered */
2769 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2771 /* Generate code to compute all the subexpression trees. This has to be
2772 * done before loading any values into MRFs for the sampler message since
2773 * generating these values may involve SEND messages that need the MRFs.
2776 int coord_components
= 0;
2777 if (ir
->coordinate
) {
2778 coord_components
= ir
->coordinate
->type
->vector_elements
;
2779 ir
->coordinate
->accept(this);
2780 coordinate
= this->result
;
2783 src_reg shadow_comparitor
;
2784 if (ir
->shadow_comparitor
) {
2785 ir
->shadow_comparitor
->accept(this);
2786 shadow_comparitor
= this->result
;
2789 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2790 src_reg offset_value
;
2791 if (has_nonconstant_offset
) {
2792 ir
->offset
->accept(this);
2793 offset_value
= src_reg(this->result
);
2796 src_reg lod
, lod2
, sample_index
, mcs
;
2799 lod
= src_reg(0.0f
);
2804 ir
->lod_info
.lod
->accept(this);
2807 case ir_query_levels
:
2811 ir
->lod_info
.sample_index
->accept(this);
2812 sample_index
= this->result
;
2814 if (devinfo
->gen
>= 7 && key_tex
->compressed_multisample_layout_mask
& (1 << sampler
))
2815 mcs
= emit_mcs_fetch(ir
->coordinate
->type
, coordinate
, sampler_reg
);
2820 ir
->lod_info
.grad
.dPdx
->accept(this);
2823 ir
->lod_info
.grad
.dPdy
->accept(this);
2824 lod2
= this->result
;
2829 case ir_texture_samples
:
2833 uint32_t constant_offset
= 0;
2834 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2836 brw_texture_offset(ir
->offset
->as_constant()->value
.i
,
2837 ir
->offset
->type
->vector_elements
);
2840 /* Stuff the channel select bits in the top of the texture offset */
2841 if (ir
->op
== ir_tg4
)
2843 gather_channel( ir
->lod_info
.component
->as_constant()->value
.i
[0],
2846 glsl_type
const *type
= ir
->sampler
->type
;
2847 bool is_cube_array
= type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2848 type
->sampler_array
;
2850 this->result
= src_reg(this, ir
->type
);
2851 dst_reg dest
= dst_reg(this->result
);
2853 emit_texture(ir
->op
, dest
, ir
->type
, coordinate
, coord_components
,
2855 lod
, lod2
, sample_index
,
2856 constant_offset
, offset_value
,
2857 mcs
, is_cube_array
, sampler
, sampler_reg
);
2861 * Apply workarounds for Gen6 gather with UINT/SINT
2864 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2869 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2870 dst_reg dst_f
= dst
;
2871 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2873 /* Convert from UNORM to UINT */
2874 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2875 emit(MOV(dst
, src_reg(dst_f
)));
2878 /* Reinterpret the UINT value as a signed INT value by
2879 * shifting the sign bit into place, then shifting back
2882 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2883 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2888 * Set up the gather channel based on the swizzle, for gather4.
2891 vec4_visitor::gather_channel(unsigned gather_component
, uint32_t sampler
)
2893 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
2895 case SWIZZLE_X
: return 0;
2897 /* gather4 sampler is broken for green channel on RG32F --
2898 * we must ask for blue instead.
2900 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
2903 case SWIZZLE_Z
: return 2;
2904 case SWIZZLE_W
: return 3;
2906 unreachable("Not reached"); /* zero, one swizzles handled already */
2911 vec4_visitor::swizzle_result(ir_texture_opcode op
, dst_reg dest
,
2912 src_reg orig_val
, uint32_t sampler
,
2913 const glsl_type
*dest_type
)
2915 int s
= key_tex
->swizzles
[sampler
];
2917 dst_reg swizzled_result
= dest
;
2919 if (op
== ir_query_levels
) {
2920 /* # levels is in .w */
2921 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2922 emit(MOV(swizzled_result
, orig_val
));
2926 if (op
== ir_txs
|| dest_type
== glsl_type::float_type
2927 || s
== SWIZZLE_NOOP
|| op
== ir_tg4
) {
2928 emit(MOV(swizzled_result
, orig_val
));
2933 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2934 int swizzle
[4] = {0};
2936 for (int i
= 0; i
< 4; i
++) {
2937 switch (GET_SWZ(s
, i
)) {
2939 zero_mask
|= (1 << i
);
2942 one_mask
|= (1 << i
);
2945 copy_mask
|= (1 << i
);
2946 swizzle
[i
] = GET_SWZ(s
, i
);
2952 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2953 swizzled_result
.writemask
= copy_mask
;
2954 emit(MOV(swizzled_result
, orig_val
));
2958 swizzled_result
.writemask
= zero_mask
;
2959 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2963 swizzled_result
.writemask
= one_mask
;
2964 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2969 vec4_visitor::visit(ir_return
*)
2971 unreachable("not reached");
2975 vec4_visitor::visit(ir_discard
*)
2977 unreachable("not reached");
2981 vec4_visitor::visit(ir_if
*ir
)
2983 /* Don't point the annotation at the if statement, because then it plus
2984 * the then and else blocks get printed.
2986 this->base_ir
= ir
->condition
;
2988 if (devinfo
->gen
== 6) {
2991 enum brw_predicate predicate
;
2992 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2993 emit(IF(predicate
));
2996 visit_instructions(&ir
->then_instructions
);
2998 if (!ir
->else_instructions
.is_empty()) {
2999 this->base_ir
= ir
->condition
;
3000 emit(BRW_OPCODE_ELSE
);
3002 visit_instructions(&ir
->else_instructions
);
3005 this->base_ir
= ir
->condition
;
3006 emit(BRW_OPCODE_ENDIF
);
3010 vec4_visitor::gs_emit_vertex(int stream_id
)
3012 unreachable("not reached");
3016 vec4_visitor::visit(ir_emit_vertex
*)
3018 unreachable("not reached");
3022 vec4_visitor::gs_end_primitive()
3024 unreachable("not reached");
3029 vec4_visitor::visit(ir_end_primitive
*)
3031 unreachable("not reached");
3035 vec4_visitor::visit(ir_barrier
*)
3037 unreachable("not reached");
3041 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
3042 dst_reg dst
, src_reg offset
,
3043 src_reg src0
, src_reg src1
)
3047 /* Set the atomic operation offset. */
3048 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
3051 /* Set the atomic operation arguments. */
3052 if (src0
.file
!= BAD_FILE
) {
3053 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
3057 if (src1
.file
!= BAD_FILE
) {
3058 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
3062 /* Emit the instruction. Note that this maps to the normal SIMD8
3063 * untyped atomic message on Ivy Bridge, but that's OK because
3064 * unused channels will be masked out.
3066 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
3068 src_reg(surf_index
), src_reg(atomic_op
));
3073 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
3076 /* Set the surface read offset. */
3077 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
3079 /* Emit the instruction. Note that this maps to the normal SIMD8
3080 * untyped surface read message, but that's OK because unused
3081 * channels will be masked out.
3083 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
,
3085 src_reg(surf_index
), src_reg(1));
3090 vec4_visitor::emit_ndc_computation()
3092 /* Get the position */
3093 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
3095 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
3096 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
3097 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
3099 current_annotation
= "NDC";
3100 dst_reg ndc_w
= ndc
;
3101 ndc_w
.writemask
= WRITEMASK_W
;
3102 src_reg pos_w
= pos
;
3103 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
3104 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
3106 dst_reg ndc_xyz
= ndc
;
3107 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
3109 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
3113 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
3115 if (devinfo
->gen
< 6 &&
3116 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
3117 output_reg
[VARYING_SLOT_CLIP_DIST0
].file
!= BAD_FILE
||
3118 devinfo
->has_negative_rhw_bug
)) {
3119 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
3120 dst_reg header1_w
= header1
;
3121 header1_w
.writemask
= WRITEMASK_W
;
3123 emit(MOV(header1
, 0u));
3125 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3126 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
3128 current_annotation
= "Point size";
3129 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
3130 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
3133 if (output_reg
[VARYING_SLOT_CLIP_DIST0
].file
!= BAD_FILE
) {
3134 current_annotation
= "Clipping flags";
3135 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
3136 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
3138 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3139 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
3140 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
3142 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
3143 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
3144 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
3145 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
3148 /* i965 clipping workaround:
3149 * 1) Test for -ve rhw
3151 * set ndc = (0,0,0,0)
3154 * Later, clipping will detect ucp[6] and ensure the primitive is
3155 * clipped against all fixed planes.
3157 if (devinfo
->has_negative_rhw_bug
) {
3158 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
3159 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
3160 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
3161 vec4_instruction
*inst
;
3162 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
3163 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3164 output_reg
[BRW_VARYING_SLOT_NDC
].type
= BRW_REGISTER_TYPE_F
;
3165 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
3166 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3169 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
3170 } else if (devinfo
->gen
< 6) {
3171 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
3173 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
3174 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3175 dst_reg reg_w
= reg
;
3176 reg_w
.writemask
= WRITEMASK_W
;
3177 src_reg reg_as_src
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
3178 reg_as_src
.type
= reg_w
.type
;
3179 reg_as_src
.swizzle
= brw_swizzle_for_size(1);
3180 emit(MOV(reg_w
, reg_as_src
));
3182 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
3183 dst_reg reg_y
= reg
;
3184 reg_y
.writemask
= WRITEMASK_Y
;
3185 reg_y
.type
= BRW_REGISTER_TYPE_D
;
3186 output_reg
[VARYING_SLOT_LAYER
].type
= reg_y
.type
;
3187 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
3189 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
3190 dst_reg reg_z
= reg
;
3191 reg_z
.writemask
= WRITEMASK_Z
;
3192 reg_z
.type
= BRW_REGISTER_TYPE_D
;
3193 output_reg
[VARYING_SLOT_VIEWPORT
].type
= reg_z
.type
;
3194 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
3200 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
3202 assert(varying
< VARYING_SLOT_MAX
);
3203 assert(output_reg
[varying
].type
== reg
.type
);
3204 current_annotation
= output_reg_annotation
[varying
];
3205 /* Copy the register, saturating if necessary */
3206 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
3210 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
3212 reg
.type
= BRW_REGISTER_TYPE_F
;
3213 output_reg
[varying
].type
= reg
.type
;
3216 case VARYING_SLOT_PSIZ
:
3218 /* PSIZ is always in slot 0, and is coupled with other flags. */
3219 current_annotation
= "indices, point width, clip flags";
3220 emit_psiz_and_flags(reg
);
3223 case BRW_VARYING_SLOT_NDC
:
3224 current_annotation
= "NDC";
3225 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
3227 case VARYING_SLOT_POS
:
3228 current_annotation
= "gl_Position";
3229 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
3231 case VARYING_SLOT_EDGE
:
3232 /* This is present when doing unfilled polygons. We're supposed to copy
3233 * the edge flag from the user-provided vertex array
3234 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3235 * of that attribute (starts as 1.0f). This is then used in clipping to
3236 * determine which edges should be drawn as wireframe.
3238 current_annotation
= "edge flag";
3239 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3240 glsl_type::float_type
, WRITEMASK_XYZW
))));
3242 case BRW_VARYING_SLOT_PAD
:
3243 /* No need to write to this slot */
3246 emit_generic_urb_slot(reg
, varying
);
3252 align_interleaved_urb_mlen(const struct brw_device_info
*devinfo
, int mlen
)
3254 if (devinfo
->gen
>= 6) {
3255 /* URB data written (does not include the message header reg) must
3256 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3257 * section 5.4.3.2.2: URB_INTERLEAVED.
3259 * URB entries are allocated on a multiple of 1024 bits, so an
3260 * extra 128 bits written here to make the end align to 256 is
3263 if ((mlen
% 2) != 1)
3272 * Generates the VUE payload plus the necessary URB write instructions to
3275 * The VUE layout is documented in Volume 2a.
3278 vec4_visitor::emit_vertex()
3280 /* MRF 0 is reserved for the debugger, so start with message header
3285 /* In the process of generating our URB write message contents, we
3286 * may need to unspill a register or load from an array. Those
3287 * reads would use MRFs 14-15.
3289 int max_usable_mrf
= FIRST_SPILL_MRF(devinfo
->gen
);
3291 /* The following assertion verifies that max_usable_mrf causes an
3292 * even-numbered amount of URB write data, which will meet gen6's
3293 * requirements for length alignment.
3295 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3297 /* First mrf is the g0-based message header containing URB handles and
3300 emit_urb_write_header(mrf
++);
3302 if (devinfo
->gen
< 6) {
3303 emit_ndc_computation();
3306 /* We may need to split this up into several URB writes, so do them in a
3310 bool complete
= false;
3312 /* URB offset is in URB row increments, and each of our MRFs is half of
3313 * one of those, since we're doing interleaved writes.
3315 int offset
= slot
/ 2;
3318 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3319 emit_urb_slot(dst_reg(MRF
, mrf
++),
3320 prog_data
->vue_map
.slot_to_varying
[slot
]);
3322 /* If this was max_usable_mrf, we can't fit anything more into this
3323 * URB WRITE. Same thing if we reached the maximum length available.
3325 if (mrf
> max_usable_mrf
||
3326 align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
+ 1) > BRW_MAX_MSG_LENGTH
) {
3332 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3333 current_annotation
= "URB write";
3334 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3335 inst
->base_mrf
= base_mrf
;
3336 inst
->mlen
= align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
);
3337 inst
->offset
+= offset
;
3343 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3344 src_reg
*reladdr
, int reg_offset
)
3346 /* Because we store the values to scratch interleaved like our
3347 * vertex data, we need to scale the vec4 index by 2.
3349 int message_header_scale
= 2;
3351 /* Pre-gen6, the message header uses byte offsets instead of vec4
3352 * (16-byte) offset units.
3354 if (devinfo
->gen
< 6)
3355 message_header_scale
*= 16;
3358 src_reg index
= src_reg(this, glsl_type::int_type
);
3360 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3361 src_reg(reg_offset
)));
3362 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3363 src_reg(message_header_scale
)));
3367 return src_reg(reg_offset
* message_header_scale
);
3372 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3373 src_reg
*reladdr
, int reg_offset
)
3376 src_reg index
= src_reg(this, glsl_type::int_type
);
3378 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3379 src_reg(reg_offset
)));
3381 /* Pre-gen6, the message header uses byte offsets instead of vec4
3382 * (16-byte) offset units.
3384 if (devinfo
->gen
< 6) {
3385 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3389 } else if (devinfo
->gen
>= 8) {
3390 /* Store the offset in a GRF so we can send-from-GRF. */
3391 src_reg offset
= src_reg(this, glsl_type::int_type
);
3392 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3395 int message_header_scale
= devinfo
->gen
< 6 ? 16 : 1;
3396 return src_reg(reg_offset
* message_header_scale
);
3401 * Emits an instruction before @inst to load the value named by @orig_src
3402 * from scratch space at @base_offset to @temp.
3404 * @base_offset is measured in 32-byte units (the size of a register).
3407 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3408 dst_reg temp
, src_reg orig_src
,
3411 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3412 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3415 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3419 * Emits an instruction after @inst to store the value to be written
3420 * to @orig_dst to scratch space at @base_offset, from @temp.
3422 * @base_offset is measured in 32-byte units (the size of a register).
3425 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3428 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3429 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3432 /* Create a temporary register to store *inst's result in.
3434 * We have to be careful in MOVing from our temporary result register in
3435 * the scratch write. If we swizzle from channels of the temporary that
3436 * weren't initialized, it will confuse live interval analysis, which will
3437 * make spilling fail to make progress.
3439 const src_reg temp
= swizzle(retype(src_reg(this, glsl_type::vec4_type
),
3441 brw_swizzle_for_mask(inst
->dst
.writemask
));
3442 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3443 inst
->dst
.writemask
));
3444 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3445 if (inst
->opcode
!= BRW_OPCODE_SEL
)
3446 write
->predicate
= inst
->predicate
;
3447 write
->ir
= inst
->ir
;
3448 write
->annotation
= inst
->annotation
;
3449 inst
->insert_after(block
, write
);
3451 inst
->dst
.file
= temp
.file
;
3452 inst
->dst
.reg
= temp
.reg
;
3453 inst
->dst
.reg_offset
= temp
.reg_offset
;
3454 inst
->dst
.reladdr
= NULL
;
3458 * Checks if \p src and/or \p src.reladdr require a scratch read, and if so,
3459 * adds the scratch read(s) before \p inst. The function also checks for
3460 * recursive reladdr scratch accesses, issuing the corresponding scratch
3461 * loads and rewriting reladdr references accordingly.
3463 * \return \p src if it did not require a scratch load, otherwise, the
3464 * register holding the result of the scratch load that the caller should
3465 * use to rewrite src.
3468 vec4_visitor::emit_resolve_reladdr(int scratch_loc
[], bblock_t
*block
,
3469 vec4_instruction
*inst
, src_reg src
)
3471 /* Resolve recursive reladdr scratch access by calling ourselves
3475 *src
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3478 /* Now handle scratch access on src */
3479 if (src
.file
== GRF
&& scratch_loc
[src
.reg
] != -1) {
3480 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3481 emit_scratch_read(block
, inst
, temp
, src
, scratch_loc
[src
.reg
]);
3483 src
.reg_offset
= temp
.reg_offset
;
3491 * We can't generally support array access in GRF space, because a
3492 * single instruction's destination can only span 2 contiguous
3493 * registers. So, we send all GRF arrays that get variable index
3494 * access to scratch space.
3497 vec4_visitor::move_grf_array_access_to_scratch()
3499 int scratch_loc
[this->alloc
.count
];
3500 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3502 /* First, calculate the set of virtual GRFs that need to be punted
3503 * to scratch due to having any array access on them, and where in
3506 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3507 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
) {
3508 if (scratch_loc
[inst
->dst
.reg
] == -1) {
3509 scratch_loc
[inst
->dst
.reg
] = last_scratch
;
3510 last_scratch
+= this->alloc
.sizes
[inst
->dst
.reg
];
3513 for (src_reg
*iter
= inst
->dst
.reladdr
;
3515 iter
= iter
->reladdr
) {
3516 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3517 scratch_loc
[iter
->reg
] = last_scratch
;
3518 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3523 for (int i
= 0 ; i
< 3; i
++) {
3524 for (src_reg
*iter
= &inst
->src
[i
];
3526 iter
= iter
->reladdr
) {
3527 if (iter
->file
== GRF
&& scratch_loc
[iter
->reg
] == -1) {
3528 scratch_loc
[iter
->reg
] = last_scratch
;
3529 last_scratch
+= this->alloc
.sizes
[iter
->reg
];
3535 /* Now, for anything that will be accessed through scratch, rewrite
3536 * it to load/store. Note that this is a _safe list walk, because
3537 * we may generate a new scratch_write instruction after the one
3540 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3541 /* Set up the annotation tracking for new generated instructions. */
3543 current_annotation
= inst
->annotation
;
3545 /* First handle scratch access on the dst. Notice we have to handle
3546 * the case where the dst's reladdr also points to scratch space.
3548 if (inst
->dst
.reladdr
)
3549 *inst
->dst
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
3550 *inst
->dst
.reladdr
);
3552 /* Now that we have handled any (possibly recursive) reladdr scratch
3553 * accesses for dst we can safely do the scratch write for dst itself
3555 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1)
3556 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3558 /* Now handle scratch access on any src. In this case, since inst->src[i]
3559 * already is a src_reg, we can just call emit_resolve_reladdr with
3560 * inst->src[i] and it will take care of handling scratch loads for
3561 * both src and src.reladdr (recursively).
3563 for (int i
= 0 ; i
< 3; i
++) {
3564 inst
->src
[i
] = emit_resolve_reladdr(scratch_loc
, block
, inst
,
3571 * Emits an instruction before @inst to load the value named by @orig_src
3572 * from the pull constant buffer (surface) at @base_offset to @temp.
3575 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3576 dst_reg temp
, src_reg orig_src
,
3579 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3580 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3581 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3584 emit_pull_constant_load_reg(temp
,
3591 * Implements array access of uniforms by inserting a
3592 * PULL_CONSTANT_LOAD instruction.
3594 * Unlike temporary GRF array access (where we don't support it due to
3595 * the difficulty of doing relative addressing on instruction
3596 * destinations), we could potentially do array access of uniforms
3597 * that were loaded in GRF space as push constants. In real-world
3598 * usage we've seen, though, the arrays being used are always larger
3599 * than we could load as push constants, so just always move all
3600 * uniform array access out to a pull constant buffer.
3603 vec4_visitor::move_uniform_array_access_to_pull_constants()
3605 int pull_constant_loc
[this->uniforms
];
3606 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3607 bool nested_reladdr
;
3609 /* Walk through and find array access of uniforms. Put a copy of that
3610 * uniform in the pull constant buffer.
3612 * Note that we don't move constant-indexed accesses to arrays. No
3613 * testing has been done of the performance impact of this choice.
3616 nested_reladdr
= false;
3618 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3619 for (int i
= 0 ; i
< 3; i
++) {
3620 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3623 int uniform
= inst
->src
[i
].reg
;
3625 if (inst
->src
[i
].reladdr
->reladdr
)
3626 nested_reladdr
= true; /* will need another pass */
3628 /* If this array isn't already present in the pull constant buffer,
3631 if (pull_constant_loc
[uniform
] == -1) {
3632 const gl_constant_value
**values
=
3633 &stage_prog_data
->param
[uniform
* 4];
3635 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3637 assert(uniform
< uniform_array_size
);
3638 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3639 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3644 /* Set up the annotation tracking for new generated instructions. */
3646 current_annotation
= inst
->annotation
;
3648 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3650 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3651 pull_constant_loc
[uniform
]);
3653 inst
->src
[i
].file
= temp
.file
;
3654 inst
->src
[i
].reg
= temp
.reg
;
3655 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3656 inst
->src
[i
].reladdr
= NULL
;
3659 } while (nested_reladdr
);
3661 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3662 * no need to track them as larger-than-vec4 objects. This will be
3663 * relied on in cutting out unused uniform vectors from push
3666 split_uniform_registers();
3670 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3672 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3676 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3677 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3682 * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
3684 * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
3685 * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
3688 vec4_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, src_reg
*reg
)
3690 assert(devinfo
->gen
<= 5);
3692 if (!rvalue
->type
->is_boolean())
3695 src_reg and_result
= src_reg(this, rvalue
->type
);
3696 src_reg neg_result
= src_reg(this, rvalue
->type
);
3697 emit(AND(dst_reg(and_result
), *reg
, src_reg(1)));
3698 emit(MOV(dst_reg(neg_result
), negate(and_result
)));
3702 vec4_visitor::vec4_visitor(const struct brw_compiler
*compiler
,
3704 struct gl_program
*prog
,
3705 const struct brw_sampler_prog_key_data
*key_tex
,
3706 struct brw_vue_prog_data
*prog_data
,
3707 struct gl_shader_program
*shader_prog
,
3708 gl_shader_stage stage
,
3711 int shader_time_index
)
3712 : backend_shader(compiler
, log_data
, mem_ctx
,
3713 shader_prog
, prog
, &prog_data
->base
, stage
),
3715 prog_data(prog_data
),
3716 sanity_param_count(0),
3718 first_non_payload_grf(0),
3719 need_all_constants_in_pull_buffer(false),
3720 no_spills(no_spills
),
3721 shader_time_index(shader_time_index
),
3724 this->failed
= false;
3726 this->base_ir
= NULL
;
3727 this->current_annotation
= NULL
;
3728 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3730 this->variable_ht
= hash_table_ctor(0,
3731 hash_table_pointer_hash
,
3732 hash_table_pointer_compare
);
3734 this->virtual_grf_start
= NULL
;
3735 this->virtual_grf_end
= NULL
;
3736 this->live_intervals
= NULL
;
3738 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3742 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3743 * at least one. See setup_uniforms() in brw_vec4.cpp.
3745 this->uniform_array_size
= 1;
3747 this->uniform_array_size
=
3748 MAX2(DIV_ROUND_UP(stage_prog_data
->nr_params
, 4), 1);
3751 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3752 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3755 vec4_visitor::~vec4_visitor()
3757 hash_table_dtor(this->variable_ht
);
3762 vec4_visitor::fail(const char *format
, ...)
3772 va_start(va
, format
);
3773 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3775 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
3777 this->fail_msg
= msg
;
3779 if (debug_enabled
) {
3780 fprintf(stderr
, "%s", msg
);
3784 } /* namespace brw */