2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
32 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
33 enum opcode opcode
, const dst_reg
&dst
,
34 const src_reg
&src0
, const src_reg
&src1
,
37 this->opcode
= opcode
;
42 this->saturate
= false;
43 this->force_writemask_all
= false;
44 this->no_dd_clear
= false;
45 this->no_dd_check
= false;
46 this->writes_accumulator
= false;
47 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
48 this->texture_offset
= 0;
50 this->shadow_compare
= false;
51 this->ir
= v
->base_ir
;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_present
= false;
57 this->annotation
= v
->current_annotation
;
61 vec4_visitor::emit(vec4_instruction
*inst
)
63 this->instructions
.push_tail(inst
);
69 vec4_visitor::emit_before(vec4_instruction
*inst
, vec4_instruction
*new_inst
)
71 new_inst
->ir
= inst
->ir
;
72 new_inst
->annotation
= inst
->annotation
;
74 inst
->insert_before(new_inst
);
80 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
,
81 src_reg src0
, src_reg src1
, src_reg src2
)
83 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
89 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
)
91 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
95 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
, src_reg src0
)
97 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
101 vec4_visitor::emit(enum opcode opcode
, dst_reg dst
)
103 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
));
107 vec4_visitor::emit(enum opcode opcode
)
109 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
114 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
116 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
122 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
123 const src_reg &src1) \
125 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
129 #define ALU2_ACC(op) \
131 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
132 const src_reg &src1) \
134 vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, \
135 BRW_OPCODE_##op, dst, src0, src1); \
136 inst->writes_accumulator = true; \
142 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
143 const src_reg &src1, const src_reg &src2) \
145 assert(brw->gen >= 6); \
146 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
183 /** Gen4 predicated IF. */
185 vec4_visitor::IF(enum brw_predicate predicate
)
187 vec4_instruction
*inst
;
189 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
190 inst
->predicate
= predicate
;
195 /** Gen6 IF with embedded comparison. */
197 vec4_visitor::IF(src_reg src0
, src_reg src1
,
198 enum brw_conditional_mod condition
)
200 assert(brw
->gen
== 6);
202 vec4_instruction
*inst
;
204 resolve_ud_negate(&src0
);
205 resolve_ud_negate(&src1
);
207 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
209 inst
->conditional_mod
= condition
;
215 * CMP: Sets the low bit of the destination channels with the result
216 * of the comparison, while the upper bits are undefined, and updates
217 * the flag register with the packed 16 bits of the result.
220 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
221 enum brw_conditional_mod condition
)
223 vec4_instruction
*inst
;
225 /* original gen4 does type conversion to the destination type
226 * before before comparison, producing garbage results for floating
230 dst
.type
= src0
.type
;
231 if (dst
.file
== HW_REG
)
232 dst
.fixed_hw_reg
.type
= dst
.type
;
235 resolve_ud_negate(&src0
);
236 resolve_ud_negate(&src1
);
238 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
239 inst
->conditional_mod
= condition
;
245 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
247 vec4_instruction
*inst
;
249 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_READ
,
258 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
259 const src_reg
&index
)
261 vec4_instruction
*inst
;
263 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
272 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
274 static enum opcode dot_opcodes
[] = {
275 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
278 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
282 vec4_visitor::fix_3src_operand(src_reg src
)
284 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
285 * able to use vertical stride of zero to replicate the vec4 uniform, like
287 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
289 * But you can't, since vertical stride is always four in three-source
290 * instructions. Instead, insert a MOV instruction to do the replication so
291 * that the three-source instruction can consume it.
294 /* The MOV is only needed if the source is a uniform or immediate. */
295 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
298 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
301 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
302 expanded
.type
= src
.type
;
303 emit(MOV(expanded
, src
));
304 return src_reg(expanded
);
308 vec4_visitor::fix_math_operand(src_reg src
)
310 /* The gen6 math instruction ignores the source modifiers --
311 * swizzle, abs, negate, and at least some parts of the register
312 * region description.
314 * Rather than trying to enumerate all these cases, *always* expand the
315 * operand to a temp GRF for gen6.
317 * For gen7, keep the operand as-is, except if immediate, which gen7 still
321 if (brw
->gen
== 7 && src
.file
!= IMM
)
324 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
325 expanded
.type
= src
.type
;
326 emit(MOV(expanded
, src
));
327 return src_reg(expanded
);
331 vec4_visitor::emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
)
333 src
= fix_math_operand(src
);
335 if (brw
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
336 /* The gen6 math instruction must be align1, so we can't do
339 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
341 emit(opcode
, temp_dst
, src
);
343 emit(MOV(dst
, src_reg(temp_dst
)));
345 emit(opcode
, dst
, src
);
350 vec4_visitor::emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
)
352 vec4_instruction
*inst
= emit(opcode
, dst
, src
);
358 vec4_visitor::emit_math(opcode opcode
, dst_reg dst
, src_reg src
)
361 case SHADER_OPCODE_RCP
:
362 case SHADER_OPCODE_RSQ
:
363 case SHADER_OPCODE_SQRT
:
364 case SHADER_OPCODE_EXP2
:
365 case SHADER_OPCODE_LOG2
:
366 case SHADER_OPCODE_SIN
:
367 case SHADER_OPCODE_COS
:
370 unreachable("not reached: bad math opcode");
374 emit(opcode
, dst
, src
);
375 } else if (brw
->gen
>= 6) {
376 emit_math1_gen6(opcode
, dst
, src
);
378 emit_math1_gen4(opcode
, dst
, src
);
383 vec4_visitor::emit_math2_gen6(enum opcode opcode
,
384 dst_reg dst
, src_reg src0
, src_reg src1
)
386 src0
= fix_math_operand(src0
);
387 src1
= fix_math_operand(src1
);
389 if (brw
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
390 /* The gen6 math instruction must be align1, so we can't do
393 dst_reg temp_dst
= dst_reg(this, glsl_type::vec4_type
);
394 temp_dst
.type
= dst
.type
;
396 emit(opcode
, temp_dst
, src0
, src1
);
398 emit(MOV(dst
, src_reg(temp_dst
)));
400 emit(opcode
, dst
, src0
, src1
);
405 vec4_visitor::emit_math2_gen4(enum opcode opcode
,
406 dst_reg dst
, src_reg src0
, src_reg src1
)
408 vec4_instruction
*inst
= emit(opcode
, dst
, src0
, src1
);
414 vec4_visitor::emit_math(enum opcode opcode
,
415 dst_reg dst
, src_reg src0
, src_reg src1
)
418 case SHADER_OPCODE_POW
:
419 case SHADER_OPCODE_INT_QUOTIENT
:
420 case SHADER_OPCODE_INT_REMAINDER
:
423 unreachable("not reached: unsupported binary math opcode");
427 emit(opcode
, dst
, src0
, src1
);
428 } else if (brw
->gen
>= 6) {
429 emit_math2_gen6(opcode
, dst
, src0
, src1
);
431 emit_math2_gen4(opcode
, dst
, src0
, src1
);
436 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
439 unreachable("ir_unop_pack_half_2x16 should be lowered");
442 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
443 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
445 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
447 * Because this instruction does not have a 16-bit floating-point type,
448 * the destination data type must be Word (W).
450 * The destination must be DWord-aligned and specify a horizontal stride
451 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
452 * each destination channel and the upper word is not modified.
454 * The above restriction implies that the f32to16 instruction must use
455 * align1 mode, because only in align1 mode is it possible to specify
456 * horizontal stride. We choose here to defy the hardware docs and emit
457 * align16 instructions.
459 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
460 * instructions. I was partially successful in that the code passed all
461 * tests. However, the code was dubiously correct and fragile, and the
462 * tests were not harsh enough to probe that frailty. Not trusting the
463 * code, I chose instead to remain in align16 mode in defiance of the hw
466 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
467 * simulator, emitting a f32to16 in align16 mode with UD as destination
468 * data type is safe. The behavior differs from that specified in the PRM
469 * in that the upper word of each destination channel is cleared to 0.
472 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
473 src_reg
tmp_src(tmp_dst
);
476 /* Verify the undocumented behavior on which the following instructions
477 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
478 * then the result of the bit-or instruction below will be incorrect.
480 * You should inspect the disasm output in order to verify that the MOV is
481 * not optimized away.
483 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
486 /* Give tmp the form below, where "." means untouched.
489 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
491 * That the upper word of each write-channel be 0 is required for the
492 * following bit-shift and bit-or instructions to work. Note that this
493 * relies on the undocumented hardware behavior mentioned above.
495 tmp_dst
.writemask
= WRITEMASK_XY
;
496 emit(F32TO16(tmp_dst
, src0
));
498 /* Give the write-channels of dst the form:
501 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
502 emit(SHL(dst
, tmp_src
, src_reg(16u)));
504 /* Finally, give the write-channels of dst the form of packHalf2x16's
508 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
509 emit(OR(dst
, src_reg(dst
), tmp_src
));
513 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
516 unreachable("ir_unop_unpack_half_2x16 should be lowered");
519 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
520 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
522 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
524 * Because this instruction does not have a 16-bit floating-point type,
525 * the source data type must be Word (W). The destination type must be
528 * To use W as the source data type, we must adjust horizontal strides,
529 * which is only possible in align1 mode. All my [chadv] attempts at
530 * emitting align1 instructions for unpackHalf2x16 failed to pass the
531 * Piglit tests, so I gave up.
533 * I've verified that, on gen7 hardware and the simulator, it is safe to
534 * emit f16to32 in align16 mode with UD as source data type.
537 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
538 src_reg
tmp_src(tmp_dst
);
540 tmp_dst
.writemask
= WRITEMASK_X
;
541 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
543 tmp_dst
.writemask
= WRITEMASK_Y
;
544 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
546 dst
.writemask
= WRITEMASK_XY
;
547 emit(F16TO32(dst
, tmp_src
));
551 vec4_visitor::visit_instructions(const exec_list
*list
)
553 foreach_in_list(ir_instruction
, ir
, list
) {
561 type_size(const struct glsl_type
*type
)
566 switch (type
->base_type
) {
569 case GLSL_TYPE_FLOAT
:
571 if (type
->is_matrix()) {
572 return type
->matrix_columns
;
574 /* Regardless of size of vector, it gets a vec4. This is bad
575 * packing for things like floats, but otherwise arrays become a
576 * mess. Hopefully a later pass over the code can pack scalars
577 * down if appropriate.
581 case GLSL_TYPE_ARRAY
:
582 assert(type
->length
> 0);
583 return type_size(type
->fields
.array
) * type
->length
;
584 case GLSL_TYPE_STRUCT
:
586 for (i
= 0; i
< type
->length
; i
++) {
587 size
+= type_size(type
->fields
.structure
[i
].type
);
590 case GLSL_TYPE_SAMPLER
:
591 /* Samplers take up one slot in UNIFORMS[], but they're baked in
595 case GLSL_TYPE_ATOMIC_UINT
:
597 case GLSL_TYPE_IMAGE
:
599 case GLSL_TYPE_ERROR
:
600 case GLSL_TYPE_INTERFACE
:
601 unreachable("not reached");
608 vec4_visitor::virtual_grf_alloc(int size
)
610 if (virtual_grf_array_size
<= virtual_grf_count
) {
611 if (virtual_grf_array_size
== 0)
612 virtual_grf_array_size
= 16;
614 virtual_grf_array_size
*= 2;
615 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
616 virtual_grf_array_size
);
617 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
618 virtual_grf_array_size
);
620 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
621 virtual_grf_reg_count
+= size
;
622 virtual_grf_sizes
[virtual_grf_count
] = size
;
623 return virtual_grf_count
++;
626 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
631 this->reg
= v
->virtual_grf_alloc(type_size(type
));
633 if (type
->is_array() || type
->is_record()) {
634 this->swizzle
= BRW_SWIZZLE_NOOP
;
636 this->swizzle
= swizzle_for_size(type
->vector_elements
);
639 this->type
= brw_type_for_base_type(type
);
642 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
647 this->reg
= v
->virtual_grf_alloc(type_size(type
));
649 if (type
->is_array() || type
->is_record()) {
650 this->writemask
= WRITEMASK_XYZW
;
652 this->writemask
= (1 << type
->vector_elements
) - 1;
655 this->type
= brw_type_for_base_type(type
);
658 /* Our support for uniforms is piggy-backed on the struct
659 * gl_fragment_program, because that's where the values actually
660 * get stored, rather than in some global gl_shader_program uniform
664 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
666 int namelen
= strlen(ir
->name
);
668 /* The data for our (non-builtin) uniforms is stored in a series of
669 * gl_uniform_driver_storage structs for each subcomponent that
670 * glGetUniformLocation() could name. We know it's been set up in the same
671 * order we'd walk the type, so walk the list of storage and find anything
672 * with our name, or the prefix of a component that starts with our name.
674 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
675 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
677 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
678 (storage
->name
[namelen
] != 0 &&
679 storage
->name
[namelen
] != '.' &&
680 storage
->name
[namelen
] != '[')) {
684 gl_constant_value
*components
= storage
->storage
;
685 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
686 storage
->type
->matrix_columns
);
688 for (unsigned s
= 0; s
< vector_count
; s
++) {
689 assert(uniforms
< uniform_array_size
);
690 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
693 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
694 stage_prog_data
->param
[uniforms
* 4 + i
] = components
;
698 static gl_constant_value zero
= { 0.0 };
699 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
708 vec4_visitor::setup_uniform_clipplane_values()
710 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
712 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
713 assert(this->uniforms
< uniform_array_size
);
714 this->uniform_vector_size
[this->uniforms
] = 4;
715 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
716 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
717 for (int j
= 0; j
< 4; ++j
) {
718 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
719 (gl_constant_value
*) &clip_planes
[i
][j
];
725 /* Our support for builtin uniforms is even scarier than non-builtin.
726 * It sits on top of the PROG_STATE_VAR parameters that are
727 * automatically updated from GL context state.
730 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
732 const ir_state_slot
*const slots
= ir
->state_slots
;
733 assert(ir
->state_slots
!= NULL
);
735 for (unsigned int i
= 0; i
< ir
->num_state_slots
; i
++) {
736 /* This state reference has already been setup by ir_to_mesa,
737 * but we'll get the same index back here. We can reference
738 * ParameterValues directly, since unlike brw_fs.cpp, we never
739 * add new state references during compile.
741 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
742 (gl_state_index
*)slots
[i
].tokens
);
743 gl_constant_value
*values
=
744 &this->prog
->Parameters
->ParameterValues
[index
][0];
746 assert(this->uniforms
< uniform_array_size
);
747 this->uniform_vector_size
[this->uniforms
] = 0;
748 /* Add each of the unique swizzled channels of the element.
749 * This will end up matching the size of the glsl_type of this field.
752 for (unsigned int j
= 0; j
< 4; j
++) {
753 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
756 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
757 assert(this->uniforms
< uniform_array_size
);
758 if (swiz
<= last_swiz
)
759 this->uniform_vector_size
[this->uniforms
]++;
766 vec4_visitor::variable_storage(ir_variable
*var
)
768 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
772 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
773 enum brw_predicate
*predicate
)
775 ir_expression
*expr
= ir
->as_expression();
777 *predicate
= BRW_PREDICATE_NORMAL
;
781 vec4_instruction
*inst
;
783 assert(expr
->get_num_operands() <= 2);
784 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
785 expr
->operands
[i
]->accept(this);
786 op
[i
] = this->result
;
788 resolve_ud_negate(&op
[i
]);
791 switch (expr
->operation
) {
792 case ir_unop_logic_not
:
793 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
794 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
797 case ir_binop_logic_xor
:
798 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
799 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
802 case ir_binop_logic_or
:
803 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
804 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
807 case ir_binop_logic_and
:
808 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
809 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
814 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
816 inst
= emit(MOV(dst_null_f(), op
[0]));
817 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
823 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
825 inst
= emit(MOV(dst_null_d(), op
[0]));
826 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
830 case ir_binop_all_equal
:
831 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
832 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
835 case ir_binop_any_nequal
:
836 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
837 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
841 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
842 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
845 case ir_binop_greater
:
846 case ir_binop_gequal
:
848 case ir_binop_lequal
:
850 case ir_binop_nequal
:
851 emit(CMP(dst_null_d(), op
[0], op
[1],
852 brw_conditional_for_comparison(expr
->operation
)));
856 unreachable("not reached");
863 resolve_ud_negate(&this->result
);
866 vec4_instruction
*inst
= emit(AND(dst_null_d(),
867 this->result
, src_reg(1)));
868 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
870 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
871 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
876 * Emit a gen6 IF statement with the comparison folded into the IF
880 vec4_visitor::emit_if_gen6(ir_if
*ir
)
882 ir_expression
*expr
= ir
->condition
->as_expression();
888 assert(expr
->get_num_operands() <= 2);
889 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
890 expr
->operands
[i
]->accept(this);
891 op
[i
] = this->result
;
894 switch (expr
->operation
) {
895 case ir_unop_logic_not
:
896 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
899 case ir_binop_logic_xor
:
900 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
903 case ir_binop_logic_or
:
904 temp
= dst_reg(this, glsl_type::bool_type
);
905 emit(OR(temp
, op
[0], op
[1]));
906 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
909 case ir_binop_logic_and
:
910 temp
= dst_reg(this, glsl_type::bool_type
);
911 emit(AND(temp
, op
[0], op
[1]));
912 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
916 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
920 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
923 case ir_binop_greater
:
924 case ir_binop_gequal
:
926 case ir_binop_lequal
:
928 case ir_binop_nequal
:
929 emit(IF(op
[0], op
[1],
930 brw_conditional_for_comparison(expr
->operation
)));
933 case ir_binop_all_equal
:
934 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
935 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
938 case ir_binop_any_nequal
:
939 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
940 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
944 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
945 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
949 unreachable("not reached");
954 ir
->condition
->accept(this);
956 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
960 vec4_visitor::visit(ir_variable
*ir
)
964 if (variable_storage(ir
))
967 switch (ir
->data
.mode
) {
968 case ir_var_shader_in
:
969 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
972 case ir_var_shader_out
:
973 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
975 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
976 output_reg
[ir
->data
.location
+ i
] = *reg
;
977 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
978 output_reg
[ir
->data
.location
+ i
].type
=
979 brw_type_for_base_type(ir
->type
->get_scalar_type());
980 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
985 case ir_var_temporary
:
986 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
990 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
992 /* Thanks to the lower_ubo_reference pass, we will see only
993 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
994 * variables, so no need for them to be in variable_ht.
996 * Atomic counters take no uniform storage, no need to do
999 if (ir
->is_in_uniform_block() || ir
->type
->contains_atomic())
1002 /* Track how big the whole uniform variable is, in case we need to put a
1003 * copy of its data into pull constants for array access.
1005 assert(this->uniforms
< uniform_array_size
);
1006 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1008 if (!strncmp(ir
->name
, "gl_", 3)) {
1009 setup_builtin_uniform_values(ir
);
1011 setup_uniform_values(ir
);
1015 case ir_var_system_value
:
1016 reg
= make_reg_for_system_value(ir
);
1020 unreachable("not reached");
1023 reg
->type
= brw_type_for_base_type(ir
->type
);
1024 hash_table_insert(this->variable_ht
, reg
, ir
);
1028 vec4_visitor::visit(ir_loop
*ir
)
1030 /* We don't want debugging output to print the whole body of the
1031 * loop as the annotation.
1033 this->base_ir
= NULL
;
1035 emit(BRW_OPCODE_DO
);
1037 visit_instructions(&ir
->body_instructions
);
1039 emit(BRW_OPCODE_WHILE
);
1043 vec4_visitor::visit(ir_loop_jump
*ir
)
1046 case ir_loop_jump::jump_break
:
1047 emit(BRW_OPCODE_BREAK
);
1049 case ir_loop_jump::jump_continue
:
1050 emit(BRW_OPCODE_CONTINUE
);
1057 vec4_visitor::visit(ir_function_signature
*)
1059 unreachable("not reached");
1063 vec4_visitor::visit(ir_function
*ir
)
1065 /* Ignore function bodies other than main() -- we shouldn't see calls to
1066 * them since they should all be inlined.
1068 if (strcmp(ir
->name
, "main") == 0) {
1069 const ir_function_signature
*sig
;
1072 sig
= ir
->matching_signature(NULL
, &empty
, false);
1076 visit_instructions(&sig
->body
);
1081 vec4_visitor::try_emit_sat(ir_expression
*ir
)
1083 ir_rvalue
*sat_src
= ir
->as_rvalue_to_saturate();
1087 sat_src
->accept(this);
1088 src_reg src
= this->result
;
1090 this->result
= src_reg(this, ir
->type
);
1091 vec4_instruction
*inst
;
1092 inst
= emit(MOV(dst_reg(this->result
), src
));
1093 inst
->saturate
= true;
1099 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1101 /* 3-src instructions were introduced in gen6. */
1105 /* MAD can only handle floating-point data. */
1106 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1109 ir_rvalue
*nonmul
= ir
->operands
[1];
1110 ir_expression
*mul
= ir
->operands
[0]->as_expression();
1112 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
1113 nonmul
= ir
->operands
[0];
1114 mul
= ir
->operands
[1]->as_expression();
1116 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1120 nonmul
->accept(this);
1121 src_reg src0
= fix_3src_operand(this->result
);
1123 mul
->operands
[0]->accept(this);
1124 src_reg src1
= fix_3src_operand(this->result
);
1126 mul
->operands
[1]->accept(this);
1127 src_reg src2
= fix_3src_operand(this->result
);
1129 this->result
= src_reg(this, ir
->type
);
1130 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1136 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1138 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1143 switch (cmp
->operation
) {
1145 case ir_binop_greater
:
1146 case ir_binop_lequal
:
1147 case ir_binop_gequal
:
1148 case ir_binop_equal
:
1149 case ir_binop_nequal
:
1156 cmp
->operands
[0]->accept(this);
1157 const src_reg cmp_src0
= this->result
;
1159 cmp
->operands
[1]->accept(this);
1160 const src_reg cmp_src1
= this->result
;
1162 this->result
= src_reg(this, ir
->type
);
1164 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1165 brw_conditional_for_comparison(cmp
->operation
)));
1167 /* If the comparison is false, this->result will just happen to be zero.
1169 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1170 this->result
, src_reg(1.0f
));
1171 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1172 inst
->predicate_inverse
= true;
1178 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1179 src_reg src0
, src_reg src1
)
1181 vec4_instruction
*inst
;
1183 if (brw
->gen
>= 6) {
1184 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1185 inst
->conditional_mod
= conditionalmod
;
1187 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1189 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1190 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1195 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1196 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1198 if (brw
->gen
>= 6) {
1199 /* Note that the instruction's argument order is reversed from GLSL
1203 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1205 /* Earlier generations don't support three source operations, so we
1206 * need to emit x*(1-a) + y*a.
1208 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1209 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1210 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1211 y_times_a
.writemask
= dst
.writemask
;
1212 one_minus_a
.writemask
= dst
.writemask
;
1213 x_times_one_minus_a
.writemask
= dst
.writemask
;
1215 emit(MUL(y_times_a
, y
, a
));
1216 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1217 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1218 emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1223 vec4_visitor::visit(ir_expression
*ir
)
1225 unsigned int operand
;
1226 src_reg op
[Elements(ir
->operands
)];
1229 vec4_instruction
*inst
;
1231 if (try_emit_sat(ir
))
1234 if (ir
->operation
== ir_binop_add
) {
1235 if (try_emit_mad(ir
))
1239 if (ir
->operation
== ir_unop_b2f
) {
1240 if (try_emit_b2f_of_compare(ir
))
1244 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1245 this->result
.file
= BAD_FILE
;
1246 ir
->operands
[operand
]->accept(this);
1247 if (this->result
.file
== BAD_FILE
) {
1248 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1249 ir
->operands
[operand
]->fprint(stderr
);
1252 op
[operand
] = this->result
;
1254 /* Matrix expression operands should have been broken down to vector
1255 * operations already.
1257 assert(!ir
->operands
[operand
]->type
->is_matrix());
1260 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1261 if (ir
->operands
[1]) {
1262 vector_elements
= MAX2(vector_elements
,
1263 ir
->operands
[1]->type
->vector_elements
);
1266 this->result
.file
= BAD_FILE
;
1268 /* Storage for our result. Ideally for an assignment we'd be using
1269 * the actual storage for the result here, instead.
1271 result_src
= src_reg(this, ir
->type
);
1272 /* convenience for the emit functions below. */
1273 result_dst
= dst_reg(result_src
);
1274 /* If nothing special happens, this is the result. */
1275 this->result
= result_src
;
1276 /* Limit writes to the channels that will be used by result_src later.
1277 * This does limit this temp's use as a temporary for multi-instruction
1280 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1282 switch (ir
->operation
) {
1283 case ir_unop_logic_not
:
1284 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
1285 * ones complement of the whole register, not just bit 0.
1287 emit(XOR(result_dst
, op
[0], src_reg(1)));
1290 op
[0].negate
= !op
[0].negate
;
1291 emit(MOV(result_dst
, op
[0]));
1295 op
[0].negate
= false;
1296 emit(MOV(result_dst
, op
[0]));
1300 if (ir
->type
->is_float()) {
1301 /* AND(val, 0x80000000) gives the sign bit.
1303 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1306 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1308 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1309 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1310 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1312 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1313 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1315 this->result
.type
= BRW_REGISTER_TYPE_F
;
1317 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1318 * -> non-negative val generates 0x00000000.
1319 * Predicated OR sets 1 if val is positive.
1321 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1323 emit(ASR(result_dst
, op
[0], src_reg(31)));
1325 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1326 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1331 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1335 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1338 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1342 unreachable("not reached: should be handled by ir_explog_to_explog2");
1344 case ir_unop_sin_reduced
:
1345 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1348 case ir_unop_cos_reduced
:
1349 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1353 case ir_unop_dFdx_coarse
:
1354 case ir_unop_dFdx_fine
:
1356 case ir_unop_dFdy_coarse
:
1357 case ir_unop_dFdy_fine
:
1358 unreachable("derivatives not valid in vertex shader");
1360 case ir_unop_bitfield_reverse
:
1361 emit(BFREV(result_dst
, op
[0]));
1363 case ir_unop_bit_count
:
1364 emit(CBIT(result_dst
, op
[0]));
1366 case ir_unop_find_msb
: {
1367 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1369 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1370 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1372 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1373 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1374 * subtract the result from 31 to convert the MSB count into an LSB count.
1377 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1378 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1379 emit(MOV(result_dst
, temp
));
1381 src_reg src_tmp
= src_reg(result_dst
);
1382 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1384 src_tmp
.negate
= true;
1385 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1386 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1389 case ir_unop_find_lsb
:
1390 emit(FBL(result_dst
, op
[0]));
1394 unreachable("not reached: should be handled by lower_noise");
1397 emit(ADD(result_dst
, op
[0], op
[1]));
1400 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1403 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
1404 /* For integer multiplication, the MUL uses the low 16 bits of one of
1405 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1406 * accumulates in the contribution of the upper 16 bits of that
1407 * operand. If we can determine that one of the args is in the low
1408 * 16 bits, though, we can just emit a single MUL.
1410 if (ir
->operands
[0]->is_uint16_constant()) {
1412 emit(MUL(result_dst
, op
[0], op
[1]));
1414 emit(MUL(result_dst
, op
[1], op
[0]));
1415 } else if (ir
->operands
[1]->is_uint16_constant()) {
1417 emit(MUL(result_dst
, op
[1], op
[0]));
1419 emit(MUL(result_dst
, op
[0], op
[1]));
1421 struct brw_reg acc
= retype(brw_acc_reg(), result_dst
.type
);
1423 emit(MUL(acc
, op
[0], op
[1]));
1424 emit(MACH(dst_null_d(), op
[0], op
[1]));
1425 emit(MOV(result_dst
, src_reg(acc
)));
1428 emit(MUL(result_dst
, op
[0], op
[1]));
1431 case ir_binop_imul_high
: {
1432 struct brw_reg acc
= retype(brw_acc_reg(), result_dst
.type
);
1434 emit(MUL(acc
, op
[0], op
[1]));
1435 emit(MACH(result_dst
, op
[0], op
[1]));
1439 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1440 assert(ir
->type
->is_integer());
1441 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1443 case ir_binop_carry
: {
1444 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
1446 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1447 emit(MOV(result_dst
, src_reg(acc
)));
1450 case ir_binop_borrow
: {
1451 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD
);
1453 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1454 emit(MOV(result_dst
, src_reg(acc
)));
1458 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1459 assert(ir
->type
->is_integer());
1460 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1464 case ir_binop_greater
:
1465 case ir_binop_lequal
:
1466 case ir_binop_gequal
:
1467 case ir_binop_equal
:
1468 case ir_binop_nequal
: {
1469 emit(CMP(result_dst
, op
[0], op
[1],
1470 brw_conditional_for_comparison(ir
->operation
)));
1471 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1475 case ir_binop_all_equal
:
1476 /* "==" operator producing a scalar boolean. */
1477 if (ir
->operands
[0]->type
->is_vector() ||
1478 ir
->operands
[1]->type
->is_vector()) {
1479 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1480 emit(MOV(result_dst
, src_reg(0)));
1481 inst
= emit(MOV(result_dst
, src_reg(1)));
1482 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1484 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1485 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1488 case ir_binop_any_nequal
:
1489 /* "!=" operator producing a scalar boolean. */
1490 if (ir
->operands
[0]->type
->is_vector() ||
1491 ir
->operands
[1]->type
->is_vector()) {
1492 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1494 emit(MOV(result_dst
, src_reg(0)));
1495 inst
= emit(MOV(result_dst
, src_reg(1)));
1496 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1498 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1499 emit(AND(result_dst
, result_src
, src_reg(0x1)));
1504 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1505 emit(MOV(result_dst
, src_reg(0)));
1507 inst
= emit(MOV(result_dst
, src_reg(1)));
1508 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1511 case ir_binop_logic_xor
:
1512 emit(XOR(result_dst
, op
[0], op
[1]));
1515 case ir_binop_logic_or
:
1516 emit(OR(result_dst
, op
[0], op
[1]));
1519 case ir_binop_logic_and
:
1520 emit(AND(result_dst
, op
[0], op
[1]));
1524 assert(ir
->operands
[0]->type
->is_vector());
1525 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1526 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1530 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1533 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1536 case ir_unop_bitcast_i2f
:
1537 case ir_unop_bitcast_u2f
:
1538 this->result
= op
[0];
1539 this->result
.type
= BRW_REGISTER_TYPE_F
;
1542 case ir_unop_bitcast_f2i
:
1543 this->result
= op
[0];
1544 this->result
.type
= BRW_REGISTER_TYPE_D
;
1547 case ir_unop_bitcast_f2u
:
1548 this->result
= op
[0];
1549 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1560 emit(MOV(result_dst
, op
[0]));
1564 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1565 emit(AND(result_dst
, result_src
, src_reg(1)));
1570 emit(RNDZ(result_dst
, op
[0]));
1573 op
[0].negate
= !op
[0].negate
;
1574 inst
= emit(RNDD(result_dst
, op
[0]));
1575 this->result
.negate
= true;
1578 inst
= emit(RNDD(result_dst
, op
[0]));
1581 inst
= emit(FRC(result_dst
, op
[0]));
1583 case ir_unop_round_even
:
1584 emit(RNDE(result_dst
, op
[0]));
1588 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1591 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1595 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1598 case ir_unop_bit_not
:
1599 inst
= emit(NOT(result_dst
, op
[0]));
1601 case ir_binop_bit_and
:
1602 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1604 case ir_binop_bit_xor
:
1605 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1607 case ir_binop_bit_or
:
1608 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1611 case ir_binop_lshift
:
1612 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1615 case ir_binop_rshift
:
1616 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1617 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1619 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1623 emit(BFI1(result_dst
, op
[0], op
[1]));
1626 case ir_binop_ubo_load
: {
1627 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1628 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1629 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1632 /* Now, load the vector from that offset. */
1633 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1635 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1636 packed_consts
.type
= result
.type
;
1639 if (const_uniform_block
) {
1640 /* The block index is a constant, so just emit the binding table entry
1643 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1644 const_uniform_block
->value
.u
[0]);
1646 /* The block index is not a constant. Evaluate the index expression
1647 * per-channel and add the base UBO index; the generator will select
1648 * a value from any live channel.
1650 surf_index
= src_reg(this, glsl_type::uint_type
);
1651 emit(ADD(dst_reg(surf_index
), op
[0],
1652 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1654 /* Assume this may touch any UBO. It would be nice to provide
1655 * a tighter bound, but the array information is already lowered away.
1657 brw_mark_surface_used(&prog_data
->base
,
1658 prog_data
->base
.binding_table
.ubo_start
+
1659 shader_prog
->NumUniformBlocks
- 1);
1662 if (const_offset_ir
) {
1663 if (brw
->gen
>= 8) {
1664 /* Store the offset in a GRF so we can send-from-GRF. */
1665 offset
= src_reg(this, glsl_type::int_type
);
1666 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1668 /* Immediates are fine on older generations since they'll be moved
1669 * to a (potentially fake) MRF at the generator level.
1671 offset
= src_reg(const_offset
/ 16);
1674 offset
= src_reg(this, glsl_type::uint_type
);
1675 emit(SHR(dst_reg(offset
), op
[1], src_reg(4)));
1678 if (brw
->gen
>= 7) {
1679 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1680 grf_offset
.type
= offset
.type
;
1682 emit(MOV(grf_offset
, offset
));
1684 emit(new(mem_ctx
) vec4_instruction(this,
1685 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1686 dst_reg(packed_consts
),
1688 src_reg(grf_offset
)));
1690 vec4_instruction
*pull
=
1691 emit(new(mem_ctx
) vec4_instruction(this,
1692 VS_OPCODE_PULL_CONSTANT_LOAD
,
1693 dst_reg(packed_consts
),
1696 pull
->base_mrf
= 14;
1700 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1701 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1702 const_offset
% 16 / 4,
1703 const_offset
% 16 / 4,
1704 const_offset
% 16 / 4);
1706 /* UBO bools are any nonzero int. We store bools as either 0 or 1. */
1707 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1708 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1709 BRW_CONDITIONAL_NZ
));
1710 emit(AND(result_dst
, result
, src_reg(0x1)));
1712 emit(MOV(result_dst
, packed_consts
));
1717 case ir_binop_vector_extract
:
1718 unreachable("should have been lowered by vec_index_to_cond_assign");
1721 op
[0] = fix_3src_operand(op
[0]);
1722 op
[1] = fix_3src_operand(op
[1]);
1723 op
[2] = fix_3src_operand(op
[2]);
1724 /* Note that the instruction's argument order is reversed from GLSL
1727 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1731 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1735 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1736 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1737 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1741 op
[0] = fix_3src_operand(op
[0]);
1742 op
[1] = fix_3src_operand(op
[1]);
1743 op
[2] = fix_3src_operand(op
[2]);
1744 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1747 case ir_triop_bitfield_extract
:
1748 op
[0] = fix_3src_operand(op
[0]);
1749 op
[1] = fix_3src_operand(op
[1]);
1750 op
[2] = fix_3src_operand(op
[2]);
1751 /* Note that the instruction's argument order is reversed from GLSL
1754 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1757 case ir_triop_vector_insert
:
1758 unreachable("should have been lowered by lower_vector_insert");
1760 case ir_quadop_bitfield_insert
:
1761 unreachable("not reached: should be handled by "
1762 "bitfield_insert_to_bfm_bfi\n");
1764 case ir_quadop_vector
:
1765 unreachable("not reached: should be handled by lower_quadop_vector");
1767 case ir_unop_pack_half_2x16
:
1768 emit_pack_half_2x16(result_dst
, op
[0]);
1770 case ir_unop_unpack_half_2x16
:
1771 emit_unpack_half_2x16(result_dst
, op
[0]);
1773 case ir_unop_pack_snorm_2x16
:
1774 case ir_unop_pack_snorm_4x8
:
1775 case ir_unop_pack_unorm_2x16
:
1776 case ir_unop_pack_unorm_4x8
:
1777 case ir_unop_unpack_snorm_2x16
:
1778 case ir_unop_unpack_snorm_4x8
:
1779 case ir_unop_unpack_unorm_2x16
:
1780 case ir_unop_unpack_unorm_4x8
:
1781 unreachable("not reached: should be handled by lower_packing_builtins");
1782 case ir_unop_unpack_half_2x16_split_x
:
1783 case ir_unop_unpack_half_2x16_split_y
:
1784 case ir_binop_pack_half_2x16_split
:
1785 case ir_unop_interpolate_at_centroid
:
1786 case ir_binop_interpolate_at_sample
:
1787 case ir_binop_interpolate_at_offset
:
1788 unreachable("not reached: should not occur in vertex shader");
1789 case ir_binop_ldexp
:
1790 unreachable("not reached: should be handled by ldexp_to_arith()");
1796 vec4_visitor::visit(ir_swizzle
*ir
)
1802 /* Note that this is only swizzles in expressions, not those on the left
1803 * hand side of an assignment, which do write masking. See ir_assignment
1807 ir
->val
->accept(this);
1809 assert(src
.file
!= BAD_FILE
);
1811 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1814 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1817 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1820 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1823 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1827 for (; i
< 4; i
++) {
1828 /* Replicate the last channel out. */
1829 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1832 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1838 vec4_visitor::visit(ir_dereference_variable
*ir
)
1840 const struct glsl_type
*type
= ir
->type
;
1841 dst_reg
*reg
= variable_storage(ir
->var
);
1844 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1845 this->result
= src_reg(brw_null_reg());
1849 this->result
= src_reg(*reg
);
1851 /* System values get their swizzle from the dst_reg writemask */
1852 if (ir
->var
->data
.mode
== ir_var_system_value
)
1855 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1856 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1861 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1863 /* Under normal circumstances array elements are stored consecutively, so
1864 * the stride is equal to the size of the array element.
1866 return type_size(ir
->type
);
1871 vec4_visitor::visit(ir_dereference_array
*ir
)
1873 ir_constant
*constant_index
;
1875 int array_stride
= compute_array_stride(ir
);
1877 constant_index
= ir
->array_index
->constant_expression_value();
1879 ir
->array
->accept(this);
1882 if (constant_index
) {
1883 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1885 /* Variable index array dereference. It eats the "vec4" of the
1886 * base of the array and an index that offsets the Mesa register
1889 ir
->array_index
->accept(this);
1893 if (array_stride
== 1) {
1894 index_reg
= this->result
;
1896 index_reg
= src_reg(this, glsl_type::int_type
);
1898 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1902 src_reg temp
= src_reg(this, glsl_type::int_type
);
1904 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1909 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1910 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1913 /* If the type is smaller than a vec4, replicate the last channel out. */
1914 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1915 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1917 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1918 src
.type
= brw_type_for_base_type(ir
->type
);
1924 vec4_visitor::visit(ir_dereference_record
*ir
)
1927 const glsl_type
*struct_type
= ir
->record
->type
;
1930 ir
->record
->accept(this);
1932 for (i
= 0; i
< struct_type
->length
; i
++) {
1933 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1935 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1938 /* If the type is smaller than a vec4, replicate the last channel out. */
1939 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1940 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1942 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1943 this->result
.type
= brw_type_for_base_type(ir
->type
);
1945 this->result
.reg_offset
+= offset
;
1949 * We want to be careful in assignment setup to hit the actual storage
1950 * instead of potentially using a temporary like we might with the
1951 * ir_dereference handler.
1954 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1956 /* The LHS must be a dereference. If the LHS is a variable indexed array
1957 * access of a vector, it must be separated into a series conditional moves
1958 * before reaching this point (see ir_vec_index_to_cond_assign).
1960 assert(ir
->as_dereference());
1961 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1963 assert(!deref_array
->array
->type
->is_vector());
1966 /* Use the rvalue deref handler for the most part. We'll ignore
1967 * swizzles in it and write swizzles using writemask, though.
1970 return dst_reg(v
->result
);
1974 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1975 const struct glsl_type
*type
,
1976 enum brw_predicate predicate
)
1978 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1979 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1980 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1985 if (type
->is_array()) {
1986 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1987 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1992 if (type
->is_matrix()) {
1993 const struct glsl_type
*vec_type
;
1995 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1996 type
->vector_elements
, 1);
1998 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1999 emit_block_move(dst
, src
, vec_type
, predicate
);
2004 assert(type
->is_scalar() || type
->is_vector());
2006 dst
->type
= brw_type_for_base_type(type
);
2007 src
->type
= dst
->type
;
2009 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2011 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
2013 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2014 inst
->predicate
= predicate
;
2021 /* If the RHS processing resulted in an instruction generating a
2022 * temporary value, and it would be easy to rewrite the instruction to
2023 * generate its result right into the LHS instead, do so. This ends
2024 * up reliably removing instructions where it can be tricky to do so
2025 * later without real UD chain information.
2028 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2031 vec4_instruction
*pre_rhs_inst
,
2032 vec4_instruction
*last_rhs_inst
)
2034 /* This could be supported, but it would take more smarts. */
2038 if (pre_rhs_inst
== last_rhs_inst
)
2039 return false; /* No instructions generated to work with. */
2041 /* Make sure the last instruction generated our source reg. */
2042 if (src
.file
!= GRF
||
2043 src
.file
!= last_rhs_inst
->dst
.file
||
2044 src
.reg
!= last_rhs_inst
->dst
.reg
||
2045 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2049 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2052 /* Check that that last instruction fully initialized the channels
2053 * we want to use, in the order we want to use them. We could
2054 * potentially reswizzle the operands of many instructions so that
2055 * we could handle out of order channels, but don't yet.
2058 for (unsigned i
= 0; i
< 4; i
++) {
2059 if (dst
.writemask
& (1 << i
)) {
2060 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2063 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2068 /* Success! Rewrite the instruction. */
2069 last_rhs_inst
->dst
.file
= dst
.file
;
2070 last_rhs_inst
->dst
.reg
= dst
.reg
;
2071 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2072 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2073 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2079 vec4_visitor::visit(ir_assignment
*ir
)
2081 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2082 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2084 if (!ir
->lhs
->type
->is_scalar() &&
2085 !ir
->lhs
->type
->is_vector()) {
2086 ir
->rhs
->accept(this);
2087 src_reg src
= this->result
;
2089 if (ir
->condition
) {
2090 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2093 /* emit_block_move doesn't account for swizzles in the source register.
2094 * This should be ok, since the source register is a structure or an
2095 * array, and those can't be swizzled. But double-check to be sure.
2097 assert(src
.swizzle
==
2098 (ir
->rhs
->type
->is_matrix()
2099 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2100 : BRW_SWIZZLE_NOOP
));
2102 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2106 /* Now we're down to just a scalar/vector with writemasks. */
2109 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2110 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2112 ir
->rhs
->accept(this);
2114 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2116 src_reg src
= this->result
;
2119 int first_enabled_chan
= 0;
2122 assert(ir
->lhs
->type
->is_vector() ||
2123 ir
->lhs
->type
->is_scalar());
2124 dst
.writemask
= ir
->write_mask
;
2126 for (int i
= 0; i
< 4; i
++) {
2127 if (dst
.writemask
& (1 << i
)) {
2128 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2133 /* Swizzle a small RHS vector into the channels being written.
2135 * glsl ir treats write_mask as dictating how many channels are
2136 * present on the RHS while in our instructions we need to make
2137 * those channels appear in the slots of the vec4 they're written to.
2139 for (int i
= 0; i
< 4; i
++) {
2140 if (dst
.writemask
& (1 << i
))
2141 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2143 swizzles
[i
] = first_enabled_chan
;
2145 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2146 swizzles
[2], swizzles
[3]);
2148 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2152 if (ir
->condition
) {
2153 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2156 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2157 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2158 inst
->predicate
= predicate
;
2166 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2168 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2169 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2170 emit_constant_values(dst
, field_value
);
2175 if (ir
->type
->is_array()) {
2176 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2177 emit_constant_values(dst
, ir
->array_elements
[i
]);
2182 if (ir
->type
->is_matrix()) {
2183 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2184 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2186 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2187 dst
->writemask
= 1 << j
;
2188 dst
->type
= BRW_REGISTER_TYPE_F
;
2190 emit(MOV(*dst
, src_reg(vec
[j
])));
2197 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2199 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2200 if (!(remaining_writemask
& (1 << i
)))
2203 dst
->writemask
= 1 << i
;
2204 dst
->type
= brw_type_for_base_type(ir
->type
);
2206 /* Find other components that match the one we're about to
2207 * write. Emits fewer instructions for things like vec4(0.5,
2210 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2211 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2212 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2213 dst
->writemask
|= (1 << j
);
2215 /* u, i, and f storage all line up, so no need for a
2216 * switch case for comparing each type.
2218 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2219 dst
->writemask
|= (1 << j
);
2223 switch (ir
->type
->base_type
) {
2224 case GLSL_TYPE_FLOAT
:
2225 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2228 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2230 case GLSL_TYPE_UINT
:
2231 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2233 case GLSL_TYPE_BOOL
:
2234 emit(MOV(*dst
, src_reg(ir
->value
.b
[i
])));
2237 unreachable("Non-float/uint/int/bool constant");
2240 remaining_writemask
&= ~dst
->writemask
;
2246 vec4_visitor::visit(ir_constant
*ir
)
2248 dst_reg dst
= dst_reg(this, ir
->type
);
2249 this->result
= src_reg(dst
);
2251 emit_constant_values(&dst
, ir
);
2255 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2257 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2258 ir
->actual_parameters
.get_head());
2259 ir_variable
*location
= deref
->variable_referenced();
2260 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2261 location
->data
.atomic
.buffer_index
);
2263 /* Calculate the surface offset */
2264 src_reg
offset(this, glsl_type::uint_type
);
2265 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2267 deref_array
->array_index
->accept(this);
2269 src_reg
tmp(this, glsl_type::uint_type
);
2270 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2271 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2273 offset
= location
->data
.atomic
.offset
;
2276 /* Emit the appropriate machine instruction */
2277 const char *callee
= ir
->callee
->function_name();
2278 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2280 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2281 emit_untyped_surface_read(surf_index
, dst
, offset
);
2283 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2284 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2285 src_reg(), src_reg());
2287 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2288 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2289 src_reg(), src_reg());
2294 vec4_visitor::visit(ir_call
*ir
)
2296 const char *callee
= ir
->callee
->function_name();
2298 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2299 !strcmp("__intrinsic_atomic_increment", callee
) ||
2300 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2301 visit_atomic_counter_intrinsic(ir
);
2303 unreachable("Unsupported intrinsic.");
2308 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, uint32_t sampler
)
2310 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_MCS
);
2313 inst
->dst
= dst_reg(this, glsl_type::uvec4_type
);
2314 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2316 inst
->src
[1] = src_reg(sampler
);
2318 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2319 int param_base
= inst
->base_mrf
;
2320 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2321 int zero_mask
= 0xf & ~coord_mask
;
2323 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2326 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2330 return src_reg(inst
->dst
);
2334 vec4_visitor::visit(ir_texture
*ir
)
2337 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2339 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2340 * emitting anything other than setting up the constant result.
2342 if (ir
->op
== ir_tg4
) {
2343 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2344 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2345 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2346 dst_reg
result(this, ir
->type
);
2347 this->result
= src_reg(result
);
2348 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2353 /* Should be lowered by do_lower_texture_projection */
2354 assert(!ir
->projector
);
2356 /* Should be lowered */
2357 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2359 /* Generate code to compute all the subexpression trees. This has to be
2360 * done before loading any values into MRFs for the sampler message since
2361 * generating these values may involve SEND messages that need the MRFs.
2364 if (ir
->coordinate
) {
2365 ir
->coordinate
->accept(this);
2366 coordinate
= this->result
;
2369 src_reg shadow_comparitor
;
2370 if (ir
->shadow_comparitor
) {
2371 ir
->shadow_comparitor
->accept(this);
2372 shadow_comparitor
= this->result
;
2375 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2376 src_reg offset_value
;
2377 if (has_nonconstant_offset
) {
2378 ir
->offset
->accept(this);
2379 offset_value
= src_reg(this->result
);
2382 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2383 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2386 lod
= src_reg(0.0f
);
2387 lod_type
= glsl_type::float_type
;
2392 ir
->lod_info
.lod
->accept(this);
2394 lod_type
= ir
->lod_info
.lod
->type
;
2396 case ir_query_levels
:
2398 lod_type
= glsl_type::int_type
;
2401 ir
->lod_info
.sample_index
->accept(this);
2402 sample_index
= this->result
;
2403 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2405 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2406 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler
);
2411 ir
->lod_info
.grad
.dPdx
->accept(this);
2412 dPdx
= this->result
;
2414 ir
->lod_info
.grad
.dPdy
->accept(this);
2415 dPdy
= this->result
;
2417 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2427 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2428 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2429 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2430 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2431 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2432 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2433 case ir_tg4
: opcode
= has_nonconstant_offset
2434 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2435 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2437 unreachable("TXB is not valid for vertex shaders.");
2439 unreachable("LOD is not valid for vertex shaders.");
2441 unreachable("Unrecognized tex op");
2444 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, opcode
);
2446 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
2447 inst
->texture_offset
= brw_texture_offset(ctx
, ir
->offset
->as_constant());
2449 /* Stuff the channel select bits in the top of the texture offset */
2450 if (ir
->op
== ir_tg4
)
2451 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16;
2453 /* The message header is necessary for:
2456 * - Gather channel selection
2457 * - Sampler indices too large to fit in a 4-bit value.
2459 inst
->header_present
=
2460 brw
->gen
< 5 || inst
->texture_offset
!= 0 || ir
->op
== ir_tg4
||
2463 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2464 inst
->dst
= dst_reg(this, ir
->type
);
2465 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2466 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2468 inst
->src
[1] = src_reg(sampler
);
2470 /* MRF for the first parameter */
2471 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2473 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2474 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2475 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2477 /* Load the coordinate */
2478 /* FINISHME: gl_clamp_mask and saturate */
2479 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2480 int zero_mask
= 0xf & ~coord_mask
;
2482 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2485 if (zero_mask
!= 0) {
2486 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2489 /* Load the shadow comparitor */
2490 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2491 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2493 shadow_comparitor
));
2497 /* Load the LOD info */
2498 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2500 if (brw
->gen
>= 5) {
2501 mrf
= param_base
+ 1;
2502 if (ir
->shadow_comparitor
) {
2503 writemask
= WRITEMASK_Y
;
2504 /* mlen already incremented */
2506 writemask
= WRITEMASK_X
;
2509 } else /* brw->gen == 4 */ {
2511 writemask
= WRITEMASK_W
;
2513 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2514 } else if (ir
->op
== ir_txf
) {
2515 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2516 } else if (ir
->op
== ir_txf_ms
) {
2517 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2520 /* MCS data is in the first channel of `mcs`, but we need to get it into
2521 * the .y channel of the second vec4 of params, so replicate .x across
2522 * the whole vec4 and then mask off everything except .y
2524 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2525 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2528 } else if (ir
->op
== ir_txd
) {
2529 const glsl_type
*type
= lod_type
;
2531 if (brw
->gen
>= 5) {
2532 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2533 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2534 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2535 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2538 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2539 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2540 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2541 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2542 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2545 if (ir
->shadow_comparitor
) {
2546 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2547 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2548 shadow_comparitor
));
2551 } else /* brw->gen == 4 */ {
2552 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2553 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2556 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2557 if (ir
->shadow_comparitor
) {
2558 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2559 shadow_comparitor
));
2562 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2570 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2571 * spec requires layers.
2573 if (ir
->op
== ir_txs
) {
2574 glsl_type
const *type
= ir
->sampler
->type
;
2575 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2576 type
->sampler_array
) {
2577 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2578 writemask(inst
->dst
, WRITEMASK_Z
),
2579 src_reg(inst
->dst
), src_reg(6));
2583 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2584 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2587 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2591 * Apply workarounds for Gen6 gather with UINT/SINT
2594 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2599 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2600 dst_reg dst_f
= dst
;
2601 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2603 /* Convert from UNORM to UINT */
2604 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2605 emit(MOV(dst
, src_reg(dst_f
)));
2608 /* Reinterpret the UINT value as a signed INT value by
2609 * shifting the sign bit into place, then shifting back
2612 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2613 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2618 * Set up the gather channel based on the swizzle, for gather4.
2621 vec4_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2623 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2624 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2626 case SWIZZLE_X
: return 0;
2628 /* gather4 sampler is broken for green channel on RG32F --
2629 * we must ask for blue instead.
2631 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2634 case SWIZZLE_Z
: return 2;
2635 case SWIZZLE_W
: return 3;
2637 unreachable("Not reached"); /* zero, one swizzles handled already */
2642 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
)
2644 int s
= key
->tex
.swizzles
[sampler
];
2646 this->result
= src_reg(this, ir
->type
);
2647 dst_reg
swizzled_result(this->result
);
2649 if (ir
->op
== ir_query_levels
) {
2650 /* # levels is in .w */
2651 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2652 emit(MOV(swizzled_result
, orig_val
));
2656 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2657 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2658 emit(MOV(swizzled_result
, orig_val
));
2663 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2664 int swizzle
[4] = {0};
2666 for (int i
= 0; i
< 4; i
++) {
2667 switch (GET_SWZ(s
, i
)) {
2669 zero_mask
|= (1 << i
);
2672 one_mask
|= (1 << i
);
2675 copy_mask
|= (1 << i
);
2676 swizzle
[i
] = GET_SWZ(s
, i
);
2682 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2683 swizzled_result
.writemask
= copy_mask
;
2684 emit(MOV(swizzled_result
, orig_val
));
2688 swizzled_result
.writemask
= zero_mask
;
2689 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2693 swizzled_result
.writemask
= one_mask
;
2694 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2699 vec4_visitor::visit(ir_return
*)
2701 unreachable("not reached");
2705 vec4_visitor::visit(ir_discard
*)
2707 unreachable("not reached");
2711 vec4_visitor::visit(ir_if
*ir
)
2713 /* Don't point the annotation at the if statement, because then it plus
2714 * the then and else blocks get printed.
2716 this->base_ir
= ir
->condition
;
2718 if (brw
->gen
== 6) {
2721 enum brw_predicate predicate
;
2722 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2723 emit(IF(predicate
));
2726 visit_instructions(&ir
->then_instructions
);
2728 if (!ir
->else_instructions
.is_empty()) {
2729 this->base_ir
= ir
->condition
;
2730 emit(BRW_OPCODE_ELSE
);
2732 visit_instructions(&ir
->else_instructions
);
2735 this->base_ir
= ir
->condition
;
2736 emit(BRW_OPCODE_ENDIF
);
2740 vec4_visitor::visit(ir_emit_vertex
*)
2742 unreachable("not reached");
2746 vec4_visitor::visit(ir_end_primitive
*)
2748 unreachable("not reached");
2752 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2753 dst_reg dst
, src_reg offset
,
2754 src_reg src0
, src_reg src1
)
2758 /* Set the atomic operation offset. */
2759 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2762 /* Set the atomic operation arguments. */
2763 if (src0
.file
!= BAD_FILE
) {
2764 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2768 if (src1
.file
!= BAD_FILE
) {
2769 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2773 /* Emit the instruction. Note that this maps to the normal SIMD8
2774 * untyped atomic message on Ivy Bridge, but that's OK because
2775 * unused channels will be masked out.
2777 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2778 src_reg(atomic_op
), src_reg(surf_index
));
2784 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
2787 /* Set the surface read offset. */
2788 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
2790 /* Emit the instruction. Note that this maps to the normal SIMD8
2791 * untyped surface read message, but that's OK because unused
2792 * channels will be masked out.
2794 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
,
2795 dst
, src_reg(surf_index
));
2801 vec4_visitor::emit_ndc_computation()
2803 /* Get the position */
2804 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2806 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2807 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2808 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2810 current_annotation
= "NDC";
2811 dst_reg ndc_w
= ndc
;
2812 ndc_w
.writemask
= WRITEMASK_W
;
2813 src_reg pos_w
= pos
;
2814 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2815 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2817 dst_reg ndc_xyz
= ndc
;
2818 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2820 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2824 vec4_visitor::emit_psiz_and_flags(struct brw_reg reg
)
2827 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2828 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2829 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2830 dst_reg header1_w
= header1
;
2831 header1_w
.writemask
= WRITEMASK_W
;
2833 emit(MOV(header1
, 0u));
2835 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2836 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2838 current_annotation
= "Point size";
2839 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2840 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2843 if (key
->userclip_active
) {
2844 current_annotation
= "Clipping flags";
2845 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
2846 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
2848 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2849 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
2850 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
2852 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2853 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
2854 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
2855 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
2858 /* i965 clipping workaround:
2859 * 1) Test for -ve rhw
2861 * set ndc = (0,0,0,0)
2864 * Later, clipping will detect ucp[6] and ensure the primitive is
2865 * clipped against all fixed planes.
2867 if (brw
->has_negative_rhw_bug
) {
2868 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2869 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2870 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2871 vec4_instruction
*inst
;
2872 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2873 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2874 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
2875 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2878 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2879 } else if (brw
->gen
< 6) {
2880 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2882 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2883 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2884 emit(MOV(brw_writemask(reg
, WRITEMASK_W
),
2885 src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
2887 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
2888 emit(MOV(retype(brw_writemask(reg
, WRITEMASK_Y
), BRW_REGISTER_TYPE_D
),
2889 src_reg(output_reg
[VARYING_SLOT_LAYER
])));
2891 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
2892 emit(MOV(retype(brw_writemask(reg
, WRITEMASK_Z
), BRW_REGISTER_TYPE_D
),
2893 src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
2899 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
2901 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2903 * "If a linked set of shaders forming the vertex stage contains no
2904 * static write to gl_ClipVertex or gl_ClipDistance, but the
2905 * application has requested clipping against user clip planes through
2906 * the API, then the coordinate written to gl_Position is used for
2907 * comparison against the user clip planes."
2909 * This function is only called if the shader didn't write to
2910 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2911 * if the user wrote to it; otherwise we use gl_Position.
2913 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
2914 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
2915 clip_vertex
= VARYING_SLOT_POS
;
2918 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
2920 reg
.writemask
= 1 << i
;
2922 src_reg(output_reg
[clip_vertex
]),
2923 src_reg(this->userplane
[i
+ offset
])));
2928 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
2930 assert (varying
< VARYING_SLOT_MAX
);
2931 reg
.type
= output_reg
[varying
].type
;
2932 current_annotation
= output_reg_annotation
[varying
];
2933 /* Copy the register, saturating if necessary */
2934 vec4_instruction
*inst
= emit(MOV(reg
,
2935 src_reg(output_reg
[varying
])));
2936 if ((varying
== VARYING_SLOT_COL0
||
2937 varying
== VARYING_SLOT_COL1
||
2938 varying
== VARYING_SLOT_BFC0
||
2939 varying
== VARYING_SLOT_BFC1
) &&
2940 key
->clamp_vertex_color
) {
2941 inst
->saturate
= true;
2946 vec4_visitor::emit_urb_slot(int mrf
, int varying
)
2948 struct brw_reg hw_reg
= brw_message_reg(mrf
);
2949 dst_reg reg
= dst_reg(MRF
, mrf
);
2950 reg
.type
= BRW_REGISTER_TYPE_F
;
2953 case VARYING_SLOT_PSIZ
:
2954 /* PSIZ is always in slot 0, and is coupled with other flags. */
2955 current_annotation
= "indices, point width, clip flags";
2956 emit_psiz_and_flags(hw_reg
);
2958 case BRW_VARYING_SLOT_NDC
:
2959 current_annotation
= "NDC";
2960 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
2962 case VARYING_SLOT_POS
:
2963 current_annotation
= "gl_Position";
2964 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
2966 case VARYING_SLOT_EDGE
:
2967 /* This is present when doing unfilled polygons. We're supposed to copy
2968 * the edge flag from the user-provided vertex array
2969 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
2970 * of that attribute (starts as 1.0f). This is then used in clipping to
2971 * determine which edges should be drawn as wireframe.
2973 current_annotation
= "edge flag";
2974 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
2975 glsl_type::float_type
, WRITEMASK_XYZW
))));
2977 case BRW_VARYING_SLOT_PAD
:
2978 /* No need to write to this slot */
2981 emit_generic_urb_slot(reg
, varying
);
2987 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
2989 if (brw
->gen
>= 6) {
2990 /* URB data written (does not include the message header reg) must
2991 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
2992 * section 5.4.3.2.2: URB_INTERLEAVED.
2994 * URB entries are allocated on a multiple of 1024 bits, so an
2995 * extra 128 bits written here to make the end align to 256 is
2998 if ((mlen
% 2) != 1)
3007 * Generates the VUE payload plus the necessary URB write instructions to
3010 * The VUE layout is documented in Volume 2a.
3013 vec4_visitor::emit_vertex()
3015 /* MRF 0 is reserved for the debugger, so start with message header
3020 /* In the process of generating our URB write message contents, we
3021 * may need to unspill a register or load from an array. Those
3022 * reads would use MRFs 14-15.
3024 int max_usable_mrf
= 13;
3026 /* The following assertion verifies that max_usable_mrf causes an
3027 * even-numbered amount of URB write data, which will meet gen6's
3028 * requirements for length alignment.
3030 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3032 /* First mrf is the g0-based message header containing URB handles and
3035 emit_urb_write_header(mrf
++);
3038 emit_ndc_computation();
3041 /* Lower legacy ff and ClipVertex clipping to clip distances */
3042 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3043 current_annotation
= "user clip distances";
3045 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3046 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3048 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3049 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3052 /* We may need to split this up into several URB writes, so do them in a
3056 bool complete
= false;
3058 /* URB offset is in URB row increments, and each of our MRFs is half of
3059 * one of those, since we're doing interleaved writes.
3061 int offset
= slot
/ 2;
3064 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3065 emit_urb_slot(mrf
++, prog_data
->vue_map
.slot_to_varying
[slot
]);
3067 /* If this was max_usable_mrf, we can't fit anything more into this
3070 if (mrf
> max_usable_mrf
) {
3076 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3077 current_annotation
= "URB write";
3078 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3079 inst
->base_mrf
= base_mrf
;
3080 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
3081 inst
->offset
+= offset
;
3087 vec4_visitor::get_scratch_offset(vec4_instruction
*inst
,
3088 src_reg
*reladdr
, int reg_offset
)
3090 /* Because we store the values to scratch interleaved like our
3091 * vertex data, we need to scale the vec4 index by 2.
3093 int message_header_scale
= 2;
3095 /* Pre-gen6, the message header uses byte offsets instead of vec4
3096 * (16-byte) offset units.
3099 message_header_scale
*= 16;
3102 src_reg index
= src_reg(this, glsl_type::int_type
);
3104 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
3105 emit_before(inst
, MUL(dst_reg(index
),
3106 index
, src_reg(message_header_scale
)));
3110 return src_reg(reg_offset
* message_header_scale
);
3115 vec4_visitor::get_pull_constant_offset(vec4_instruction
*inst
,
3116 src_reg
*reladdr
, int reg_offset
)
3119 src_reg index
= src_reg(this, glsl_type::int_type
);
3121 emit_before(inst
, ADD(dst_reg(index
), *reladdr
, src_reg(reg_offset
)));
3123 /* Pre-gen6, the message header uses byte offsets instead of vec4
3124 * (16-byte) offset units.
3127 emit_before(inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3131 } else if (brw
->gen
>= 8) {
3132 /* Store the offset in a GRF so we can send-from-GRF. */
3133 src_reg offset
= src_reg(this, glsl_type::int_type
);
3134 emit_before(inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3137 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
3138 return src_reg(reg_offset
* message_header_scale
);
3143 * Emits an instruction before @inst to load the value named by @orig_src
3144 * from scratch space at @base_offset to @temp.
3146 * @base_offset is measured in 32-byte units (the size of a register).
3149 vec4_visitor::emit_scratch_read(vec4_instruction
*inst
,
3150 dst_reg temp
, src_reg orig_src
,
3153 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3154 src_reg index
= get_scratch_offset(inst
, orig_src
.reladdr
, reg_offset
);
3156 emit_before(inst
, SCRATCH_READ(temp
, index
));
3160 * Emits an instruction after @inst to store the value to be written
3161 * to @orig_dst to scratch space at @base_offset, from @temp.
3163 * @base_offset is measured in 32-byte units (the size of a register).
3166 vec4_visitor::emit_scratch_write(vec4_instruction
*inst
, int base_offset
)
3168 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3169 src_reg index
= get_scratch_offset(inst
, inst
->dst
.reladdr
, reg_offset
);
3171 /* Create a temporary register to store *inst's result in.
3173 * We have to be careful in MOVing from our temporary result register in
3174 * the scratch write. If we swizzle from channels of the temporary that
3175 * weren't initialized, it will confuse live interval analysis, which will
3176 * make spilling fail to make progress.
3178 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
3179 temp
.type
= inst
->dst
.type
;
3180 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
3182 for (int i
= 0; i
< 4; i
++)
3183 if (inst
->dst
.writemask
& (1 << i
))
3186 swizzles
[i
] = first_writemask_chan
;
3187 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3188 swizzles
[2], swizzles
[3]);
3190 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3191 inst
->dst
.writemask
));
3192 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3193 write
->predicate
= inst
->predicate
;
3194 write
->ir
= inst
->ir
;
3195 write
->annotation
= inst
->annotation
;
3196 inst
->insert_after(write
);
3198 inst
->dst
.file
= temp
.file
;
3199 inst
->dst
.reg
= temp
.reg
;
3200 inst
->dst
.reg_offset
= temp
.reg_offset
;
3201 inst
->dst
.reladdr
= NULL
;
3205 * We can't generally support array access in GRF space, because a
3206 * single instruction's destination can only span 2 contiguous
3207 * registers. So, we send all GRF arrays that get variable index
3208 * access to scratch space.
3211 vec4_visitor::move_grf_array_access_to_scratch()
3213 int scratch_loc
[this->virtual_grf_count
];
3215 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
3216 scratch_loc
[i
] = -1;
3219 /* First, calculate the set of virtual GRFs that need to be punted
3220 * to scratch due to having any array access on them, and where in
3223 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
3224 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3225 scratch_loc
[inst
->dst
.reg
] == -1) {
3226 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3227 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
3230 for (int i
= 0 ; i
< 3; i
++) {
3231 src_reg
*src
= &inst
->src
[i
];
3233 if (src
->file
== GRF
&& src
->reladdr
&&
3234 scratch_loc
[src
->reg
] == -1) {
3235 scratch_loc
[src
->reg
] = c
->last_scratch
;
3236 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
3241 /* Now, for anything that will be accessed through scratch, rewrite
3242 * it to load/store. Note that this is a _safe list walk, because
3243 * we may generate a new scratch_write instruction after the one
3246 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
3247 /* Set up the annotation tracking for new generated instructions. */
3249 current_annotation
= inst
->annotation
;
3251 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3252 emit_scratch_write(inst
, scratch_loc
[inst
->dst
.reg
]);
3255 for (int i
= 0 ; i
< 3; i
++) {
3256 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3259 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3261 emit_scratch_read(inst
, temp
, inst
->src
[i
],
3262 scratch_loc
[inst
->src
[i
].reg
]);
3264 inst
->src
[i
].file
= temp
.file
;
3265 inst
->src
[i
].reg
= temp
.reg
;
3266 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3267 inst
->src
[i
].reladdr
= NULL
;
3273 * Emits an instruction before @inst to load the value named by @orig_src
3274 * from the pull constant buffer (surface) at @base_offset to @temp.
3277 vec4_visitor::emit_pull_constant_load(vec4_instruction
*inst
,
3278 dst_reg temp
, src_reg orig_src
,
3281 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3282 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3283 src_reg offset
= get_pull_constant_offset(inst
, orig_src
.reladdr
, reg_offset
);
3284 vec4_instruction
*load
;
3286 if (brw
->gen
>= 7) {
3287 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3288 grf_offset
.type
= offset
.type
;
3289 emit_before(inst
, MOV(grf_offset
, offset
));
3291 load
= new(mem_ctx
) vec4_instruction(this,
3292 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3293 temp
, index
, src_reg(grf_offset
));
3295 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
3296 temp
, index
, offset
);
3297 load
->base_mrf
= 14;
3300 emit_before(inst
, load
);
3304 * Implements array access of uniforms by inserting a
3305 * PULL_CONSTANT_LOAD instruction.
3307 * Unlike temporary GRF array access (where we don't support it due to
3308 * the difficulty of doing relative addressing on instruction
3309 * destinations), we could potentially do array access of uniforms
3310 * that were loaded in GRF space as push constants. In real-world
3311 * usage we've seen, though, the arrays being used are always larger
3312 * than we could load as push constants, so just always move all
3313 * uniform array access out to a pull constant buffer.
3316 vec4_visitor::move_uniform_array_access_to_pull_constants()
3318 int pull_constant_loc
[this->uniforms
];
3320 for (int i
= 0; i
< this->uniforms
; i
++) {
3321 pull_constant_loc
[i
] = -1;
3324 /* Walk through and find array access of uniforms. Put a copy of that
3325 * uniform in the pull constant buffer.
3327 * Note that we don't move constant-indexed accesses to arrays. No
3328 * testing has been done of the performance impact of this choice.
3330 foreach_in_list_safe(vec4_instruction
, inst
, &instructions
) {
3331 for (int i
= 0 ; i
< 3; i
++) {
3332 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3335 int uniform
= inst
->src
[i
].reg
;
3337 /* If this array isn't already present in the pull constant buffer,
3340 if (pull_constant_loc
[uniform
] == -1) {
3341 const gl_constant_value
**values
=
3342 &stage_prog_data
->param
[uniform
* 4];
3344 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3346 assert(uniform
< uniform_array_size
);
3347 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3348 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3353 /* Set up the annotation tracking for new generated instructions. */
3355 current_annotation
= inst
->annotation
;
3357 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3359 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
3360 pull_constant_loc
[uniform
]);
3362 inst
->src
[i
].file
= temp
.file
;
3363 inst
->src
[i
].reg
= temp
.reg
;
3364 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3365 inst
->src
[i
].reladdr
= NULL
;
3369 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3370 * no need to track them as larger-than-vec4 objects. This will be
3371 * relied on in cutting out unused uniform vectors from push
3374 split_uniform_registers();
3378 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3380 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3384 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3385 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3389 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3390 struct brw_vec4_compile
*c
,
3391 struct gl_program
*prog
,
3392 const struct brw_vec4_prog_key
*key
,
3393 struct brw_vec4_prog_data
*prog_data
,
3394 struct gl_shader_program
*shader_prog
,
3395 gl_shader_stage stage
,
3399 shader_time_shader_type st_base
,
3400 shader_time_shader_type st_written
,
3401 shader_time_shader_type st_reset
)
3402 : backend_visitor(brw
, shader_prog
, prog
, &prog_data
->base
, stage
),
3405 prog_data(prog_data
),
3406 sanity_param_count(0),
3408 first_non_payload_grf(0),
3409 need_all_constants_in_pull_buffer(false),
3410 debug_flag(debug_flag
),
3411 no_spills(no_spills
),
3413 st_written(st_written
),
3416 this->mem_ctx
= mem_ctx
;
3417 this->failed
= false;
3419 this->base_ir
= NULL
;
3420 this->current_annotation
= NULL
;
3421 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3423 this->variable_ht
= hash_table_ctor(0,
3424 hash_table_pointer_hash
,
3425 hash_table_pointer_compare
);
3427 this->virtual_grf_start
= NULL
;
3428 this->virtual_grf_end
= NULL
;
3429 this->virtual_grf_sizes
= NULL
;
3430 this->virtual_grf_count
= 0;
3431 this->virtual_grf_reg_map
= NULL
;
3432 this->virtual_grf_reg_count
= 0;
3433 this->virtual_grf_array_size
= 0;
3434 this->live_intervals_valid
= false;
3436 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3440 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3441 * at least one. See setup_uniforms() in brw_vec4.cpp.
3443 this->uniform_array_size
= 1;
3445 this->uniform_array_size
= MAX2(stage_prog_data
->nr_params
, 1);
3448 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3449 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3452 vec4_visitor::~vec4_visitor()
3454 hash_table_dtor(this->variable_ht
);
3459 vec4_visitor::fail(const char *format
, ...)
3469 va_start(va
, format
);
3470 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3472 msg
= ralloc_asprintf(mem_ctx
, "vec4 compile failed: %s\n", msg
);
3474 this->fail_msg
= msg
;
3477 fprintf(stderr
, "%s", msg
);
3481 } /* namespace brw */