2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
28 #include "program/sampler.h"
33 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
34 enum opcode opcode
, const dst_reg
&dst
,
35 const src_reg
&src0
, const src_reg
&src1
,
38 this->opcode
= opcode
;
43 this->saturate
= false;
44 this->force_writemask_all
= false;
45 this->no_dd_clear
= false;
46 this->no_dd_check
= false;
47 this->writes_accumulator
= false;
48 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
50 this->shadow_compare
= false;
51 this->ir
= v
->base_ir
;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_present
= false;
57 this->annotation
= v
->current_annotation
;
61 vec4_visitor::emit(vec4_instruction
*inst
)
63 this->instructions
.push_tail(inst
);
69 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
70 vec4_instruction
*new_inst
)
72 new_inst
->ir
= inst
->ir
;
73 new_inst
->annotation
= inst
->annotation
;
75 inst
->insert_before(block
, new_inst
);
81 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
82 const src_reg
&src1
, const src_reg
&src2
)
84 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
90 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
93 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
97 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
99 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
103 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
105 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
));
109 vec4_visitor::emit(enum opcode opcode
)
111 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
116 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
118 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
124 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
125 const src_reg &src1) \
127 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
131 #define ALU2_ACC(op) \
133 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
134 const src_reg &src1) \
136 vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, \
137 BRW_OPCODE_##op, dst, src0, src1); \
138 inst->writes_accumulator = true; \
144 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
145 const src_reg &src1, const src_reg &src2) \
147 assert(brw->gen >= 6); \
148 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
185 /** Gen4 predicated IF. */
187 vec4_visitor::IF(enum brw_predicate predicate
)
189 vec4_instruction
*inst
;
191 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
192 inst
->predicate
= predicate
;
197 /** Gen6 IF with embedded comparison. */
199 vec4_visitor::IF(src_reg src0
, src_reg src1
,
200 enum brw_conditional_mod condition
)
202 assert(brw
->gen
== 6);
204 vec4_instruction
*inst
;
206 resolve_ud_negate(&src0
);
207 resolve_ud_negate(&src1
);
209 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
211 inst
->conditional_mod
= condition
;
217 * CMP: Sets the low bit of the destination channels with the result
218 * of the comparison, while the upper bits are undefined, and updates
219 * the flag register with the packed 16 bits of the result.
222 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
223 enum brw_conditional_mod condition
)
225 vec4_instruction
*inst
;
227 /* original gen4 does type conversion to the destination type
228 * before before comparison, producing garbage results for floating
232 dst
.type
= src0
.type
;
233 if (dst
.file
== HW_REG
)
234 dst
.fixed_hw_reg
.type
= dst
.type
;
237 resolve_ud_negate(&src0
);
238 resolve_ud_negate(&src1
);
240 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
241 inst
->conditional_mod
= condition
;
247 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
249 vec4_instruction
*inst
;
251 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_READ
,
260 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
261 const src_reg
&index
)
263 vec4_instruction
*inst
;
265 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
274 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
276 static enum opcode dot_opcodes
[] = {
277 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
280 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
284 vec4_visitor::fix_3src_operand(src_reg src
)
286 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
287 * able to use vertical stride of zero to replicate the vec4 uniform, like
289 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
291 * But you can't, since vertical stride is always four in three-source
292 * instructions. Instead, insert a MOV instruction to do the replication so
293 * that the three-source instruction can consume it.
296 /* The MOV is only needed if the source is a uniform or immediate. */
297 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
300 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
303 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
304 expanded
.type
= src
.type
;
305 emit(MOV(expanded
, src
));
306 return src_reg(expanded
);
310 vec4_visitor::fix_math_operand(src_reg src
)
312 if (brw
->gen
< 6 || brw
->gen
>= 8 || src
.file
== BAD_FILE
)
315 /* The gen6 math instruction ignores the source modifiers --
316 * swizzle, abs, negate, and at least some parts of the register
317 * region description.
319 * Rather than trying to enumerate all these cases, *always* expand the
320 * operand to a temp GRF for gen6.
322 * For gen7, keep the operand as-is, except if immediate, which gen7 still
326 if (brw
->gen
== 7 && src
.file
!= IMM
)
329 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
330 expanded
.type
= src
.type
;
331 emit(MOV(expanded
, src
));
332 return src_reg(expanded
);
336 vec4_visitor::emit_math(enum opcode opcode
,
338 const src_reg
&src0
, const src_reg
&src1
)
340 vec4_instruction
*math
=
341 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
343 if (brw
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
344 /* MATH on Gen6 must be align1, so we can't do writemasks. */
345 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
346 math
->dst
.type
= dst
.type
;
347 emit(MOV(dst
, src_reg(math
->dst
)));
348 } else if (brw
->gen
< 6) {
350 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
355 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
358 unreachable("ir_unop_pack_half_2x16 should be lowered");
361 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
362 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
364 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
366 * Because this instruction does not have a 16-bit floating-point type,
367 * the destination data type must be Word (W).
369 * The destination must be DWord-aligned and specify a horizontal stride
370 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
371 * each destination channel and the upper word is not modified.
373 * The above restriction implies that the f32to16 instruction must use
374 * align1 mode, because only in align1 mode is it possible to specify
375 * horizontal stride. We choose here to defy the hardware docs and emit
376 * align16 instructions.
378 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
379 * instructions. I was partially successful in that the code passed all
380 * tests. However, the code was dubiously correct and fragile, and the
381 * tests were not harsh enough to probe that frailty. Not trusting the
382 * code, I chose instead to remain in align16 mode in defiance of the hw
385 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
386 * simulator, emitting a f32to16 in align16 mode with UD as destination
387 * data type is safe. The behavior differs from that specified in the PRM
388 * in that the upper word of each destination channel is cleared to 0.
391 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
392 src_reg
tmp_src(tmp_dst
);
395 /* Verify the undocumented behavior on which the following instructions
396 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
397 * then the result of the bit-or instruction below will be incorrect.
399 * You should inspect the disasm output in order to verify that the MOV is
400 * not optimized away.
402 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
405 /* Give tmp the form below, where "." means untouched.
408 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
410 * That the upper word of each write-channel be 0 is required for the
411 * following bit-shift and bit-or instructions to work. Note that this
412 * relies on the undocumented hardware behavior mentioned above.
414 tmp_dst
.writemask
= WRITEMASK_XY
;
415 emit(F32TO16(tmp_dst
, src0
));
417 /* Give the write-channels of dst the form:
420 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
421 emit(SHL(dst
, tmp_src
, src_reg(16u)));
423 /* Finally, give the write-channels of dst the form of packHalf2x16's
427 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
428 emit(OR(dst
, src_reg(dst
), tmp_src
));
432 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
435 unreachable("ir_unop_unpack_half_2x16 should be lowered");
438 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
439 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
441 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
443 * Because this instruction does not have a 16-bit floating-point type,
444 * the source data type must be Word (W). The destination type must be
447 * To use W as the source data type, we must adjust horizontal strides,
448 * which is only possible in align1 mode. All my [chadv] attempts at
449 * emitting align1 instructions for unpackHalf2x16 failed to pass the
450 * Piglit tests, so I gave up.
452 * I've verified that, on gen7 hardware and the simulator, it is safe to
453 * emit f16to32 in align16 mode with UD as source data type.
456 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
457 src_reg
tmp_src(tmp_dst
);
459 tmp_dst
.writemask
= WRITEMASK_X
;
460 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
462 tmp_dst
.writemask
= WRITEMASK_Y
;
463 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
465 dst
.writemask
= WRITEMASK_XY
;
466 emit(F16TO32(dst
, tmp_src
));
470 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
472 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
473 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
474 * is not suitable to generate the shift values, but we can use the packed
475 * vector float and a type-converting MOV.
477 dst_reg
shift(this, glsl_type::uvec4_type
);
478 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
480 dst_reg
shifted(this, glsl_type::uvec4_type
);
481 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
482 emit(SHR(shifted
, src0
, src_reg(shift
)));
484 shifted
.type
= BRW_REGISTER_TYPE_UB
;
485 dst_reg
f(this, glsl_type::vec4_type
);
486 emit(MOV(f
, src_reg(shifted
)));
488 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
492 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
494 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
495 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
496 * is not suitable to generate the shift values, but we can use the packed
497 * vector float and a type-converting MOV.
499 dst_reg
shift(this, glsl_type::uvec4_type
);
500 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
502 dst_reg
shifted(this, glsl_type::uvec4_type
);
503 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
504 emit(SHR(shifted
, src0
, src_reg(shift
)));
506 shifted
.type
= BRW_REGISTER_TYPE_B
;
507 dst_reg
f(this, glsl_type::vec4_type
);
508 emit(MOV(f
, src_reg(shifted
)));
510 dst_reg
scaled(this, glsl_type::vec4_type
);
511 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
513 dst_reg
max(this, glsl_type::vec4_type
);
514 emit_minmax(BRW_CONDITIONAL_G
, max
, src_reg(scaled
), src_reg(-1.0f
));
515 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
519 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
521 dst_reg
saturated(this, glsl_type::vec4_type
);
522 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
523 inst
->saturate
= true;
525 dst_reg
scaled(this, glsl_type::vec4_type
);
526 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
528 dst_reg
rounded(this, glsl_type::vec4_type
);
529 emit(RNDE(rounded
, src_reg(scaled
)));
531 dst_reg
u(this, glsl_type::uvec4_type
);
532 emit(MOV(u
, src_reg(rounded
)));
535 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
539 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
541 dst_reg
max(this, glsl_type::vec4_type
);
542 emit_minmax(BRW_CONDITIONAL_G
, max
, src0
, src_reg(-1.0f
));
544 dst_reg
min(this, glsl_type::vec4_type
);
545 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
547 dst_reg
scaled(this, glsl_type::vec4_type
);
548 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
550 dst_reg
rounded(this, glsl_type::vec4_type
);
551 emit(RNDE(rounded
, src_reg(scaled
)));
553 dst_reg
i(this, glsl_type::ivec4_type
);
554 emit(MOV(i
, src_reg(rounded
)));
557 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
561 vec4_visitor::visit_instructions(const exec_list
*list
)
563 foreach_in_list(ir_instruction
, ir
, list
) {
571 type_size(const struct glsl_type
*type
)
576 switch (type
->base_type
) {
579 case GLSL_TYPE_FLOAT
:
581 if (type
->is_matrix()) {
582 return type
->matrix_columns
;
584 /* Regardless of size of vector, it gets a vec4. This is bad
585 * packing for things like floats, but otherwise arrays become a
586 * mess. Hopefully a later pass over the code can pack scalars
587 * down if appropriate.
591 case GLSL_TYPE_ARRAY
:
592 assert(type
->length
> 0);
593 return type_size(type
->fields
.array
) * type
->length
;
594 case GLSL_TYPE_STRUCT
:
596 for (i
= 0; i
< type
->length
; i
++) {
597 size
+= type_size(type
->fields
.structure
[i
].type
);
600 case GLSL_TYPE_SAMPLER
:
601 /* Samplers take up no register space, since they're baked in at
605 case GLSL_TYPE_ATOMIC_UINT
:
607 case GLSL_TYPE_IMAGE
:
609 case GLSL_TYPE_ERROR
:
610 case GLSL_TYPE_INTERFACE
:
611 unreachable("not reached");
618 vec4_visitor::virtual_grf_alloc(int size
)
620 if (virtual_grf_array_size
<= virtual_grf_count
) {
621 if (virtual_grf_array_size
== 0)
622 virtual_grf_array_size
= 16;
624 virtual_grf_array_size
*= 2;
625 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
626 virtual_grf_array_size
);
627 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
628 virtual_grf_array_size
);
630 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
631 virtual_grf_reg_count
+= size
;
632 virtual_grf_sizes
[virtual_grf_count
] = size
;
633 return virtual_grf_count
++;
636 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
641 this->reg
= v
->virtual_grf_alloc(type_size(type
));
643 if (type
->is_array() || type
->is_record()) {
644 this->swizzle
= BRW_SWIZZLE_NOOP
;
646 this->swizzle
= swizzle_for_size(type
->vector_elements
);
649 this->type
= brw_type_for_base_type(type
);
652 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
659 this->reg
= v
->virtual_grf_alloc(type_size(type
) * size
);
661 this->swizzle
= BRW_SWIZZLE_NOOP
;
663 this->type
= brw_type_for_base_type(type
);
666 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
671 this->reg
= v
->virtual_grf_alloc(type_size(type
));
673 if (type
->is_array() || type
->is_record()) {
674 this->writemask
= WRITEMASK_XYZW
;
676 this->writemask
= (1 << type
->vector_elements
) - 1;
679 this->type
= brw_type_for_base_type(type
);
682 /* Our support for uniforms is piggy-backed on the struct
683 * gl_fragment_program, because that's where the values actually
684 * get stored, rather than in some global gl_shader_program uniform
688 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
690 int namelen
= strlen(ir
->name
);
692 /* The data for our (non-builtin) uniforms is stored in a series of
693 * gl_uniform_driver_storage structs for each subcomponent that
694 * glGetUniformLocation() could name. We know it's been set up in the same
695 * order we'd walk the type, so walk the list of storage and find anything
696 * with our name, or the prefix of a component that starts with our name.
698 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
699 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
701 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
702 (storage
->name
[namelen
] != 0 &&
703 storage
->name
[namelen
] != '.' &&
704 storage
->name
[namelen
] != '[')) {
708 gl_constant_value
*components
= storage
->storage
;
709 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
710 storage
->type
->matrix_columns
);
712 for (unsigned s
= 0; s
< vector_count
; s
++) {
713 assert(uniforms
< uniform_array_size
);
714 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
717 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
718 stage_prog_data
->param
[uniforms
* 4 + i
] = components
;
722 static gl_constant_value zero
= { 0.0 };
723 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
732 vec4_visitor::setup_uniform_clipplane_values()
734 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
736 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
737 assert(this->uniforms
< uniform_array_size
);
738 this->uniform_vector_size
[this->uniforms
] = 4;
739 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
740 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
741 for (int j
= 0; j
< 4; ++j
) {
742 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
743 (gl_constant_value
*) &clip_planes
[i
][j
];
749 /* Our support for builtin uniforms is even scarier than non-builtin.
750 * It sits on top of the PROG_STATE_VAR parameters that are
751 * automatically updated from GL context state.
754 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
756 const ir_state_slot
*const slots
= ir
->get_state_slots();
757 assert(slots
!= NULL
);
759 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
760 /* This state reference has already been setup by ir_to_mesa,
761 * but we'll get the same index back here. We can reference
762 * ParameterValues directly, since unlike brw_fs.cpp, we never
763 * add new state references during compile.
765 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
766 (gl_state_index
*)slots
[i
].tokens
);
767 gl_constant_value
*values
=
768 &this->prog
->Parameters
->ParameterValues
[index
][0];
770 assert(this->uniforms
< uniform_array_size
);
771 this->uniform_vector_size
[this->uniforms
] = 0;
772 /* Add each of the unique swizzled channels of the element.
773 * This will end up matching the size of the glsl_type of this field.
776 for (unsigned int j
= 0; j
< 4; j
++) {
777 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
780 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
781 assert(this->uniforms
< uniform_array_size
);
782 if (swiz
<= last_swiz
)
783 this->uniform_vector_size
[this->uniforms
]++;
790 vec4_visitor::variable_storage(ir_variable
*var
)
792 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
796 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
797 enum brw_predicate
*predicate
)
799 ir_expression
*expr
= ir
->as_expression();
801 *predicate
= BRW_PREDICATE_NORMAL
;
803 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
805 vec4_instruction
*inst
;
807 assert(expr
->get_num_operands() <= 3);
808 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
809 expr
->operands
[i
]->accept(this);
810 op
[i
] = this->result
;
812 resolve_ud_negate(&op
[i
]);
815 switch (expr
->operation
) {
816 case ir_unop_logic_not
:
817 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
818 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
821 case ir_binop_logic_xor
:
822 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
823 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
826 case ir_binop_logic_or
:
827 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
828 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
831 case ir_binop_logic_and
:
832 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
833 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
838 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
840 inst
= emit(MOV(dst_null_f(), op
[0]));
841 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
847 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
849 inst
= emit(MOV(dst_null_d(), op
[0]));
850 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
854 case ir_binop_all_equal
:
855 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
856 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
859 case ir_binop_any_nequal
:
860 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
861 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
865 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
866 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
869 case ir_binop_greater
:
870 case ir_binop_gequal
:
872 case ir_binop_lequal
:
874 case ir_binop_nequal
:
875 emit(CMP(dst_null_d(), op
[0], op
[1],
876 brw_conditional_for_comparison(expr
->operation
)));
879 case ir_triop_csel
: {
880 /* Expand the boolean condition into the flag register. */
881 inst
= emit(MOV(dst_null_d(), op
[0]));
882 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
884 /* Select which boolean to return. */
885 dst_reg
temp(this, expr
->operands
[1]->type
);
886 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
887 inst
->predicate
= BRW_PREDICATE_NORMAL
;
889 /* Expand the result to a condition code. */
890 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
891 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
896 unreachable("not reached");
903 resolve_ud_negate(&this->result
);
906 vec4_instruction
*inst
= emit(AND(dst_null_d(),
907 this->result
, src_reg(1)));
908 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
910 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
911 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
916 * Emit a gen6 IF statement with the comparison folded into the IF
920 vec4_visitor::emit_if_gen6(ir_if
*ir
)
922 ir_expression
*expr
= ir
->condition
->as_expression();
924 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
928 assert(expr
->get_num_operands() <= 3);
929 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
930 expr
->operands
[i
]->accept(this);
931 op
[i
] = this->result
;
934 switch (expr
->operation
) {
935 case ir_unop_logic_not
:
936 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
939 case ir_binop_logic_xor
:
940 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
943 case ir_binop_logic_or
:
944 temp
= dst_reg(this, glsl_type::bool_type
);
945 emit(OR(temp
, op
[0], op
[1]));
946 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
949 case ir_binop_logic_and
:
950 temp
= dst_reg(this, glsl_type::bool_type
);
951 emit(AND(temp
, op
[0], op
[1]));
952 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
956 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
960 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
963 case ir_binop_greater
:
964 case ir_binop_gequal
:
966 case ir_binop_lequal
:
968 case ir_binop_nequal
:
969 emit(IF(op
[0], op
[1],
970 brw_conditional_for_comparison(expr
->operation
)));
973 case ir_binop_all_equal
:
974 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
975 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
978 case ir_binop_any_nequal
:
979 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
980 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
984 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
985 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
988 case ir_triop_csel
: {
989 /* Expand the boolean condition into the flag register. */
990 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
991 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
993 /* Select which boolean to return. */
994 dst_reg
temp(this, expr
->operands
[1]->type
);
995 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
996 inst
->predicate
= BRW_PREDICATE_NORMAL
;
998 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
1003 unreachable("not reached");
1008 ir
->condition
->accept(this);
1010 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
1014 vec4_visitor::visit(ir_variable
*ir
)
1016 dst_reg
*reg
= NULL
;
1018 if (variable_storage(ir
))
1021 switch (ir
->data
.mode
) {
1022 case ir_var_shader_in
:
1023 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
1026 case ir_var_shader_out
:
1027 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1029 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
1030 output_reg
[ir
->data
.location
+ i
] = *reg
;
1031 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
1032 output_reg
[ir
->data
.location
+ i
].type
=
1033 brw_type_for_base_type(ir
->type
->get_scalar_type());
1034 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
1039 case ir_var_temporary
:
1040 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
1043 case ir_var_uniform
:
1044 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
1046 /* Thanks to the lower_ubo_reference pass, we will see only
1047 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
1048 * variables, so no need for them to be in variable_ht.
1050 * Some uniforms, such as samplers and atomic counters, have no actual
1051 * storage, so we should ignore them.
1053 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
1056 /* Track how big the whole uniform variable is, in case we need to put a
1057 * copy of its data into pull constants for array access.
1059 assert(this->uniforms
< uniform_array_size
);
1060 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
1062 if (!strncmp(ir
->name
, "gl_", 3)) {
1063 setup_builtin_uniform_values(ir
);
1065 setup_uniform_values(ir
);
1069 case ir_var_system_value
:
1070 reg
= make_reg_for_system_value(ir
);
1074 unreachable("not reached");
1077 reg
->type
= brw_type_for_base_type(ir
->type
);
1078 hash_table_insert(this->variable_ht
, reg
, ir
);
1082 vec4_visitor::visit(ir_loop
*ir
)
1084 /* We don't want debugging output to print the whole body of the
1085 * loop as the annotation.
1087 this->base_ir
= NULL
;
1089 emit(BRW_OPCODE_DO
);
1091 visit_instructions(&ir
->body_instructions
);
1093 emit(BRW_OPCODE_WHILE
);
1097 vec4_visitor::visit(ir_loop_jump
*ir
)
1100 case ir_loop_jump::jump_break
:
1101 emit(BRW_OPCODE_BREAK
);
1103 case ir_loop_jump::jump_continue
:
1104 emit(BRW_OPCODE_CONTINUE
);
1111 vec4_visitor::visit(ir_function_signature
*)
1113 unreachable("not reached");
1117 vec4_visitor::visit(ir_function
*ir
)
1119 /* Ignore function bodies other than main() -- we shouldn't see calls to
1120 * them since they should all be inlined.
1122 if (strcmp(ir
->name
, "main") == 0) {
1123 const ir_function_signature
*sig
;
1126 sig
= ir
->matching_signature(NULL
, &empty
, false);
1130 visit_instructions(&sig
->body
);
1135 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1137 /* 3-src instructions were introduced in gen6. */
1141 /* MAD can only handle floating-point data. */
1142 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1145 ir_rvalue
*nonmul
= ir
->operands
[1];
1146 ir_expression
*mul
= ir
->operands
[0]->as_expression();
1148 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
1149 nonmul
= ir
->operands
[0];
1150 mul
= ir
->operands
[1]->as_expression();
1152 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1156 nonmul
->accept(this);
1157 src_reg src0
= fix_3src_operand(this->result
);
1159 mul
->operands
[0]->accept(this);
1160 src_reg src1
= fix_3src_operand(this->result
);
1162 mul
->operands
[1]->accept(this);
1163 src_reg src2
= fix_3src_operand(this->result
);
1165 this->result
= src_reg(this, ir
->type
);
1166 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1172 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1174 /* This optimization relies on CMP setting the destination to 0 when
1175 * false. Early hardware only sets the least significant bit, and
1176 * leaves the other bits undefined. So we can't use it.
1181 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1186 switch (cmp
->operation
) {
1188 case ir_binop_greater
:
1189 case ir_binop_lequal
:
1190 case ir_binop_gequal
:
1191 case ir_binop_equal
:
1192 case ir_binop_nequal
:
1199 cmp
->operands
[0]->accept(this);
1200 const src_reg cmp_src0
= this->result
;
1202 cmp
->operands
[1]->accept(this);
1203 const src_reg cmp_src1
= this->result
;
1205 this->result
= src_reg(this, ir
->type
);
1207 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1208 brw_conditional_for_comparison(cmp
->operation
)));
1210 /* If the comparison is false, this->result will just happen to be zero.
1212 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1213 this->result
, src_reg(1.0f
));
1214 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1215 inst
->predicate_inverse
= true;
1221 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1222 src_reg src0
, src_reg src1
)
1224 vec4_instruction
*inst
;
1226 if (brw
->gen
>= 6) {
1227 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1228 inst
->conditional_mod
= conditionalmod
;
1230 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1232 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1233 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1238 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1239 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1241 if (brw
->gen
>= 6) {
1242 /* Note that the instruction's argument order is reversed from GLSL
1246 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1248 /* Earlier generations don't support three source operations, so we
1249 * need to emit x*(1-a) + y*a.
1251 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1252 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1253 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1254 y_times_a
.writemask
= dst
.writemask
;
1255 one_minus_a
.writemask
= dst
.writemask
;
1256 x_times_one_minus_a
.writemask
= dst
.writemask
;
1258 emit(MUL(y_times_a
, y
, a
));
1259 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1260 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1261 emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1266 vec4_visitor::visit(ir_expression
*ir
)
1268 unsigned int operand
;
1269 src_reg op
[Elements(ir
->operands
)];
1270 vec4_instruction
*inst
;
1272 if (ir
->operation
== ir_binop_add
) {
1273 if (try_emit_mad(ir
))
1277 if (ir
->operation
== ir_unop_b2f
) {
1278 if (try_emit_b2f_of_compare(ir
))
1282 /* Storage for our result. Ideally for an assignment we'd be using
1283 * the actual storage for the result here, instead.
1285 dst_reg
result_dst(this, ir
->type
);
1286 src_reg
result_src(result_dst
);
1288 if (ir
->operation
== ir_triop_csel
) {
1289 ir
->operands
[1]->accept(this);
1290 op
[1] = this->result
;
1291 ir
->operands
[2]->accept(this);
1292 op
[2] = this->result
;
1294 enum brw_predicate predicate
;
1295 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1296 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1297 inst
->predicate
= predicate
;
1298 this->result
= result_src
;
1302 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1303 this->result
.file
= BAD_FILE
;
1304 ir
->operands
[operand
]->accept(this);
1305 if (this->result
.file
== BAD_FILE
) {
1306 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1307 ir
->operands
[operand
]->fprint(stderr
);
1310 op
[operand
] = this->result
;
1312 /* Matrix expression operands should have been broken down to vector
1313 * operations already.
1315 assert(!ir
->operands
[operand
]->type
->is_matrix());
1318 /* If nothing special happens, this is the result. */
1319 this->result
= result_src
;
1321 switch (ir
->operation
) {
1322 case ir_unop_logic_not
:
1323 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
1324 emit(NOT(result_dst
, op
[0]));
1326 emit(XOR(result_dst
, op
[0], src_reg(1u)));
1330 op
[0].negate
= !op
[0].negate
;
1331 emit(MOV(result_dst
, op
[0]));
1335 op
[0].negate
= false;
1336 emit(MOV(result_dst
, op
[0]));
1340 if (ir
->type
->is_float()) {
1341 /* AND(val, 0x80000000) gives the sign bit.
1343 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1346 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1348 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1349 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1350 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1352 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1353 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1355 this->result
.type
= BRW_REGISTER_TYPE_F
;
1357 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1358 * -> non-negative val generates 0x00000000.
1359 * Predicated OR sets 1 if val is positive.
1361 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1363 emit(ASR(result_dst
, op
[0], src_reg(31)));
1365 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1366 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1371 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1375 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1378 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1382 unreachable("not reached: should be handled by ir_explog_to_explog2");
1384 case ir_unop_sin_reduced
:
1385 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1388 case ir_unop_cos_reduced
:
1389 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1393 case ir_unop_dFdx_coarse
:
1394 case ir_unop_dFdx_fine
:
1396 case ir_unop_dFdy_coarse
:
1397 case ir_unop_dFdy_fine
:
1398 unreachable("derivatives not valid in vertex shader");
1400 case ir_unop_bitfield_reverse
:
1401 emit(BFREV(result_dst
, op
[0]));
1403 case ir_unop_bit_count
:
1404 emit(CBIT(result_dst
, op
[0]));
1406 case ir_unop_find_msb
: {
1407 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1409 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1410 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1412 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1413 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1414 * subtract the result from 31 to convert the MSB count into an LSB count.
1417 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1418 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1419 emit(MOV(result_dst
, temp
));
1421 src_reg src_tmp
= src_reg(result_dst
);
1422 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1424 src_tmp
.negate
= true;
1425 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1426 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1429 case ir_unop_find_lsb
:
1430 emit(FBL(result_dst
, op
[0]));
1432 case ir_unop_saturate
:
1433 inst
= emit(MOV(result_dst
, op
[0]));
1434 inst
->saturate
= true;
1438 unreachable("not reached: should be handled by lower_noise");
1441 emit(ADD(result_dst
, op
[0], op
[1]));
1444 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1447 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
1448 /* For integer multiplication, the MUL uses the low 16 bits of one of
1449 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1450 * accumulates in the contribution of the upper 16 bits of that
1451 * operand. If we can determine that one of the args is in the low
1452 * 16 bits, though, we can just emit a single MUL.
1454 if (ir
->operands
[0]->is_uint16_constant()) {
1456 emit(MUL(result_dst
, op
[0], op
[1]));
1458 emit(MUL(result_dst
, op
[1], op
[0]));
1459 } else if (ir
->operands
[1]->is_uint16_constant()) {
1461 emit(MUL(result_dst
, op
[1], op
[0]));
1463 emit(MUL(result_dst
, op
[0], op
[1]));
1465 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1467 emit(MUL(acc
, op
[0], op
[1]));
1468 emit(MACH(dst_null_d(), op
[0], op
[1]));
1469 emit(MOV(result_dst
, src_reg(acc
)));
1472 emit(MUL(result_dst
, op
[0], op
[1]));
1475 case ir_binop_imul_high
: {
1476 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1478 emit(MUL(acc
, op
[0], op
[1]));
1479 emit(MACH(result_dst
, op
[0], op
[1]));
1483 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1484 assert(ir
->type
->is_integer());
1485 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1487 case ir_binop_carry
: {
1488 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1490 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1491 emit(MOV(result_dst
, src_reg(acc
)));
1494 case ir_binop_borrow
: {
1495 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1497 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1498 emit(MOV(result_dst
, src_reg(acc
)));
1502 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1503 assert(ir
->type
->is_integer());
1504 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1508 case ir_binop_greater
:
1509 case ir_binop_lequal
:
1510 case ir_binop_gequal
:
1511 case ir_binop_equal
:
1512 case ir_binop_nequal
: {
1513 emit(CMP(result_dst
, op
[0], op
[1],
1514 brw_conditional_for_comparison(ir
->operation
)));
1515 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1516 emit(AND(result_dst
, result_src
, src_reg(1u)));
1521 case ir_binop_all_equal
:
1522 /* "==" operator producing a scalar boolean. */
1523 if (ir
->operands
[0]->type
->is_vector() ||
1524 ir
->operands
[1]->type
->is_vector()) {
1525 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1526 emit(MOV(result_dst
, src_reg(0)));
1527 inst
= emit(MOV(result_dst
, src_reg(ctx
->Const
.UniformBooleanTrue
)));
1528 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1530 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1531 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1532 emit(AND(result_dst
, result_src
, src_reg(1u)));
1536 case ir_binop_any_nequal
:
1537 /* "!=" operator producing a scalar boolean. */
1538 if (ir
->operands
[0]->type
->is_vector() ||
1539 ir
->operands
[1]->type
->is_vector()) {
1540 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1542 emit(MOV(result_dst
, src_reg(0)));
1543 inst
= emit(MOV(result_dst
, src_reg(ctx
->Const
.UniformBooleanTrue
)));
1544 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1546 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1547 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1548 emit(AND(result_dst
, result_src
, src_reg(1u)));
1554 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1555 emit(MOV(result_dst
, src_reg(0)));
1557 inst
= emit(MOV(result_dst
, src_reg(ctx
->Const
.UniformBooleanTrue
)));
1558 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1561 case ir_binop_logic_xor
:
1562 emit(XOR(result_dst
, op
[0], op
[1]));
1565 case ir_binop_logic_or
:
1566 emit(OR(result_dst
, op
[0], op
[1]));
1569 case ir_binop_logic_and
:
1570 emit(AND(result_dst
, op
[0], op
[1]));
1574 assert(ir
->operands
[0]->type
->is_vector());
1575 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1576 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1580 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1583 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1586 case ir_unop_bitcast_i2f
:
1587 case ir_unop_bitcast_u2f
:
1588 this->result
= op
[0];
1589 this->result
.type
= BRW_REGISTER_TYPE_F
;
1592 case ir_unop_bitcast_f2i
:
1593 this->result
= op
[0];
1594 this->result
.type
= BRW_REGISTER_TYPE_D
;
1597 case ir_unop_bitcast_f2u
:
1598 this->result
= op
[0];
1599 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1608 emit(MOV(result_dst
, op
[0]));
1611 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
1612 emit(AND(result_dst
, op
[0], src_reg(1u)));
1614 emit(MOV(result_dst
, op
[0]));
1618 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
1619 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1620 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1621 emit(AND(result_dst
, op
[0], src_reg(0x3f800000u
)));
1622 result_dst
.type
= BRW_REGISTER_TYPE_F
;
1624 emit(MOV(result_dst
, op
[0]));
1629 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1630 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1631 emit(AND(result_dst
, result_src
, src_reg(1u)));
1636 emit(RNDZ(result_dst
, op
[0]));
1639 op
[0].negate
= !op
[0].negate
;
1640 inst
= emit(RNDD(result_dst
, op
[0]));
1641 this->result
.negate
= true;
1644 inst
= emit(RNDD(result_dst
, op
[0]));
1647 inst
= emit(FRC(result_dst
, op
[0]));
1649 case ir_unop_round_even
:
1650 emit(RNDE(result_dst
, op
[0]));
1654 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1657 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1661 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1664 case ir_unop_bit_not
:
1665 inst
= emit(NOT(result_dst
, op
[0]));
1667 case ir_binop_bit_and
:
1668 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1670 case ir_binop_bit_xor
:
1671 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1673 case ir_binop_bit_or
:
1674 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1677 case ir_binop_lshift
:
1678 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1681 case ir_binop_rshift
:
1682 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1683 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1685 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1689 emit(BFI1(result_dst
, op
[0], op
[1]));
1692 case ir_binop_ubo_load
: {
1693 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1694 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1695 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1698 /* Now, load the vector from that offset. */
1699 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1701 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1702 packed_consts
.type
= result
.type
;
1705 if (const_uniform_block
) {
1706 /* The block index is a constant, so just emit the binding table entry
1709 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1710 const_uniform_block
->value
.u
[0]);
1712 /* The block index is not a constant. Evaluate the index expression
1713 * per-channel and add the base UBO index; the generator will select
1714 * a value from any live channel.
1716 surf_index
= src_reg(this, glsl_type::uint_type
);
1717 emit(ADD(dst_reg(surf_index
), op
[0],
1718 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1720 /* Assume this may touch any UBO. It would be nice to provide
1721 * a tighter bound, but the array information is already lowered away.
1723 brw_mark_surface_used(&prog_data
->base
,
1724 prog_data
->base
.binding_table
.ubo_start
+
1725 shader_prog
->NumUniformBlocks
- 1);
1728 if (const_offset_ir
) {
1729 if (brw
->gen
>= 8) {
1730 /* Store the offset in a GRF so we can send-from-GRF. */
1731 offset
= src_reg(this, glsl_type::int_type
);
1732 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1734 /* Immediates are fine on older generations since they'll be moved
1735 * to a (potentially fake) MRF at the generator level.
1737 offset
= src_reg(const_offset
/ 16);
1740 offset
= src_reg(this, glsl_type::uint_type
);
1741 emit(SHR(dst_reg(offset
), op
[1], src_reg(4)));
1744 if (brw
->gen
>= 7) {
1745 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1746 grf_offset
.type
= offset
.type
;
1748 emit(MOV(grf_offset
, offset
));
1750 emit(new(mem_ctx
) vec4_instruction(this,
1751 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1752 dst_reg(packed_consts
),
1754 src_reg(grf_offset
)));
1756 vec4_instruction
*pull
=
1757 emit(new(mem_ctx
) vec4_instruction(this,
1758 VS_OPCODE_PULL_CONSTANT_LOAD
,
1759 dst_reg(packed_consts
),
1762 pull
->base_mrf
= 14;
1766 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1767 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1768 const_offset
% 16 / 4,
1769 const_offset
% 16 / 4,
1770 const_offset
% 16 / 4);
1772 /* UBO bools are any nonzero int. We need to convert them to use the
1773 * value of true stored in ctx->Const.UniformBooleanTrue.
1775 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1776 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1777 BRW_CONDITIONAL_NZ
));
1778 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1779 emit(AND(result_dst
, result
, src_reg(1u)));
1782 emit(MOV(result_dst
, packed_consts
));
1787 case ir_binop_vector_extract
:
1788 unreachable("should have been lowered by vec_index_to_cond_assign");
1791 op
[0] = fix_3src_operand(op
[0]);
1792 op
[1] = fix_3src_operand(op
[1]);
1793 op
[2] = fix_3src_operand(op
[2]);
1794 /* Note that the instruction's argument order is reversed from GLSL
1797 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1801 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1805 unreachable("already handled above");
1809 op
[0] = fix_3src_operand(op
[0]);
1810 op
[1] = fix_3src_operand(op
[1]);
1811 op
[2] = fix_3src_operand(op
[2]);
1812 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1815 case ir_triop_bitfield_extract
:
1816 op
[0] = fix_3src_operand(op
[0]);
1817 op
[1] = fix_3src_operand(op
[1]);
1818 op
[2] = fix_3src_operand(op
[2]);
1819 /* Note that the instruction's argument order is reversed from GLSL
1822 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1825 case ir_triop_vector_insert
:
1826 unreachable("should have been lowered by lower_vector_insert");
1828 case ir_quadop_bitfield_insert
:
1829 unreachable("not reached: should be handled by "
1830 "bitfield_insert_to_bfm_bfi\n");
1832 case ir_quadop_vector
:
1833 unreachable("not reached: should be handled by lower_quadop_vector");
1835 case ir_unop_pack_half_2x16
:
1836 emit_pack_half_2x16(result_dst
, op
[0]);
1838 case ir_unop_unpack_half_2x16
:
1839 emit_unpack_half_2x16(result_dst
, op
[0]);
1841 case ir_unop_unpack_unorm_4x8
:
1842 emit_unpack_unorm_4x8(result_dst
, op
[0]);
1844 case ir_unop_unpack_snorm_4x8
:
1845 emit_unpack_snorm_4x8(result_dst
, op
[0]);
1847 case ir_unop_pack_unorm_4x8
:
1848 emit_pack_unorm_4x8(result_dst
, op
[0]);
1850 case ir_unop_pack_snorm_4x8
:
1851 emit_pack_snorm_4x8(result_dst
, op
[0]);
1853 case ir_unop_pack_snorm_2x16
:
1854 case ir_unop_pack_unorm_2x16
:
1855 case ir_unop_unpack_snorm_2x16
:
1856 case ir_unop_unpack_unorm_2x16
:
1857 unreachable("not reached: should be handled by lower_packing_builtins");
1858 case ir_unop_unpack_half_2x16_split_x
:
1859 case ir_unop_unpack_half_2x16_split_y
:
1860 case ir_binop_pack_half_2x16_split
:
1861 case ir_unop_interpolate_at_centroid
:
1862 case ir_binop_interpolate_at_sample
:
1863 case ir_binop_interpolate_at_offset
:
1864 unreachable("not reached: should not occur in vertex shader");
1865 case ir_binop_ldexp
:
1866 unreachable("not reached: should be handled by ldexp_to_arith()");
1872 vec4_visitor::visit(ir_swizzle
*ir
)
1878 /* Note that this is only swizzles in expressions, not those on the left
1879 * hand side of an assignment, which do write masking. See ir_assignment
1883 ir
->val
->accept(this);
1885 assert(src
.file
!= BAD_FILE
);
1887 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1890 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1893 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1896 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1899 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1903 for (; i
< 4; i
++) {
1904 /* Replicate the last channel out. */
1905 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1908 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1914 vec4_visitor::visit(ir_dereference_variable
*ir
)
1916 const struct glsl_type
*type
= ir
->type
;
1917 dst_reg
*reg
= variable_storage(ir
->var
);
1920 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1921 this->result
= src_reg(brw_null_reg());
1925 this->result
= src_reg(*reg
);
1927 /* System values get their swizzle from the dst_reg writemask */
1928 if (ir
->var
->data
.mode
== ir_var_system_value
)
1931 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1932 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1937 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1939 /* Under normal circumstances array elements are stored consecutively, so
1940 * the stride is equal to the size of the array element.
1942 return type_size(ir
->type
);
1947 vec4_visitor::visit(ir_dereference_array
*ir
)
1949 ir_constant
*constant_index
;
1951 int array_stride
= compute_array_stride(ir
);
1953 constant_index
= ir
->array_index
->constant_expression_value();
1955 ir
->array
->accept(this);
1958 if (constant_index
) {
1959 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1961 /* Variable index array dereference. It eats the "vec4" of the
1962 * base of the array and an index that offsets the Mesa register
1965 ir
->array_index
->accept(this);
1969 if (array_stride
== 1) {
1970 index_reg
= this->result
;
1972 index_reg
= src_reg(this, glsl_type::int_type
);
1974 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1978 src_reg temp
= src_reg(this, glsl_type::int_type
);
1980 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1985 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1986 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1989 /* If the type is smaller than a vec4, replicate the last channel out. */
1990 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1991 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1993 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1994 src
.type
= brw_type_for_base_type(ir
->type
);
2000 vec4_visitor::visit(ir_dereference_record
*ir
)
2003 const glsl_type
*struct_type
= ir
->record
->type
;
2006 ir
->record
->accept(this);
2008 for (i
= 0; i
< struct_type
->length
; i
++) {
2009 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2011 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2014 /* If the type is smaller than a vec4, replicate the last channel out. */
2015 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
2016 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2018 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
2019 this->result
.type
= brw_type_for_base_type(ir
->type
);
2021 this->result
.reg_offset
+= offset
;
2025 * We want to be careful in assignment setup to hit the actual storage
2026 * instead of potentially using a temporary like we might with the
2027 * ir_dereference handler.
2030 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
2032 /* The LHS must be a dereference. If the LHS is a variable indexed array
2033 * access of a vector, it must be separated into a series conditional moves
2034 * before reaching this point (see ir_vec_index_to_cond_assign).
2036 assert(ir
->as_dereference());
2037 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2039 assert(!deref_array
->array
->type
->is_vector());
2042 /* Use the rvalue deref handler for the most part. We'll ignore
2043 * swizzles in it and write swizzles using writemask, though.
2046 return dst_reg(v
->result
);
2050 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
2051 const struct glsl_type
*type
,
2052 enum brw_predicate predicate
)
2054 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2055 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2056 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
2061 if (type
->is_array()) {
2062 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2063 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
2068 if (type
->is_matrix()) {
2069 const struct glsl_type
*vec_type
;
2071 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2072 type
->vector_elements
, 1);
2074 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2075 emit_block_move(dst
, src
, vec_type
, predicate
);
2080 assert(type
->is_scalar() || type
->is_vector());
2082 dst
->type
= brw_type_for_base_type(type
);
2083 src
->type
= dst
->type
;
2085 dst
->writemask
= (1 << type
->vector_elements
) - 1;
2087 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
2089 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
2090 inst
->predicate
= predicate
;
2097 /* If the RHS processing resulted in an instruction generating a
2098 * temporary value, and it would be easy to rewrite the instruction to
2099 * generate its result right into the LHS instead, do so. This ends
2100 * up reliably removing instructions where it can be tricky to do so
2101 * later without real UD chain information.
2104 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2107 vec4_instruction
*pre_rhs_inst
,
2108 vec4_instruction
*last_rhs_inst
)
2110 /* This could be supported, but it would take more smarts. */
2114 if (pre_rhs_inst
== last_rhs_inst
)
2115 return false; /* No instructions generated to work with. */
2117 /* Make sure the last instruction generated our source reg. */
2118 if (src
.file
!= GRF
||
2119 src
.file
!= last_rhs_inst
->dst
.file
||
2120 src
.reg
!= last_rhs_inst
->dst
.reg
||
2121 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2125 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2128 /* Check that that last instruction fully initialized the channels
2129 * we want to use, in the order we want to use them. We could
2130 * potentially reswizzle the operands of many instructions so that
2131 * we could handle out of order channels, but don't yet.
2134 for (unsigned i
= 0; i
< 4; i
++) {
2135 if (dst
.writemask
& (1 << i
)) {
2136 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2139 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2144 /* Success! Rewrite the instruction. */
2145 last_rhs_inst
->dst
.file
= dst
.file
;
2146 last_rhs_inst
->dst
.reg
= dst
.reg
;
2147 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2148 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2149 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2155 vec4_visitor::visit(ir_assignment
*ir
)
2157 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2158 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2160 if (!ir
->lhs
->type
->is_scalar() &&
2161 !ir
->lhs
->type
->is_vector()) {
2162 ir
->rhs
->accept(this);
2163 src_reg src
= this->result
;
2165 if (ir
->condition
) {
2166 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2169 /* emit_block_move doesn't account for swizzles in the source register.
2170 * This should be ok, since the source register is a structure or an
2171 * array, and those can't be swizzled. But double-check to be sure.
2173 assert(src
.swizzle
==
2174 (ir
->rhs
->type
->is_matrix()
2175 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2176 : BRW_SWIZZLE_NOOP
));
2178 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2182 /* Now we're down to just a scalar/vector with writemasks. */
2185 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2186 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2188 ir
->rhs
->accept(this);
2190 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2192 src_reg src
= this->result
;
2195 int first_enabled_chan
= 0;
2198 assert(ir
->lhs
->type
->is_vector() ||
2199 ir
->lhs
->type
->is_scalar());
2200 dst
.writemask
= ir
->write_mask
;
2202 for (int i
= 0; i
< 4; i
++) {
2203 if (dst
.writemask
& (1 << i
)) {
2204 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2209 /* Swizzle a small RHS vector into the channels being written.
2211 * glsl ir treats write_mask as dictating how many channels are
2212 * present on the RHS while in our instructions we need to make
2213 * those channels appear in the slots of the vec4 they're written to.
2215 for (int i
= 0; i
< 4; i
++) {
2216 if (dst
.writemask
& (1 << i
))
2217 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2219 swizzles
[i
] = first_enabled_chan
;
2221 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2222 swizzles
[2], swizzles
[3]);
2224 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2228 if (ir
->condition
) {
2229 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2232 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2233 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2234 inst
->predicate
= predicate
;
2242 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2244 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2245 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2246 emit_constant_values(dst
, field_value
);
2251 if (ir
->type
->is_array()) {
2252 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2253 emit_constant_values(dst
, ir
->array_elements
[i
]);
2258 if (ir
->type
->is_matrix()) {
2259 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2260 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2262 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2263 dst
->writemask
= 1 << j
;
2264 dst
->type
= BRW_REGISTER_TYPE_F
;
2266 emit(MOV(*dst
, src_reg(vec
[j
])));
2273 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2275 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2276 if (!(remaining_writemask
& (1 << i
)))
2279 dst
->writemask
= 1 << i
;
2280 dst
->type
= brw_type_for_base_type(ir
->type
);
2282 /* Find other components that match the one we're about to
2283 * write. Emits fewer instructions for things like vec4(0.5,
2286 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2287 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2288 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2289 dst
->writemask
|= (1 << j
);
2291 /* u, i, and f storage all line up, so no need for a
2292 * switch case for comparing each type.
2294 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2295 dst
->writemask
|= (1 << j
);
2299 switch (ir
->type
->base_type
) {
2300 case GLSL_TYPE_FLOAT
:
2301 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2304 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2306 case GLSL_TYPE_UINT
:
2307 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2309 case GLSL_TYPE_BOOL
:
2311 src_reg(ir
->value
.b
[i
] != 0 ? ctx
->Const
.UniformBooleanTrue
2315 unreachable("Non-float/uint/int/bool constant");
2318 remaining_writemask
&= ~dst
->writemask
;
2324 vec4_visitor::visit(ir_constant
*ir
)
2326 dst_reg dst
= dst_reg(this, ir
->type
);
2327 this->result
= src_reg(dst
);
2329 emit_constant_values(&dst
, ir
);
2333 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2335 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2336 ir
->actual_parameters
.get_head());
2337 ir_variable
*location
= deref
->variable_referenced();
2338 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2339 location
->data
.binding
);
2341 /* Calculate the surface offset */
2342 src_reg
offset(this, glsl_type::uint_type
);
2343 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2345 deref_array
->array_index
->accept(this);
2347 src_reg
tmp(this, glsl_type::uint_type
);
2348 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2349 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2351 offset
= location
->data
.atomic
.offset
;
2354 /* Emit the appropriate machine instruction */
2355 const char *callee
= ir
->callee
->function_name();
2356 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2358 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2359 emit_untyped_surface_read(surf_index
, dst
, offset
);
2361 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2362 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2363 src_reg(), src_reg());
2365 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2366 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2367 src_reg(), src_reg());
2372 vec4_visitor::visit(ir_call
*ir
)
2374 const char *callee
= ir
->callee
->function_name();
2376 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2377 !strcmp("__intrinsic_atomic_increment", callee
) ||
2378 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2379 visit_atomic_counter_intrinsic(ir
);
2381 unreachable("Unsupported intrinsic.");
2386 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
)
2388 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_MCS
);
2391 inst
->dst
= dst_reg(this, glsl_type::uvec4_type
);
2392 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2394 inst
->src
[1] = sampler
;
2396 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2397 int param_base
= inst
->base_mrf
;
2398 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2399 int zero_mask
= 0xf & ~coord_mask
;
2401 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2404 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2408 return src_reg(inst
->dst
);
2412 is_high_sampler(struct brw_context
*brw
, src_reg sampler
)
2414 if (brw
->gen
< 8 && !brw
->is_haswell
)
2417 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2421 vec4_visitor::visit(ir_texture
*ir
)
2424 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2426 ir_rvalue
*nonconst_sampler_index
=
2427 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2429 /* Handle non-constant sampler array indexing */
2430 src_reg sampler_reg
;
2431 if (nonconst_sampler_index
) {
2432 /* The highest sampler which may be used by this operation is
2433 * the last element of the array. Mark it here, because the generator
2434 * doesn't have enough information to determine the bound.
2436 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2437 ->array
->type
->array_size();
2439 uint32_t max_used
= sampler
+ array_size
- 1;
2440 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
2441 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2443 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2446 brw_mark_surface_used(&prog_data
->base
, max_used
);
2448 /* Emit code to evaluate the actual indexing expression */
2449 nonconst_sampler_index
->accept(this);
2450 dst_reg
temp(this, glsl_type::uint_type
);
2451 emit(ADD(temp
, this->result
, src_reg(sampler
)))
2452 ->force_writemask_all
= true;
2453 sampler_reg
= src_reg(temp
);
2455 /* Single sampler, or constant array index; the indexing expression
2456 * is just an immediate.
2458 sampler_reg
= src_reg(sampler
);
2461 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2462 * emitting anything other than setting up the constant result.
2464 if (ir
->op
== ir_tg4
) {
2465 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2466 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2467 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2468 dst_reg
result(this, ir
->type
);
2469 this->result
= src_reg(result
);
2470 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2475 /* Should be lowered by do_lower_texture_projection */
2476 assert(!ir
->projector
);
2478 /* Should be lowered */
2479 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2481 /* Generate code to compute all the subexpression trees. This has to be
2482 * done before loading any values into MRFs for the sampler message since
2483 * generating these values may involve SEND messages that need the MRFs.
2486 if (ir
->coordinate
) {
2487 ir
->coordinate
->accept(this);
2488 coordinate
= this->result
;
2491 src_reg shadow_comparitor
;
2492 if (ir
->shadow_comparitor
) {
2493 ir
->shadow_comparitor
->accept(this);
2494 shadow_comparitor
= this->result
;
2497 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2498 src_reg offset_value
;
2499 if (has_nonconstant_offset
) {
2500 ir
->offset
->accept(this);
2501 offset_value
= src_reg(this->result
);
2504 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2505 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2508 lod
= src_reg(0.0f
);
2509 lod_type
= glsl_type::float_type
;
2514 ir
->lod_info
.lod
->accept(this);
2516 lod_type
= ir
->lod_info
.lod
->type
;
2518 case ir_query_levels
:
2520 lod_type
= glsl_type::int_type
;
2523 ir
->lod_info
.sample_index
->accept(this);
2524 sample_index
= this->result
;
2525 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2527 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2528 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
2533 ir
->lod_info
.grad
.dPdx
->accept(this);
2534 dPdx
= this->result
;
2536 ir
->lod_info
.grad
.dPdy
->accept(this);
2537 dPdy
= this->result
;
2539 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2549 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2550 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2551 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2552 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2553 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2554 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2555 case ir_tg4
: opcode
= has_nonconstant_offset
2556 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2557 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2559 unreachable("TXB is not valid for vertex shaders.");
2561 unreachable("LOD is not valid for vertex shaders.");
2563 unreachable("Unrecognized tex op");
2566 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, opcode
);
2568 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2570 brw_texture_offset(ctx
, ir
->offset
->as_constant()->value
.i
,
2571 ir
->offset
->type
->vector_elements
);
2574 /* Stuff the channel select bits in the top of the texture offset */
2575 if (ir
->op
== ir_tg4
)
2576 inst
->offset
|= gather_channel(ir
, sampler
) << 16;
2578 /* The message header is necessary for:
2581 * - Gather channel selection
2582 * - Sampler indices too large to fit in a 4-bit value.
2584 inst
->header_present
=
2585 brw
->gen
< 5 || inst
->offset
!= 0 || ir
->op
== ir_tg4
||
2586 is_high_sampler(brw
, sampler_reg
);
2588 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2589 inst
->dst
= dst_reg(this, ir
->type
);
2590 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2591 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2593 inst
->src
[1] = sampler_reg
;
2595 /* MRF for the first parameter */
2596 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2598 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2599 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2600 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2602 /* Load the coordinate */
2603 /* FINISHME: gl_clamp_mask and saturate */
2604 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2605 int zero_mask
= 0xf & ~coord_mask
;
2607 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2610 if (zero_mask
!= 0) {
2611 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2614 /* Load the shadow comparitor */
2615 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2616 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2618 shadow_comparitor
));
2622 /* Load the LOD info */
2623 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2625 if (brw
->gen
>= 5) {
2626 mrf
= param_base
+ 1;
2627 if (ir
->shadow_comparitor
) {
2628 writemask
= WRITEMASK_Y
;
2629 /* mlen already incremented */
2631 writemask
= WRITEMASK_X
;
2634 } else /* brw->gen == 4 */ {
2636 writemask
= WRITEMASK_W
;
2638 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2639 } else if (ir
->op
== ir_txf
) {
2640 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2641 } else if (ir
->op
== ir_txf_ms
) {
2642 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2644 if (brw
->gen
>= 7) {
2645 /* MCS data is in the first channel of `mcs`, but we need to get it into
2646 * the .y channel of the second vec4 of params, so replicate .x across
2647 * the whole vec4 and then mask off everything except .y
2649 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2650 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2654 } else if (ir
->op
== ir_txd
) {
2655 const glsl_type
*type
= lod_type
;
2657 if (brw
->gen
>= 5) {
2658 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2659 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2660 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2661 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2664 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2665 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2666 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2667 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2668 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2671 if (ir
->shadow_comparitor
) {
2672 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2673 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2674 shadow_comparitor
));
2677 } else /* brw->gen == 4 */ {
2678 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2679 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2682 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2683 if (ir
->shadow_comparitor
) {
2684 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2685 shadow_comparitor
));
2688 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2696 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2697 * spec requires layers.
2699 if (ir
->op
== ir_txs
) {
2700 glsl_type
const *type
= ir
->sampler
->type
;
2701 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2702 type
->sampler_array
) {
2703 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2704 writemask(inst
->dst
, WRITEMASK_Z
),
2705 src_reg(inst
->dst
), src_reg(6));
2709 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2710 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2713 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2717 * Apply workarounds for Gen6 gather with UINT/SINT
2720 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2725 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2726 dst_reg dst_f
= dst
;
2727 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2729 /* Convert from UNORM to UINT */
2730 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2731 emit(MOV(dst
, src_reg(dst_f
)));
2734 /* Reinterpret the UINT value as a signed INT value by
2735 * shifting the sign bit into place, then shifting back
2738 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2739 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2744 * Set up the gather channel based on the swizzle, for gather4.
2747 vec4_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2749 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2750 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2752 case SWIZZLE_X
: return 0;
2754 /* gather4 sampler is broken for green channel on RG32F --
2755 * we must ask for blue instead.
2757 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2760 case SWIZZLE_Z
: return 2;
2761 case SWIZZLE_W
: return 3;
2763 unreachable("Not reached"); /* zero, one swizzles handled already */
2768 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
)
2770 int s
= key
->tex
.swizzles
[sampler
];
2772 this->result
= src_reg(this, ir
->type
);
2773 dst_reg
swizzled_result(this->result
);
2775 if (ir
->op
== ir_query_levels
) {
2776 /* # levels is in .w */
2777 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2778 emit(MOV(swizzled_result
, orig_val
));
2782 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2783 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2784 emit(MOV(swizzled_result
, orig_val
));
2789 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2790 int swizzle
[4] = {0};
2792 for (int i
= 0; i
< 4; i
++) {
2793 switch (GET_SWZ(s
, i
)) {
2795 zero_mask
|= (1 << i
);
2798 one_mask
|= (1 << i
);
2801 copy_mask
|= (1 << i
);
2802 swizzle
[i
] = GET_SWZ(s
, i
);
2808 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2809 swizzled_result
.writemask
= copy_mask
;
2810 emit(MOV(swizzled_result
, orig_val
));
2814 swizzled_result
.writemask
= zero_mask
;
2815 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2819 swizzled_result
.writemask
= one_mask
;
2820 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2825 vec4_visitor::visit(ir_return
*)
2827 unreachable("not reached");
2831 vec4_visitor::visit(ir_discard
*)
2833 unreachable("not reached");
2837 vec4_visitor::visit(ir_if
*ir
)
2839 /* Don't point the annotation at the if statement, because then it plus
2840 * the then and else blocks get printed.
2842 this->base_ir
= ir
->condition
;
2844 if (brw
->gen
== 6) {
2847 enum brw_predicate predicate
;
2848 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2849 emit(IF(predicate
));
2852 visit_instructions(&ir
->then_instructions
);
2854 if (!ir
->else_instructions
.is_empty()) {
2855 this->base_ir
= ir
->condition
;
2856 emit(BRW_OPCODE_ELSE
);
2858 visit_instructions(&ir
->else_instructions
);
2861 this->base_ir
= ir
->condition
;
2862 emit(BRW_OPCODE_ENDIF
);
2866 vec4_visitor::visit(ir_emit_vertex
*)
2868 unreachable("not reached");
2872 vec4_visitor::visit(ir_end_primitive
*)
2874 unreachable("not reached");
2878 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2879 dst_reg dst
, src_reg offset
,
2880 src_reg src0
, src_reg src1
)
2884 /* Set the atomic operation offset. */
2885 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2888 /* Set the atomic operation arguments. */
2889 if (src0
.file
!= BAD_FILE
) {
2890 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2894 if (src1
.file
!= BAD_FILE
) {
2895 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2899 /* Emit the instruction. Note that this maps to the normal SIMD8
2900 * untyped atomic message on Ivy Bridge, but that's OK because
2901 * unused channels will be masked out.
2903 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2904 src_reg(atomic_op
), src_reg(surf_index
));
2910 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
2913 /* Set the surface read offset. */
2914 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
2916 /* Emit the instruction. Note that this maps to the normal SIMD8
2917 * untyped surface read message, but that's OK because unused
2918 * channels will be masked out.
2920 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
,
2921 dst
, src_reg(surf_index
));
2927 vec4_visitor::emit_ndc_computation()
2929 /* Get the position */
2930 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2932 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2933 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2934 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2936 current_annotation
= "NDC";
2937 dst_reg ndc_w
= ndc
;
2938 ndc_w
.writemask
= WRITEMASK_W
;
2939 src_reg pos_w
= pos
;
2940 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2941 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2943 dst_reg ndc_xyz
= ndc
;
2944 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2946 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2950 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
2953 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2954 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2955 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2956 dst_reg header1_w
= header1
;
2957 header1_w
.writemask
= WRITEMASK_W
;
2959 emit(MOV(header1
, 0u));
2961 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2962 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2964 current_annotation
= "Point size";
2965 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2966 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2969 if (key
->userclip_active
) {
2970 current_annotation
= "Clipping flags";
2971 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
2972 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
2974 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2975 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
2976 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
2978 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2979 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
2980 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
2981 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
2984 /* i965 clipping workaround:
2985 * 1) Test for -ve rhw
2987 * set ndc = (0,0,0,0)
2990 * Later, clipping will detect ucp[6] and ensure the primitive is
2991 * clipped against all fixed planes.
2993 if (brw
->has_negative_rhw_bug
) {
2994 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2995 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2996 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2997 vec4_instruction
*inst
;
2998 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2999 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3000 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
3001 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3004 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
3005 } else if (brw
->gen
< 6) {
3006 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
3008 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
3009 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
3010 dst_reg reg_w
= reg
;
3011 reg_w
.writemask
= WRITEMASK_W
;
3012 emit(MOV(reg_w
, src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
3014 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
3015 dst_reg reg_y
= reg
;
3016 reg_y
.writemask
= WRITEMASK_Y
;
3017 reg_y
.type
= BRW_REGISTER_TYPE_D
;
3018 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
3020 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
3021 dst_reg reg_z
= reg
;
3022 reg_z
.writemask
= WRITEMASK_Z
;
3023 reg_z
.type
= BRW_REGISTER_TYPE_D
;
3024 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
3030 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
3032 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
3034 * "If a linked set of shaders forming the vertex stage contains no
3035 * static write to gl_ClipVertex or gl_ClipDistance, but the
3036 * application has requested clipping against user clip planes through
3037 * the API, then the coordinate written to gl_Position is used for
3038 * comparison against the user clip planes."
3040 * This function is only called if the shader didn't write to
3041 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
3042 * if the user wrote to it; otherwise we use gl_Position.
3044 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
3045 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
3046 clip_vertex
= VARYING_SLOT_POS
;
3049 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
3051 reg
.writemask
= 1 << i
;
3053 src_reg(output_reg
[clip_vertex
]),
3054 src_reg(this->userplane
[i
+ offset
])));
3059 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
3061 assert (varying
< VARYING_SLOT_MAX
);
3062 reg
.type
= output_reg
[varying
].type
;
3063 current_annotation
= output_reg_annotation
[varying
];
3064 /* Copy the register, saturating if necessary */
3065 vec4_instruction
*inst
= emit(MOV(reg
,
3066 src_reg(output_reg
[varying
])));
3067 if ((varying
== VARYING_SLOT_COL0
||
3068 varying
== VARYING_SLOT_COL1
||
3069 varying
== VARYING_SLOT_BFC0
||
3070 varying
== VARYING_SLOT_BFC1
) &&
3071 key
->clamp_vertex_color
) {
3072 inst
->saturate
= true;
3077 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
3079 reg
.type
= BRW_REGISTER_TYPE_F
;
3082 case VARYING_SLOT_PSIZ
:
3084 /* PSIZ is always in slot 0, and is coupled with other flags. */
3085 current_annotation
= "indices, point width, clip flags";
3086 emit_psiz_and_flags(reg
);
3089 case BRW_VARYING_SLOT_NDC
:
3090 current_annotation
= "NDC";
3091 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
3093 case VARYING_SLOT_POS
:
3094 current_annotation
= "gl_Position";
3095 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
3097 case VARYING_SLOT_EDGE
:
3098 /* This is present when doing unfilled polygons. We're supposed to copy
3099 * the edge flag from the user-provided vertex array
3100 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3101 * of that attribute (starts as 1.0f). This is then used in clipping to
3102 * determine which edges should be drawn as wireframe.
3104 current_annotation
= "edge flag";
3105 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3106 glsl_type::float_type
, WRITEMASK_XYZW
))));
3108 case BRW_VARYING_SLOT_PAD
:
3109 /* No need to write to this slot */
3112 emit_generic_urb_slot(reg
, varying
);
3118 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
3120 if (brw
->gen
>= 6) {
3121 /* URB data written (does not include the message header reg) must
3122 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3123 * section 5.4.3.2.2: URB_INTERLEAVED.
3125 * URB entries are allocated on a multiple of 1024 bits, so an
3126 * extra 128 bits written here to make the end align to 256 is
3129 if ((mlen
% 2) != 1)
3138 * Generates the VUE payload plus the necessary URB write instructions to
3141 * The VUE layout is documented in Volume 2a.
3144 vec4_visitor::emit_vertex()
3146 /* MRF 0 is reserved for the debugger, so start with message header
3151 /* In the process of generating our URB write message contents, we
3152 * may need to unspill a register or load from an array. Those
3153 * reads would use MRFs 14-15.
3155 int max_usable_mrf
= 13;
3157 /* The following assertion verifies that max_usable_mrf causes an
3158 * even-numbered amount of URB write data, which will meet gen6's
3159 * requirements for length alignment.
3161 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3163 /* First mrf is the g0-based message header containing URB handles and
3166 emit_urb_write_header(mrf
++);
3169 emit_ndc_computation();
3172 /* Lower legacy ff and ClipVertex clipping to clip distances */
3173 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3174 current_annotation
= "user clip distances";
3176 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3177 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3179 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3180 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3183 /* We may need to split this up into several URB writes, so do them in a
3187 bool complete
= false;
3189 /* URB offset is in URB row increments, and each of our MRFs is half of
3190 * one of those, since we're doing interleaved writes.
3192 int offset
= slot
/ 2;
3195 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3196 emit_urb_slot(dst_reg(MRF
, mrf
++),
3197 prog_data
->vue_map
.slot_to_varying
[slot
]);
3199 /* If this was max_usable_mrf, we can't fit anything more into this
3202 if (mrf
> max_usable_mrf
) {
3208 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3209 current_annotation
= "URB write";
3210 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3211 inst
->base_mrf
= base_mrf
;
3212 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
3213 inst
->offset
+= offset
;
3219 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3220 src_reg
*reladdr
, int reg_offset
)
3222 /* Because we store the values to scratch interleaved like our
3223 * vertex data, we need to scale the vec4 index by 2.
3225 int message_header_scale
= 2;
3227 /* Pre-gen6, the message header uses byte offsets instead of vec4
3228 * (16-byte) offset units.
3231 message_header_scale
*= 16;
3234 src_reg index
= src_reg(this, glsl_type::int_type
);
3236 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3237 src_reg(reg_offset
)));
3238 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3239 src_reg(message_header_scale
)));
3243 return src_reg(reg_offset
* message_header_scale
);
3248 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3249 src_reg
*reladdr
, int reg_offset
)
3252 src_reg index
= src_reg(this, glsl_type::int_type
);
3254 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3255 src_reg(reg_offset
)));
3257 /* Pre-gen6, the message header uses byte offsets instead of vec4
3258 * (16-byte) offset units.
3261 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3265 } else if (brw
->gen
>= 8) {
3266 /* Store the offset in a GRF so we can send-from-GRF. */
3267 src_reg offset
= src_reg(this, glsl_type::int_type
);
3268 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3271 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
3272 return src_reg(reg_offset
* message_header_scale
);
3277 * Emits an instruction before @inst to load the value named by @orig_src
3278 * from scratch space at @base_offset to @temp.
3280 * @base_offset is measured in 32-byte units (the size of a register).
3283 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3284 dst_reg temp
, src_reg orig_src
,
3287 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3288 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3291 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3295 * Emits an instruction after @inst to store the value to be written
3296 * to @orig_dst to scratch space at @base_offset, from @temp.
3298 * @base_offset is measured in 32-byte units (the size of a register).
3301 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3304 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3305 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3308 /* Create a temporary register to store *inst's result in.
3310 * We have to be careful in MOVing from our temporary result register in
3311 * the scratch write. If we swizzle from channels of the temporary that
3312 * weren't initialized, it will confuse live interval analysis, which will
3313 * make spilling fail to make progress.
3315 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
3316 temp
.type
= inst
->dst
.type
;
3317 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
3319 for (int i
= 0; i
< 4; i
++)
3320 if (inst
->dst
.writemask
& (1 << i
))
3323 swizzles
[i
] = first_writemask_chan
;
3324 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3325 swizzles
[2], swizzles
[3]);
3327 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3328 inst
->dst
.writemask
));
3329 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3330 write
->predicate
= inst
->predicate
;
3331 write
->ir
= inst
->ir
;
3332 write
->annotation
= inst
->annotation
;
3333 inst
->insert_after(block
, write
);
3335 inst
->dst
.file
= temp
.file
;
3336 inst
->dst
.reg
= temp
.reg
;
3337 inst
->dst
.reg_offset
= temp
.reg_offset
;
3338 inst
->dst
.reladdr
= NULL
;
3342 * We can't generally support array access in GRF space, because a
3343 * single instruction's destination can only span 2 contiguous
3344 * registers. So, we send all GRF arrays that get variable index
3345 * access to scratch space.
3348 vec4_visitor::move_grf_array_access_to_scratch()
3350 int scratch_loc
[this->virtual_grf_count
];
3351 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3353 /* First, calculate the set of virtual GRFs that need to be punted
3354 * to scratch due to having any array access on them, and where in
3357 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3358 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3359 scratch_loc
[inst
->dst
.reg
] == -1) {
3360 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3361 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
3364 for (int i
= 0 ; i
< 3; i
++) {
3365 src_reg
*src
= &inst
->src
[i
];
3367 if (src
->file
== GRF
&& src
->reladdr
&&
3368 scratch_loc
[src
->reg
] == -1) {
3369 scratch_loc
[src
->reg
] = c
->last_scratch
;
3370 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
3375 /* Now, for anything that will be accessed through scratch, rewrite
3376 * it to load/store. Note that this is a _safe list walk, because
3377 * we may generate a new scratch_write instruction after the one
3380 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3381 /* Set up the annotation tracking for new generated instructions. */
3383 current_annotation
= inst
->annotation
;
3385 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3386 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3389 for (int i
= 0 ; i
< 3; i
++) {
3390 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3393 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3395 emit_scratch_read(block
, inst
, temp
, inst
->src
[i
],
3396 scratch_loc
[inst
->src
[i
].reg
]);
3398 inst
->src
[i
].file
= temp
.file
;
3399 inst
->src
[i
].reg
= temp
.reg
;
3400 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3401 inst
->src
[i
].reladdr
= NULL
;
3407 * Emits an instruction before @inst to load the value named by @orig_src
3408 * from the pull constant buffer (surface) at @base_offset to @temp.
3411 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3412 dst_reg temp
, src_reg orig_src
,
3415 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3416 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3417 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3419 vec4_instruction
*load
;
3421 if (brw
->gen
>= 7) {
3422 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3423 grf_offset
.type
= offset
.type
;
3424 emit_before(block
, inst
, MOV(grf_offset
, offset
));
3426 load
= new(mem_ctx
) vec4_instruction(this,
3427 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3428 temp
, index
, src_reg(grf_offset
));
3430 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
3431 temp
, index
, offset
);
3432 load
->base_mrf
= 14;
3435 emit_before(block
, inst
, load
);
3439 * Implements array access of uniforms by inserting a
3440 * PULL_CONSTANT_LOAD instruction.
3442 * Unlike temporary GRF array access (where we don't support it due to
3443 * the difficulty of doing relative addressing on instruction
3444 * destinations), we could potentially do array access of uniforms
3445 * that were loaded in GRF space as push constants. In real-world
3446 * usage we've seen, though, the arrays being used are always larger
3447 * than we could load as push constants, so just always move all
3448 * uniform array access out to a pull constant buffer.
3451 vec4_visitor::move_uniform_array_access_to_pull_constants()
3453 int pull_constant_loc
[this->uniforms
];
3454 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3455 bool nested_reladdr
;
3457 /* Walk through and find array access of uniforms. Put a copy of that
3458 * uniform in the pull constant buffer.
3460 * Note that we don't move constant-indexed accesses to arrays. No
3461 * testing has been done of the performance impact of this choice.
3464 nested_reladdr
= false;
3466 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3467 for (int i
= 0 ; i
< 3; i
++) {
3468 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3471 int uniform
= inst
->src
[i
].reg
;
3473 if (inst
->src
[i
].reladdr
->reladdr
)
3474 nested_reladdr
= true; /* will need another pass */
3476 /* If this array isn't already present in the pull constant buffer,
3479 if (pull_constant_loc
[uniform
] == -1) {
3480 const gl_constant_value
**values
=
3481 &stage_prog_data
->param
[uniform
* 4];
3483 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3485 assert(uniform
< uniform_array_size
);
3486 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3487 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3492 /* Set up the annotation tracking for new generated instructions. */
3494 current_annotation
= inst
->annotation
;
3496 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3498 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3499 pull_constant_loc
[uniform
]);
3501 inst
->src
[i
].file
= temp
.file
;
3502 inst
->src
[i
].reg
= temp
.reg
;
3503 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3504 inst
->src
[i
].reladdr
= NULL
;
3507 } while (nested_reladdr
);
3509 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3510 * no need to track them as larger-than-vec4 objects. This will be
3511 * relied on in cutting out unused uniform vectors from push
3514 split_uniform_registers();
3518 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3520 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3524 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3525 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3529 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3530 struct brw_vec4_compile
*c
,
3531 struct gl_program
*prog
,
3532 const struct brw_vec4_prog_key
*key
,
3533 struct brw_vec4_prog_data
*prog_data
,
3534 struct gl_shader_program
*shader_prog
,
3535 gl_shader_stage stage
,
3539 shader_time_shader_type st_base
,
3540 shader_time_shader_type st_written
,
3541 shader_time_shader_type st_reset
)
3542 : backend_visitor(brw
, shader_prog
, prog
, &prog_data
->base
, stage
),
3545 prog_data(prog_data
),
3546 sanity_param_count(0),
3548 first_non_payload_grf(0),
3549 need_all_constants_in_pull_buffer(false),
3550 debug_flag(debug_flag
),
3551 no_spills(no_spills
),
3553 st_written(st_written
),
3556 this->mem_ctx
= mem_ctx
;
3557 this->failed
= false;
3559 this->base_ir
= NULL
;
3560 this->current_annotation
= NULL
;
3561 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3563 this->variable_ht
= hash_table_ctor(0,
3564 hash_table_pointer_hash
,
3565 hash_table_pointer_compare
);
3567 this->virtual_grf_start
= NULL
;
3568 this->virtual_grf_end
= NULL
;
3569 this->virtual_grf_sizes
= NULL
;
3570 this->virtual_grf_count
= 0;
3571 this->virtual_grf_reg_map
= NULL
;
3572 this->virtual_grf_reg_count
= 0;
3573 this->virtual_grf_array_size
= 0;
3574 this->live_intervals_valid
= false;
3576 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3580 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3581 * at least one. See setup_uniforms() in brw_vec4.cpp.
3583 this->uniform_array_size
= 1;
3585 this->uniform_array_size
= MAX2(stage_prog_data
->nr_params
, 1);
3588 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3589 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3592 vec4_visitor::~vec4_visitor()
3594 hash_table_dtor(this->variable_ht
);
3599 vec4_visitor::fail(const char *format
, ...)
3609 va_start(va
, format
);
3610 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3612 msg
= ralloc_asprintf(mem_ctx
, "vec4 compile failed: %s\n", msg
);
3614 this->fail_msg
= msg
;
3617 fprintf(stderr
, "%s", msg
);
3621 } /* namespace brw */