2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
27 #include "program/sampler.h"
31 vec4_instruction::vec4_instruction(enum opcode opcode
, const dst_reg
&dst
,
32 const src_reg
&src0
, const src_reg
&src1
,
35 this->opcode
= opcode
;
40 this->saturate
= false;
41 this->force_writemask_all
= false;
42 this->no_dd_clear
= false;
43 this->no_dd_check
= false;
44 this->writes_accumulator
= false;
45 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
46 this->predicate
= BRW_PREDICATE_NONE
;
47 this->predicate_inverse
= false;
49 this->regs_written
= (dst
.file
== BAD_FILE
? 0 : 1);
50 this->shadow_compare
= false;
52 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
53 this->header_size
= 0;
54 this->flag_subreg
= 0;
58 this->annotation
= NULL
;
62 vec4_visitor::emit(vec4_instruction
*inst
)
64 inst
->ir
= this->base_ir
;
65 inst
->annotation
= this->current_annotation
;
67 this->instructions
.push_tail(inst
);
73 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
74 vec4_instruction
*new_inst
)
76 new_inst
->ir
= inst
->ir
;
77 new_inst
->annotation
= inst
->annotation
;
79 inst
->insert_before(block
, new_inst
);
85 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
86 const src_reg
&src1
, const src_reg
&src2
)
88 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
, src2
));
93 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
96 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
, src1
));
100 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
102 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
, src0
));
106 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
108 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst
));
112 vec4_visitor::emit(enum opcode opcode
)
114 return emit(new(mem_ctx
) vec4_instruction(opcode
, dst_reg()));
119 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
121 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, src0); \
126 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
127 const src_reg &src1) \
129 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
133 #define ALU2_ACC(op) \
135 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
136 const src_reg &src1) \
138 vec4_instruction *inst = new(mem_ctx) vec4_instruction( \
139 BRW_OPCODE_##op, dst, src0, src1); \
140 inst->writes_accumulator = true; \
146 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
147 const src_reg &src1, const src_reg &src2) \
149 assert(devinfo->gen >= 6); \
150 return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst, \
187 /** Gen4 predicated IF. */
189 vec4_visitor::IF(enum brw_predicate predicate
)
191 vec4_instruction
*inst
;
193 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
);
194 inst
->predicate
= predicate
;
199 /** Gen6 IF with embedded comparison. */
201 vec4_visitor::IF(src_reg src0
, src_reg src1
,
202 enum brw_conditional_mod condition
)
204 assert(devinfo
->gen
== 6);
206 vec4_instruction
*inst
;
208 resolve_ud_negate(&src0
);
209 resolve_ud_negate(&src1
);
211 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_IF
, dst_null_d(),
213 inst
->conditional_mod
= condition
;
219 * CMP: Sets the low bit of the destination channels with the result
220 * of the comparison, while the upper bits are undefined, and updates
221 * the flag register with the packed 16 bits of the result.
224 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
225 enum brw_conditional_mod condition
)
227 vec4_instruction
*inst
;
229 /* Take the instruction:
231 * CMP null<d> src0<f> src1<f>
233 * Original gen4 does type conversion to the destination type before
234 * comparison, producing garbage results for floating point comparisons.
236 * The destination type doesn't matter on newer generations, so we set the
237 * type to match src0 so we can compact the instruction.
239 dst
.type
= src0
.type
;
241 resolve_ud_negate(&src0
);
242 resolve_ud_negate(&src1
);
244 inst
= new(mem_ctx
) vec4_instruction(BRW_OPCODE_CMP
, dst
, src0
, src1
);
245 inst
->conditional_mod
= condition
;
251 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
253 vec4_instruction
*inst
;
255 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_READ
,
257 inst
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
) + 1;
264 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
265 const src_reg
&index
)
267 vec4_instruction
*inst
;
269 inst
= new(mem_ctx
) vec4_instruction(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
271 inst
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
);
278 vec4_visitor::fix_3src_operand(const src_reg
&src
)
280 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
281 * able to use vertical stride of zero to replicate the vec4 uniform, like
283 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
285 * But you can't, since vertical stride is always four in three-source
286 * instructions. Instead, insert a MOV instruction to do the replication so
287 * that the three-source instruction can consume it.
290 /* The MOV is only needed if the source is a uniform or immediate. */
291 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
294 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
297 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
298 expanded
.type
= src
.type
;
299 emit(VEC4_OPCODE_UNPACK_UNIFORM
, expanded
, src
);
300 return src_reg(expanded
);
304 vec4_visitor::resolve_source_modifiers(const src_reg
&src
)
306 if (!src
.abs
&& !src
.negate
)
309 dst_reg resolved
= dst_reg(this, glsl_type::ivec4_type
);
310 resolved
.type
= src
.type
;
311 emit(MOV(resolved
, src
));
313 return src_reg(resolved
);
317 vec4_visitor::fix_math_operand(const src_reg
&src
)
319 if (devinfo
->gen
< 6 || devinfo
->gen
>= 8 || src
.file
== BAD_FILE
)
322 /* The gen6 math instruction ignores the source modifiers --
323 * swizzle, abs, negate, and at least some parts of the register
324 * region description.
326 * Rather than trying to enumerate all these cases, *always* expand the
327 * operand to a temp GRF for gen6.
329 * For gen7, keep the operand as-is, except if immediate, which gen7 still
333 if (devinfo
->gen
== 7 && src
.file
!= IMM
)
336 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
337 expanded
.type
= src
.type
;
338 emit(MOV(expanded
, src
));
339 return src_reg(expanded
);
343 vec4_visitor::emit_math(enum opcode opcode
,
345 const src_reg
&src0
, const src_reg
&src1
)
347 vec4_instruction
*math
=
348 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
350 if (devinfo
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
351 /* MATH on Gen6 must be align1, so we can't do writemasks. */
352 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
353 math
->dst
.type
= dst
.type
;
354 math
= emit(MOV(dst
, src_reg(math
->dst
)));
355 } else if (devinfo
->gen
< 6) {
357 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
364 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
366 if (devinfo
->gen
< 7) {
367 unreachable("ir_unop_pack_half_2x16 should be lowered");
370 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
371 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
373 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
375 * Because this instruction does not have a 16-bit floating-point type,
376 * the destination data type must be Word (W).
378 * The destination must be DWord-aligned and specify a horizontal stride
379 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
380 * each destination channel and the upper word is not modified.
382 * The above restriction implies that the f32to16 instruction must use
383 * align1 mode, because only in align1 mode is it possible to specify
384 * horizontal stride. We choose here to defy the hardware docs and emit
385 * align16 instructions.
387 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
388 * instructions. I was partially successful in that the code passed all
389 * tests. However, the code was dubiously correct and fragile, and the
390 * tests were not harsh enough to probe that frailty. Not trusting the
391 * code, I chose instead to remain in align16 mode in defiance of the hw
394 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
395 * simulator, emitting a f32to16 in align16 mode with UD as destination
396 * data type is safe. The behavior differs from that specified in the PRM
397 * in that the upper word of each destination channel is cleared to 0.
400 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
401 src_reg
tmp_src(tmp_dst
);
404 /* Verify the undocumented behavior on which the following instructions
405 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
406 * then the result of the bit-or instruction below will be incorrect.
408 * You should inspect the disasm output in order to verify that the MOV is
409 * not optimized away.
411 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
414 /* Give tmp the form below, where "." means untouched.
417 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
419 * That the upper word of each write-channel be 0 is required for the
420 * following bit-shift and bit-or instructions to work. Note that this
421 * relies on the undocumented hardware behavior mentioned above.
423 tmp_dst
.writemask
= WRITEMASK_XY
;
424 emit(F32TO16(tmp_dst
, src0
));
426 /* Give the write-channels of dst the form:
429 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
430 emit(SHL(dst
, tmp_src
, src_reg(16u)));
432 /* Finally, give the write-channels of dst the form of packHalf2x16's
436 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
437 emit(OR(dst
, src_reg(dst
), tmp_src
));
441 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
443 if (devinfo
->gen
< 7) {
444 unreachable("ir_unop_unpack_half_2x16 should be lowered");
447 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
448 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
450 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
452 * Because this instruction does not have a 16-bit floating-point type,
453 * the source data type must be Word (W). The destination type must be
456 * To use W as the source data type, we must adjust horizontal strides,
457 * which is only possible in align1 mode. All my [chadv] attempts at
458 * emitting align1 instructions for unpackHalf2x16 failed to pass the
459 * Piglit tests, so I gave up.
461 * I've verified that, on gen7 hardware and the simulator, it is safe to
462 * emit f16to32 in align16 mode with UD as source data type.
465 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
466 src_reg
tmp_src(tmp_dst
);
468 tmp_dst
.writemask
= WRITEMASK_X
;
469 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
471 tmp_dst
.writemask
= WRITEMASK_Y
;
472 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
474 dst
.writemask
= WRITEMASK_XY
;
475 emit(F16TO32(dst
, tmp_src
));
479 vec4_visitor::emit_unpack_unorm_4x8(const dst_reg
&dst
, src_reg src0
)
481 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
482 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
483 * is not suitable to generate the shift values, but we can use the packed
484 * vector float and a type-converting MOV.
486 dst_reg
shift(this, glsl_type::uvec4_type
);
487 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
489 dst_reg
shifted(this, glsl_type::uvec4_type
);
490 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
491 emit(SHR(shifted
, src0
, src_reg(shift
)));
493 shifted
.type
= BRW_REGISTER_TYPE_UB
;
494 dst_reg
f(this, glsl_type::vec4_type
);
495 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
497 emit(MUL(dst
, src_reg(f
), src_reg(1.0f
/ 255.0f
)));
501 vec4_visitor::emit_unpack_snorm_4x8(const dst_reg
&dst
, src_reg src0
)
503 /* Instead of splitting the 32-bit integer, shifting, and ORing it back
504 * together, we can shift it by <0, 8, 16, 24>. The packed integer immediate
505 * is not suitable to generate the shift values, but we can use the packed
506 * vector float and a type-converting MOV.
508 dst_reg
shift(this, glsl_type::uvec4_type
);
509 emit(MOV(shift
, src_reg(0x00, 0x60, 0x70, 0x78)));
511 dst_reg
shifted(this, glsl_type::uvec4_type
);
512 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
513 emit(SHR(shifted
, src0
, src_reg(shift
)));
515 shifted
.type
= BRW_REGISTER_TYPE_B
;
516 dst_reg
f(this, glsl_type::vec4_type
);
517 emit(VEC4_OPCODE_MOV_BYTES
, f
, src_reg(shifted
));
519 dst_reg
scaled(this, glsl_type::vec4_type
);
520 emit(MUL(scaled
, src_reg(f
), src_reg(1.0f
/ 127.0f
)));
522 dst_reg
max(this, glsl_type::vec4_type
);
523 emit_minmax(BRW_CONDITIONAL_GE
, max
, src_reg(scaled
), src_reg(-1.0f
));
524 emit_minmax(BRW_CONDITIONAL_L
, dst
, src_reg(max
), src_reg(1.0f
));
528 vec4_visitor::emit_pack_unorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
530 dst_reg
saturated(this, glsl_type::vec4_type
);
531 vec4_instruction
*inst
= emit(MOV(saturated
, src0
));
532 inst
->saturate
= true;
534 dst_reg
scaled(this, glsl_type::vec4_type
);
535 emit(MUL(scaled
, src_reg(saturated
), src_reg(255.0f
)));
537 dst_reg
rounded(this, glsl_type::vec4_type
);
538 emit(RNDE(rounded
, src_reg(scaled
)));
540 dst_reg
u(this, glsl_type::uvec4_type
);
541 emit(MOV(u
, src_reg(rounded
)));
544 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
548 vec4_visitor::emit_pack_snorm_4x8(const dst_reg
&dst
, const src_reg
&src0
)
550 dst_reg
max(this, glsl_type::vec4_type
);
551 emit_minmax(BRW_CONDITIONAL_GE
, max
, src0
, src_reg(-1.0f
));
553 dst_reg
min(this, glsl_type::vec4_type
);
554 emit_minmax(BRW_CONDITIONAL_L
, min
, src_reg(max
), src_reg(1.0f
));
556 dst_reg
scaled(this, glsl_type::vec4_type
);
557 emit(MUL(scaled
, src_reg(min
), src_reg(127.0f
)));
559 dst_reg
rounded(this, glsl_type::vec4_type
);
560 emit(RNDE(rounded
, src_reg(scaled
)));
562 dst_reg
i(this, glsl_type::ivec4_type
);
563 emit(MOV(i
, src_reg(rounded
)));
566 emit(VEC4_OPCODE_PACK_BYTES
, dst
, bytes
);
570 * Returns the minimum number of vec4 elements needed to pack a type.
572 * For simple types, it will return 1 (a single vec4); for matrices, the
573 * number of columns; for array and struct, the sum of the vec4_size of
574 * each of its elements; and for sampler and atomic, zero.
576 * This method is useful to calculate how much register space is needed to
577 * store a particular type.
580 type_size_vec4(const struct glsl_type
*type
)
585 switch (type
->base_type
) {
588 case GLSL_TYPE_FLOAT
:
590 if (type
->is_matrix()) {
591 return type
->matrix_columns
;
593 /* Regardless of size of vector, it gets a vec4. This is bad
594 * packing for things like floats, but otherwise arrays become a
595 * mess. Hopefully a later pass over the code can pack scalars
596 * down if appropriate.
600 case GLSL_TYPE_ARRAY
:
601 assert(type
->length
> 0);
602 return type_size_vec4(type
->fields
.array
) * type
->length
;
603 case GLSL_TYPE_STRUCT
:
605 for (i
= 0; i
< type
->length
; i
++) {
606 size
+= type_size_vec4(type
->fields
.structure
[i
].type
);
609 case GLSL_TYPE_SUBROUTINE
:
612 case GLSL_TYPE_SAMPLER
:
613 /* Samplers take up no register space, since they're baked in at
617 case GLSL_TYPE_ATOMIC_UINT
:
619 case GLSL_TYPE_IMAGE
:
620 return DIV_ROUND_UP(BRW_IMAGE_PARAM_SIZE
, 4);
622 case GLSL_TYPE_DOUBLE
:
623 case GLSL_TYPE_ERROR
:
624 case GLSL_TYPE_INTERFACE
:
625 unreachable("not reached");
631 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
636 this->nr
= v
->alloc
.allocate(type_size_vec4(type
));
638 if (type
->is_array() || type
->is_record()) {
639 this->swizzle
= BRW_SWIZZLE_NOOP
;
641 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
644 this->type
= brw_type_for_base_type(type
);
647 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
654 this->nr
= v
->alloc
.allocate(type_size_vec4(type
) * size
);
656 this->swizzle
= BRW_SWIZZLE_NOOP
;
658 this->type
= brw_type_for_base_type(type
);
661 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
666 this->nr
= v
->alloc
.allocate(type_size_vec4(type
));
668 if (type
->is_array() || type
->is_record()) {
669 this->writemask
= WRITEMASK_XYZW
;
671 this->writemask
= (1 << type
->vector_elements
) - 1;
674 this->type
= brw_type_for_base_type(type
);
678 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
679 src_reg src0
, src_reg src1
)
681 vec4_instruction
*inst
;
683 if (devinfo
->gen
>= 6) {
684 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
685 inst
->conditional_mod
= conditionalmod
;
687 emit(CMP(dst
, src0
, src1
, conditionalmod
));
689 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
690 inst
->predicate
= BRW_PREDICATE_NORMAL
;
697 vec4_visitor::emit_lrp(const dst_reg
&dst
,
698 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
700 if (devinfo
->gen
>= 6) {
701 /* Note that the instruction's argument order is reversed from GLSL
704 return emit(LRP(dst
, fix_3src_operand(a
), fix_3src_operand(y
),
705 fix_3src_operand(x
)));
707 /* Earlier generations don't support three source operations, so we
708 * need to emit x*(1-a) + y*a.
710 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
711 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
712 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
713 y_times_a
.writemask
= dst
.writemask
;
714 one_minus_a
.writemask
= dst
.writemask
;
715 x_times_one_minus_a
.writemask
= dst
.writemask
;
717 emit(MUL(y_times_a
, y
, a
));
718 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
719 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
720 return emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
725 * Emits the instructions needed to perform a pull constant load. before_block
726 * and before_inst can be NULL in which case the instruction will be appended
727 * to the end of the instruction list.
730 vec4_visitor::emit_pull_constant_load_reg(dst_reg dst
,
733 bblock_t
*before_block
,
734 vec4_instruction
*before_inst
)
736 assert((before_inst
== NULL
&& before_block
== NULL
) ||
737 (before_inst
&& before_block
));
739 vec4_instruction
*pull
;
741 if (devinfo
->gen
>= 9) {
742 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
743 src_reg
header(this, glsl_type::uvec4_type
, 2);
746 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
750 emit_before(before_block
, before_inst
, pull
);
754 dst_reg index_reg
= retype(offset(dst_reg(header
), 1),
756 pull
= MOV(writemask(index_reg
, WRITEMASK_X
), offset_reg
);
759 emit_before(before_block
, before_inst
, pull
);
763 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
768 pull
->header_size
= 1;
769 } else if (devinfo
->gen
>= 7) {
770 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
772 grf_offset
.type
= offset_reg
.type
;
774 pull
= MOV(grf_offset
, offset_reg
);
777 emit_before(before_block
, before_inst
, pull
);
781 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
784 src_reg(grf_offset
));
787 pull
= new(mem_ctx
) vec4_instruction(VS_OPCODE_PULL_CONSTANT_LOAD
,
791 pull
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
796 emit_before(before_block
, before_inst
, pull
);
802 vec4_visitor::emit_uniformize(const src_reg
&src
)
804 const src_reg
chan_index(this, glsl_type::uint_type
);
805 const dst_reg dst
= retype(dst_reg(this, glsl_type::uint_type
),
808 emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, dst_reg(chan_index
))
809 ->force_writemask_all
= true;
810 emit(SHADER_OPCODE_BROADCAST
, dst
, src
, chan_index
)
811 ->force_writemask_all
= true;
817 vec4_visitor::emit_mcs_fetch(const glsl_type
*coordinate_type
,
818 src_reg coordinate
, src_reg sampler
)
820 vec4_instruction
*inst
=
821 new(mem_ctx
) vec4_instruction(SHADER_OPCODE_TXF_MCS
,
822 dst_reg(this, glsl_type::uvec4_type
));
824 inst
->src
[1] = sampler
;
828 if (devinfo
->gen
>= 9) {
829 /* Gen9+ needs a message header in order to use SIMD4x2 mode */
830 vec4_instruction
*header_inst
= new(mem_ctx
)
831 vec4_instruction(VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
,
832 dst_reg(MRF
, inst
->base_mrf
));
837 inst
->header_size
= 1;
838 param_base
= inst
->base_mrf
+ 1;
841 param_base
= inst
->base_mrf
;
844 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
845 int coord_mask
= (1 << coordinate_type
->vector_elements
) - 1;
846 int zero_mask
= 0xf & ~coord_mask
;
848 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, coord_mask
),
851 emit(MOV(dst_reg(MRF
, param_base
, coordinate_type
, zero_mask
),
855 return src_reg(inst
->dst
);
859 vec4_visitor::is_high_sampler(src_reg sampler
)
861 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
864 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
868 vec4_visitor::emit_texture(ir_texture_opcode op
,
870 const glsl_type
*dest_type
,
872 int coord_components
,
873 src_reg shadow_comparitor
,
874 src_reg lod
, src_reg lod2
,
875 src_reg sample_index
,
876 uint32_t constant_offset
,
877 src_reg offset_value
,
883 /* The sampler can only meaningfully compute LOD for fragment shader
884 * messages. For all other stages, we change the opcode to TXL and hardcode
887 * textureQueryLevels() is implemented in terms of TXS so we need to pass a
888 * valid LOD argument.
890 if (op
== ir_tex
|| op
== ir_query_levels
) {
891 assert(lod
.file
== BAD_FILE
);
897 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
898 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
899 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
900 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
901 case ir_txf_ms
: opcode
= (devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W
:
902 SHADER_OPCODE_TXF_CMS
); break;
903 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
904 case ir_tg4
: opcode
= offset_value
.file
!= BAD_FILE
905 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
906 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
907 case ir_texture_samples
: opcode
= SHADER_OPCODE_SAMPLEINFO
; break;
909 unreachable("TXB is not valid for vertex shaders.");
911 unreachable("LOD is not valid for vertex shaders.");
913 unreachable("Unrecognized tex op");
916 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(
917 opcode
, dst_reg(this, dest_type
));
919 inst
->offset
= constant_offset
;
921 /* The message header is necessary for:
923 * - Gen9+ for selecting SIMD4x2
925 * - Gather channel selection
926 * - Sampler indices too large to fit in a 4-bit value.
927 * - Sampleinfo message - takes no parameters, but mlen = 0 is illegal
930 (devinfo
->gen
< 5 || devinfo
->gen
>= 9 ||
931 inst
->offset
!= 0 || op
== ir_tg4
||
932 op
== ir_texture_samples
||
933 is_high_sampler(sampler_reg
)) ? 1 : 0;
935 inst
->mlen
= inst
->header_size
;
936 inst
->dst
.writemask
= WRITEMASK_XYZW
;
937 inst
->shadow_compare
= shadow_comparitor
.file
!= BAD_FILE
;
939 inst
->src
[1] = sampler_reg
;
941 /* MRF for the first parameter */
942 int param_base
= inst
->base_mrf
+ inst
->header_size
;
944 if (op
== ir_txs
|| op
== ir_query_levels
) {
945 int writemask
= devinfo
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
946 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, writemask
), lod
));
948 } else if (op
== ir_texture_samples
) {
949 inst
->dst
.writemask
= WRITEMASK_X
;
951 /* Load the coordinate */
952 /* FINISHME: gl_clamp_mask and saturate */
953 int coord_mask
= (1 << coord_components
) - 1;
954 int zero_mask
= 0xf & ~coord_mask
;
956 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, coord_mask
),
960 if (zero_mask
!= 0) {
961 emit(MOV(dst_reg(MRF
, param_base
, coordinate
.type
, zero_mask
),
964 /* Load the shadow comparitor */
965 if (shadow_comparitor
.file
!= BAD_FILE
&& op
!= ir_txd
&& (op
!= ir_tg4
|| offset_value
.file
== BAD_FILE
)) {
966 emit(MOV(dst_reg(MRF
, param_base
+ 1, shadow_comparitor
.type
,
972 /* Load the LOD info */
973 if (op
== ir_tex
|| op
== ir_txl
) {
975 if (devinfo
->gen
>= 5) {
976 mrf
= param_base
+ 1;
977 if (shadow_comparitor
.file
!= BAD_FILE
) {
978 writemask
= WRITEMASK_Y
;
979 /* mlen already incremented */
981 writemask
= WRITEMASK_X
;
984 } else /* devinfo->gen == 4 */ {
986 writemask
= WRITEMASK_W
;
988 emit(MOV(dst_reg(MRF
, mrf
, lod
.type
, writemask
), lod
));
989 } else if (op
== ir_txf
) {
990 emit(MOV(dst_reg(MRF
, param_base
, lod
.type
, WRITEMASK_W
), lod
));
991 } else if (op
== ir_txf_ms
) {
992 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index
.type
, WRITEMASK_X
),
994 if (opcode
== SHADER_OPCODE_TXF_CMS_W
) {
995 /* MCS data is stored in the first two channels of ‘mcs’, but we
996 * need to get it into the .y and .z channels of the second vec4
999 mcs
.swizzle
= BRW_SWIZZLE4(0, 0, 1, 1);
1000 emit(MOV(dst_reg(MRF
, param_base
+ 1,
1001 glsl_type::uint_type
, WRITEMASK_YZ
),
1003 } else if (devinfo
->gen
>= 7) {
1004 /* MCS data is in the first channel of `mcs`, but we need to get it into
1005 * the .y channel of the second vec4 of params, so replicate .x across
1006 * the whole vec4 and then mask off everything except .y
1008 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
1009 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
1013 } else if (op
== ir_txd
) {
1014 const brw_reg_type type
= lod
.type
;
1016 if (devinfo
->gen
>= 5) {
1017 lod
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
1018 lod2
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
1019 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), lod
));
1020 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), lod2
));
1023 if (dest_type
->vector_elements
== 3 || shadow_comparitor
.file
!= BAD_FILE
) {
1024 lod
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1025 lod2
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1026 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), lod
));
1027 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), lod2
));
1030 if (shadow_comparitor
.file
!= BAD_FILE
) {
1031 emit(MOV(dst_reg(MRF
, param_base
+ 2,
1032 shadow_comparitor
.type
, WRITEMASK_Z
),
1033 shadow_comparitor
));
1036 } else /* devinfo->gen == 4 */ {
1037 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), lod
));
1038 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), lod2
));
1041 } else if (op
== ir_tg4
&& offset_value
.file
!= BAD_FILE
) {
1042 if (shadow_comparitor
.file
!= BAD_FILE
) {
1043 emit(MOV(dst_reg(MRF
, param_base
, shadow_comparitor
.type
, WRITEMASK_W
),
1044 shadow_comparitor
));
1047 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
1055 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
1056 * spec requires layers.
1058 if (op
== ir_txs
&& is_cube_array
) {
1059 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
1060 writemask(inst
->dst
, WRITEMASK_Z
),
1061 src_reg(inst
->dst
), src_reg(6));
1064 if (devinfo
->gen
== 6 && op
== ir_tg4
) {
1065 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[sampler
], inst
->dst
);
1068 swizzle_result(op
, dest
,
1069 src_reg(inst
->dst
), sampler
, dest_type
);
1073 * Apply workarounds for Gen6 gather with UINT/SINT
1076 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
1081 int width
= (wa
& WA_8BIT
) ? 8 : 16;
1082 dst_reg dst_f
= dst
;
1083 dst_f
.type
= BRW_REGISTER_TYPE_F
;
1085 /* Convert from UNORM to UINT */
1086 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
1087 emit(MOV(dst
, src_reg(dst_f
)));
1090 /* Reinterpret the UINT value as a signed INT value by
1091 * shifting the sign bit into place, then shifting back
1094 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
1095 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
1100 * Set up the gather channel based on the swizzle, for gather4.
1103 vec4_visitor::gather_channel(unsigned gather_component
, uint32_t sampler
)
1105 int swiz
= GET_SWZ(key_tex
->swizzles
[sampler
], gather_component
);
1107 case SWIZZLE_X
: return 0;
1109 /* gather4 sampler is broken for green channel on RG32F --
1110 * we must ask for blue instead.
1112 if (key_tex
->gather_channel_quirk_mask
& (1 << sampler
))
1115 case SWIZZLE_Z
: return 2;
1116 case SWIZZLE_W
: return 3;
1118 unreachable("Not reached"); /* zero, one swizzles handled already */
1123 vec4_visitor::swizzle_result(ir_texture_opcode op
, dst_reg dest
,
1124 src_reg orig_val
, uint32_t sampler
,
1125 const glsl_type
*dest_type
)
1127 int s
= key_tex
->swizzles
[sampler
];
1129 dst_reg swizzled_result
= dest
;
1131 if (op
== ir_query_levels
) {
1132 /* # levels is in .w */
1133 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1134 emit(MOV(swizzled_result
, orig_val
));
1138 if (op
== ir_txs
|| dest_type
== glsl_type::float_type
1139 || s
== SWIZZLE_NOOP
|| op
== ir_tg4
) {
1140 emit(MOV(swizzled_result
, orig_val
));
1145 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
1146 int swizzle
[4] = {0};
1148 for (int i
= 0; i
< 4; i
++) {
1149 switch (GET_SWZ(s
, i
)) {
1151 zero_mask
|= (1 << i
);
1154 one_mask
|= (1 << i
);
1157 copy_mask
|= (1 << i
);
1158 swizzle
[i
] = GET_SWZ(s
, i
);
1164 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1165 swizzled_result
.writemask
= copy_mask
;
1166 emit(MOV(swizzled_result
, orig_val
));
1170 swizzled_result
.writemask
= zero_mask
;
1171 emit(MOV(swizzled_result
, src_reg(0.0f
)));
1175 swizzled_result
.writemask
= one_mask
;
1176 emit(MOV(swizzled_result
, src_reg(1.0f
)));
1181 vec4_visitor::gs_emit_vertex(int stream_id
)
1183 unreachable("not reached");
1187 vec4_visitor::gs_end_primitive()
1189 unreachable("not reached");
1193 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
1194 dst_reg dst
, src_reg surf_offset
,
1195 src_reg src0
, src_reg src1
)
1197 unsigned mlen
= 1 + (src0
.file
!= BAD_FILE
) + (src1
.file
!= BAD_FILE
);
1198 src_reg
src_payload(this, glsl_type::uint_type
, mlen
);
1199 dst_reg
payload(src_payload
);
1200 payload
.writemask
= WRITEMASK_X
;
1202 /* Set the atomic operation offset. */
1203 emit(MOV(offset(payload
, 0), surf_offset
));
1206 /* Set the atomic operation arguments. */
1207 if (src0
.file
!= BAD_FILE
) {
1208 emit(MOV(offset(payload
, i
), src0
));
1212 if (src1
.file
!= BAD_FILE
) {
1213 emit(MOV(offset(payload
, i
), src1
));
1217 /* Emit the instruction. Note that this maps to the normal SIMD8
1218 * untyped atomic message on Ivy Bridge, but that's OK because
1219 * unused channels will be masked out.
1221 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
1223 src_reg(surf_index
), src_reg(atomic_op
));
1228 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
1229 src_reg surf_offset
)
1231 dst_reg
offset(this, glsl_type::uint_type
);
1232 offset
.writemask
= WRITEMASK_X
;
1234 /* Set the surface read offset. */
1235 emit(MOV(offset
, surf_offset
));
1237 /* Emit the instruction. Note that this maps to the normal SIMD8
1238 * untyped surface read message, but that's OK because unused
1239 * channels will be masked out.
1241 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
,
1243 src_reg(surf_index
), src_reg(1));
1248 vec4_visitor::emit_ndc_computation()
1250 if (output_reg
[VARYING_SLOT_POS
].file
== BAD_FILE
)
1253 /* Get the position */
1254 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
1256 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
1257 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
1258 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
1260 current_annotation
= "NDC";
1261 dst_reg ndc_w
= ndc
;
1262 ndc_w
.writemask
= WRITEMASK_W
;
1263 src_reg pos_w
= pos
;
1264 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
1265 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
1267 dst_reg ndc_xyz
= ndc
;
1268 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
1270 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
1274 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
1276 if (devinfo
->gen
< 6 &&
1277 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
1278 output_reg
[VARYING_SLOT_CLIP_DIST0
].file
!= BAD_FILE
||
1279 devinfo
->has_negative_rhw_bug
)) {
1280 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
1281 dst_reg header1_w
= header1
;
1282 header1_w
.writemask
= WRITEMASK_W
;
1284 emit(MOV(header1
, 0u));
1286 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
1287 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
1289 current_annotation
= "Point size";
1290 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
1291 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
1294 if (output_reg
[VARYING_SLOT_CLIP_DIST0
].file
!= BAD_FILE
) {
1295 current_annotation
= "Clipping flags";
1296 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
1297 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
1299 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
1300 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
1301 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
1303 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
1304 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
1305 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
1306 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
1309 /* i965 clipping workaround:
1310 * 1) Test for -ve rhw
1312 * set ndc = (0,0,0,0)
1315 * Later, clipping will detect ucp[6] and ensure the primitive is
1316 * clipped against all fixed planes.
1318 if (devinfo
->has_negative_rhw_bug
&&
1319 output_reg
[BRW_VARYING_SLOT_NDC
].file
!= BAD_FILE
) {
1320 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
1321 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
1322 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
1323 vec4_instruction
*inst
;
1324 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
1325 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1326 output_reg
[BRW_VARYING_SLOT_NDC
].type
= BRW_REGISTER_TYPE_F
;
1327 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
1328 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1331 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
1332 } else if (devinfo
->gen
< 6) {
1333 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
1335 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
1336 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
1337 dst_reg reg_w
= reg
;
1338 reg_w
.writemask
= WRITEMASK_W
;
1339 src_reg reg_as_src
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
1340 reg_as_src
.type
= reg_w
.type
;
1341 reg_as_src
.swizzle
= brw_swizzle_for_size(1);
1342 emit(MOV(reg_w
, reg_as_src
));
1344 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
1345 dst_reg reg_y
= reg
;
1346 reg_y
.writemask
= WRITEMASK_Y
;
1347 reg_y
.type
= BRW_REGISTER_TYPE_D
;
1348 output_reg
[VARYING_SLOT_LAYER
].type
= reg_y
.type
;
1349 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
1351 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
1352 dst_reg reg_z
= reg
;
1353 reg_z
.writemask
= WRITEMASK_Z
;
1354 reg_z
.type
= BRW_REGISTER_TYPE_D
;
1355 output_reg
[VARYING_SLOT_VIEWPORT
].type
= reg_z
.type
;
1356 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
1362 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
1364 assert(varying
< VARYING_SLOT_MAX
);
1365 assert(output_reg
[varying
].type
== reg
.type
);
1366 current_annotation
= output_reg_annotation
[varying
];
1367 if (output_reg
[varying
].file
!= BAD_FILE
)
1368 return emit(MOV(reg
, src_reg(output_reg
[varying
])));
1374 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
1376 reg
.type
= BRW_REGISTER_TYPE_F
;
1377 output_reg
[varying
].type
= reg
.type
;
1380 case VARYING_SLOT_PSIZ
:
1382 /* PSIZ is always in slot 0, and is coupled with other flags. */
1383 current_annotation
= "indices, point width, clip flags";
1384 emit_psiz_and_flags(reg
);
1387 case BRW_VARYING_SLOT_NDC
:
1388 current_annotation
= "NDC";
1389 if (output_reg
[BRW_VARYING_SLOT_NDC
].file
!= BAD_FILE
)
1390 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
1392 case VARYING_SLOT_POS
:
1393 current_annotation
= "gl_Position";
1394 if (output_reg
[VARYING_SLOT_POS
].file
!= BAD_FILE
)
1395 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
1397 case VARYING_SLOT_EDGE
:
1398 /* This is present when doing unfilled polygons. We're supposed to copy
1399 * the edge flag from the user-provided vertex array
1400 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
1401 * of that attribute (starts as 1.0f). This is then used in clipping to
1402 * determine which edges should be drawn as wireframe.
1404 current_annotation
= "edge flag";
1405 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
1406 glsl_type::float_type
, WRITEMASK_XYZW
))));
1408 case BRW_VARYING_SLOT_PAD
:
1409 /* No need to write to this slot */
1412 emit_generic_urb_slot(reg
, varying
);
1418 align_interleaved_urb_mlen(const struct brw_device_info
*devinfo
, int mlen
)
1420 if (devinfo
->gen
>= 6) {
1421 /* URB data written (does not include the message header reg) must
1422 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
1423 * section 5.4.3.2.2: URB_INTERLEAVED.
1425 * URB entries are allocated on a multiple of 1024 bits, so an
1426 * extra 128 bits written here to make the end align to 256 is
1429 if ((mlen
% 2) != 1)
1438 * Generates the VUE payload plus the necessary URB write instructions to
1441 * The VUE layout is documented in Volume 2a.
1444 vec4_visitor::emit_vertex()
1446 /* MRF 0 is reserved for the debugger, so start with message header
1451 /* In the process of generating our URB write message contents, we
1452 * may need to unspill a register or load from an array. Those
1453 * reads would use MRFs 14-15.
1455 int max_usable_mrf
= FIRST_SPILL_MRF(devinfo
->gen
);
1457 /* The following assertion verifies that max_usable_mrf causes an
1458 * even-numbered amount of URB write data, which will meet gen6's
1459 * requirements for length alignment.
1461 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
1463 /* First mrf is the g0-based message header containing URB handles and
1466 emit_urb_write_header(mrf
++);
1468 if (devinfo
->gen
< 6) {
1469 emit_ndc_computation();
1472 /* We may need to split this up into several URB writes, so do them in a
1476 bool complete
= false;
1478 /* URB offset is in URB row increments, and each of our MRFs is half of
1479 * one of those, since we're doing interleaved writes.
1481 int offset
= slot
/ 2;
1484 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
1485 emit_urb_slot(dst_reg(MRF
, mrf
++),
1486 prog_data
->vue_map
.slot_to_varying
[slot
]);
1488 /* If this was max_usable_mrf, we can't fit anything more into this
1489 * URB WRITE. Same thing if we reached the maximum length available.
1491 if (mrf
> max_usable_mrf
||
1492 align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
+ 1) > BRW_MAX_MSG_LENGTH
) {
1498 complete
= slot
>= prog_data
->vue_map
.num_slots
;
1499 current_annotation
= "URB write";
1500 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
1501 inst
->base_mrf
= base_mrf
;
1502 inst
->mlen
= align_interleaved_urb_mlen(devinfo
, mrf
- base_mrf
);
1503 inst
->offset
+= offset
;
1509 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
1510 src_reg
*reladdr
, int reg_offset
)
1512 /* Because we store the values to scratch interleaved like our
1513 * vertex data, we need to scale the vec4 index by 2.
1515 int message_header_scale
= 2;
1517 /* Pre-gen6, the message header uses byte offsets instead of vec4
1518 * (16-byte) offset units.
1520 if (devinfo
->gen
< 6)
1521 message_header_scale
*= 16;
1524 src_reg index
= src_reg(this, glsl_type::int_type
);
1526 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
1527 src_reg(reg_offset
)));
1528 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
1529 src_reg(message_header_scale
)));
1533 return src_reg(reg_offset
* message_header_scale
);
1538 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
1539 src_reg
*reladdr
, int reg_offset
)
1542 src_reg index
= src_reg(this, glsl_type::int_type
);
1544 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
1545 src_reg(reg_offset
)));
1547 /* Pre-gen6, the message header uses byte offsets instead of vec4
1548 * (16-byte) offset units.
1550 if (devinfo
->gen
< 6) {
1551 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
1555 } else if (devinfo
->gen
>= 8) {
1556 /* Store the offset in a GRF so we can send-from-GRF. */
1557 src_reg offset
= src_reg(this, glsl_type::int_type
);
1558 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
1561 int message_header_scale
= devinfo
->gen
< 6 ? 16 : 1;
1562 return src_reg(reg_offset
* message_header_scale
);
1567 * Emits an instruction before @inst to load the value named by @orig_src
1568 * from scratch space at @base_offset to @temp.
1570 * @base_offset is measured in 32-byte units (the size of a register).
1573 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
1574 dst_reg temp
, src_reg orig_src
,
1577 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
1578 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
1581 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
1585 * Emits an instruction after @inst to store the value to be written
1586 * to @orig_dst to scratch space at @base_offset, from @temp.
1588 * @base_offset is measured in 32-byte units (the size of a register).
1591 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
1594 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
1595 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
1598 /* Create a temporary register to store *inst's result in.
1600 * We have to be careful in MOVing from our temporary result register in
1601 * the scratch write. If we swizzle from channels of the temporary that
1602 * weren't initialized, it will confuse live interval analysis, which will
1603 * make spilling fail to make progress.
1605 const src_reg temp
= swizzle(retype(src_reg(this, glsl_type::vec4_type
),
1607 brw_swizzle_for_mask(inst
->dst
.writemask
));
1608 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
1609 inst
->dst
.writemask
));
1610 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
1611 if (inst
->opcode
!= BRW_OPCODE_SEL
)
1612 write
->predicate
= inst
->predicate
;
1613 write
->ir
= inst
->ir
;
1614 write
->annotation
= inst
->annotation
;
1615 inst
->insert_after(block
, write
);
1617 inst
->dst
.file
= temp
.file
;
1618 inst
->dst
.nr
= temp
.nr
;
1619 inst
->dst
.reg_offset
= temp
.reg_offset
;
1620 inst
->dst
.reladdr
= NULL
;
1624 * Checks if \p src and/or \p src.reladdr require a scratch read, and if so,
1625 * adds the scratch read(s) before \p inst. The function also checks for
1626 * recursive reladdr scratch accesses, issuing the corresponding scratch
1627 * loads and rewriting reladdr references accordingly.
1629 * \return \p src if it did not require a scratch load, otherwise, the
1630 * register holding the result of the scratch load that the caller should
1631 * use to rewrite src.
1634 vec4_visitor::emit_resolve_reladdr(int scratch_loc
[], bblock_t
*block
,
1635 vec4_instruction
*inst
, src_reg src
)
1637 /* Resolve recursive reladdr scratch access by calling ourselves
1641 *src
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
1644 /* Now handle scratch access on src */
1645 if (src
.file
== GRF
&& scratch_loc
[src
.nr
] != -1) {
1646 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
1647 emit_scratch_read(block
, inst
, temp
, src
, scratch_loc
[src
.nr
]);
1649 src
.reg_offset
= temp
.reg_offset
;
1657 * We can't generally support array access in GRF space, because a
1658 * single instruction's destination can only span 2 contiguous
1659 * registers. So, we send all GRF arrays that get variable index
1660 * access to scratch space.
1663 vec4_visitor::move_grf_array_access_to_scratch()
1665 int scratch_loc
[this->alloc
.count
];
1666 memset(scratch_loc
, -1, sizeof(scratch_loc
));
1668 /* First, calculate the set of virtual GRFs that need to be punted
1669 * to scratch due to having any array access on them, and where in
1672 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1673 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
) {
1674 if (scratch_loc
[inst
->dst
.nr
] == -1) {
1675 scratch_loc
[inst
->dst
.nr
] = last_scratch
;
1676 last_scratch
+= this->alloc
.sizes
[inst
->dst
.nr
];
1679 for (src_reg
*iter
= inst
->dst
.reladdr
;
1681 iter
= iter
->reladdr
) {
1682 if (iter
->file
== GRF
&& scratch_loc
[iter
->nr
] == -1) {
1683 scratch_loc
[iter
->nr
] = last_scratch
;
1684 last_scratch
+= this->alloc
.sizes
[iter
->nr
];
1689 for (int i
= 0 ; i
< 3; i
++) {
1690 for (src_reg
*iter
= &inst
->src
[i
];
1692 iter
= iter
->reladdr
) {
1693 if (iter
->file
== GRF
&& scratch_loc
[iter
->nr
] == -1) {
1694 scratch_loc
[iter
->nr
] = last_scratch
;
1695 last_scratch
+= this->alloc
.sizes
[iter
->nr
];
1701 /* Now, for anything that will be accessed through scratch, rewrite
1702 * it to load/store. Note that this is a _safe list walk, because
1703 * we may generate a new scratch_write instruction after the one
1706 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1707 /* Set up the annotation tracking for new generated instructions. */
1709 current_annotation
= inst
->annotation
;
1711 /* First handle scratch access on the dst. Notice we have to handle
1712 * the case where the dst's reladdr also points to scratch space.
1714 if (inst
->dst
.reladdr
)
1715 *inst
->dst
.reladdr
= emit_resolve_reladdr(scratch_loc
, block
, inst
,
1716 *inst
->dst
.reladdr
);
1718 /* Now that we have handled any (possibly recursive) reladdr scratch
1719 * accesses for dst we can safely do the scratch write for dst itself
1721 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.nr
] != -1)
1722 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.nr
]);
1724 /* Now handle scratch access on any src. In this case, since inst->src[i]
1725 * already is a src_reg, we can just call emit_resolve_reladdr with
1726 * inst->src[i] and it will take care of handling scratch loads for
1727 * both src and src.reladdr (recursively).
1729 for (int i
= 0 ; i
< 3; i
++) {
1730 inst
->src
[i
] = emit_resolve_reladdr(scratch_loc
, block
, inst
,
1737 * Emits an instruction before @inst to load the value named by @orig_src
1738 * from the pull constant buffer (surface) at @base_offset to @temp.
1741 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
1742 dst_reg temp
, src_reg orig_src
,
1745 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
1746 const unsigned index
= prog_data
->base
.binding_table
.pull_constants_start
;
1747 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
1750 emit_pull_constant_load_reg(temp
,
1755 brw_mark_surface_used(&prog_data
->base
, index
);
1759 * Implements array access of uniforms by inserting a
1760 * PULL_CONSTANT_LOAD instruction.
1762 * Unlike temporary GRF array access (where we don't support it due to
1763 * the difficulty of doing relative addressing on instruction
1764 * destinations), we could potentially do array access of uniforms
1765 * that were loaded in GRF space as push constants. In real-world
1766 * usage we've seen, though, the arrays being used are always larger
1767 * than we could load as push constants, so just always move all
1768 * uniform array access out to a pull constant buffer.
1771 vec4_visitor::move_uniform_array_access_to_pull_constants()
1773 int pull_constant_loc
[this->uniforms
];
1774 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
1775 bool nested_reladdr
;
1777 /* Walk through and find array access of uniforms. Put a copy of that
1778 * uniform in the pull constant buffer.
1780 * Note that we don't move constant-indexed accesses to arrays. No
1781 * testing has been done of the performance impact of this choice.
1784 nested_reladdr
= false;
1786 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1787 for (int i
= 0 ; i
< 3; i
++) {
1788 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
1791 int uniform
= inst
->src
[i
].nr
;
1793 if (inst
->src
[i
].reladdr
->reladdr
)
1794 nested_reladdr
= true; /* will need another pass */
1796 /* If this array isn't already present in the pull constant buffer,
1799 if (pull_constant_loc
[uniform
] == -1) {
1800 const gl_constant_value
**values
=
1801 &stage_prog_data
->param
[uniform
* 4];
1803 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
1805 assert(uniform
< uniform_array_size
);
1806 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
1807 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
1812 /* Set up the annotation tracking for new generated instructions. */
1814 current_annotation
= inst
->annotation
;
1816 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
1818 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
1819 pull_constant_loc
[uniform
]);
1821 inst
->src
[i
].file
= temp
.file
;
1822 inst
->src
[i
].nr
= temp
.nr
;
1823 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
1824 inst
->src
[i
].reladdr
= NULL
;
1827 } while (nested_reladdr
);
1829 /* Now there are no accesses of the UNIFORM file with a reladdr, so
1830 * no need to track them as larger-than-vec4 objects. This will be
1831 * relied on in cutting out unused uniform vectors from push
1834 split_uniform_registers();
1838 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
1840 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
1844 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
1845 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
1849 vec4_visitor::vec4_visitor(const struct brw_compiler
*compiler
,
1851 const struct brw_sampler_prog_key_data
*key_tex
,
1852 struct brw_vue_prog_data
*prog_data
,
1853 const nir_shader
*shader
,
1856 int shader_time_index
)
1857 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, &prog_data
->base
),
1859 prog_data(prog_data
),
1861 first_non_payload_grf(0),
1862 need_all_constants_in_pull_buffer(false),
1863 no_spills(no_spills
),
1864 shader_time_index(shader_time_index
),
1867 this->failed
= false;
1869 this->base_ir
= NULL
;
1870 this->current_annotation
= NULL
;
1871 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
1873 this->virtual_grf_start
= NULL
;
1874 this->virtual_grf_end
= NULL
;
1875 this->live_intervals
= NULL
;
1877 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1881 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
1882 * at least one. See setup_uniforms() in brw_vec4.cpp.
1884 this->uniform_array_size
= 1;
1886 this->uniform_array_size
=
1887 MAX2(DIV_ROUND_UP(stage_prog_data
->nr_params
, 4), 1);
1890 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
1893 vec4_visitor::~vec4_visitor()
1899 vec4_visitor::fail(const char *format
, ...)
1909 va_start(va
, format
);
1910 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
1912 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
1914 this->fail_msg
= msg
;
1916 if (debug_enabled
) {
1917 fprintf(stderr
, "%s", msg
);
1921 } /* namespace brw */