2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "glsl/ir_uniform.h"
28 #include "program/sampler.h"
33 vec4_instruction::vec4_instruction(vec4_visitor
*v
,
34 enum opcode opcode
, const dst_reg
&dst
,
35 const src_reg
&src0
, const src_reg
&src1
,
38 this->opcode
= opcode
;
43 this->saturate
= false;
44 this->force_writemask_all
= false;
45 this->no_dd_clear
= false;
46 this->no_dd_check
= false;
47 this->writes_accumulator
= false;
48 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
49 this->texture_offset
= 0;
51 this->shadow_compare
= false;
52 this->ir
= v
->base_ir
;
53 this->urb_write_flags
= BRW_URB_WRITE_NO_FLAGS
;
54 this->header_present
= false;
58 this->annotation
= v
->current_annotation
;
62 vec4_visitor::emit(vec4_instruction
*inst
)
64 this->instructions
.push_tail(inst
);
70 vec4_visitor::emit_before(bblock_t
*block
, vec4_instruction
*inst
,
71 vec4_instruction
*new_inst
)
73 new_inst
->ir
= inst
->ir
;
74 new_inst
->annotation
= inst
->annotation
;
76 inst
->insert_before(block
, new_inst
);
82 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
83 const src_reg
&src1
, const src_reg
&src2
)
85 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
,
91 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
,
94 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
, src1
));
98 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
, const src_reg
&src0
)
100 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
, src0
));
104 vec4_visitor::emit(enum opcode opcode
, const dst_reg
&dst
)
106 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst
));
110 vec4_visitor::emit(enum opcode opcode
)
112 return emit(new(mem_ctx
) vec4_instruction(this, opcode
, dst_reg()));
117 vec4_visitor::op(const dst_reg &dst, const src_reg &src0) \
119 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
125 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
126 const src_reg &src1) \
128 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
132 #define ALU2_ACC(op) \
134 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
135 const src_reg &src1) \
137 vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, \
138 BRW_OPCODE_##op, dst, src0, src1); \
139 inst->writes_accumulator = true; \
145 vec4_visitor::op(const dst_reg &dst, const src_reg &src0, \
146 const src_reg &src1, const src_reg &src2) \
148 assert(brw->gen >= 6); \
149 return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
186 /** Gen4 predicated IF. */
188 vec4_visitor::IF(enum brw_predicate predicate
)
190 vec4_instruction
*inst
;
192 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
);
193 inst
->predicate
= predicate
;
198 /** Gen6 IF with embedded comparison. */
200 vec4_visitor::IF(src_reg src0
, src_reg src1
,
201 enum brw_conditional_mod condition
)
203 assert(brw
->gen
== 6);
205 vec4_instruction
*inst
;
207 resolve_ud_negate(&src0
);
208 resolve_ud_negate(&src1
);
210 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_IF
, dst_null_d(),
212 inst
->conditional_mod
= condition
;
218 * CMP: Sets the low bit of the destination channels with the result
219 * of the comparison, while the upper bits are undefined, and updates
220 * the flag register with the packed 16 bits of the result.
223 vec4_visitor::CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
224 enum brw_conditional_mod condition
)
226 vec4_instruction
*inst
;
228 /* original gen4 does type conversion to the destination type
229 * before before comparison, producing garbage results for floating
233 dst
.type
= src0
.type
;
234 if (dst
.file
== HW_REG
)
235 dst
.fixed_hw_reg
.type
= dst
.type
;
238 resolve_ud_negate(&src0
);
239 resolve_ud_negate(&src1
);
241 inst
= new(mem_ctx
) vec4_instruction(this, BRW_OPCODE_CMP
, dst
, src0
, src1
);
242 inst
->conditional_mod
= condition
;
248 vec4_visitor::SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
)
250 vec4_instruction
*inst
;
252 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_READ
,
261 vec4_visitor::SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
262 const src_reg
&index
)
264 vec4_instruction
*inst
;
266 inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
275 vec4_visitor::emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
)
277 static enum opcode dot_opcodes
[] = {
278 BRW_OPCODE_DP2
, BRW_OPCODE_DP3
, BRW_OPCODE_DP4
281 emit(dot_opcodes
[elements
- 2], dst
, src0
, src1
);
285 vec4_visitor::fix_3src_operand(src_reg src
)
287 /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
288 * able to use vertical stride of zero to replicate the vec4 uniform, like
290 * g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
292 * But you can't, since vertical stride is always four in three-source
293 * instructions. Instead, insert a MOV instruction to do the replication so
294 * that the three-source instruction can consume it.
297 /* The MOV is only needed if the source is a uniform or immediate. */
298 if (src
.file
!= UNIFORM
&& src
.file
!= IMM
)
301 if (src
.file
== UNIFORM
&& brw_is_single_value_swizzle(src
.swizzle
))
304 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
305 expanded
.type
= src
.type
;
306 emit(MOV(expanded
, src
));
307 return src_reg(expanded
);
311 vec4_visitor::fix_math_operand(src_reg src
)
313 if (brw
->gen
< 6 || brw
->gen
>= 8 || src
.file
== BAD_FILE
)
316 /* The gen6 math instruction ignores the source modifiers --
317 * swizzle, abs, negate, and at least some parts of the register
318 * region description.
320 * Rather than trying to enumerate all these cases, *always* expand the
321 * operand to a temp GRF for gen6.
323 * For gen7, keep the operand as-is, except if immediate, which gen7 still
327 if (brw
->gen
== 7 && src
.file
!= IMM
)
330 dst_reg expanded
= dst_reg(this, glsl_type::vec4_type
);
331 expanded
.type
= src
.type
;
332 emit(MOV(expanded
, src
));
333 return src_reg(expanded
);
337 vec4_visitor::emit_math(enum opcode opcode
,
339 const src_reg
&src0
, const src_reg
&src1
)
341 vec4_instruction
*math
=
342 emit(opcode
, dst
, fix_math_operand(src0
), fix_math_operand(src1
));
344 if (brw
->gen
== 6 && dst
.writemask
!= WRITEMASK_XYZW
) {
345 /* MATH on Gen6 must be align1, so we can't do writemasks. */
346 math
->dst
= dst_reg(this, glsl_type::vec4_type
);
347 math
->dst
.type
= dst
.type
;
348 emit(MOV(dst
, src_reg(math
->dst
)));
349 } else if (brw
->gen
< 6) {
351 math
->mlen
= src1
.file
== BAD_FILE
? 1 : 2;
356 vec4_visitor::emit_pack_half_2x16(dst_reg dst
, src_reg src0
)
359 unreachable("ir_unop_pack_half_2x16 should be lowered");
362 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
363 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
365 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
367 * Because this instruction does not have a 16-bit floating-point type,
368 * the destination data type must be Word (W).
370 * The destination must be DWord-aligned and specify a horizontal stride
371 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
372 * each destination channel and the upper word is not modified.
374 * The above restriction implies that the f32to16 instruction must use
375 * align1 mode, because only in align1 mode is it possible to specify
376 * horizontal stride. We choose here to defy the hardware docs and emit
377 * align16 instructions.
379 * (I [chadv] did attempt to emit align1 instructions for VS f32to16
380 * instructions. I was partially successful in that the code passed all
381 * tests. However, the code was dubiously correct and fragile, and the
382 * tests were not harsh enough to probe that frailty. Not trusting the
383 * code, I chose instead to remain in align16 mode in defiance of the hw
386 * I've [chadv] experimentally confirmed that, on gen7 hardware and the
387 * simulator, emitting a f32to16 in align16 mode with UD as destination
388 * data type is safe. The behavior differs from that specified in the PRM
389 * in that the upper word of each destination channel is cleared to 0.
392 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
393 src_reg
tmp_src(tmp_dst
);
396 /* Verify the undocumented behavior on which the following instructions
397 * rely. If f32to16 fails to clear the upper word of the X and Y channels,
398 * then the result of the bit-or instruction below will be incorrect.
400 * You should inspect the disasm output in order to verify that the MOV is
401 * not optimized away.
403 emit(MOV(tmp_dst
, src_reg(0x12345678u
)));
406 /* Give tmp the form below, where "." means untouched.
409 * |.|.|0x0000hhhh|0x0000llll|.|.|0x0000hhhh|0x0000llll|
411 * That the upper word of each write-channel be 0 is required for the
412 * following bit-shift and bit-or instructions to work. Note that this
413 * relies on the undocumented hardware behavior mentioned above.
415 tmp_dst
.writemask
= WRITEMASK_XY
;
416 emit(F32TO16(tmp_dst
, src0
));
418 /* Give the write-channels of dst the form:
421 tmp_src
.swizzle
= BRW_SWIZZLE_YYYY
;
422 emit(SHL(dst
, tmp_src
, src_reg(16u)));
424 /* Finally, give the write-channels of dst the form of packHalf2x16's
428 tmp_src
.swizzle
= BRW_SWIZZLE_XXXX
;
429 emit(OR(dst
, src_reg(dst
), tmp_src
));
433 vec4_visitor::emit_unpack_half_2x16(dst_reg dst
, src_reg src0
)
436 unreachable("ir_unop_unpack_half_2x16 should be lowered");
439 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
440 assert(src0
.type
== BRW_REGISTER_TYPE_UD
);
442 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
444 * Because this instruction does not have a 16-bit floating-point type,
445 * the source data type must be Word (W). The destination type must be
448 * To use W as the source data type, we must adjust horizontal strides,
449 * which is only possible in align1 mode. All my [chadv] attempts at
450 * emitting align1 instructions for unpackHalf2x16 failed to pass the
451 * Piglit tests, so I gave up.
453 * I've verified that, on gen7 hardware and the simulator, it is safe to
454 * emit f16to32 in align16 mode with UD as source data type.
457 dst_reg
tmp_dst(this, glsl_type::uvec2_type
);
458 src_reg
tmp_src(tmp_dst
);
460 tmp_dst
.writemask
= WRITEMASK_X
;
461 emit(AND(tmp_dst
, src0
, src_reg(0xffffu
)));
463 tmp_dst
.writemask
= WRITEMASK_Y
;
464 emit(SHR(tmp_dst
, src0
, src_reg(16u)));
466 dst
.writemask
= WRITEMASK_XY
;
467 emit(F16TO32(dst
, tmp_src
));
471 vec4_visitor::visit_instructions(const exec_list
*list
)
473 foreach_in_list(ir_instruction
, ir
, list
) {
481 type_size(const struct glsl_type
*type
)
486 switch (type
->base_type
) {
489 case GLSL_TYPE_FLOAT
:
491 if (type
->is_matrix()) {
492 return type
->matrix_columns
;
494 /* Regardless of size of vector, it gets a vec4. This is bad
495 * packing for things like floats, but otherwise arrays become a
496 * mess. Hopefully a later pass over the code can pack scalars
497 * down if appropriate.
501 case GLSL_TYPE_ARRAY
:
502 assert(type
->length
> 0);
503 return type_size(type
->fields
.array
) * type
->length
;
504 case GLSL_TYPE_STRUCT
:
506 for (i
= 0; i
< type
->length
; i
++) {
507 size
+= type_size(type
->fields
.structure
[i
].type
);
510 case GLSL_TYPE_SAMPLER
:
511 /* Samplers take up no register space, since they're baked in at
515 case GLSL_TYPE_ATOMIC_UINT
:
517 case GLSL_TYPE_IMAGE
:
519 case GLSL_TYPE_ERROR
:
520 case GLSL_TYPE_INTERFACE
:
521 unreachable("not reached");
528 vec4_visitor::virtual_grf_alloc(int size
)
530 if (virtual_grf_array_size
<= virtual_grf_count
) {
531 if (virtual_grf_array_size
== 0)
532 virtual_grf_array_size
= 16;
534 virtual_grf_array_size
*= 2;
535 virtual_grf_sizes
= reralloc(mem_ctx
, virtual_grf_sizes
, int,
536 virtual_grf_array_size
);
537 virtual_grf_reg_map
= reralloc(mem_ctx
, virtual_grf_reg_map
, int,
538 virtual_grf_array_size
);
540 virtual_grf_reg_map
[virtual_grf_count
] = virtual_grf_reg_count
;
541 virtual_grf_reg_count
+= size
;
542 virtual_grf_sizes
[virtual_grf_count
] = size
;
543 return virtual_grf_count
++;
546 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
551 this->reg
= v
->virtual_grf_alloc(type_size(type
));
553 if (type
->is_array() || type
->is_record()) {
554 this->swizzle
= BRW_SWIZZLE_NOOP
;
556 this->swizzle
= swizzle_for_size(type
->vector_elements
);
559 this->type
= brw_type_for_base_type(type
);
562 src_reg::src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
)
569 this->reg
= v
->virtual_grf_alloc(type_size(type
) * size
);
571 this->swizzle
= BRW_SWIZZLE_NOOP
;
573 this->type
= brw_type_for_base_type(type
);
576 dst_reg::dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
)
581 this->reg
= v
->virtual_grf_alloc(type_size(type
));
583 if (type
->is_array() || type
->is_record()) {
584 this->writemask
= WRITEMASK_XYZW
;
586 this->writemask
= (1 << type
->vector_elements
) - 1;
589 this->type
= brw_type_for_base_type(type
);
592 /* Our support for uniforms is piggy-backed on the struct
593 * gl_fragment_program, because that's where the values actually
594 * get stored, rather than in some global gl_shader_program uniform
598 vec4_visitor::setup_uniform_values(ir_variable
*ir
)
600 int namelen
= strlen(ir
->name
);
602 /* The data for our (non-builtin) uniforms is stored in a series of
603 * gl_uniform_driver_storage structs for each subcomponent that
604 * glGetUniformLocation() could name. We know it's been set up in the same
605 * order we'd walk the type, so walk the list of storage and find anything
606 * with our name, or the prefix of a component that starts with our name.
608 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
609 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
611 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
612 (storage
->name
[namelen
] != 0 &&
613 storage
->name
[namelen
] != '.' &&
614 storage
->name
[namelen
] != '[')) {
618 gl_constant_value
*components
= storage
->storage
;
619 unsigned vector_count
= (MAX2(storage
->array_elements
, 1) *
620 storage
->type
->matrix_columns
);
622 for (unsigned s
= 0; s
< vector_count
; s
++) {
623 assert(uniforms
< uniform_array_size
);
624 uniform_vector_size
[uniforms
] = storage
->type
->vector_elements
;
627 for (i
= 0; i
< uniform_vector_size
[uniforms
]; i
++) {
628 stage_prog_data
->param
[uniforms
* 4 + i
] = components
;
632 static gl_constant_value zero
= { 0.0 };
633 stage_prog_data
->param
[uniforms
* 4 + i
] = &zero
;
642 vec4_visitor::setup_uniform_clipplane_values()
644 gl_clip_plane
*clip_planes
= brw_select_clip_planes(ctx
);
646 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; ++i
) {
647 assert(this->uniforms
< uniform_array_size
);
648 this->uniform_vector_size
[this->uniforms
] = 4;
649 this->userplane
[i
] = dst_reg(UNIFORM
, this->uniforms
);
650 this->userplane
[i
].type
= BRW_REGISTER_TYPE_F
;
651 for (int j
= 0; j
< 4; ++j
) {
652 stage_prog_data
->param
[this->uniforms
* 4 + j
] =
653 (gl_constant_value
*) &clip_planes
[i
][j
];
659 /* Our support for builtin uniforms is even scarier than non-builtin.
660 * It sits on top of the PROG_STATE_VAR parameters that are
661 * automatically updated from GL context state.
664 vec4_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
666 const ir_state_slot
*const slots
= ir
->get_state_slots();
667 assert(slots
!= NULL
);
669 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
670 /* This state reference has already been setup by ir_to_mesa,
671 * but we'll get the same index back here. We can reference
672 * ParameterValues directly, since unlike brw_fs.cpp, we never
673 * add new state references during compile.
675 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
676 (gl_state_index
*)slots
[i
].tokens
);
677 gl_constant_value
*values
=
678 &this->prog
->Parameters
->ParameterValues
[index
][0];
680 assert(this->uniforms
< uniform_array_size
);
681 this->uniform_vector_size
[this->uniforms
] = 0;
682 /* Add each of the unique swizzled channels of the element.
683 * This will end up matching the size of the glsl_type of this field.
686 for (unsigned int j
= 0; j
< 4; j
++) {
687 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
690 stage_prog_data
->param
[this->uniforms
* 4 + j
] = &values
[swiz
];
691 assert(this->uniforms
< uniform_array_size
);
692 if (swiz
<= last_swiz
)
693 this->uniform_vector_size
[this->uniforms
]++;
700 vec4_visitor::variable_storage(ir_variable
*var
)
702 return (dst_reg
*)hash_table_find(this->variable_ht
, var
);
706 vec4_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
,
707 enum brw_predicate
*predicate
)
709 ir_expression
*expr
= ir
->as_expression();
711 *predicate
= BRW_PREDICATE_NORMAL
;
713 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
715 vec4_instruction
*inst
;
717 assert(expr
->get_num_operands() <= 3);
718 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
719 expr
->operands
[i
]->accept(this);
720 op
[i
] = this->result
;
722 resolve_ud_negate(&op
[i
]);
725 switch (expr
->operation
) {
726 case ir_unop_logic_not
:
727 inst
= emit(AND(dst_null_d(), op
[0], src_reg(1)));
728 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
731 case ir_binop_logic_xor
:
732 inst
= emit(XOR(dst_null_d(), op
[0], op
[1]));
733 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
736 case ir_binop_logic_or
:
737 inst
= emit(OR(dst_null_d(), op
[0], op
[1]));
738 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
741 case ir_binop_logic_and
:
742 inst
= emit(AND(dst_null_d(), op
[0], op
[1]));
743 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
748 emit(CMP(dst_null_d(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
750 inst
= emit(MOV(dst_null_f(), op
[0]));
751 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
757 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
759 inst
= emit(MOV(dst_null_d(), op
[0]));
760 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
764 case ir_binop_all_equal
:
765 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
766 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
769 case ir_binop_any_nequal
:
770 inst
= emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
771 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
775 inst
= emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
776 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
779 case ir_binop_greater
:
780 case ir_binop_gequal
:
782 case ir_binop_lequal
:
784 case ir_binop_nequal
:
785 emit(CMP(dst_null_d(), op
[0], op
[1],
786 brw_conditional_for_comparison(expr
->operation
)));
789 case ir_triop_csel
: {
790 /* Expand the boolean condition into the flag register. */
791 inst
= emit(MOV(dst_null_d(), op
[0]));
792 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
794 /* Select which boolean to return. */
795 dst_reg
temp(this, expr
->operands
[1]->type
);
796 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
797 inst
->predicate
= BRW_PREDICATE_NORMAL
;
799 /* Expand the result to a condition code. */
800 inst
= emit(MOV(dst_null_d(), src_reg(temp
)));
801 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
806 unreachable("not reached");
813 resolve_ud_negate(&this->result
);
816 vec4_instruction
*inst
= emit(AND(dst_null_d(),
817 this->result
, src_reg(1)));
818 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
820 vec4_instruction
*inst
= emit(MOV(dst_null_d(), this->result
));
821 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
826 * Emit a gen6 IF statement with the comparison folded into the IF
830 vec4_visitor::emit_if_gen6(ir_if
*ir
)
832 ir_expression
*expr
= ir
->condition
->as_expression();
834 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
838 assert(expr
->get_num_operands() <= 3);
839 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
840 expr
->operands
[i
]->accept(this);
841 op
[i
] = this->result
;
844 switch (expr
->operation
) {
845 case ir_unop_logic_not
:
846 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_Z
));
849 case ir_binop_logic_xor
:
850 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
853 case ir_binop_logic_or
:
854 temp
= dst_reg(this, glsl_type::bool_type
);
855 emit(OR(temp
, op
[0], op
[1]));
856 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
859 case ir_binop_logic_and
:
860 temp
= dst_reg(this, glsl_type::bool_type
);
861 emit(AND(temp
, op
[0], op
[1]));
862 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
866 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
870 emit(IF(op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
873 case ir_binop_greater
:
874 case ir_binop_gequal
:
876 case ir_binop_lequal
:
878 case ir_binop_nequal
:
879 emit(IF(op
[0], op
[1],
880 brw_conditional_for_comparison(expr
->operation
)));
883 case ir_binop_all_equal
:
884 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
885 emit(IF(BRW_PREDICATE_ALIGN16_ALL4H
));
888 case ir_binop_any_nequal
:
889 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
890 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
894 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
895 emit(IF(BRW_PREDICATE_ALIGN16_ANY4H
));
898 case ir_triop_csel
: {
899 /* Expand the boolean condition into the flag register. */
900 vec4_instruction
*inst
= emit(MOV(dst_null_d(), op
[0]));
901 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
903 /* Select which boolean to return. */
904 dst_reg
temp(this, expr
->operands
[1]->type
);
905 inst
= emit(BRW_OPCODE_SEL
, temp
, op
[1], op
[2]);
906 inst
->predicate
= BRW_PREDICATE_NORMAL
;
908 emit(IF(src_reg(temp
), src_reg(0), BRW_CONDITIONAL_NZ
));
913 unreachable("not reached");
918 ir
->condition
->accept(this);
920 emit(IF(this->result
, src_reg(0), BRW_CONDITIONAL_NZ
));
924 vec4_visitor::visit(ir_variable
*ir
)
928 if (variable_storage(ir
))
931 switch (ir
->data
.mode
) {
932 case ir_var_shader_in
:
933 reg
= new(mem_ctx
) dst_reg(ATTR
, ir
->data
.location
);
936 case ir_var_shader_out
:
937 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
939 for (int i
= 0; i
< type_size(ir
->type
); i
++) {
940 output_reg
[ir
->data
.location
+ i
] = *reg
;
941 output_reg
[ir
->data
.location
+ i
].reg_offset
= i
;
942 output_reg
[ir
->data
.location
+ i
].type
=
943 brw_type_for_base_type(ir
->type
->get_scalar_type());
944 output_reg_annotation
[ir
->data
.location
+ i
] = ir
->name
;
949 case ir_var_temporary
:
950 reg
= new(mem_ctx
) dst_reg(this, ir
->type
);
954 reg
= new(this->mem_ctx
) dst_reg(UNIFORM
, this->uniforms
);
956 /* Thanks to the lower_ubo_reference pass, we will see only
957 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
958 * variables, so no need for them to be in variable_ht.
960 * Some uniforms, such as samplers and atomic counters, have no actual
961 * storage, so we should ignore them.
963 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
966 /* Track how big the whole uniform variable is, in case we need to put a
967 * copy of its data into pull constants for array access.
969 assert(this->uniforms
< uniform_array_size
);
970 this->uniform_size
[this->uniforms
] = type_size(ir
->type
);
972 if (!strncmp(ir
->name
, "gl_", 3)) {
973 setup_builtin_uniform_values(ir
);
975 setup_uniform_values(ir
);
979 case ir_var_system_value
:
980 reg
= make_reg_for_system_value(ir
);
984 unreachable("not reached");
987 reg
->type
= brw_type_for_base_type(ir
->type
);
988 hash_table_insert(this->variable_ht
, reg
, ir
);
992 vec4_visitor::visit(ir_loop
*ir
)
994 /* We don't want debugging output to print the whole body of the
995 * loop as the annotation.
997 this->base_ir
= NULL
;
1001 visit_instructions(&ir
->body_instructions
);
1003 emit(BRW_OPCODE_WHILE
);
1007 vec4_visitor::visit(ir_loop_jump
*ir
)
1010 case ir_loop_jump::jump_break
:
1011 emit(BRW_OPCODE_BREAK
);
1013 case ir_loop_jump::jump_continue
:
1014 emit(BRW_OPCODE_CONTINUE
);
1021 vec4_visitor::visit(ir_function_signature
*)
1023 unreachable("not reached");
1027 vec4_visitor::visit(ir_function
*ir
)
1029 /* Ignore function bodies other than main() -- we shouldn't see calls to
1030 * them since they should all be inlined.
1032 if (strcmp(ir
->name
, "main") == 0) {
1033 const ir_function_signature
*sig
;
1036 sig
= ir
->matching_signature(NULL
, &empty
, false);
1040 visit_instructions(&sig
->body
);
1045 vec4_visitor::try_emit_mad(ir_expression
*ir
)
1047 /* 3-src instructions were introduced in gen6. */
1051 /* MAD can only handle floating-point data. */
1052 if (ir
->type
->base_type
!= GLSL_TYPE_FLOAT
)
1055 ir_rvalue
*nonmul
= ir
->operands
[1];
1056 ir_expression
*mul
= ir
->operands
[0]->as_expression();
1058 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
1059 nonmul
= ir
->operands
[0];
1060 mul
= ir
->operands
[1]->as_expression();
1062 if (!mul
|| mul
->operation
!= ir_binop_mul
)
1066 nonmul
->accept(this);
1067 src_reg src0
= fix_3src_operand(this->result
);
1069 mul
->operands
[0]->accept(this);
1070 src_reg src1
= fix_3src_operand(this->result
);
1072 mul
->operands
[1]->accept(this);
1073 src_reg src2
= fix_3src_operand(this->result
);
1075 this->result
= src_reg(this, ir
->type
);
1076 emit(BRW_OPCODE_MAD
, dst_reg(this->result
), src0
, src1
, src2
);
1082 vec4_visitor::try_emit_b2f_of_compare(ir_expression
*ir
)
1084 /* This optimization relies on CMP setting the destination to 0 when
1085 * false. Early hardware only sets the least significant bit, and
1086 * leaves the other bits undefined. So we can't use it.
1091 ir_expression
*const cmp
= ir
->operands
[0]->as_expression();
1096 switch (cmp
->operation
) {
1098 case ir_binop_greater
:
1099 case ir_binop_lequal
:
1100 case ir_binop_gequal
:
1101 case ir_binop_equal
:
1102 case ir_binop_nequal
:
1109 cmp
->operands
[0]->accept(this);
1110 const src_reg cmp_src0
= this->result
;
1112 cmp
->operands
[1]->accept(this);
1113 const src_reg cmp_src1
= this->result
;
1115 this->result
= src_reg(this, ir
->type
);
1117 emit(CMP(dst_reg(this->result
), cmp_src0
, cmp_src1
,
1118 brw_conditional_for_comparison(cmp
->operation
)));
1120 /* If the comparison is false, this->result will just happen to be zero.
1122 vec4_instruction
*const inst
= emit(BRW_OPCODE_SEL
, dst_reg(this->result
),
1123 this->result
, src_reg(1.0f
));
1124 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1125 inst
->predicate_inverse
= true;
1131 vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
1132 src_reg src0
, src_reg src1
)
1134 vec4_instruction
*inst
;
1136 if (brw
->gen
>= 6) {
1137 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1138 inst
->conditional_mod
= conditionalmod
;
1140 emit(CMP(dst
, src0
, src1
, conditionalmod
));
1142 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
1143 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1148 vec4_visitor::emit_lrp(const dst_reg
&dst
,
1149 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
)
1151 if (brw
->gen
>= 6) {
1152 /* Note that the instruction's argument order is reversed from GLSL
1156 fix_3src_operand(a
), fix_3src_operand(y
), fix_3src_operand(x
)));
1158 /* Earlier generations don't support three source operations, so we
1159 * need to emit x*(1-a) + y*a.
1161 dst_reg y_times_a
= dst_reg(this, glsl_type::vec4_type
);
1162 dst_reg one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1163 dst_reg x_times_one_minus_a
= dst_reg(this, glsl_type::vec4_type
);
1164 y_times_a
.writemask
= dst
.writemask
;
1165 one_minus_a
.writemask
= dst
.writemask
;
1166 x_times_one_minus_a
.writemask
= dst
.writemask
;
1168 emit(MUL(y_times_a
, y
, a
));
1169 emit(ADD(one_minus_a
, negate(a
), src_reg(1.0f
)));
1170 emit(MUL(x_times_one_minus_a
, x
, src_reg(one_minus_a
)));
1171 emit(ADD(dst
, src_reg(x_times_one_minus_a
), src_reg(y_times_a
)));
1176 vec4_visitor::visit(ir_expression
*ir
)
1178 unsigned int operand
;
1179 src_reg op
[Elements(ir
->operands
)];
1180 vec4_instruction
*inst
;
1182 if (ir
->operation
== ir_binop_add
) {
1183 if (try_emit_mad(ir
))
1187 if (ir
->operation
== ir_unop_b2f
) {
1188 if (try_emit_b2f_of_compare(ir
))
1192 /* Storage for our result. Ideally for an assignment we'd be using
1193 * the actual storage for the result here, instead.
1195 dst_reg
result_dst(this, ir
->type
);
1196 src_reg
result_src(result_dst
);
1198 if (ir
->operation
== ir_triop_csel
) {
1199 ir
->operands
[1]->accept(this);
1200 op
[1] = this->result
;
1201 ir
->operands
[2]->accept(this);
1202 op
[2] = this->result
;
1204 enum brw_predicate predicate
;
1205 emit_bool_to_cond_code(ir
->operands
[0], &predicate
);
1206 inst
= emit(BRW_OPCODE_SEL
, result_dst
, op
[1], op
[2]);
1207 inst
->predicate
= predicate
;
1208 this->result
= result_src
;
1212 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1213 this->result
.file
= BAD_FILE
;
1214 ir
->operands
[operand
]->accept(this);
1215 if (this->result
.file
== BAD_FILE
) {
1216 fprintf(stderr
, "Failed to get tree for expression operand:\n");
1217 ir
->operands
[operand
]->fprint(stderr
);
1220 op
[operand
] = this->result
;
1222 /* Matrix expression operands should have been broken down to vector
1223 * operations already.
1225 assert(!ir
->operands
[operand
]->type
->is_matrix());
1228 /* If nothing special happens, this is the result. */
1229 this->result
= result_src
;
1231 switch (ir
->operation
) {
1232 case ir_unop_logic_not
:
1233 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
1234 emit(NOT(result_dst
, op
[0]));
1236 emit(XOR(result_dst
, op
[0], src_reg(1u)));
1240 op
[0].negate
= !op
[0].negate
;
1241 emit(MOV(result_dst
, op
[0]));
1245 op
[0].negate
= false;
1246 emit(MOV(result_dst
, op
[0]));
1250 if (ir
->type
->is_float()) {
1251 /* AND(val, 0x80000000) gives the sign bit.
1253 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1256 emit(CMP(dst_null_f(), op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1258 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1259 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1260 emit(AND(result_dst
, op
[0], src_reg(0x80000000u
)));
1262 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(0x3f800000u
)));
1263 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1265 this->result
.type
= BRW_REGISTER_TYPE_F
;
1267 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1268 * -> non-negative val generates 0x00000000.
1269 * Predicated OR sets 1 if val is positive.
1271 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_G
));
1273 emit(ASR(result_dst
, op
[0], src_reg(31)));
1275 inst
= emit(OR(result_dst
, src_reg(result_dst
), src_reg(1)));
1276 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1281 emit_math(SHADER_OPCODE_RCP
, result_dst
, op
[0]);
1285 emit_math(SHADER_OPCODE_EXP2
, result_dst
, op
[0]);
1288 emit_math(SHADER_OPCODE_LOG2
, result_dst
, op
[0]);
1292 unreachable("not reached: should be handled by ir_explog_to_explog2");
1294 case ir_unop_sin_reduced
:
1295 emit_math(SHADER_OPCODE_SIN
, result_dst
, op
[0]);
1298 case ir_unop_cos_reduced
:
1299 emit_math(SHADER_OPCODE_COS
, result_dst
, op
[0]);
1303 case ir_unop_dFdx_coarse
:
1304 case ir_unop_dFdx_fine
:
1306 case ir_unop_dFdy_coarse
:
1307 case ir_unop_dFdy_fine
:
1308 unreachable("derivatives not valid in vertex shader");
1310 case ir_unop_bitfield_reverse
:
1311 emit(BFREV(result_dst
, op
[0]));
1313 case ir_unop_bit_count
:
1314 emit(CBIT(result_dst
, op
[0]));
1316 case ir_unop_find_msb
: {
1317 src_reg temp
= src_reg(this, glsl_type::uint_type
);
1319 inst
= emit(FBH(dst_reg(temp
), op
[0]));
1320 inst
->dst
.writemask
= WRITEMASK_XYZW
;
1322 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1323 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1324 * subtract the result from 31 to convert the MSB count into an LSB count.
1327 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
1328 temp
.swizzle
= BRW_SWIZZLE_NOOP
;
1329 emit(MOV(result_dst
, temp
));
1331 src_reg src_tmp
= src_reg(result_dst
);
1332 emit(CMP(dst_null_d(), src_tmp
, src_reg(-1), BRW_CONDITIONAL_NZ
));
1334 src_tmp
.negate
= true;
1335 inst
= emit(ADD(result_dst
, src_tmp
, src_reg(31)));
1336 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1339 case ir_unop_find_lsb
:
1340 emit(FBL(result_dst
, op
[0]));
1342 case ir_unop_saturate
:
1343 inst
= emit(MOV(result_dst
, op
[0]));
1344 inst
->saturate
= true;
1348 unreachable("not reached: should be handled by lower_noise");
1351 emit(ADD(result_dst
, op
[0], op
[1]));
1354 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1357 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
1358 /* For integer multiplication, the MUL uses the low 16 bits of one of
1359 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1360 * accumulates in the contribution of the upper 16 bits of that
1361 * operand. If we can determine that one of the args is in the low
1362 * 16 bits, though, we can just emit a single MUL.
1364 if (ir
->operands
[0]->is_uint16_constant()) {
1366 emit(MUL(result_dst
, op
[0], op
[1]));
1368 emit(MUL(result_dst
, op
[1], op
[0]));
1369 } else if (ir
->operands
[1]->is_uint16_constant()) {
1371 emit(MUL(result_dst
, op
[1], op
[0]));
1373 emit(MUL(result_dst
, op
[0], op
[1]));
1375 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1377 emit(MUL(acc
, op
[0], op
[1]));
1378 emit(MACH(dst_null_d(), op
[0], op
[1]));
1379 emit(MOV(result_dst
, src_reg(acc
)));
1382 emit(MUL(result_dst
, op
[0], op
[1]));
1385 case ir_binop_imul_high
: {
1386 struct brw_reg acc
= retype(brw_acc_reg(8), result_dst
.type
);
1388 emit(MUL(acc
, op
[0], op
[1]));
1389 emit(MACH(result_dst
, op
[0], op
[1]));
1393 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
1394 assert(ir
->type
->is_integer());
1395 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result_dst
, op
[0], op
[1]);
1397 case ir_binop_carry
: {
1398 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1400 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1401 emit(MOV(result_dst
, src_reg(acc
)));
1404 case ir_binop_borrow
: {
1405 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1407 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1408 emit(MOV(result_dst
, src_reg(acc
)));
1412 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
1413 assert(ir
->type
->is_integer());
1414 emit_math(SHADER_OPCODE_INT_REMAINDER
, result_dst
, op
[0], op
[1]);
1418 case ir_binop_greater
:
1419 case ir_binop_lequal
:
1420 case ir_binop_gequal
:
1421 case ir_binop_equal
:
1422 case ir_binop_nequal
: {
1423 emit(CMP(result_dst
, op
[0], op
[1],
1424 brw_conditional_for_comparison(ir
->operation
)));
1425 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1426 emit(AND(result_dst
, result_src
, src_reg(1u)));
1431 case ir_binop_all_equal
:
1432 /* "==" operator producing a scalar boolean. */
1433 if (ir
->operands
[0]->type
->is_vector() ||
1434 ir
->operands
[1]->type
->is_vector()) {
1435 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_Z
));
1436 emit(MOV(result_dst
, src_reg(0)));
1437 inst
= emit(MOV(result_dst
, src_reg(ctx
->Const
.UniformBooleanTrue
)));
1438 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1440 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1441 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1442 emit(AND(result_dst
, result_src
, src_reg(1u)));
1446 case ir_binop_any_nequal
:
1447 /* "!=" operator producing a scalar boolean. */
1448 if (ir
->operands
[0]->type
->is_vector() ||
1449 ir
->operands
[1]->type
->is_vector()) {
1450 emit(CMP(dst_null_d(), op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1452 emit(MOV(result_dst
, src_reg(0)));
1453 inst
= emit(MOV(result_dst
, src_reg(ctx
->Const
.UniformBooleanTrue
)));
1454 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1456 emit(CMP(result_dst
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1457 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1458 emit(AND(result_dst
, result_src
, src_reg(1u)));
1464 emit(CMP(dst_null_d(), op
[0], src_reg(0), BRW_CONDITIONAL_NZ
));
1465 emit(MOV(result_dst
, src_reg(0)));
1467 inst
= emit(MOV(result_dst
, src_reg(ctx
->Const
.UniformBooleanTrue
)));
1468 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1471 case ir_binop_logic_xor
:
1472 emit(XOR(result_dst
, op
[0], op
[1]));
1475 case ir_binop_logic_or
:
1476 emit(OR(result_dst
, op
[0], op
[1]));
1479 case ir_binop_logic_and
:
1480 emit(AND(result_dst
, op
[0], op
[1]));
1484 assert(ir
->operands
[0]->type
->is_vector());
1485 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1486 emit_dp(result_dst
, op
[0], op
[1], ir
->operands
[0]->type
->vector_elements
);
1490 emit_math(SHADER_OPCODE_SQRT
, result_dst
, op
[0]);
1493 emit_math(SHADER_OPCODE_RSQ
, result_dst
, op
[0]);
1496 case ir_unop_bitcast_i2f
:
1497 case ir_unop_bitcast_u2f
:
1498 this->result
= op
[0];
1499 this->result
.type
= BRW_REGISTER_TYPE_F
;
1502 case ir_unop_bitcast_f2i
:
1503 this->result
= op
[0];
1504 this->result
.type
= BRW_REGISTER_TYPE_D
;
1507 case ir_unop_bitcast_f2u
:
1508 this->result
= op
[0];
1509 this->result
.type
= BRW_REGISTER_TYPE_UD
;
1518 emit(MOV(result_dst
, op
[0]));
1521 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
1522 emit(AND(result_dst
, op
[0], src_reg(1u)));
1524 emit(MOV(result_dst
, op
[0]));
1528 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
1529 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1530 result_dst
.type
= BRW_REGISTER_TYPE_UD
;
1531 emit(AND(result_dst
, op
[0], src_reg(0x3f800000u
)));
1532 result_dst
.type
= BRW_REGISTER_TYPE_F
;
1534 emit(MOV(result_dst
, op
[0]));
1539 emit(CMP(result_dst
, op
[0], src_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1540 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1541 emit(AND(result_dst
, result_src
, src_reg(1u)));
1546 emit(RNDZ(result_dst
, op
[0]));
1549 op
[0].negate
= !op
[0].negate
;
1550 inst
= emit(RNDD(result_dst
, op
[0]));
1551 this->result
.negate
= true;
1554 inst
= emit(RNDD(result_dst
, op
[0]));
1557 inst
= emit(FRC(result_dst
, op
[0]));
1559 case ir_unop_round_even
:
1560 emit(RNDE(result_dst
, op
[0]));
1564 emit_minmax(BRW_CONDITIONAL_L
, result_dst
, op
[0], op
[1]);
1567 emit_minmax(BRW_CONDITIONAL_G
, result_dst
, op
[0], op
[1]);
1571 emit_math(SHADER_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1574 case ir_unop_bit_not
:
1575 inst
= emit(NOT(result_dst
, op
[0]));
1577 case ir_binop_bit_and
:
1578 inst
= emit(AND(result_dst
, op
[0], op
[1]));
1580 case ir_binop_bit_xor
:
1581 inst
= emit(XOR(result_dst
, op
[0], op
[1]));
1583 case ir_binop_bit_or
:
1584 inst
= emit(OR(result_dst
, op
[0], op
[1]));
1587 case ir_binop_lshift
:
1588 inst
= emit(SHL(result_dst
, op
[0], op
[1]));
1591 case ir_binop_rshift
:
1592 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
1593 inst
= emit(ASR(result_dst
, op
[0], op
[1]));
1595 inst
= emit(SHR(result_dst
, op
[0], op
[1]));
1599 emit(BFI1(result_dst
, op
[0], op
[1]));
1602 case ir_binop_ubo_load
: {
1603 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1604 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1605 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
1608 /* Now, load the vector from that offset. */
1609 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1611 src_reg packed_consts
= src_reg(this, glsl_type::vec4_type
);
1612 packed_consts
.type
= result
.type
;
1615 if (const_uniform_block
) {
1616 /* The block index is a constant, so just emit the binding table entry
1619 surf_index
= src_reg(prog_data
->base
.binding_table
.ubo_start
+
1620 const_uniform_block
->value
.u
[0]);
1622 /* The block index is not a constant. Evaluate the index expression
1623 * per-channel and add the base UBO index; the generator will select
1624 * a value from any live channel.
1626 surf_index
= src_reg(this, glsl_type::uint_type
);
1627 emit(ADD(dst_reg(surf_index
), op
[0],
1628 src_reg(prog_data
->base
.binding_table
.ubo_start
)));
1630 /* Assume this may touch any UBO. It would be nice to provide
1631 * a tighter bound, but the array information is already lowered away.
1633 brw_mark_surface_used(&prog_data
->base
,
1634 prog_data
->base
.binding_table
.ubo_start
+
1635 shader_prog
->NumUniformBlocks
- 1);
1638 if (const_offset_ir
) {
1639 if (brw
->gen
>= 8) {
1640 /* Store the offset in a GRF so we can send-from-GRF. */
1641 offset
= src_reg(this, glsl_type::int_type
);
1642 emit(MOV(dst_reg(offset
), src_reg(const_offset
/ 16)));
1644 /* Immediates are fine on older generations since they'll be moved
1645 * to a (potentially fake) MRF at the generator level.
1647 offset
= src_reg(const_offset
/ 16);
1650 offset
= src_reg(this, glsl_type::uint_type
);
1651 emit(SHR(dst_reg(offset
), op
[1], src_reg(4)));
1654 if (brw
->gen
>= 7) {
1655 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
1656 grf_offset
.type
= offset
.type
;
1658 emit(MOV(grf_offset
, offset
));
1660 emit(new(mem_ctx
) vec4_instruction(this,
1661 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
1662 dst_reg(packed_consts
),
1664 src_reg(grf_offset
)));
1666 vec4_instruction
*pull
=
1667 emit(new(mem_ctx
) vec4_instruction(this,
1668 VS_OPCODE_PULL_CONSTANT_LOAD
,
1669 dst_reg(packed_consts
),
1672 pull
->base_mrf
= 14;
1676 packed_consts
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1677 packed_consts
.swizzle
+= BRW_SWIZZLE4(const_offset
% 16 / 4,
1678 const_offset
% 16 / 4,
1679 const_offset
% 16 / 4,
1680 const_offset
% 16 / 4);
1682 /* UBO bools are any nonzero int. We need to convert them to use the
1683 * value of true stored in ctx->Const.UniformBooleanTrue.
1685 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1686 emit(CMP(result_dst
, packed_consts
, src_reg(0u),
1687 BRW_CONDITIONAL_NZ
));
1688 if (ctx
->Const
.UniformBooleanTrue
== 1) {
1689 emit(AND(result_dst
, result
, src_reg(1u)));
1692 emit(MOV(result_dst
, packed_consts
));
1697 case ir_binop_vector_extract
:
1698 unreachable("should have been lowered by vec_index_to_cond_assign");
1701 op
[0] = fix_3src_operand(op
[0]);
1702 op
[1] = fix_3src_operand(op
[1]);
1703 op
[2] = fix_3src_operand(op
[2]);
1704 /* Note that the instruction's argument order is reversed from GLSL
1707 emit(MAD(result_dst
, op
[2], op
[1], op
[0]));
1711 emit_lrp(result_dst
, op
[0], op
[1], op
[2]);
1715 unreachable("already handled above");
1719 op
[0] = fix_3src_operand(op
[0]);
1720 op
[1] = fix_3src_operand(op
[1]);
1721 op
[2] = fix_3src_operand(op
[2]);
1722 emit(BFI2(result_dst
, op
[0], op
[1], op
[2]));
1725 case ir_triop_bitfield_extract
:
1726 op
[0] = fix_3src_operand(op
[0]);
1727 op
[1] = fix_3src_operand(op
[1]);
1728 op
[2] = fix_3src_operand(op
[2]);
1729 /* Note that the instruction's argument order is reversed from GLSL
1732 emit(BFE(result_dst
, op
[2], op
[1], op
[0]));
1735 case ir_triop_vector_insert
:
1736 unreachable("should have been lowered by lower_vector_insert");
1738 case ir_quadop_bitfield_insert
:
1739 unreachable("not reached: should be handled by "
1740 "bitfield_insert_to_bfm_bfi\n");
1742 case ir_quadop_vector
:
1743 unreachable("not reached: should be handled by lower_quadop_vector");
1745 case ir_unop_pack_half_2x16
:
1746 emit_pack_half_2x16(result_dst
, op
[0]);
1748 case ir_unop_unpack_half_2x16
:
1749 emit_unpack_half_2x16(result_dst
, op
[0]);
1751 case ir_unop_pack_snorm_2x16
:
1752 case ir_unop_pack_snorm_4x8
:
1753 case ir_unop_pack_unorm_2x16
:
1754 case ir_unop_pack_unorm_4x8
:
1755 case ir_unop_unpack_snorm_2x16
:
1756 case ir_unop_unpack_snorm_4x8
:
1757 case ir_unop_unpack_unorm_2x16
:
1758 case ir_unop_unpack_unorm_4x8
:
1759 unreachable("not reached: should be handled by lower_packing_builtins");
1760 case ir_unop_unpack_half_2x16_split_x
:
1761 case ir_unop_unpack_half_2x16_split_y
:
1762 case ir_binop_pack_half_2x16_split
:
1763 case ir_unop_interpolate_at_centroid
:
1764 case ir_binop_interpolate_at_sample
:
1765 case ir_binop_interpolate_at_offset
:
1766 unreachable("not reached: should not occur in vertex shader");
1767 case ir_binop_ldexp
:
1768 unreachable("not reached: should be handled by ldexp_to_arith()");
1774 vec4_visitor::visit(ir_swizzle
*ir
)
1780 /* Note that this is only swizzles in expressions, not those on the left
1781 * hand side of an assignment, which do write masking. See ir_assignment
1785 ir
->val
->accept(this);
1787 assert(src
.file
!= BAD_FILE
);
1789 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1792 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.x
);
1795 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.y
);
1798 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.z
);
1801 swizzle
[i
] = BRW_GET_SWZ(src
.swizzle
, ir
->mask
.w
);
1805 for (; i
< 4; i
++) {
1806 /* Replicate the last channel out. */
1807 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
1810 src
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1816 vec4_visitor::visit(ir_dereference_variable
*ir
)
1818 const struct glsl_type
*type
= ir
->type
;
1819 dst_reg
*reg
= variable_storage(ir
->var
);
1822 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
1823 this->result
= src_reg(brw_null_reg());
1827 this->result
= src_reg(*reg
);
1829 /* System values get their swizzle from the dst_reg writemask */
1830 if (ir
->var
->data
.mode
== ir_var_system_value
)
1833 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
1834 this->result
.swizzle
= swizzle_for_size(type
->vector_elements
);
1839 vec4_visitor::compute_array_stride(ir_dereference_array
*ir
)
1841 /* Under normal circumstances array elements are stored consecutively, so
1842 * the stride is equal to the size of the array element.
1844 return type_size(ir
->type
);
1849 vec4_visitor::visit(ir_dereference_array
*ir
)
1851 ir_constant
*constant_index
;
1853 int array_stride
= compute_array_stride(ir
);
1855 constant_index
= ir
->array_index
->constant_expression_value();
1857 ir
->array
->accept(this);
1860 if (constant_index
) {
1861 src
.reg_offset
+= constant_index
->value
.i
[0] * array_stride
;
1863 /* Variable index array dereference. It eats the "vec4" of the
1864 * base of the array and an index that offsets the Mesa register
1867 ir
->array_index
->accept(this);
1871 if (array_stride
== 1) {
1872 index_reg
= this->result
;
1874 index_reg
= src_reg(this, glsl_type::int_type
);
1876 emit(MUL(dst_reg(index_reg
), this->result
, src_reg(array_stride
)));
1880 src_reg temp
= src_reg(this, glsl_type::int_type
);
1882 emit(ADD(dst_reg(temp
), *src
.reladdr
, index_reg
));
1887 src
.reladdr
= ralloc(mem_ctx
, src_reg
);
1888 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
1891 /* If the type is smaller than a vec4, replicate the last channel out. */
1892 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1893 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1895 src
.swizzle
= BRW_SWIZZLE_NOOP
;
1896 src
.type
= brw_type_for_base_type(ir
->type
);
1902 vec4_visitor::visit(ir_dereference_record
*ir
)
1905 const glsl_type
*struct_type
= ir
->record
->type
;
1908 ir
->record
->accept(this);
1910 for (i
= 0; i
< struct_type
->length
; i
++) {
1911 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
1913 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
1916 /* If the type is smaller than a vec4, replicate the last channel out. */
1917 if (ir
->type
->is_scalar() || ir
->type
->is_vector() || ir
->type
->is_matrix())
1918 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1920 this->result
.swizzle
= BRW_SWIZZLE_NOOP
;
1921 this->result
.type
= brw_type_for_base_type(ir
->type
);
1923 this->result
.reg_offset
+= offset
;
1927 * We want to be careful in assignment setup to hit the actual storage
1928 * instead of potentially using a temporary like we might with the
1929 * ir_dereference handler.
1932 get_assignment_lhs(ir_dereference
*ir
, vec4_visitor
*v
)
1934 /* The LHS must be a dereference. If the LHS is a variable indexed array
1935 * access of a vector, it must be separated into a series conditional moves
1936 * before reaching this point (see ir_vec_index_to_cond_assign).
1938 assert(ir
->as_dereference());
1939 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
1941 assert(!deref_array
->array
->type
->is_vector());
1944 /* Use the rvalue deref handler for the most part. We'll ignore
1945 * swizzles in it and write swizzles using writemask, though.
1948 return dst_reg(v
->result
);
1952 vec4_visitor::emit_block_move(dst_reg
*dst
, src_reg
*src
,
1953 const struct glsl_type
*type
,
1954 enum brw_predicate predicate
)
1956 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
1957 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1958 emit_block_move(dst
, src
, type
->fields
.structure
[i
].type
, predicate
);
1963 if (type
->is_array()) {
1964 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1965 emit_block_move(dst
, src
, type
->fields
.array
, predicate
);
1970 if (type
->is_matrix()) {
1971 const struct glsl_type
*vec_type
;
1973 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
1974 type
->vector_elements
, 1);
1976 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
1977 emit_block_move(dst
, src
, vec_type
, predicate
);
1982 assert(type
->is_scalar() || type
->is_vector());
1984 dst
->type
= brw_type_for_base_type(type
);
1985 src
->type
= dst
->type
;
1987 dst
->writemask
= (1 << type
->vector_elements
) - 1;
1989 src
->swizzle
= swizzle_for_size(type
->vector_elements
);
1991 vec4_instruction
*inst
= emit(MOV(*dst
, *src
));
1992 inst
->predicate
= predicate
;
1999 /* If the RHS processing resulted in an instruction generating a
2000 * temporary value, and it would be easy to rewrite the instruction to
2001 * generate its result right into the LHS instead, do so. This ends
2002 * up reliably removing instructions where it can be tricky to do so
2003 * later without real UD chain information.
2006 vec4_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
2009 vec4_instruction
*pre_rhs_inst
,
2010 vec4_instruction
*last_rhs_inst
)
2012 /* This could be supported, but it would take more smarts. */
2016 if (pre_rhs_inst
== last_rhs_inst
)
2017 return false; /* No instructions generated to work with. */
2019 /* Make sure the last instruction generated our source reg. */
2020 if (src
.file
!= GRF
||
2021 src
.file
!= last_rhs_inst
->dst
.file
||
2022 src
.reg
!= last_rhs_inst
->dst
.reg
||
2023 src
.reg_offset
!= last_rhs_inst
->dst
.reg_offset
||
2027 last_rhs_inst
->predicate
!= BRW_PREDICATE_NONE
)
2030 /* Check that that last instruction fully initialized the channels
2031 * we want to use, in the order we want to use them. We could
2032 * potentially reswizzle the operands of many instructions so that
2033 * we could handle out of order channels, but don't yet.
2036 for (unsigned i
= 0; i
< 4; i
++) {
2037 if (dst
.writemask
& (1 << i
)) {
2038 if (!(last_rhs_inst
->dst
.writemask
& (1 << i
)))
2041 if (BRW_GET_SWZ(src
.swizzle
, i
) != i
)
2046 /* Success! Rewrite the instruction. */
2047 last_rhs_inst
->dst
.file
= dst
.file
;
2048 last_rhs_inst
->dst
.reg
= dst
.reg
;
2049 last_rhs_inst
->dst
.reg_offset
= dst
.reg_offset
;
2050 last_rhs_inst
->dst
.reladdr
= dst
.reladdr
;
2051 last_rhs_inst
->dst
.writemask
&= dst
.writemask
;
2057 vec4_visitor::visit(ir_assignment
*ir
)
2059 dst_reg dst
= get_assignment_lhs(ir
->lhs
, this);
2060 enum brw_predicate predicate
= BRW_PREDICATE_NONE
;
2062 if (!ir
->lhs
->type
->is_scalar() &&
2063 !ir
->lhs
->type
->is_vector()) {
2064 ir
->rhs
->accept(this);
2065 src_reg src
= this->result
;
2067 if (ir
->condition
) {
2068 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2071 /* emit_block_move doesn't account for swizzles in the source register.
2072 * This should be ok, since the source register is a structure or an
2073 * array, and those can't be swizzled. But double-check to be sure.
2075 assert(src
.swizzle
==
2076 (ir
->rhs
->type
->is_matrix()
2077 ? swizzle_for_size(ir
->rhs
->type
->vector_elements
)
2078 : BRW_SWIZZLE_NOOP
));
2080 emit_block_move(&dst
, &src
, ir
->rhs
->type
, predicate
);
2084 /* Now we're down to just a scalar/vector with writemasks. */
2087 vec4_instruction
*pre_rhs_inst
, *last_rhs_inst
;
2088 pre_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2090 ir
->rhs
->accept(this);
2092 last_rhs_inst
= (vec4_instruction
*)this->instructions
.get_tail();
2094 src_reg src
= this->result
;
2097 int first_enabled_chan
= 0;
2100 assert(ir
->lhs
->type
->is_vector() ||
2101 ir
->lhs
->type
->is_scalar());
2102 dst
.writemask
= ir
->write_mask
;
2104 for (int i
= 0; i
< 4; i
++) {
2105 if (dst
.writemask
& (1 << i
)) {
2106 first_enabled_chan
= BRW_GET_SWZ(src
.swizzle
, i
);
2111 /* Swizzle a small RHS vector into the channels being written.
2113 * glsl ir treats write_mask as dictating how many channels are
2114 * present on the RHS while in our instructions we need to make
2115 * those channels appear in the slots of the vec4 they're written to.
2117 for (int i
= 0; i
< 4; i
++) {
2118 if (dst
.writemask
& (1 << i
))
2119 swizzles
[i
] = BRW_GET_SWZ(src
.swizzle
, src_chan
++);
2121 swizzles
[i
] = first_enabled_chan
;
2123 src
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
2124 swizzles
[2], swizzles
[3]);
2126 if (try_rewrite_rhs_to_dst(ir
, dst
, src
, pre_rhs_inst
, last_rhs_inst
)) {
2130 if (ir
->condition
) {
2131 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2134 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
2135 vec4_instruction
*inst
= emit(MOV(dst
, src
));
2136 inst
->predicate
= predicate
;
2144 vec4_visitor::emit_constant_values(dst_reg
*dst
, ir_constant
*ir
)
2146 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2147 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2148 emit_constant_values(dst
, field_value
);
2153 if (ir
->type
->is_array()) {
2154 for (unsigned int i
= 0; i
< ir
->type
->length
; i
++) {
2155 emit_constant_values(dst
, ir
->array_elements
[i
]);
2160 if (ir
->type
->is_matrix()) {
2161 for (int i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2162 float *vec
= &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2164 for (int j
= 0; j
< ir
->type
->vector_elements
; j
++) {
2165 dst
->writemask
= 1 << j
;
2166 dst
->type
= BRW_REGISTER_TYPE_F
;
2168 emit(MOV(*dst
, src_reg(vec
[j
])));
2175 int remaining_writemask
= (1 << ir
->type
->vector_elements
) - 1;
2177 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2178 if (!(remaining_writemask
& (1 << i
)))
2181 dst
->writemask
= 1 << i
;
2182 dst
->type
= brw_type_for_base_type(ir
->type
);
2184 /* Find other components that match the one we're about to
2185 * write. Emits fewer instructions for things like vec4(0.5,
2188 for (int j
= i
+ 1; j
< ir
->type
->vector_elements
; j
++) {
2189 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2190 if (ir
->value
.b
[i
] == ir
->value
.b
[j
])
2191 dst
->writemask
|= (1 << j
);
2193 /* u, i, and f storage all line up, so no need for a
2194 * switch case for comparing each type.
2196 if (ir
->value
.u
[i
] == ir
->value
.u
[j
])
2197 dst
->writemask
|= (1 << j
);
2201 switch (ir
->type
->base_type
) {
2202 case GLSL_TYPE_FLOAT
:
2203 emit(MOV(*dst
, src_reg(ir
->value
.f
[i
])));
2206 emit(MOV(*dst
, src_reg(ir
->value
.i
[i
])));
2208 case GLSL_TYPE_UINT
:
2209 emit(MOV(*dst
, src_reg(ir
->value
.u
[i
])));
2211 case GLSL_TYPE_BOOL
:
2213 src_reg(ir
->value
.b
[i
] != 0 ? ctx
->Const
.UniformBooleanTrue
2217 unreachable("Non-float/uint/int/bool constant");
2220 remaining_writemask
&= ~dst
->writemask
;
2226 vec4_visitor::visit(ir_constant
*ir
)
2228 dst_reg dst
= dst_reg(this, ir
->type
);
2229 this->result
= src_reg(dst
);
2231 emit_constant_values(&dst
, ir
);
2235 vec4_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2237 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2238 ir
->actual_parameters
.get_head());
2239 ir_variable
*location
= deref
->variable_referenced();
2240 unsigned surf_index
= (prog_data
->base
.binding_table
.abo_start
+
2241 location
->data
.binding
);
2243 /* Calculate the surface offset */
2244 src_reg
offset(this, glsl_type::uint_type
);
2245 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2247 deref_array
->array_index
->accept(this);
2249 src_reg
tmp(this, glsl_type::uint_type
);
2250 emit(MUL(dst_reg(tmp
), this->result
, ATOMIC_COUNTER_SIZE
));
2251 emit(ADD(dst_reg(offset
), tmp
, location
->data
.atomic
.offset
));
2253 offset
= location
->data
.atomic
.offset
;
2256 /* Emit the appropriate machine instruction */
2257 const char *callee
= ir
->callee
->function_name();
2258 dst_reg dst
= get_assignment_lhs(ir
->return_deref
, this);
2260 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2261 emit_untyped_surface_read(surf_index
, dst
, offset
);
2263 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2264 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2265 src_reg(), src_reg());
2267 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2268 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2269 src_reg(), src_reg());
2274 vec4_visitor::visit(ir_call
*ir
)
2276 const char *callee
= ir
->callee
->function_name();
2278 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2279 !strcmp("__intrinsic_atomic_increment", callee
) ||
2280 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2281 visit_atomic_counter_intrinsic(ir
);
2283 unreachable("Unsupported intrinsic.");
2288 vec4_visitor::emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
)
2290 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, SHADER_OPCODE_TXF_MCS
);
2293 inst
->dst
= dst_reg(this, glsl_type::uvec4_type
);
2294 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2296 inst
->src
[1] = sampler
;
2298 /* parameters are: u, v, r, lod; lod will always be zero due to api restrictions */
2299 int param_base
= inst
->base_mrf
;
2300 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2301 int zero_mask
= 0xf & ~coord_mask
;
2303 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2306 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2310 return src_reg(inst
->dst
);
2314 is_high_sampler(struct brw_context
*brw
, src_reg sampler
)
2316 if (brw
->gen
< 8 && !brw
->is_haswell
)
2319 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
2323 vec4_visitor::visit(ir_texture
*ir
)
2326 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
2328 ir_rvalue
*nonconst_sampler_index
=
2329 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
2331 /* Handle non-constant sampler array indexing */
2332 src_reg sampler_reg
;
2333 if (nonconst_sampler_index
) {
2334 /* The highest sampler which may be used by this operation is
2335 * the last element of the array. Mark it here, because the generator
2336 * doesn't have enough information to determine the bound.
2338 uint32_t array_size
= ir
->sampler
->as_dereference_array()
2339 ->array
->type
->array_size();
2341 uint32_t max_used
= sampler
+ array_size
- 1;
2342 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
2343 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2345 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2348 brw_mark_surface_used(&prog_data
->base
, max_used
);
2350 /* Emit code to evaluate the actual indexing expression */
2351 nonconst_sampler_index
->accept(this);
2352 dst_reg
temp(this, glsl_type::uint_type
);
2353 emit(ADD(temp
, this->result
, src_reg(sampler
)))
2354 ->force_writemask_all
= true;
2355 sampler_reg
= src_reg(temp
);
2357 /* Single sampler, or constant array index; the indexing expression
2358 * is just an immediate.
2360 sampler_reg
= src_reg(sampler
);
2363 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
2364 * emitting anything other than setting up the constant result.
2366 if (ir
->op
== ir_tg4
) {
2367 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2368 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2369 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
2370 dst_reg
result(this, ir
->type
);
2371 this->result
= src_reg(result
);
2372 emit(MOV(result
, src_reg(swiz
== SWIZZLE_ONE
? 1.0f
: 0.0f
)));
2377 /* Should be lowered by do_lower_texture_projection */
2378 assert(!ir
->projector
);
2380 /* Should be lowered */
2381 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2383 /* Generate code to compute all the subexpression trees. This has to be
2384 * done before loading any values into MRFs for the sampler message since
2385 * generating these values may involve SEND messages that need the MRFs.
2388 if (ir
->coordinate
) {
2389 ir
->coordinate
->accept(this);
2390 coordinate
= this->result
;
2393 src_reg shadow_comparitor
;
2394 if (ir
->shadow_comparitor
) {
2395 ir
->shadow_comparitor
->accept(this);
2396 shadow_comparitor
= this->result
;
2399 bool has_nonconstant_offset
= ir
->offset
&& !ir
->offset
->as_constant();
2400 src_reg offset_value
;
2401 if (has_nonconstant_offset
) {
2402 ir
->offset
->accept(this);
2403 offset_value
= src_reg(this->result
);
2406 const glsl_type
*lod_type
= NULL
, *sample_index_type
= NULL
;
2407 src_reg lod
, dPdx
, dPdy
, sample_index
, mcs
;
2410 lod
= src_reg(0.0f
);
2411 lod_type
= glsl_type::float_type
;
2416 ir
->lod_info
.lod
->accept(this);
2418 lod_type
= ir
->lod_info
.lod
->type
;
2420 case ir_query_levels
:
2422 lod_type
= glsl_type::int_type
;
2425 ir
->lod_info
.sample_index
->accept(this);
2426 sample_index
= this->result
;
2427 sample_index_type
= ir
->lod_info
.sample_index
->type
;
2429 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
2430 mcs
= emit_mcs_fetch(ir
, coordinate
, sampler_reg
);
2435 ir
->lod_info
.grad
.dPdx
->accept(this);
2436 dPdx
= this->result
;
2438 ir
->lod_info
.grad
.dPdy
->accept(this);
2439 dPdy
= this->result
;
2441 lod_type
= ir
->lod_info
.grad
.dPdx
->type
;
2451 case ir_tex
: opcode
= SHADER_OPCODE_TXL
; break;
2452 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
2453 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
2454 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
2455 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
2456 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
2457 case ir_tg4
: opcode
= has_nonconstant_offset
2458 ? SHADER_OPCODE_TG4_OFFSET
: SHADER_OPCODE_TG4
; break;
2459 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
2461 unreachable("TXB is not valid for vertex shaders.");
2463 unreachable("LOD is not valid for vertex shaders.");
2465 unreachable("Unrecognized tex op");
2468 vec4_instruction
*inst
= new(mem_ctx
) vec4_instruction(this, opcode
);
2470 if (ir
->offset
!= NULL
&& !has_nonconstant_offset
) {
2471 inst
->texture_offset
=
2472 brw_texture_offset(ctx
, ir
->offset
->as_constant()->value
.i
,
2473 ir
->offset
->type
->vector_elements
);
2476 /* Stuff the channel select bits in the top of the texture offset */
2477 if (ir
->op
== ir_tg4
)
2478 inst
->texture_offset
|= gather_channel(ir
, sampler
) << 16;
2480 /* The message header is necessary for:
2483 * - Gather channel selection
2484 * - Sampler indices too large to fit in a 4-bit value.
2486 inst
->header_present
=
2487 brw
->gen
< 5 || inst
->texture_offset
!= 0 || ir
->op
== ir_tg4
||
2488 is_high_sampler(brw
, sampler_reg
);
2490 inst
->mlen
= inst
->header_present
+ 1; /* always at least one */
2491 inst
->dst
= dst_reg(this, ir
->type
);
2492 inst
->dst
.writemask
= WRITEMASK_XYZW
;
2493 inst
->shadow_compare
= ir
->shadow_comparitor
!= NULL
;
2495 inst
->src
[1] = sampler_reg
;
2497 /* MRF for the first parameter */
2498 int param_base
= inst
->base_mrf
+ inst
->header_present
;
2500 if (ir
->op
== ir_txs
|| ir
->op
== ir_query_levels
) {
2501 int writemask
= brw
->gen
== 4 ? WRITEMASK_W
: WRITEMASK_X
;
2502 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, writemask
), lod
));
2504 /* Load the coordinate */
2505 /* FINISHME: gl_clamp_mask and saturate */
2506 int coord_mask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
2507 int zero_mask
= 0xf & ~coord_mask
;
2509 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, coord_mask
),
2512 if (zero_mask
!= 0) {
2513 emit(MOV(dst_reg(MRF
, param_base
, ir
->coordinate
->type
, zero_mask
),
2516 /* Load the shadow comparitor */
2517 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
&& (ir
->op
!= ir_tg4
|| !has_nonconstant_offset
)) {
2518 emit(MOV(dst_reg(MRF
, param_base
+ 1, ir
->shadow_comparitor
->type
,
2520 shadow_comparitor
));
2524 /* Load the LOD info */
2525 if (ir
->op
== ir_tex
|| ir
->op
== ir_txl
) {
2527 if (brw
->gen
>= 5) {
2528 mrf
= param_base
+ 1;
2529 if (ir
->shadow_comparitor
) {
2530 writemask
= WRITEMASK_Y
;
2531 /* mlen already incremented */
2533 writemask
= WRITEMASK_X
;
2536 } else /* brw->gen == 4 */ {
2538 writemask
= WRITEMASK_W
;
2540 emit(MOV(dst_reg(MRF
, mrf
, lod_type
, writemask
), lod
));
2541 } else if (ir
->op
== ir_txf
) {
2542 emit(MOV(dst_reg(MRF
, param_base
, lod_type
, WRITEMASK_W
), lod
));
2543 } else if (ir
->op
== ir_txf_ms
) {
2544 emit(MOV(dst_reg(MRF
, param_base
+ 1, sample_index_type
, WRITEMASK_X
),
2546 if (brw
->gen
>= 7) {
2547 /* MCS data is in the first channel of `mcs`, but we need to get it into
2548 * the .y channel of the second vec4 of params, so replicate .x across
2549 * the whole vec4 and then mask off everything except .y
2551 mcs
.swizzle
= BRW_SWIZZLE_XXXX
;
2552 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::uint_type
, WRITEMASK_Y
),
2556 } else if (ir
->op
== ir_txd
) {
2557 const glsl_type
*type
= lod_type
;
2559 if (brw
->gen
>= 5) {
2560 dPdx
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2561 dPdy
.swizzle
= BRW_SWIZZLE4(SWIZZLE_X
,SWIZZLE_X
,SWIZZLE_Y
,SWIZZLE_Y
);
2562 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XZ
), dPdx
));
2563 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_YW
), dPdy
));
2566 if (ir
->type
->vector_elements
== 3 || ir
->shadow_comparitor
) {
2567 dPdx
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2568 dPdy
.swizzle
= BRW_SWIZZLE_ZZZZ
;
2569 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_X
), dPdx
));
2570 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_Y
), dPdy
));
2573 if (ir
->shadow_comparitor
) {
2574 emit(MOV(dst_reg(MRF
, param_base
+ 2,
2575 ir
->shadow_comparitor
->type
, WRITEMASK_Z
),
2576 shadow_comparitor
));
2579 } else /* brw->gen == 4 */ {
2580 emit(MOV(dst_reg(MRF
, param_base
+ 1, type
, WRITEMASK_XYZ
), dPdx
));
2581 emit(MOV(dst_reg(MRF
, param_base
+ 2, type
, WRITEMASK_XYZ
), dPdy
));
2584 } else if (ir
->op
== ir_tg4
&& has_nonconstant_offset
) {
2585 if (ir
->shadow_comparitor
) {
2586 emit(MOV(dst_reg(MRF
, param_base
, ir
->shadow_comparitor
->type
, WRITEMASK_W
),
2587 shadow_comparitor
));
2590 emit(MOV(dst_reg(MRF
, param_base
+ 1, glsl_type::ivec2_type
, WRITEMASK_XY
),
2598 /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
2599 * spec requires layers.
2601 if (ir
->op
== ir_txs
) {
2602 glsl_type
const *type
= ir
->sampler
->type
;
2603 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2604 type
->sampler_array
) {
2605 emit_math(SHADER_OPCODE_INT_QUOTIENT
,
2606 writemask(inst
->dst
, WRITEMASK_Z
),
2607 src_reg(inst
->dst
), src_reg(6));
2611 if (brw
->gen
== 6 && ir
->op
== ir_tg4
) {
2612 emit_gen6_gather_wa(key
->tex
.gen6_gather_wa
[sampler
], inst
->dst
);
2615 swizzle_result(ir
, src_reg(inst
->dst
), sampler
);
2619 * Apply workarounds for Gen6 gather with UINT/SINT
2622 vec4_visitor::emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
)
2627 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2628 dst_reg dst_f
= dst
;
2629 dst_f
.type
= BRW_REGISTER_TYPE_F
;
2631 /* Convert from UNORM to UINT */
2632 emit(MUL(dst_f
, src_reg(dst_f
), src_reg((float)((1 << width
) - 1))));
2633 emit(MOV(dst
, src_reg(dst_f
)));
2636 /* Reinterpret the UINT value as a signed INT value by
2637 * shifting the sign bit into place, then shifting back
2640 emit(SHL(dst
, src_reg(dst
), src_reg(32 - width
)));
2641 emit(ASR(dst
, src_reg(dst
), src_reg(32 - width
)));
2646 * Set up the gather channel based on the swizzle, for gather4.
2649 vec4_visitor::gather_channel(ir_texture
*ir
, uint32_t sampler
)
2651 ir_constant
*chan
= ir
->lod_info
.component
->as_constant();
2652 int swiz
= GET_SWZ(key
->tex
.swizzles
[sampler
], chan
->value
.i
[0]);
2654 case SWIZZLE_X
: return 0;
2656 /* gather4 sampler is broken for green channel on RG32F --
2657 * we must ask for blue instead.
2659 if (key
->tex
.gather_channel_quirk_mask
& (1<<sampler
))
2662 case SWIZZLE_Z
: return 2;
2663 case SWIZZLE_W
: return 3;
2665 unreachable("Not reached"); /* zero, one swizzles handled already */
2670 vec4_visitor::swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
)
2672 int s
= key
->tex
.swizzles
[sampler
];
2674 this->result
= src_reg(this, ir
->type
);
2675 dst_reg
swizzled_result(this->result
);
2677 if (ir
->op
== ir_query_levels
) {
2678 /* # levels is in .w */
2679 orig_val
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2680 emit(MOV(swizzled_result
, orig_val
));
2684 if (ir
->op
== ir_txs
|| ir
->type
== glsl_type::float_type
2685 || s
== SWIZZLE_NOOP
|| ir
->op
== ir_tg4
) {
2686 emit(MOV(swizzled_result
, orig_val
));
2691 int zero_mask
= 0, one_mask
= 0, copy_mask
= 0;
2692 int swizzle
[4] = {0};
2694 for (int i
= 0; i
< 4; i
++) {
2695 switch (GET_SWZ(s
, i
)) {
2697 zero_mask
|= (1 << i
);
2700 one_mask
|= (1 << i
);
2703 copy_mask
|= (1 << i
);
2704 swizzle
[i
] = GET_SWZ(s
, i
);
2710 orig_val
.swizzle
= BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2711 swizzled_result
.writemask
= copy_mask
;
2712 emit(MOV(swizzled_result
, orig_val
));
2716 swizzled_result
.writemask
= zero_mask
;
2717 emit(MOV(swizzled_result
, src_reg(0.0f
)));
2721 swizzled_result
.writemask
= one_mask
;
2722 emit(MOV(swizzled_result
, src_reg(1.0f
)));
2727 vec4_visitor::visit(ir_return
*)
2729 unreachable("not reached");
2733 vec4_visitor::visit(ir_discard
*)
2735 unreachable("not reached");
2739 vec4_visitor::visit(ir_if
*ir
)
2741 /* Don't point the annotation at the if statement, because then it plus
2742 * the then and else blocks get printed.
2744 this->base_ir
= ir
->condition
;
2746 if (brw
->gen
== 6) {
2749 enum brw_predicate predicate
;
2750 emit_bool_to_cond_code(ir
->condition
, &predicate
);
2751 emit(IF(predicate
));
2754 visit_instructions(&ir
->then_instructions
);
2756 if (!ir
->else_instructions
.is_empty()) {
2757 this->base_ir
= ir
->condition
;
2758 emit(BRW_OPCODE_ELSE
);
2760 visit_instructions(&ir
->else_instructions
);
2763 this->base_ir
= ir
->condition
;
2764 emit(BRW_OPCODE_ENDIF
);
2768 vec4_visitor::visit(ir_emit_vertex
*)
2770 unreachable("not reached");
2774 vec4_visitor::visit(ir_end_primitive
*)
2776 unreachable("not reached");
2780 vec4_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2781 dst_reg dst
, src_reg offset
,
2782 src_reg src0
, src_reg src1
)
2786 /* Set the atomic operation offset. */
2787 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), offset
));
2790 /* Set the atomic operation arguments. */
2791 if (src0
.file
!= BAD_FILE
) {
2792 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src0
));
2796 if (src1
.file
!= BAD_FILE
) {
2797 emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen
, 0), WRITEMASK_X
), src1
));
2801 /* Emit the instruction. Note that this maps to the normal SIMD8
2802 * untyped atomic message on Ivy Bridge, but that's OK because
2803 * unused channels will be masked out.
2805 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
,
2806 src_reg(atomic_op
), src_reg(surf_index
));
2812 vec4_visitor::emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
2815 /* Set the surface read offset. */
2816 emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X
), offset
));
2818 /* Emit the instruction. Note that this maps to the normal SIMD8
2819 * untyped surface read message, but that's OK because unused
2820 * channels will be masked out.
2822 vec4_instruction
*inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
,
2823 dst
, src_reg(surf_index
));
2829 vec4_visitor::emit_ndc_computation()
2831 /* Get the position */
2832 src_reg pos
= src_reg(output_reg
[VARYING_SLOT_POS
]);
2834 /* Build ndc coords, which are (x/w, y/w, z/w, 1/w) */
2835 dst_reg ndc
= dst_reg(this, glsl_type::vec4_type
);
2836 output_reg
[BRW_VARYING_SLOT_NDC
] = ndc
;
2838 current_annotation
= "NDC";
2839 dst_reg ndc_w
= ndc
;
2840 ndc_w
.writemask
= WRITEMASK_W
;
2841 src_reg pos_w
= pos
;
2842 pos_w
.swizzle
= BRW_SWIZZLE4(SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
, SWIZZLE_W
);
2843 emit_math(SHADER_OPCODE_RCP
, ndc_w
, pos_w
);
2845 dst_reg ndc_xyz
= ndc
;
2846 ndc_xyz
.writemask
= WRITEMASK_XYZ
;
2848 emit(MUL(ndc_xyz
, pos
, src_reg(ndc_w
)));
2852 vec4_visitor::emit_psiz_and_flags(dst_reg reg
)
2855 ((prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) ||
2856 key
->userclip_active
|| brw
->has_negative_rhw_bug
)) {
2857 dst_reg header1
= dst_reg(this, glsl_type::uvec4_type
);
2858 dst_reg header1_w
= header1
;
2859 header1_w
.writemask
= WRITEMASK_W
;
2861 emit(MOV(header1
, 0u));
2863 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2864 src_reg psiz
= src_reg(output_reg
[VARYING_SLOT_PSIZ
]);
2866 current_annotation
= "Point size";
2867 emit(MUL(header1_w
, psiz
, src_reg((float)(1 << 11))));
2868 emit(AND(header1_w
, src_reg(header1_w
), 0x7ff << 8));
2871 if (key
->userclip_active
) {
2872 current_annotation
= "Clipping flags";
2873 dst_reg flags0
= dst_reg(this, glsl_type::uint_type
);
2874 dst_reg flags1
= dst_reg(this, glsl_type::uint_type
);
2876 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST0
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2877 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags0
, src_reg(0));
2878 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags0
)));
2880 emit(CMP(dst_null_f(), src_reg(output_reg
[VARYING_SLOT_CLIP_DIST1
]), src_reg(0.0f
), BRW_CONDITIONAL_L
));
2881 emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2
, flags1
, src_reg(0));
2882 emit(SHL(flags1
, src_reg(flags1
), src_reg(4)));
2883 emit(OR(header1_w
, src_reg(header1_w
), src_reg(flags1
)));
2886 /* i965 clipping workaround:
2887 * 1) Test for -ve rhw
2889 * set ndc = (0,0,0,0)
2892 * Later, clipping will detect ucp[6] and ensure the primitive is
2893 * clipped against all fixed planes.
2895 if (brw
->has_negative_rhw_bug
) {
2896 src_reg ndc_w
= src_reg(output_reg
[BRW_VARYING_SLOT_NDC
]);
2897 ndc_w
.swizzle
= BRW_SWIZZLE_WWWW
;
2898 emit(CMP(dst_null_f(), ndc_w
, src_reg(0.0f
), BRW_CONDITIONAL_L
));
2899 vec4_instruction
*inst
;
2900 inst
= emit(OR(header1_w
, src_reg(header1_w
), src_reg(1u << 6)));
2901 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2902 inst
= emit(MOV(output_reg
[BRW_VARYING_SLOT_NDC
], src_reg(0.0f
)));
2903 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2906 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), src_reg(header1
)));
2907 } else if (brw
->gen
< 6) {
2908 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_UD
), 0u));
2910 emit(MOV(retype(reg
, BRW_REGISTER_TYPE_D
), src_reg(0)));
2911 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_PSIZ
) {
2912 dst_reg reg_w
= reg
;
2913 reg_w
.writemask
= WRITEMASK_W
;
2914 emit(MOV(reg_w
, src_reg(output_reg
[VARYING_SLOT_PSIZ
])));
2916 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_LAYER
) {
2917 dst_reg reg_y
= reg
;
2918 reg_y
.writemask
= WRITEMASK_Y
;
2919 reg_y
.type
= BRW_REGISTER_TYPE_D
;
2920 emit(MOV(reg_y
, src_reg(output_reg
[VARYING_SLOT_LAYER
])));
2922 if (prog_data
->vue_map
.slots_valid
& VARYING_BIT_VIEWPORT
) {
2923 dst_reg reg_z
= reg
;
2924 reg_z
.writemask
= WRITEMASK_Z
;
2925 reg_z
.type
= BRW_REGISTER_TYPE_D
;
2926 emit(MOV(reg_z
, src_reg(output_reg
[VARYING_SLOT_VIEWPORT
])));
2932 vec4_visitor::emit_clip_distances(dst_reg reg
, int offset
)
2934 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
2936 * "If a linked set of shaders forming the vertex stage contains no
2937 * static write to gl_ClipVertex or gl_ClipDistance, but the
2938 * application has requested clipping against user clip planes through
2939 * the API, then the coordinate written to gl_Position is used for
2940 * comparison against the user clip planes."
2942 * This function is only called if the shader didn't write to
2943 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
2944 * if the user wrote to it; otherwise we use gl_Position.
2946 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
2947 if (!(prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
)) {
2948 clip_vertex
= VARYING_SLOT_POS
;
2951 for (int i
= 0; i
+ offset
< key
->nr_userclip_plane_consts
&& i
< 4;
2953 reg
.writemask
= 1 << i
;
2955 src_reg(output_reg
[clip_vertex
]),
2956 src_reg(this->userplane
[i
+ offset
])));
2961 vec4_visitor::emit_generic_urb_slot(dst_reg reg
, int varying
)
2963 assert (varying
< VARYING_SLOT_MAX
);
2964 reg
.type
= output_reg
[varying
].type
;
2965 current_annotation
= output_reg_annotation
[varying
];
2966 /* Copy the register, saturating if necessary */
2967 vec4_instruction
*inst
= emit(MOV(reg
,
2968 src_reg(output_reg
[varying
])));
2969 if ((varying
== VARYING_SLOT_COL0
||
2970 varying
== VARYING_SLOT_COL1
||
2971 varying
== VARYING_SLOT_BFC0
||
2972 varying
== VARYING_SLOT_BFC1
) &&
2973 key
->clamp_vertex_color
) {
2974 inst
->saturate
= true;
2979 vec4_visitor::emit_urb_slot(dst_reg reg
, int varying
)
2981 reg
.type
= BRW_REGISTER_TYPE_F
;
2984 case VARYING_SLOT_PSIZ
:
2986 /* PSIZ is always in slot 0, and is coupled with other flags. */
2987 current_annotation
= "indices, point width, clip flags";
2988 emit_psiz_and_flags(reg
);
2991 case BRW_VARYING_SLOT_NDC
:
2992 current_annotation
= "NDC";
2993 emit(MOV(reg
, src_reg(output_reg
[BRW_VARYING_SLOT_NDC
])));
2995 case VARYING_SLOT_POS
:
2996 current_annotation
= "gl_Position";
2997 emit(MOV(reg
, src_reg(output_reg
[VARYING_SLOT_POS
])));
2999 case VARYING_SLOT_EDGE
:
3000 /* This is present when doing unfilled polygons. We're supposed to copy
3001 * the edge flag from the user-provided vertex array
3002 * (glEdgeFlagPointer), or otherwise we'll copy from the current value
3003 * of that attribute (starts as 1.0f). This is then used in clipping to
3004 * determine which edges should be drawn as wireframe.
3006 current_annotation
= "edge flag";
3007 emit(MOV(reg
, src_reg(dst_reg(ATTR
, VERT_ATTRIB_EDGEFLAG
,
3008 glsl_type::float_type
, WRITEMASK_XYZW
))));
3010 case BRW_VARYING_SLOT_PAD
:
3011 /* No need to write to this slot */
3014 emit_generic_urb_slot(reg
, varying
);
3020 align_interleaved_urb_mlen(struct brw_context
*brw
, int mlen
)
3022 if (brw
->gen
>= 6) {
3023 /* URB data written (does not include the message header reg) must
3024 * be a multiple of 256 bits, or 2 VS registers. See vol5c.5,
3025 * section 5.4.3.2.2: URB_INTERLEAVED.
3027 * URB entries are allocated on a multiple of 1024 bits, so an
3028 * extra 128 bits written here to make the end align to 256 is
3031 if ((mlen
% 2) != 1)
3040 * Generates the VUE payload plus the necessary URB write instructions to
3043 * The VUE layout is documented in Volume 2a.
3046 vec4_visitor::emit_vertex()
3048 /* MRF 0 is reserved for the debugger, so start with message header
3053 /* In the process of generating our URB write message contents, we
3054 * may need to unspill a register or load from an array. Those
3055 * reads would use MRFs 14-15.
3057 int max_usable_mrf
= 13;
3059 /* The following assertion verifies that max_usable_mrf causes an
3060 * even-numbered amount of URB write data, which will meet gen6's
3061 * requirements for length alignment.
3063 assert ((max_usable_mrf
- base_mrf
) % 2 == 0);
3065 /* First mrf is the g0-based message header containing URB handles and
3068 emit_urb_write_header(mrf
++);
3071 emit_ndc_computation();
3074 /* Lower legacy ff and ClipVertex clipping to clip distances */
3075 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
) {
3076 current_annotation
= "user clip distances";
3078 output_reg
[VARYING_SLOT_CLIP_DIST0
] = dst_reg(this, glsl_type::vec4_type
);
3079 output_reg
[VARYING_SLOT_CLIP_DIST1
] = dst_reg(this, glsl_type::vec4_type
);
3081 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST0
], 0);
3082 emit_clip_distances(output_reg
[VARYING_SLOT_CLIP_DIST1
], 4);
3085 /* We may need to split this up into several URB writes, so do them in a
3089 bool complete
= false;
3091 /* URB offset is in URB row increments, and each of our MRFs is half of
3092 * one of those, since we're doing interleaved writes.
3094 int offset
= slot
/ 2;
3097 for (; slot
< prog_data
->vue_map
.num_slots
; ++slot
) {
3098 emit_urb_slot(dst_reg(MRF
, mrf
++),
3099 prog_data
->vue_map
.slot_to_varying
[slot
]);
3101 /* If this was max_usable_mrf, we can't fit anything more into this
3104 if (mrf
> max_usable_mrf
) {
3110 complete
= slot
>= prog_data
->vue_map
.num_slots
;
3111 current_annotation
= "URB write";
3112 vec4_instruction
*inst
= emit_urb_write_opcode(complete
);
3113 inst
->base_mrf
= base_mrf
;
3114 inst
->mlen
= align_interleaved_urb_mlen(brw
, mrf
- base_mrf
);
3115 inst
->offset
+= offset
;
3121 vec4_visitor::get_scratch_offset(bblock_t
*block
, vec4_instruction
*inst
,
3122 src_reg
*reladdr
, int reg_offset
)
3124 /* Because we store the values to scratch interleaved like our
3125 * vertex data, we need to scale the vec4 index by 2.
3127 int message_header_scale
= 2;
3129 /* Pre-gen6, the message header uses byte offsets instead of vec4
3130 * (16-byte) offset units.
3133 message_header_scale
*= 16;
3136 src_reg index
= src_reg(this, glsl_type::int_type
);
3138 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3139 src_reg(reg_offset
)));
3140 emit_before(block
, inst
, MUL(dst_reg(index
), index
,
3141 src_reg(message_header_scale
)));
3145 return src_reg(reg_offset
* message_header_scale
);
3150 vec4_visitor::get_pull_constant_offset(bblock_t
* block
, vec4_instruction
*inst
,
3151 src_reg
*reladdr
, int reg_offset
)
3154 src_reg index
= src_reg(this, glsl_type::int_type
);
3156 emit_before(block
, inst
, ADD(dst_reg(index
), *reladdr
,
3157 src_reg(reg_offset
)));
3159 /* Pre-gen6, the message header uses byte offsets instead of vec4
3160 * (16-byte) offset units.
3163 emit_before(block
, inst
, MUL(dst_reg(index
), index
, src_reg(16)));
3167 } else if (brw
->gen
>= 8) {
3168 /* Store the offset in a GRF so we can send-from-GRF. */
3169 src_reg offset
= src_reg(this, glsl_type::int_type
);
3170 emit_before(block
, inst
, MOV(dst_reg(offset
), src_reg(reg_offset
)));
3173 int message_header_scale
= brw
->gen
< 6 ? 16 : 1;
3174 return src_reg(reg_offset
* message_header_scale
);
3179 * Emits an instruction before @inst to load the value named by @orig_src
3180 * from scratch space at @base_offset to @temp.
3182 * @base_offset is measured in 32-byte units (the size of a register).
3185 vec4_visitor::emit_scratch_read(bblock_t
*block
, vec4_instruction
*inst
,
3186 dst_reg temp
, src_reg orig_src
,
3189 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3190 src_reg index
= get_scratch_offset(block
, inst
, orig_src
.reladdr
,
3193 emit_before(block
, inst
, SCRATCH_READ(temp
, index
));
3197 * Emits an instruction after @inst to store the value to be written
3198 * to @orig_dst to scratch space at @base_offset, from @temp.
3200 * @base_offset is measured in 32-byte units (the size of a register).
3203 vec4_visitor::emit_scratch_write(bblock_t
*block
, vec4_instruction
*inst
,
3206 int reg_offset
= base_offset
+ inst
->dst
.reg_offset
;
3207 src_reg index
= get_scratch_offset(block
, inst
, inst
->dst
.reladdr
,
3210 /* Create a temporary register to store *inst's result in.
3212 * We have to be careful in MOVing from our temporary result register in
3213 * the scratch write. If we swizzle from channels of the temporary that
3214 * weren't initialized, it will confuse live interval analysis, which will
3215 * make spilling fail to make progress.
3217 src_reg temp
= src_reg(this, glsl_type::vec4_type
);
3218 temp
.type
= inst
->dst
.type
;
3219 int first_writemask_chan
= ffs(inst
->dst
.writemask
) - 1;
3221 for (int i
= 0; i
< 4; i
++)
3222 if (inst
->dst
.writemask
& (1 << i
))
3225 swizzles
[i
] = first_writemask_chan
;
3226 temp
.swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
3227 swizzles
[2], swizzles
[3]);
3229 dst_reg dst
= dst_reg(brw_writemask(brw_vec8_grf(0, 0),
3230 inst
->dst
.writemask
));
3231 vec4_instruction
*write
= SCRATCH_WRITE(dst
, temp
, index
);
3232 write
->predicate
= inst
->predicate
;
3233 write
->ir
= inst
->ir
;
3234 write
->annotation
= inst
->annotation
;
3235 inst
->insert_after(block
, write
);
3237 inst
->dst
.file
= temp
.file
;
3238 inst
->dst
.reg
= temp
.reg
;
3239 inst
->dst
.reg_offset
= temp
.reg_offset
;
3240 inst
->dst
.reladdr
= NULL
;
3244 * We can't generally support array access in GRF space, because a
3245 * single instruction's destination can only span 2 contiguous
3246 * registers. So, we send all GRF arrays that get variable index
3247 * access to scratch space.
3250 vec4_visitor::move_grf_array_access_to_scratch()
3252 int scratch_loc
[this->virtual_grf_count
];
3253 memset(scratch_loc
, -1, sizeof(scratch_loc
));
3255 /* First, calculate the set of virtual GRFs that need to be punted
3256 * to scratch due to having any array access on them, and where in
3259 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
3260 if (inst
->dst
.file
== GRF
&& inst
->dst
.reladdr
&&
3261 scratch_loc
[inst
->dst
.reg
] == -1) {
3262 scratch_loc
[inst
->dst
.reg
] = c
->last_scratch
;
3263 c
->last_scratch
+= this->virtual_grf_sizes
[inst
->dst
.reg
];
3266 for (int i
= 0 ; i
< 3; i
++) {
3267 src_reg
*src
= &inst
->src
[i
];
3269 if (src
->file
== GRF
&& src
->reladdr
&&
3270 scratch_loc
[src
->reg
] == -1) {
3271 scratch_loc
[src
->reg
] = c
->last_scratch
;
3272 c
->last_scratch
+= this->virtual_grf_sizes
[src
->reg
];
3277 /* Now, for anything that will be accessed through scratch, rewrite
3278 * it to load/store. Note that this is a _safe list walk, because
3279 * we may generate a new scratch_write instruction after the one
3282 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3283 /* Set up the annotation tracking for new generated instructions. */
3285 current_annotation
= inst
->annotation
;
3287 if (inst
->dst
.file
== GRF
&& scratch_loc
[inst
->dst
.reg
] != -1) {
3288 emit_scratch_write(block
, inst
, scratch_loc
[inst
->dst
.reg
]);
3291 for (int i
= 0 ; i
< 3; i
++) {
3292 if (inst
->src
[i
].file
!= GRF
|| scratch_loc
[inst
->src
[i
].reg
] == -1)
3295 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3297 emit_scratch_read(block
, inst
, temp
, inst
->src
[i
],
3298 scratch_loc
[inst
->src
[i
].reg
]);
3300 inst
->src
[i
].file
= temp
.file
;
3301 inst
->src
[i
].reg
= temp
.reg
;
3302 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3303 inst
->src
[i
].reladdr
= NULL
;
3309 * Emits an instruction before @inst to load the value named by @orig_src
3310 * from the pull constant buffer (surface) at @base_offset to @temp.
3313 vec4_visitor::emit_pull_constant_load(bblock_t
*block
, vec4_instruction
*inst
,
3314 dst_reg temp
, src_reg orig_src
,
3317 int reg_offset
= base_offset
+ orig_src
.reg_offset
;
3318 src_reg index
= src_reg(prog_data
->base
.binding_table
.pull_constants_start
);
3319 src_reg offset
= get_pull_constant_offset(block
, inst
, orig_src
.reladdr
,
3321 vec4_instruction
*load
;
3323 if (brw
->gen
>= 7) {
3324 dst_reg grf_offset
= dst_reg(this, glsl_type::int_type
);
3325 grf_offset
.type
= offset
.type
;
3326 emit_before(block
, inst
, MOV(grf_offset
, offset
));
3328 load
= new(mem_ctx
) vec4_instruction(this,
3329 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
3330 temp
, index
, src_reg(grf_offset
));
3332 load
= new(mem_ctx
) vec4_instruction(this, VS_OPCODE_PULL_CONSTANT_LOAD
,
3333 temp
, index
, offset
);
3334 load
->base_mrf
= 14;
3337 emit_before(block
, inst
, load
);
3341 * Implements array access of uniforms by inserting a
3342 * PULL_CONSTANT_LOAD instruction.
3344 * Unlike temporary GRF array access (where we don't support it due to
3345 * the difficulty of doing relative addressing on instruction
3346 * destinations), we could potentially do array access of uniforms
3347 * that were loaded in GRF space as push constants. In real-world
3348 * usage we've seen, though, the arrays being used are always larger
3349 * than we could load as push constants, so just always move all
3350 * uniform array access out to a pull constant buffer.
3353 vec4_visitor::move_uniform_array_access_to_pull_constants()
3355 int pull_constant_loc
[this->uniforms
];
3356 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
));
3358 /* Walk through and find array access of uniforms. Put a copy of that
3359 * uniform in the pull constant buffer.
3361 * Note that we don't move constant-indexed accesses to arrays. No
3362 * testing has been done of the performance impact of this choice.
3364 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
3365 for (int i
= 0 ; i
< 3; i
++) {
3366 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
3369 int uniform
= inst
->src
[i
].reg
;
3371 /* If this array isn't already present in the pull constant buffer,
3374 if (pull_constant_loc
[uniform
] == -1) {
3375 const gl_constant_value
**values
=
3376 &stage_prog_data
->param
[uniform
* 4];
3378 pull_constant_loc
[uniform
] = stage_prog_data
->nr_pull_params
/ 4;
3380 assert(uniform
< uniform_array_size
);
3381 for (int j
= 0; j
< uniform_size
[uniform
] * 4; j
++) {
3382 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++]
3387 /* Set up the annotation tracking for new generated instructions. */
3389 current_annotation
= inst
->annotation
;
3391 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
3393 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
3394 pull_constant_loc
[uniform
]);
3396 inst
->src
[i
].file
= temp
.file
;
3397 inst
->src
[i
].reg
= temp
.reg
;
3398 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
3399 inst
->src
[i
].reladdr
= NULL
;
3403 /* Now there are no accesses of the UNIFORM file with a reladdr, so
3404 * no need to track them as larger-than-vec4 objects. This will be
3405 * relied on in cutting out unused uniform vectors from push
3408 split_uniform_registers();
3412 vec4_visitor::resolve_ud_negate(src_reg
*reg
)
3414 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3418 src_reg temp
= src_reg(this, glsl_type::uvec4_type
);
3419 emit(BRW_OPCODE_MOV
, dst_reg(temp
), *reg
);
3423 vec4_visitor::vec4_visitor(struct brw_context
*brw
,
3424 struct brw_vec4_compile
*c
,
3425 struct gl_program
*prog
,
3426 const struct brw_vec4_prog_key
*key
,
3427 struct brw_vec4_prog_data
*prog_data
,
3428 struct gl_shader_program
*shader_prog
,
3429 gl_shader_stage stage
,
3433 shader_time_shader_type st_base
,
3434 shader_time_shader_type st_written
,
3435 shader_time_shader_type st_reset
)
3436 : backend_visitor(brw
, shader_prog
, prog
, &prog_data
->base
, stage
),
3439 prog_data(prog_data
),
3440 sanity_param_count(0),
3442 first_non_payload_grf(0),
3443 need_all_constants_in_pull_buffer(false),
3444 debug_flag(debug_flag
),
3445 no_spills(no_spills
),
3447 st_written(st_written
),
3450 this->mem_ctx
= mem_ctx
;
3451 this->failed
= false;
3453 this->base_ir
= NULL
;
3454 this->current_annotation
= NULL
;
3455 memset(this->output_reg_annotation
, 0, sizeof(this->output_reg_annotation
));
3457 this->variable_ht
= hash_table_ctor(0,
3458 hash_table_pointer_hash
,
3459 hash_table_pointer_compare
);
3461 this->virtual_grf_start
= NULL
;
3462 this->virtual_grf_end
= NULL
;
3463 this->virtual_grf_sizes
= NULL
;
3464 this->virtual_grf_count
= 0;
3465 this->virtual_grf_reg_map
= NULL
;
3466 this->virtual_grf_reg_count
= 0;
3467 this->virtual_grf_array_size
= 0;
3468 this->live_intervals_valid
= false;
3470 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3474 /* Initialize uniform_array_size to at least 1 because pre-gen6 VS requires
3475 * at least one. See setup_uniforms() in brw_vec4.cpp.
3477 this->uniform_array_size
= 1;
3479 this->uniform_array_size
= MAX2(stage_prog_data
->nr_params
, 1);
3482 this->uniform_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3483 this->uniform_vector_size
= rzalloc_array(mem_ctx
, int, this->uniform_array_size
);
3486 vec4_visitor::~vec4_visitor()
3488 hash_table_dtor(this->variable_ht
);
3493 vec4_visitor::fail(const char *format
, ...)
3503 va_start(va
, format
);
3504 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
3506 msg
= ralloc_asprintf(mem_ctx
, "vec4 compile failed: %s\n", msg
);
3508 this->fail_msg
= msg
;
3511 fprintf(stderr
, "%s", msg
);
3515 } /* namespace brw */